[PATCH 00/10] drm/i915: Enable vblanks after the timing generator has started

[PATCH 00/10] drm/i915: Enable vblanks after the timing generator has started

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we may enable the vblank machinery before the
timing generator has actually started, which means the
frame/scanline counters read out during the vblank enabling
may be complete nonsense. When the timing generator finally
starts running and we get the first vblank interrupt the
sampled counters may jump erratically, which could cause
the vblank code to get confused as to how many frames have
actually elapsed.

The series fixes the problem for HSW+ by making sure the
timing generator is actually ticking before we enable
the vblank machinery. I also plan to fix the pre-HSW
platforms but I'll need to do a bit more reverse
engineering to figure out the final details.

While doing this I also ended up fixing some related
FEC issues with port sync, and finally enable joiner+port
sync because we no longer have any need to keep the two
apart from each other.

Ville Syrjälä (10):
  drm/i915: Disable port sync if VRR is enabled
  drm/i915: Do intel_crtc_vblank_on() later on HSW+
  drm/i915: Handle joined pipes inside intel_crtc_vblank_{on,off}()
  Revert "drm/i915/display: Avoid stale PIPE_SCANLINE values after
    crtc_enable"
  drm/i915: Fix intel_crtc_vblank_on() with port sync
  drm/i915: Wait for timing generator to start in intel_crtc_vblank_on()
    on HSW+
  drm/i915: Reduce the sleep inside pipe_scanline_is_moving()
  drm/i915: Document timing generator start/stop behaviour on HSW+
  drm/i915: Fix FEC wait with port sync on pre-LNL
  drm/i915: Allow joiner with port sync

 drivers/gpu/drm/i915/display/icl_dsi.c        |   4 +-
 drivers/gpu/drm/i915/display/intel_crt.c      |   6 +-
 drivers/gpu/drm/i915/display/intel_crtc.c     |  45 ++++++-
 drivers/gpu/drm/i915/display/intel_crtc.h     |   8 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 120 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_display.c  |  12 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  17 +--
 .../drm/i915/display/intel_modeset_setup.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   |   2 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |   4 +-
 10 files changed, 166 insertions(+), 54 deletions(-)

-- 
2.55.0

[PATCH 01/10] drm/i915: Disable port sync if VRR is enabled

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Using both VRR and port sync together would require extra
work, which we don't do. Trying this with the current code
will anger the hardware. Disable port sync if VRR is enabled.

This will of course allow the previously synced outputs
to go out of sync. It would probably make more sense to
reject VRR instead when port sync is used, but that's not
possible right now because VRR state is computed from
.compute_config() and port sync from .compute_config_late().
So let's take the easy way out for now, which at least
keeps the hardware happy.

Cc: stable@vger.kernel.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a0aff087fafa..ed7d4cbbfb5a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4599,9 +4599,12 @@ static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state
 	/*
 	 * FIXME the modeset sequence is currently wrong and
 	 * can't deal with joiner + port sync at the same time.
+	 *
+	 * TODO VRR + port sync needs special handling
 	 */
 	return crtc_state1->hw.active && crtc_state2->hw.active &&
 		!crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes &&
+		!crtc_state1->vrr.enable && !crtc_state2->vrr.enable &&
 		crtc_state1->output_types == crtc_state2->output_types &&
 		crtc_state1->output_format == crtc_state2->output_format &&
 		crtc_state1->lane_count == crtc_state2->lane_count &&
-- 
2.55.0

[PATCH 02/10] drm/i915: Do intel_crtc_vblank_on() later on HSW+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We are doing intel_crtc_vblank_on() too early. The timing generator
doesn't actually start until:
HDMI: DDI_BUF_CTL is enabled, TRANSCONF is already enabled earlier
DP SST: switching DP_TP_CTL to normal mode or enabling TRANSCONF.
        The order varies between the platorms a bit, but whichever
        happens last is the important step

All of that is guaranteed to have happened after
intel_ddi_enable_{dp,hdmi}() have been called, not before.
Reorder the function calls appropriately. This takes care of the
typical use cases. Fixing the more exotic port sync case will
need a bit of extra work.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ed7d4cbbfb5a..9fb455d980ce 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3572,6 +3572,11 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 
 	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
 
+	if (is_hdmi)
+		intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);
+	else
+		intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
+
 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
@@ -3579,13 +3584,7 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 		intel_crtc_vblank_on(pipe_crtc_state);
 	}
 
-	if (is_hdmi)
-		intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);
-	else
-		intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
-
 	intel_hdcp_enable(state, encoder, crtc_state, conn_state);
-
 }
 
 static void intel_ddi_disable_dp(struct intel_atomic_state *state,
-- 
2.55.0

[PATCH 03/10] drm/i915: Handle joined pipes inside intel_crtc_vblank_{on, off}()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make life easier for the callers of intel_crtc_vblank_{on,off}()
by handling the joined pipes inside the function itself.

We do still need the leave the per-pipe variant exposed for
intel_modeset_setup_hw_state().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |  4 +--
 drivers/gpu/drm/i915/display/intel_crt.c      |  4 +--
 drivers/gpu/drm/i915/display/intel_crtc.c     | 32 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_crtc.h     |  8 +++--
 drivers/gpu/drm/i915/display/intel_ddi.c      | 15 ++-------
 drivers/gpu/drm/i915/display/intel_display.c  | 10 +++---
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 15 ++-------
 .../drm/i915/display/intel_modeset_setup.c    |  2 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |  4 +--
 9 files changed, 52 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ea0cdb7822f3..381cdf7d5131 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1304,7 +1304,7 @@ static void gen11_dsi_enable(struct intel_atomic_state *state,
 
 	intel_panel_prepare(crtc_state, conn_state);
 
-	intel_crtc_vblank_on(crtc_state);
+	intel_crtc_vblank_on(state, crtc_state);
 }
 
 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
@@ -1455,7 +1455,7 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state,
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 
-	intel_crtc_vblank_off(old_crtc_state);
+	intel_crtc_vblank_off(state, old_crtc_state);
 
 	/* step2d,e: disable transcoder and wait */
 	gen11_dsi_disable_transcoder(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 5b8968197fbc..b814b84c650f 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -265,7 +265,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 
-	intel_crtc_vblank_off(old_crtc_state);
+	intel_crtc_vblank_off(state, old_crtc_state);
 
 	intel_disable_transcoder(old_crtc_state);
 
@@ -333,7 +333,7 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
 
 	lpt_pch_enable(state, crtc);
 
-	intel_crtc_vblank_on(crtc_state);
+	intel_crtc_vblank_on(state, crtc_state);
 
 	intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 139c9dae536e..fe7af983f9f5 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -126,7 +126,7 @@ u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
 		return 0; /* Gen2 doesn't have a hardware frame counter */
 }
 
-void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
+void intel_pipe_vblank_on(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
@@ -145,7 +145,7 @@ void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
 	trace_intel_pipe_enable(crtc);
 }
 
-void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
+void intel_pipe_vblank_off(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -165,6 +165,34 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
 	flush_work(&display->irq.vblank_notify_work);
 }
 
+void intel_crtc_vblank_on(struct intel_atomic_state *state,
+			  const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_crtc *pipe_crtc;
+
+	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
+		const struct intel_crtc_state *pipe_crtc_state =
+			intel_atomic_get_new_crtc_state(state, pipe_crtc);
+
+		intel_pipe_vblank_on(pipe_crtc_state);
+	}
+}
+
+void intel_crtc_vblank_off(struct intel_atomic_state *state,
+			   const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_crtc *pipe_crtc;
+
+	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
+		const struct intel_crtc_state *old_pipe_crtc_state =
+			intel_atomic_get_old_crtc_state(state, pipe_crtc);
+
+		intel_pipe_vblank_off(old_pipe_crtc_state);
+	}
+}
+
 struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
 {
 	struct intel_crtc_state *crtc_state;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
index 12507b51ee77..959a009efd3e 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc.h
@@ -44,8 +44,12 @@ struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
 void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
 			    struct intel_crtc *crtc);
 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
-void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
-void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
+void intel_pipe_vblank_on(const struct intel_crtc_state *crtc_state);
+void intel_pipe_vblank_off(const struct intel_crtc_state *crtc_state);
+void intel_crtc_vblank_on(struct intel_atomic_state *state,
+			  const struct intel_crtc_state *crtc_state);
+void intel_crtc_vblank_off(struct intel_atomic_state *state,
+			   const struct intel_crtc_state *old_crtc_state);
 void intel_pipe_update_start(struct intel_atomic_state *state,
 			     struct intel_crtc *crtc);
 void intel_pipe_update_end(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9fb455d980ce..12222e5096d4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3253,12 +3253,7 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
 	struct intel_crtc *pipe_crtc;
 	bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI);
 
-	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
-		const struct intel_crtc_state *old_pipe_crtc_state =
-			intel_atomic_get_old_crtc_state(state, pipe_crtc);
-
-		intel_crtc_vblank_off(old_pipe_crtc_state);
-	}
+	intel_crtc_vblank_off(state, old_crtc_state);
 
 	intel_disable_transcoder(old_crtc_state);
 
@@ -3536,7 +3531,6 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 			     const struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
-	struct intel_crtc *pipe_crtc;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
 
@@ -3577,12 +3571,7 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 	else
 		intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
 
-	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
-		const struct intel_crtc_state *pipe_crtc_state =
-			intel_atomic_get_new_crtc_state(state, pipe_crtc);
-
-		intel_crtc_vblank_on(pipe_crtc_state);
-	}
+	intel_crtc_vblank_on(state, crtc_state);
 
 	intel_hdcp_enable(state, encoder, crtc_state, conn_state);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5e40487e9ab0..7dd857b0b8e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1626,7 +1626,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	if (new_crtc_state->has_pch_encoder)
 		ilk_pch_enable(state, crtc);
 
-	intel_crtc_vblank_on(new_crtc_state);
+	intel_crtc_vblank_on(state, new_crtc_state);
 
 	intel_encoders_enable(state, crtc);
 
@@ -1828,7 +1828,7 @@ static void ilk_crtc_disable(struct intel_atomic_state *state,
 
 	intel_encoders_disable(state, crtc);
 
-	intel_crtc_vblank_off(old_crtc_state);
+	intel_crtc_vblank_off(state, old_crtc_state);
 
 	intel_disable_transcoder(old_crtc_state);
 
@@ -2175,7 +2175,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 	intel_initial_watermarks(state, crtc);
 	intel_enable_transcoder(new_crtc_state);
 
-	intel_crtc_vblank_on(new_crtc_state);
+	intel_crtc_vblank_on(state, new_crtc_state);
 
 	intel_encoders_enable(state, crtc);
 }
@@ -2212,7 +2212,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 		intel_update_watermarks(display);
 	intel_enable_transcoder(new_crtc_state);
 
-	intel_crtc_vblank_on(new_crtc_state);
+	intel_crtc_vblank_on(state, new_crtc_state);
 
 	intel_encoders_enable(state, crtc);
 
@@ -2238,7 +2238,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
 
 	intel_encoders_disable(state, crtc);
 
-	intel_crtc_vblank_off(old_crtc_state);
+	intel_crtc_vblank_off(state, old_crtc_state);
 
 	intel_disable_transcoder(old_crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1e6190689e6b..84e69f37deff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1114,12 +1114,7 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
 	drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && last_mst_stream &&
 		    !intel_dp_mst_is_master_trans(old_crtc_state));
 
-	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
-		const struct intel_crtc_state *old_pipe_crtc_state =
-			intel_atomic_get_old_crtc_state(state, pipe_crtc);
-
-		intel_crtc_vblank_off(old_pipe_crtc_state);
-	}
+	intel_crtc_vblank_off(state, old_crtc_state);
 
 	intel_disable_transcoder(old_crtc_state);
 
@@ -1351,7 +1346,6 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 		drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr);
 	enum transcoder trans = pipe_config->cpu_transcoder;
 	bool first_mst_stream = intel_dp_mst_active_streams(intel_dp) == 1;
-	struct intel_crtc *pipe_crtc;
 	int ret;
 
 	drm_WARN_ON(display->drm, pipe_config->has_pch_encoder);
@@ -1397,12 +1391,7 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 
 	intel_enable_transcoder(pipe_config);
 
-	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
-		const struct intel_crtc_state *pipe_crtc_state =
-			intel_atomic_get_new_crtc_state(state, pipe_crtc);
-
-		intel_crtc_vblank_on(pipe_crtc_state);
-	}
+	intel_crtc_vblank_on(state, pipe_config);
 
 	intel_hdcp_enable(state, encoder, pipe_config, conn_state);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 6aed88173770..db8af96782f8 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -969,7 +969,7 @@ void intel_modeset_setup_hw_state(struct intel_display *display,
 
 		if (crtc_state->hw.active) {
 			intel_dmc_enable_pipe(crtc_state);
-			intel_crtc_vblank_on(crtc_state);
+			intel_pipe_vblank_on(crtc_state);
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 8829f365592e..ee3196e40ca7 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -821,7 +821,7 @@ static void bxt_dsi_enable(struct intel_atomic_state *state,
 			   const struct intel_crtc_state *crtc_state,
 			   const struct drm_connector_state *conn_state)
 {
-	intel_crtc_vblank_on(crtc_state);
+	intel_crtc_vblank_on(state, crtc_state);
 }
 
 /*
@@ -877,7 +877,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state,
 	drm_dbg_kms(display->drm, "\n");
 
 	if (display->platform.geminilake || display->platform.broxton) {
-		intel_crtc_vblank_off(old_crtc_state);
+		intel_crtc_vblank_off(state, old_crtc_state);
 
 		skl_scaler_disable(old_crtc_state);
 	}
-- 
2.55.0

[PATCH 04/10] Revert "drm/i915/display: Avoid stale PIPE_SCANLINE values after crtc_enable"

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This reverts commit d08e46efae16b607f13d95a4cd5b84a958b7e995.

This extra vblank wait in intel_update_crtc() seems to have been some
kind of hack to hide the problems caused by enabling the vblank
machinery before the timing generator has actually started. That
is now getting fixed properly and this extra vblank wait has in fact
become a hindrance. Once properly handled, port sync secondaries will
not have enabled vblanks at this point, and trying to call
drm_crtc_wait_one_vblank() with vblanks off will result in a WARN.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Pranay Samala <pranay.samala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7dd857b0b8e7..40ffa031cfea 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7003,8 +7003,6 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 
 	display->modeset.funcs->crtc_enable(state, crtc);
 
-	intel_crtc_wait_for_next_vblank(crtc);
-
 	/* vblanks work again, re-enable pipe CRC. */
 	intel_crtc_enable_pipe_crc(crtc);
 }
-- 
2.55.0

[PATCH 05/10] drm/i915: Fix intel_crtc_vblank_on() with port sync

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When port sync is used we first iterate the secondary transcoders
and leave them transmitting the idle pattern rather than producing
actual pixels. Only after the primary transcoder has finished its
link training we switch DP_TP_CTL on all the transcoders over to
normal mode, after which all the timings generators will start.

Defer the intel_crtc_vblank_on() calls for all the transcoders until
the timing generators have started, to avoid the frame/scanline
counters jumping erratically after the vblank machinery is up and
running.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 12222e5096d4..ed39f1e265a9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3243,6 +3243,35 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
 }
 
+static void trans_port_sync_vblank_on(struct intel_atomic_state *state,
+				      const struct intel_crtc_state *crtc_state)
+{
+	const struct drm_connector_state *conn_state;
+	struct drm_connector *conn;
+	int i;
+
+	if (!crtc_state->sync_mode_slaves_mask)
+		return;
+
+	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+		struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
+		const struct intel_crtc_state *slave_crtc_state;
+
+		if (!slave_crtc)
+			continue;
+
+		slave_crtc_state =
+			intel_atomic_get_new_crtc_state(state, slave_crtc);
+
+		if (slave_crtc_state->master_transcoder != crtc_state->cpu_transcoder)
+			continue;
+
+		intel_crtc_vblank_on(state, slave_crtc_state);
+	}
+
+	intel_crtc_vblank_on(state, crtc_state);
+}
+
 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
 					       struct intel_encoder *encoder,
 					       const struct intel_crtc_state *old_crtc_state,
@@ -3571,7 +3600,10 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 	else
 		intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
 
-	intel_crtc_vblank_on(state, crtc_state);
+	if (is_trans_port_sync_mode(crtc_state))
+		trans_port_sync_vblank_on(state, crtc_state);
+	else
+		intel_crtc_vblank_on(state, crtc_state);
 
 	intel_hdcp_enable(state, encoder, crtc_state, conn_state);
 }
-- 
2.55.0

[PATCH 06/10] drm/i915: Wait for timing generator to start in intel_crtc_vblank_on() on HSW+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The HSW+ modeset sequences (perhaps excluding DSI) should now do the
intel_crtc_vblank_on() calls after the timing generator has actually
been started. However it looks it may take a few moments until the
scanline counter actually starts to tick. Wait for that to happen
before we enabled vblank interrupts for the pipe. This should
guarantee that the vblank machinery will never see the frame/scanline
counters jumping erratically, which can cause real problems.

As for DSI, I have no hardware to test it, so can't tell whether
we're calling intel_crtc_vblank_on() in a good spot or not. I
guess we'll eventually find out when someone tries runs this on
machine with DSI...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index fe7af983f9f5..ae720e400073 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -128,8 +128,21 @@ u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
 
 void intel_pipe_vblank_on(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
+	/*
+	 * Make sure the timing generator has really started so
+	 * the sampled frame/scanline counter values don't jump
+	 * erratically.
+	 *
+	 * TODO do this for older platforms as well after
+	 * rearranging the modeset sequence a bit.
+	 */
+	if (DISPLAY_VER(display) >= 9 ||
+	    display->platform.broadwell || display->platform.haswell)
+		intel_wait_for_pipe_scanline_moving(crtc);
+
 	crtc->vblank_psr_notify = intel_psr_needs_vblank_notification(crtc_state);
 
 	assert_vblank_disabled(&crtc->base);
-- 
2.55.0

[PATCH 07/10] drm/i915: Reduce the sleep inside pipe_scanline_is_moving()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The msleep(5) inside pipe_scanline_is_moving() seems rather
excessive. Sleeping for too long might in fact be harmful
as it may even increase the chance that we end up sampling
the scanline at the same spot between two completely different
frames. With high refresh rate display frame durations are
now in the few millisecond range.

Let's use a 250-500 usec sleep instead, which more or less
matches what the poll_timeout_us() uses for the sleep duration
between the samplings. We reject any mode whose line time
excees 64 usec, so that number should guarantee that at least
a few scanlines will have elapsed, but not a whole frame.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 1d4753605675..749640007140 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -477,7 +477,7 @@ static bool pipe_scanline_is_moving(struct intel_display *display,
 	u32 line1, line2;
 
 	line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
-	msleep(5);
+	usleep_range(250, 500);
 	line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
 
 	return line1 != line2;
-- 
2.55.0

[PATCH 08/10] drm/i915: Document timing generator start/stop behaviour on HSW+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Document the HSW+ timing generator start/stop behaviour so
I don't have to reverse engineer it again in the future.

TODO: DSI behavior is unknown

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c    |  2 ++
 drivers/gpu/drm/i915/display/intel_ddi.c    | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  2 ++
 3 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index b814b84c650f..532617bf626f 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -265,6 +265,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 
+	/* timing generator stops after disabling TRANSCONF */
 	intel_crtc_vblank_off(state, old_crtc_state);
 
 	intel_disable_transcoder(old_crtc_state);
@@ -333,6 +334,7 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
 
 	lpt_pch_enable(state, crtc);
 
+	/* timing generator starts after enabling PCH_TRANSCONF */
 	intel_crtc_vblank_on(state, crtc_state);
 
 	intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ed39f1e265a9..e97e586bed72 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2961,6 +2961,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 						   crtc_state);
 	intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
 	intel_dp_start_link_train(state, intel_dp, crtc_state);
+
 	if ((port != PORT_A || DISPLAY_VER(display) >= 9) &&
 	    !is_trans_port_sync_mode(crtc_state))
 		intel_dp_stop_link_train(intel_dp, crtc_state);
@@ -3282,6 +3283,7 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
 	struct intel_crtc *pipe_crtc;
 	bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI);
 
+	/* timing generator stops after disabling TRANSCONF */
 	intel_crtc_vblank_off(state, old_crtc_state);
 
 	intel_disable_transcoder(old_crtc_state);
@@ -3600,6 +3602,22 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 	else
 		intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
 
+	/*
+	 * HDMI:
+	 *  timing generator starts after enabling DDI_BUF_CTL
+	 *  TRANSCONF is enabled beforehand
+	 * DP SST:
+	 *  timing generator starts after switching DP_TP_CTL
+	 *  link training to normal or enabling TRANSCONF
+	 *  (whichever happens last).
+	 *
+	 * With port sync the secondaries will be transmitting
+	 * the idle pattern (and thus their timing generators
+	 * will not run) until the primary has finished its
+	 * link training. At that point everyone will switch
+	 * DP_TP_CTL link training to normal all the timings
+	 * generators will start.
+	 */
 	if (is_trans_port_sync_mode(crtc_state))
 		trans_port_sync_vblank_on(state, crtc_state);
 	else
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 84e69f37deff..56734016cd19 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1114,6 +1114,7 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
 	drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && last_mst_stream &&
 		    !intel_dp_mst_is_master_trans(old_crtc_state));
 
+	/* timing generator stops after disabling TRANSCONF */
 	intel_crtc_vblank_off(state, old_crtc_state);
 
 	intel_disable_transcoder(old_crtc_state);
@@ -1391,6 +1392,7 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 
 	intel_enable_transcoder(pipe_config);
 
+	/* timing generator starts after enabling TRANSCONF */
 	intel_crtc_vblank_on(state, pipe_config);
 
 	intel_hdcp_enable(state, encoder, pipe_config, conn_state);
-- 
2.55.0

[PATCH 09/10] drm/i915: Fix FEC wait with port sync on pre-LNL

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On pre-LNL platforms FEC_DECODE_EN isn't transmitted until
the timing generator starts, which happens after TRANSCONF
has enabled and DP_TP_CTL link training is switched to
normal. With port sync enabled we always enable TRANSCONF
for all the synced transcoders first, but defer the DP_TP_CTL
switch until the primary transcoder (which is done last)
has finished its link training.

Defer the FEC status checks to the point where all the
synced timing generators have started, and thus FEC_DECODE_EN
has actually been sent on all the links.

On LNL+ FEC_DECODE_EN gets sent immediately when enabling
FEC in DP_TP_CTL, so it can stick to its way of checking for
FEC status immediately after enabling FEC. Looks like there
is still some kind of vestigial timing generator dependency
even on LNL+ as I can't seem  to re-transmit FEC_DECODE_EN
after both DP_TP_CTL has been switched to normal and
TRANSCONF has been enabled. But as long as we enable FEC
before enabling TRANSCONF (which we always do) FEC_DECODE_EN
is apparently sent immediately. Currently we actually double
check the FEC on LNL+ (once immediately on enabling FEC, and
a second time where we also check it on pre-LNL). But apart
for wasting a bit of time the second check is harmless.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 45 ++++++++++++++++++++++--
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e97e586bed72..4f335bbf7076 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2431,6 +2431,39 @@ int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
 	return 0;
 }
 
+static void trans_port_sync_wait_for_fec_status(struct intel_atomic_state *state,
+						struct intel_encoder *encoder,
+						const struct intel_crtc_state *crtc_state,
+						bool enabled)
+{
+	const struct drm_connector_state *conn_state;
+	struct drm_connector *conn;
+	int i;
+
+	if (!crtc_state->sync_mode_slaves_mask)
+		return;
+
+	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+		struct intel_encoder *slave_encoder =
+			to_intel_encoder(conn_state->best_encoder);
+		struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
+		const struct intel_crtc_state *slave_crtc_state;
+
+		if (!slave_crtc)
+			continue;
+
+		slave_crtc_state =
+			intel_atomic_get_new_crtc_state(state, slave_crtc);
+
+		if (slave_crtc_state->master_transcoder != crtc_state->cpu_transcoder)
+			continue;
+
+		intel_ddi_wait_for_fec_status(slave_encoder, slave_crtc_state, enabled);
+	}
+
+	intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled);
+}
+
 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state)
 {
@@ -3595,8 +3628,6 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 
 	intel_enable_transcoder(crtc_state);
 
-	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
-
 	if (is_hdmi)
 		intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);
 	else
@@ -3623,6 +3654,16 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 	else
 		intel_crtc_vblank_on(state, crtc_state);
 
+	/*
+	 * On pre-LNL FEC_DECODE_EN will only be sent when the timing
+	 * generator starts. Also note that FEC_DECODE_EN cannot be
+	 * re-sent without restarting the timing generator.
+	 */
+	if (is_trans_port_sync_mode(crtc_state))
+		trans_port_sync_wait_for_fec_status(state, encoder, crtc_state, true);
+	else
+		intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
+
 	intel_hdcp_enable(state, encoder, crtc_state, conn_state);
 }
 
-- 
2.55.0

[PATCH 10/10] drm/i915: Allow joiner with port sync

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Ever since the overhaul to use
for_each_pipe_crtc_modeset_{enable,disable)()/etc
joiner no longer interferes with the transcoder
based order imposed in skl_commit_modeset_enables()
and intel_commit_modeset_disables(). Thus we can
now allow joiner to be used in conjunction with
port sync.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4f335bbf7076..faddb69d4403 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4675,14 +4675,8 @@ static bool m_n_equal(const struct intel_link_m_n *m_n_1,
 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
 				       const struct intel_crtc_state *crtc_state2)
 {
-	/*
-	 * FIXME the modeset sequence is currently wrong and
-	 * can't deal with joiner + port sync at the same time.
-	 *
-	 * TODO VRR + port sync needs special handling
-	 */
+	/* TODO VRR + port sync needs special handling */
 	return crtc_state1->hw.active && crtc_state2->hw.active &&
-		!crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes &&
 		!crtc_state1->vrr.enable && !crtc_state2->vrr.enable &&
 		crtc_state1->output_types == crtc_state2->output_types &&
 		crtc_state1->output_format == crtc_state2->output_format &&
-- 
2.55.0

✗ CI.checkpatch: warning for drm/i915: Enable vblanks after the timing generator has started

[Patchwork]

== Series Details ==

Series: drm/i915: Enable vblanks after the timing generator has started
URL   : https://patchwork.freedesktop.org/series/177276/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
3009867cd31863246e4afc138520a7a8bd37bb11
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit d31616db6c784efd0e452167789a1321b0b6611c
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Fri Oct 30 19:13:26 2026 +0200

    drm/i915: Allow joiner with port sync
    
    Ever since the overhaul to use
    for_each_pipe_crtc_modeset_{enable,disable)()/etc
    joiner no longer interferes with the transcoder
    based order imposed in skl_commit_modeset_enables()
    and intel_commit_modeset_disables(). Thus we can
    now allow joiner to be used in conjunction with
    port sync.
    
    Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ /mt/dim checkpatch 238c1e3e984e2b7f948cb24165314b8d719a23d6 drm-intel
79db06dd3082 drm/i915: Disable port sync if VRR is enabled
-:40: WARNING:MISSING_FIXES_TAG: The commit message has 'stable@', perhaps it also needs a 'Fixes:' tag?

total: 0 errors, 1 warnings, 0 checks, 12 lines checked
ee1f94c183f5 drm/i915: Do intel_crtc_vblank_on() later on HSW+
cd1c69dc29ba drm/i915: Handle joined pipes inside intel_crtc_vblank_{on, off}()
b37fbffd9179 Revert "drm/i915/display: Avoid stale PIPE_SCANLINE values after crtc_enable"
500668b4cbab drm/i915: Fix intel_crtc_vblank_on() with port sync
4a594a5ce23a drm/i915: Wait for timing generator to start in intel_crtc_vblank_on() on HSW+
25f18502452c drm/i915: Reduce the sleep inside pipe_scanline_is_moving()
1cf7dbfe21bc drm/i915: Document timing generator start/stop behaviour on HSW+
2ab175d615be drm/i915: Fix FEC wait with port sync on pre-LNL
d31616db6c78 drm/i915: Allow joiner with port sync

✓ CI.KUnit: success for drm/i915: Enable vblanks after the timing generator has started

[Patchwork]

== Series Details ==

Series: drm/i915: Enable vblanks after the timing generator has started
URL   : https://patchwork.freedesktop.org/series/177276/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[17:20:56] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:21:01] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:21:21] Starting KUnit Kernel (1/1)...
[17:21:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:21:22] ================= gpu_buddy (14 subtests) ==================
[17:21:22] [PASSED] gpu_test_buddy_alloc_limit
[17:21:22] [PASSED] gpu_test_buddy_alloc_optimistic
[17:21:22] [PASSED] gpu_test_buddy_alloc_pessimistic
[17:21:22] [PASSED] gpu_test_buddy_alloc_pathological
[17:21:22] [PASSED] gpu_test_buddy_alloc_contiguous
[17:21:22] [PASSED] gpu_test_buddy_alloc_clear
[17:21:22] [PASSED] gpu_test_buddy_alloc_range
[17:21:22] [PASSED] gpu_test_buddy_alloc_range_bias
[17:21:23] [PASSED] gpu_test_buddy_fragmentation_performance
[17:21:23] [PASSED] gpu_test_buddy_dirty_tracker_performance
[17:21:23] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[17:21:23] [PASSED] gpu_test_buddy_offset_aligned_allocation
[17:21:23] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[17:21:23] [PASSED] gpu_test_buddy_addr_to_block
[17:21:23] ==================== [PASSED] gpu_buddy ====================
[17:21:23] ============================================================
[17:21:23] Testing complete. Ran 14 tests: passed: 14
[17:21:23] Elapsed time: 27.131s total, 4.426s configuring, 20.738s building, 1.893s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:21:24] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:21:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:22:05] Starting KUnit Kernel (1/1)...
[17:22:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:22:05] ================== guc_buf (11 subtests) ===================
[17:22:05] [PASSED] test_smallest
[17:22:05] [PASSED] test_largest
[17:22:05] [PASSED] test_granular
[17:22:05] [PASSED] test_unique
[17:22:05] [PASSED] test_overlap
[17:22:05] [PASSED] test_reusable
[17:22:05] [PASSED] test_too_big
[17:22:05] [PASSED] test_flush
[17:22:05] [PASSED] test_lookup
[17:22:05] [PASSED] test_data
[17:22:05] [PASSED] test_class
[17:22:05] ===================== [PASSED] guc_buf =====================
[17:22:05] =================== guc_dbm (7 subtests) ===================
[17:22:05] [PASSED] test_empty
[17:22:05] [PASSED] test_default
[17:22:05] ======================== test_size  ========================
[17:22:05] [PASSED] 4
[17:22:05] [PASSED] 8
[17:22:05] [PASSED] 32
[17:22:05] [PASSED] 256
[17:22:05] ==================== [PASSED] test_size ====================
[17:22:05] ======================= test_reuse  ========================
[17:22:05] [PASSED] 4
[17:22:05] [PASSED] 8
[17:22:05] [PASSED] 32
[17:22:05] [PASSED] 256
[17:22:05] =================== [PASSED] test_reuse ====================
[17:22:05] =================== test_range_overlap  ====================
[17:22:05] [PASSED] 4
[17:22:05] [PASSED] 8
[17:22:05] [PASSED] 32
[17:22:05] [PASSED] 256
[17:22:05] =============== [PASSED] test_range_overlap ================
[17:22:05] =================== test_range_compact  ====================
[17:22:05] [PASSED] 4
[17:22:05] [PASSED] 8
[17:22:05] [PASSED] 32
[17:22:05] [PASSED] 256
[17:22:05] =============== [PASSED] test_range_compact ================
[17:22:05] ==================== test_range_spare  =====================
[17:22:05] [PASSED] 4
[17:22:05] [PASSED] 8
[17:22:05] [PASSED] 32
[17:22:05] [PASSED] 256
[17:22:05] ================ [PASSED] test_range_spare =================
[17:22:05] ===================== [PASSED] guc_dbm =====================
[17:22:05] ================== guc_idm (22 subtests) ===================
[17:22:05] [PASSED] bad_init
[17:22:05] [PASSED] no_init
[17:22:05] [PASSED] init_fini
[17:22:05] [PASSED] check_init_small
[17:22:05] [PASSED] check_init_shared
[17:22:05] [PASSED] check_used
[17:22:05] [PASSED] check_quota
[17:22:05] [PASSED] check_all
[17:22:05] [PASSED] check_limits
[17:22:05] [PASSED] check_overlap
[17:22:05] [PASSED] check_overlap_alloc
[17:22:05] [PASSED] check_overlap_release
[17:22:05] [PASSED] check_overlap_partial_init
[17:22:05] [PASSED] check_overlap_partial_shared_range_blocking
[17:22:05] [PASSED] check_used_usable
[17:22:05] [PASSED] check_used_shareable
[17:22:05] [PASSED] check_used_mixed
[17:22:05] [PASSED] check_release_usable_range
[17:22:05] [PASSED] check_release_shareable_range
[17:22:05] [PASSED] check_split_boundaries
[17:22:05] [PASSED] check_shareable_spare
[17:22:05] [PASSED] check_shareable_spare_fragmented_tail
[17:22:05] ===================== [PASSED] guc_idm =====================
[17:22:05] ============== guc_klv_helpers (13 subtests) ===============
[17:22:05] [PASSED] test_count
[17:22:05] [PASSED] test_encode_u32
[17:22:05] [PASSED] test_encode_u64
[17:22:05] [PASSED] test_encode_string
[17:22:05] [PASSED] test_encode_object_raw
[17:22:05] [PASSED] test_encode_object_klv
[17:22:05] [PASSED] test_encode_object_nested
[17:22:05] [PASSED] test_encode_object_basic
[17:22:05] ===================== test_decode_u16  =====================
[17:22:05] [PASSED] empty
[17:22:05] [PASSED] valid
[17:22:05] [PASSED] max
[17:22:05] [PASSED] big
[17:22:05] [PASSED] long
[17:22:05] ================= [PASSED] test_decode_u16 =================
[17:22:05] ===================== test_decode_u32  =====================
[17:22:05] [PASSED] empty
[17:22:05] [PASSED] valid
[17:22:05] [PASSED] max
[17:22:05] [PASSED] long
[17:22:05] ================= [PASSED] test_decode_u32 =================
[17:22:05] ===================== test_decode_u64  =====================
[17:22:05] [PASSED] empty
[17:22:05] [PASSED] short
[17:22:05] [PASSED] valid
[17:22:05] [PASSED] max
[17:22:05] [PASSED] long
[17:22:05] ================= [PASSED] test_decode_u64 =================
[17:22:05] ===================== test_decode_str  =====================
[17:22:05] [PASSED] empty
[17:22:05] [PASSED] one
[17:22:05] [PASSED] one_trash
[17:22:05] [PASSED] two
[17:22:05] [PASSED] two_trash
[17:22:05] [PASSED] three
[17:22:05] [PASSED] dword
[17:22:05] [PASSED] four
[17:22:05] [PASSED] five
[17:22:05] [PASSED] six
[17:22:05] [PASSED] seven
[17:22:05] [PASSED] qword
[17:22:05] ================= [PASSED] test_decode_str =================
[17:22:05] [PASSED] test_print
[17:22:05] ================= [PASSED] guc_klv_helpers =================
[17:22:05] =================== xe_log (4 subtests) ====================
[17:22:05] [PASSED] demo_cper
[17:22:05] [PASSED] demo_dmesg
[17:22:05] ======================= test_dmesg  ========================
[17:22:05] [PASSED] test_fatal
[17:22:05] [PASSED] test_fatal_tile
[17:22:05] [PASSED] test_fatal_gt
[17:22:05] [PASSED] test_fatal_comp
[17:22:05] [PASSED] test_fatal_comp_tile
[17:22:05] [PASSED] test_fatal_comp_gt
[17:22:05] [PASSED] test_fatal_all
[17:22:05] [PASSED] test_recoverable
[17:22:05] [PASSED] test_recoverable_tile
[17:22:05] [PASSED] test_recoverable_gt
[17:22:05] [PASSED] test_recoverable_comp
[17:22:05] [PASSED] test_recoverable_comp_tile
[17:22:05] [PASSED] test_recoverable_comp_gt
[17:22:05] [PASSED] test_recoverable_all
[17:22:05] [PASSED] test_info
[17:22:05] [PASSED] test_info_tile
[17:22:05] [PASSED] test_info_gt
[17:22:05] [PASSED] test_info_err
[17:22:05] [PASSED] test_info_comp
[17:22:05] [PASSED] test_info_comp_tile
[17:22:05] [PASSED] test_info_comp_gt
[17:22:05] [PASSED] test_info_all
[17:22:05] [PASSED] test_hw_fatal
[17:22:05] [PASSED] test_hw_recoverable
[17:22:05] [PASSED] test_hw_corrected
[17:22:05] [PASSED] test_hw_informational
[17:22:05] =================== [PASSED] test_dmesg ====================
[17:22:05] ====================== test_invalid  =======================
[17:22:05] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[17:22:05] ================== [SKIPPED] test_invalid ==================
[17:22:05] ===================== [PASSED] xe_log ======================
[17:22:05] ================== no_relay (3 subtests) ===================
[17:22:05] [PASSED] xe_drops_guc2pf_if_not_ready
[17:22:05] [PASSED] xe_drops_guc2vf_if_not_ready
[17:22:05] [PASSED] xe_rejects_send_if_not_ready
[17:22:05] ==================== [PASSED] no_relay =====================
[17:22:05] ================== pf_relay (14 subtests) ==================
[17:22:05] [PASSED] pf_rejects_guc2pf_too_short
[17:22:05] [PASSED] pf_rejects_guc2pf_too_long
[17:22:05] [PASSED] pf_rejects_guc2pf_no_payload
[17:22:05] [PASSED] pf_fails_no_payload
[17:22:05] [PASSED] pf_fails_bad_origin
[17:22:05] [PASSED] pf_fails_bad_type
[17:22:05] [PASSED] pf_txn_reports_error
[17:22:05] [PASSED] pf_txn_sends_pf2guc
[17:22:05] [PASSED] pf_sends_pf2guc
[17:22:05] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:22:05] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:22:05] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:22:05] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:22:05] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:22:05] ==================== [PASSED] pf_relay =====================
[17:22:05] ================== vf_relay (3 subtests) ===================
[17:22:05] [PASSED] vf_rejects_guc2vf_too_short
[17:22:05] [PASSED] vf_rejects_guc2vf_too_long
[17:22:05] [PASSED] vf_rejects_guc2vf_no_payload
[17:22:05] ==================== [PASSED] vf_relay =====================
[17:22:05] ================ pf_gt_config (9 subtests) =================
[17:22:05] [PASSED] fair_contexts_1vf
[17:22:05] [PASSED] fair_doorbells_1vf
[17:22:05] [PASSED] fair_ggtt_1vf
[17:22:05] ====================== fair_vram_1vf  ======================
[17:22:05] [PASSED] 3.50 GiB
[17:22:05] [PASSED] 11.5 GiB
[17:22:05] [PASSED] 15.5 GiB
[17:22:05] [PASSED] 31.5 GiB
[17:22:05] [PASSED] 63.5 GiB
[17:22:05] [PASSED] 1.91 GiB
[17:22:05] ================== [PASSED] fair_vram_1vf ==================
[17:22:05] ================ fair_vram_1vf_admin_only  =================
[17:22:05] [PASSED] 3.50 GiB
[17:22:05] [PASSED] 11.5 GiB
[17:22:05] [PASSED] 15.5 GiB
[17:22:05] [PASSED] 31.5 GiB
[17:22:05] [PASSED] 63.5 GiB
[17:22:05] [PASSED] 1.91 GiB
[17:22:05] ============ [PASSED] fair_vram_1vf_admin_only =============
[17:22:05] ====================== fair_contexts  ======================
[17:22:05] [PASSED] 1 VF
[17:22:05] [PASSED] 2 VFs
[17:22:05] [PASSED] 3 VFs
[17:22:05] [PASSED] 4 VFs
[17:22:05] [PASSED] 5 VFs
[17:22:05] [PASSED] 6 VFs
[17:22:05] [PASSED] 7 VFs
[17:22:05] [PASSED] 8 VFs
[17:22:05] [PASSED] 9 VFs
[17:22:05] [PASSED] 10 VFs
[17:22:05] [PASSED] 11 VFs
[17:22:05] [PASSED] 12 VFs
[17:22:05] [PASSED] 13 VFs
[17:22:05] [PASSED] 14 VFs
[17:22:05] [PASSED] 15 VFs
[17:22:05] [PASSED] 16 VFs
[17:22:05] [PASSED] 17 VFs
[17:22:05] [PASSED] 18 VFs
[17:22:05] [PASSED] 19 VFs
[17:22:05] [PASSED] 20 VFs
[17:22:05] [PASSED] 21 VFs
[17:22:05] [PASSED] 22 VFs
[17:22:05] [PASSED] 23 VFs
[17:22:05] [PASSED] 24 VFs
[17:22:05] [PASSED] 25 VFs
[17:22:05] [PASSED] 26 VFs
[17:22:05] [PASSED] 27 VFs
[17:22:05] [PASSED] 28 VFs
[17:22:05] [PASSED] 29 VFs
[17:22:05] [PASSED] 30 VFs
[17:22:05] [PASSED] 31 VFs
[17:22:05] [PASSED] 32 VFs
[17:22:05] [PASSED] 33 VFs
[17:22:05] [PASSED] 34 VFs
[17:22:05] [PASSED] 35 VFs
[17:22:05] [PASSED] 36 VFs
[17:22:05] [PASSED] 37 VFs
[17:22:05] [PASSED] 38 VFs
[17:22:05] [PASSED] 39 VFs
[17:22:05] [PASSED] 40 VFs
[17:22:05] [PASSED] 41 VFs
[17:22:05] [PASSED] 42 VFs
[17:22:05] [PASSED] 43 VFs
[17:22:05] [PASSED] 44 VFs
[17:22:05] [PASSED] 45 VFs
[17:22:05] [PASSED] 46 VFs
[17:22:05] [PASSED] 47 VFs
[17:22:05] [PASSED] 48 VFs
[17:22:05] [PASSED] 49 VFs
[17:22:05] [PASSED] 50 VFs
[17:22:05] [PASSED] 51 VFs
[17:22:05] [PASSED] 52 VFs
[17:22:05] [PASSED] 53 VFs
[17:22:05] [PASSED] 54 VFs
[17:22:05] [PASSED] 55 VFs
[17:22:05] [PASSED] 56 VFs
[17:22:05] [PASSED] 57 VFs
[17:22:05] [PASSED] 58 VFs
[17:22:05] [PASSED] 59 VFs
[17:22:05] [PASSED] 60 VFs
[17:22:05] [PASSED] 61 VFs
[17:22:05] [PASSED] 62 VFs
[17:22:05] [PASSED] 63 VFs
[17:22:05] ================== [PASSED] fair_contexts ==================
[17:22:05] ===================== fair_doorbells  ======================
[17:22:05] [PASSED] 1 VF
[17:22:05] [PASSED] 2 VFs
[17:22:05] [PASSED] 3 VFs
[17:22:05] [PASSED] 4 VFs
[17:22:05] [PASSED] 5 VFs
[17:22:05] [PASSED] 6 VFs
[17:22:05] [PASSED] 7 VFs
[17:22:05] [PASSED] 8 VFs
[17:22:05] [PASSED] 9 VFs
[17:22:05] [PASSED] 10 VFs
[17:22:05] [PASSED] 11 VFs
[17:22:05] [PASSED] 12 VFs
[17:22:05] [PASSED] 13 VFs
[17:22:05] [PASSED] 14 VFs
[17:22:05] [PASSED] 15 VFs
[17:22:05] [PASSED] 16 VFs
[17:22:05] [PASSED] 17 VFs
[17:22:05] [PASSED] 18 VFs
[17:22:05] [PASSED] 19 VFs
[17:22:05] [PASSED] 20 VFs
[17:22:05] [PASSED] 21 VFs
[17:22:05] [PASSED] 22 VFs
[17:22:05] [PASSED] 23 VFs
[17:22:05] [PASSED] 24 VFs
[17:22:05] [PASSED] 25 VFs
[17:22:05] [PASSED] 26 VFs
[17:22:05] [PASSED] 27 VFs
[17:22:05] [PASSED] 28 VFs
[17:22:05] [PASSED] 29 VFs
[17:22:05] [PASSED] 30 VFs
[17:22:05] [PASSED] 31 VFs
[17:22:05] [PASSED] 32 VFs
[17:22:05] [PASSED] 33 VFs
[17:22:05] [PASSED] 34 VFs
[17:22:05] [PASSED] 35 VFs
[17:22:05] [PASSED] 36 VFs
[17:22:05] [PASSED] 37 VFs
[17:22:05] [PASSED] 38 VFs
[17:22:05] [PASSED] 39 VFs
[17:22:05] [PASSED] 40 VFs
[17:22:05] [PASSED] 41 VFs
[17:22:05] [PASSED] 42 VFs
[17:22:05] [PASSED] 43 VFs
[17:22:05] [PASSED] 44 VFs
[17:22:05] [PASSED] 45 VFs
[17:22:05] [PASSED] 46 VFs
[17:22:05] [PASSED] 47 VFs
[17:22:05] [PASSED] 48 VFs
[17:22:05] [PASSED] 49 VFs
[17:22:05] [PASSED] 50 VFs
[17:22:05] [PASSED] 51 VFs
[17:22:05] [PASSED] 52 VFs
[17:22:05] [PASSED] 53 VFs
[17:22:05] [PASSED] 54 VFs
[17:22:05] [PASSED] 55 VFs
[17:22:05] [PASSED] 56 VFs
[17:22:05] [PASSED] 57 VFs
[17:22:05] [PASSED] 58 VFs
[17:22:05] [PASSED] 59 VFs
[17:22:05] [PASSED] 60 VFs
[17:22:05] [PASSED] 61 VFs
[17:22:05] [PASSED] 62 VFs
[17:22:05] [PASSED] 63 VFs
[17:22:05] ================= [PASSED] fair_doorbells ==================
[17:22:05] ======================== fair_ggtt  ========================
[17:22:05] [PASSED] 1 VF
[17:22:05] [PASSED] 2 VFs
[17:22:05] [PASSED] 3 VFs
[17:22:05] [PASSED] 4 VFs
[17:22:05] [PASSED] 5 VFs
[17:22:05] [PASSED] 6 VFs
[17:22:05] [PASSED] 7 VFs
[17:22:05] [PASSED] 8 VFs
[17:22:05] [PASSED] 9 VFs
[17:22:05] [PASSED] 10 VFs
[17:22:05] [PASSED] 11 VFs
[17:22:05] [PASSED] 12 VFs
[17:22:05] [PASSED] 13 VFs
[17:22:05] [PASSED] 14 VFs
[17:22:05] [PASSED] 15 VFs
[17:22:05] [PASSED] 16 VFs
[17:22:05] [PASSED] 17 VFs
[17:22:05] [PASSED] 18 VFs
[17:22:05] [PASSED] 19 VFs
[17:22:05] [PASSED] 20 VFs
[17:22:05] [PASSED] 21 VFs
[17:22:05] [PASSED] 22 VFs
[17:22:05] [PASSED] 23 VFs
[17:22:05] [PASSED] 24 VFs
[17:22:05] [PASSED] 25 VFs
[17:22:05] [PASSED] 26 VFs
[17:22:05] [PASSED] 27 VFs
[17:22:05] [PASSED] 28 VFs
[17:22:05] [PASSED] 29 VFs
[17:22:05] [PASSED] 30 VFs
[17:22:05] [PASSED] 31 VFs
[17:22:05] [PASSED] 32 VFs
[17:22:05] [PASSED] 33 VFs
[17:22:05] [PASSED] 34 VFs
[17:22:05] [PASSED] 35 VFs
[17:22:05] [PASSED] 36 VFs
[17:22:05] [PASSED] 37 VFs
[17:22:05] [PASSED] 38 VFs
[17:22:05] [PASSED] 39 VFs
[17:22:05] [PASSED] 40 VFs
[17:22:05] [PASSED] 41 VFs
[17:22:05] [PASSED] 42 VFs
[17:22:05] [PASSED] 43 VFs
[17:22:05] [PASSED] 44 VFs
[17:22:05] [PASSED] 45 VFs
[17:22:05] [PASSED] 46 VFs
[17:22:05] [PASSED] 47 VFs
[17:22:05] [PASSED] 48 VFs
[17:22:05] [PASSED] 49 VFs
[17:22:05] [PASSED] 50 VFs
[17:22:05] [PASSED] 51 VFs
[17:22:05] [PASSED] 52 VFs
[17:22:05] [PASSED] 53 VFs
[17:22:05] [PASSED] 54 VFs
[17:22:05] [PASSED] 55 VFs
[17:22:05] [PASSED] 56 VFs
[17:22:05] [PASSED] 57 VFs
[17:22:05] [PASSED] 58 VFs
[17:22:05] [PASSED] 59 VFs
[17:22:05] [PASSED] 60 VFs
[17:22:05] [PASSED] 61 VFs
[17:22:05] [PASSED] 62 VFs
[17:22:05] [PASSED] 63 VFs
[17:22:05] ==================== [PASSED] fair_ggtt ====================
[17:22:05] ======================== fair_vram  ========================
[17:22:05] [PASSED] 1 VF
[17:22:05] [PASSED] 2 VFs
[17:22:05] [PASSED] 3 VFs
[17:22:05] [PASSED] 4 VFs
[17:22:05] [PASSED] 5 VFs
[17:22:05] [PASSED] 6 VFs
[17:22:05] [PASSED] 7 VFs
[17:22:05] [PASSED] 8 VFs
[17:22:05] [PASSED] 9 VFs
[17:22:05] [PASSED] 10 VFs
[17:22:05] [PASSED] 11 VFs
[17:22:05] [PASSED] 12 VFs
[17:22:05] [PASSED] 13 VFs
[17:22:05] [PASSED] 14 VFs
[17:22:05] [PASSED] 15 VFs
[17:22:05] [PASSED] 16 VFs
[17:22:05] [PASSED] 17 VFs
[17:22:05] [PASSED] 18 VFs
[17:22:05] [PASSED] 19 VFs
[17:22:05] [PASSED] 20 VFs
[17:22:05] [PASSED] 21 VFs
[17:22:05] [PASSED] 22 VFs
[17:22:05] [PASSED] 23 VFs
[17:22:05] [PASSED] 24 VFs
[17:22:05] [PASSED] 25 VFs
[17:22:05] [PASSED] 26 VFs
[17:22:05] [PASSED] 27 VFs
[17:22:05] [PASSED] 28 VFs
[17:22:05] [PASSED] 29 VFs
[17:22:05] [PASSED] 30 VFs
[17:22:05] [PASSED] 31 VFs
[17:22:05] [PASSED] 32 VFs
[17:22:05] [PASSED] 33 VFs
[17:22:05] [PASSED] 34 VFs
[17:22:05] [PASSED] 35 VFs
[17:22:05] [PASSED] 36 VFs
[17:22:05] [PASSED] 37 VFs
[17:22:05] [PASSED] 38 VFs
[17:22:05] [PASSED] 39 VFs
[17:22:05] [PASSED] 40 VFs
[17:22:05] [PASSED] 41 VFs
[17:22:05] [PASSED] 42 VFs
[17:22:05] [PASSED] 43 VFs
[17:22:05] [PASSED] 44 VFs
[17:22:05] [PASSED] 45 VFs
[17:22:05] [PASSED] 46 VFs
[17:22:05] [PASSED] 47 VFs
[17:22:05] [PASSED] 48 VFs
[17:22:05] [PASSED] 49 VFs
[17:22:05] [PASSED] 50 VFs
[17:22:05] [PASSED] 51 VFs
[17:22:05] [PASSED] 52 VFs
[17:22:05] [PASSED] 53 VFs
[17:22:05] [PASSED] 54 VFs
[17:22:05] [PASSED] 55 VFs
[17:22:05] [PASSED] 56 VFs
[17:22:05] [PASSED] 57 VFs
[17:22:05] [PASSED] 58 VFs
[17:22:05] [PASSED] 59 VFs
[17:22:05] [PASSED] 60 VFs
[17:22:05] [PASSED] 61 VFs
[17:22:05] [PASSED] 62 VFs
[17:22:05] [PASSED] 63 VFs
[17:22:05] ==================== [PASSED] fair_vram ====================
[17:22:05] ================== [PASSED] pf_gt_config ===================
[17:22:05] ===================== lmtt (1 subtest) =====================
[17:22:05] ======================== test_ops  =========================
[17:22:05] [PASSED] 2-level
[17:22:05] [PASSED] multi-level
[17:22:05] ==================== [PASSED] test_ops =====================
[17:22:05] ====================== [PASSED] lmtt =======================
[17:22:05] ================= sriov_packet (1 subtest) =================
[17:22:05] [PASSED] test_descriptor_init
[17:22:05] ================== [PASSED] sriov_packet ===================
[17:22:05] ================= pf_service (11 subtests) =================
[17:22:05] [PASSED] pf_negotiate_any
[17:22:05] [PASSED] pf_negotiate_base_match
[17:22:05] [PASSED] pf_negotiate_base_newer
[17:22:05] [PASSED] pf_negotiate_base_next
[17:22:05] [SKIPPED] pf_negotiate_base_older (no older minor)
[17:22:05] [PASSED] pf_negotiate_base_prev
[17:22:05] [PASSED] pf_negotiate_latest_match
[17:22:05] [PASSED] pf_negotiate_latest_newer
[17:22:05] [PASSED] pf_negotiate_latest_next
[17:22:05] [SKIPPED] pf_negotiate_latest_older (no older minor)
[17:22:05] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[17:22:05] =================== [PASSED] pf_service ====================
[17:22:05] ================= xe_guc_g2g (2 subtests) ==================
[17:22:05] ============== xe_live_guc_g2g_kunit_default  ==============
[17:22:05] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:22:05] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:22:05] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:22:05] =================== [SKIPPED] xe_guc_g2g ===================
[17:22:05] =================== xe_mocs (2 subtests) ===================
[17:22:05] ================ xe_live_mocs_kernel_kunit  ================
[17:22:05] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:22:05] ================ xe_live_mocs_reset_kunit  =================
[17:22:05] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:22:05] ==================== [SKIPPED] xe_mocs =====================
[17:22:05] ================= xe_migrate (3 subtests) ==================
[17:22:05] ================= xe_migrate_sanity_kunit  =================
[17:22:05] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:22:05] ================== xe_validate_ccs_kunit  ==================
[17:22:05] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:22:05] ============= xe_migrate_access_memory_kunit  ==============
[17:22:05] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[17:22:05] =================== [SKIPPED] xe_migrate ===================
[17:22:05] ================== xe_dma_buf (1 subtest) ==================
[17:22:05] ==================== xe_dma_buf_kunit  =====================
[17:22:05] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:22:05] =================== [SKIPPED] xe_dma_buf ===================
[17:22:05] ================= xe_bo_shrink (1 subtest) =================
[17:22:05] =================== xe_bo_shrink_kunit  ====================
[17:22:05] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:22:05] ================== [SKIPPED] xe_bo_shrink ==================
[17:22:05] ==================== xe_bo (2 subtests) ====================
[17:22:05] ================== xe_ccs_migrate_kunit  ===================
[17:22:05] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:22:05] ==================== xe_bo_evict_kunit  ====================
[17:22:05] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:22:05] ===================== [SKIPPED] xe_bo ======================
[17:22:05] =================== xe_any (9 subtests) ====================
[17:22:05] [PASSED] test_to_xe
[17:22:05] [PASSED] test_to_dev
[17:22:05] [PASSED] test_to_pdev
[17:22:05] [PASSED] test_to_drm
[17:22:05] [PASSED] test_if_pdev
[17:22:05] [PASSED] test_if_xe
[17:22:05] [PASSED] test_if_tile
[17:22:05] [PASSED] test_if_gt
[17:22:05] [PASSED] test_to_id
[17:22:05] ===================== [PASSED] xe_any ======================
[17:22:05] ==================== args (13 subtests) ====================
[17:22:05] [PASSED] count_args_test
[17:22:05] [PASSED] call_args_example
[17:22:05] [PASSED] call_args_test
[17:22:05] [PASSED] drop_first_arg_example
[17:22:05] [PASSED] drop_first_arg_test
[17:22:05] [PASSED] first_arg_example
[17:22:05] [PASSED] first_arg_test
[17:22:05] [PASSED] last_arg_example
[17:22:05] [PASSED] last_arg_test
[17:22:05] [PASSED] pick_arg_example
[17:22:05] [PASSED] if_args_example
[17:22:05] [PASSED] if_args_test
[17:22:05] [PASSED] sep_comma_example
[17:22:05] ====================== [PASSED] args =======================
[17:22:05] =================== xe_pci (3 subtests) ====================
[17:22:05] ==================== check_graphics_ip  ====================
[17:22:05] [PASSED] 12.00 Xe_LP
[17:22:05] [PASSED] 12.10 Xe_LP+
[17:22:05] [PASSED] 12.55 Xe_HPG
[17:22:05] [PASSED] 12.60 Xe_HPC
[17:22:05] [PASSED] 12.70 Xe_LPG
[17:22:05] [PASSED] 12.71 Xe_LPG
[17:22:05] [PASSED] 12.74 Xe_LPG+
[17:22:05] [PASSED] 20.01 Xe2_HPG
[17:22:05] [PASSED] 20.02 Xe2_HPG
[17:22:05] [PASSED] 20.04 Xe2_LPG
[17:22:05] [PASSED] 30.00 Xe3_LPG
[17:22:05] [PASSED] 30.01 Xe3_LPG
[17:22:05] [PASSED] 30.03 Xe3_LPG
[17:22:05] [PASSED] 30.04 Xe3_LPG
[17:22:05] [PASSED] 30.05 Xe3_LPG
[17:22:05] [PASSED] 35.10 Xe3p_LPG
[17:22:05] [PASSED] 35.11 Xe3p_XPC
[17:22:05] ================ [PASSED] check_graphics_ip ================
[17:22:05] ===================== check_media_ip  ======================
[17:22:05] [PASSED] 12.00 Xe_M
[17:22:05] [PASSED] 12.55 Xe_HPM
[17:22:05] [PASSED] 13.00 Xe_LPM+
[17:22:05] [PASSED] 13.01 Xe2_HPM
[17:22:05] [PASSED] 20.00 Xe2_LPM
[17:22:05] [PASSED] 30.00 Xe3_LPM
[17:22:05] [PASSED] 30.02 Xe3_LPM
[17:22:05] [PASSED] 35.00 Xe3p_LPM
[17:22:05] [PASSED] 35.03 Xe3p_HPM
[17:22:05] ================= [PASSED] check_media_ip ==================
[17:22:05] =================== check_platform_desc  ===================
[17:22:05] [PASSED] 0x9A60 (TIGERLAKE)
[17:22:05] [PASSED] 0x9A68 (TIGERLAKE)
[17:22:05] [PASSED] 0x9A70 (TIGERLAKE)
[17:22:05] [PASSED] 0x9A40 (TIGERLAKE)
[17:22:05] [PASSED] 0x9A49 (TIGERLAKE)
[17:22:05] [PASSED] 0x9A59 (TIGERLAKE)
[17:22:05] [PASSED] 0x9A78 (TIGERLAKE)
[17:22:05] [PASSED] 0x9AC0 (TIGERLAKE)
[17:22:05] [PASSED] 0x9AC9 (TIGERLAKE)
[17:22:05] [PASSED] 0x9AD9 (TIGERLAKE)
[17:22:05] [PASSED] 0x9AF8 (TIGERLAKE)
[17:22:05] [PASSED] 0x4C80 (ROCKETLAKE)
[17:22:05] [PASSED] 0x4C8A (ROCKETLAKE)
[17:22:05] [PASSED] 0x4C8B (ROCKETLAKE)
[17:22:05] [PASSED] 0x4C8C (ROCKETLAKE)
[17:22:05] [PASSED] 0x4C90 (ROCKETLAKE)
[17:22:05] [PASSED] 0x4C9A (ROCKETLAKE)
[17:22:05] [PASSED] 0x4680 (ALDERLAKE_S)
[17:22:05] [PASSED] 0x4682 (ALDERLAKE_S)
[17:22:05] [PASSED] 0x4688 (ALDERLAKE_S)
[17:22:05] [PASSED] 0x468A (ALDERLAKE_S)
[17:22:05] [PASSED] 0x468B (ALDERLAKE_S)
[17:22:05] [PASSED] 0x4690 (ALDERLAKE_S)
[17:22:05] [PASSED] 0x4692 (ALDERLAKE_S)
[17:22:05] [PASSED] 0x4693 (ALDERLAKE_S)
[17:22:05] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46AA (ALDERLAKE_P)
[17:22:05] [PASSED] 0x462A (ALDERLAKE_P)
[17:22:05] [PASSED] 0x4626 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x4628 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:22:05] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:22:05] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:22:05] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:22:05] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:22:05] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:22:05] [PASSED] 0xA721 (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA720 (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:22:05] [PASSED] 0xA780 (ALDERLAKE_S)
[17:22:05] [PASSED] 0xA781 (ALDERLAKE_S)
[17:22:05] [PASSED] 0xA782 (ALDERLAKE_S)
[17:22:05] [PASSED] 0xA783 (ALDERLAKE_S)
[17:22:05] [PASSED] 0xA788 (ALDERLAKE_S)
[17:22:05] [PASSED] 0xA789 (ALDERLAKE_S)
[17:22:05] [PASSED] 0xA78A (ALDERLAKE_S)
[17:22:05] [PASSED] 0xA78B (ALDERLAKE_S)
[17:22:05] [PASSED] 0x4905 (DG1)
[17:22:05] [PASSED] 0x4906 (DG1)
[17:22:05] [PASSED] 0x4907 (DG1)
[17:22:05] [PASSED] 0x4908 (DG1)
[17:22:05] [PASSED] 0x4909 (DG1)
[17:22:05] [PASSED] 0x56C0 (DG2)
[17:22:05] [PASSED] 0x56C2 (DG2)
[17:22:05] [PASSED] 0x56C1 (DG2)
[17:22:05] [PASSED] 0x7D51 (METEORLAKE)
[17:22:05] [PASSED] 0x7DD1 (METEORLAKE)
[17:22:05] [PASSED] 0x7D41 (METEORLAKE)
[17:22:05] [PASSED] 0x7D67 (METEORLAKE)
[17:22:05] [PASSED] 0xB640 (METEORLAKE)
[17:22:05] [PASSED] 0x56A0 (DG2)
[17:22:05] [PASSED] 0x56A1 (DG2)
[17:22:05] [PASSED] 0x56A2 (DG2)
[17:22:05] [PASSED] 0x56BE (DG2)
[17:22:05] [PASSED] 0x56BF (DG2)
[17:22:05] [PASSED] 0x5690 (DG2)
[17:22:05] [PASSED] 0x5691 (DG2)
[17:22:05] [PASSED] 0x5692 (DG2)
[17:22:05] [PASSED] 0x56A5 (DG2)
[17:22:05] [PASSED] 0x56A6 (DG2)
[17:22:05] [PASSED] 0x56B0 (DG2)
[17:22:05] [PASSED] 0x56B1 (DG2)
[17:22:05] [PASSED] 0x56BA (DG2)
[17:22:05] [PASSED] 0x56BB (DG2)
[17:22:05] [PASSED] 0x56BC (DG2)
[17:22:05] [PASSED] 0x56BD (DG2)
[17:22:05] [PASSED] 0x5693 (DG2)
[17:22:05] [PASSED] 0x5694 (DG2)
[17:22:05] [PASSED] 0x5695 (DG2)
[17:22:05] [PASSED] 0x56A3 (DG2)
[17:22:05] [PASSED] 0x56A4 (DG2)
[17:22:05] [PASSED] 0x56B2 (DG2)
[17:22:05] [PASSED] 0x56B3 (DG2)
[17:22:05] [PASSED] 0x5696 (DG2)
[17:22:05] [PASSED] 0x5697 (DG2)
[17:22:05] [PASSED] 0xB69 (PVC)
[17:22:05] [PASSED] 0xB6E (PVC)
[17:22:05] [PASSED] 0xBD4 (PVC)
[17:22:05] [PASSED] 0xBD5 (PVC)
[17:22:05] [PASSED] 0xBD6 (PVC)
[17:22:05] [PASSED] 0xBD7 (PVC)
[17:22:05] [PASSED] 0xBD8 (PVC)
[17:22:05] [PASSED] 0xBD9 (PVC)
[17:22:05] [PASSED] 0xBDA (PVC)
[17:22:05] [PASSED] 0xBDB (PVC)
[17:22:05] [PASSED] 0xBE0 (PVC)
[17:22:05] [PASSED] 0xBE1 (PVC)
[17:22:05] [PASSED] 0xBE5 (PVC)
[17:22:05] [PASSED] 0x7D40 (METEORLAKE)
[17:22:05] [PASSED] 0x7D45 (METEORLAKE)
[17:22:05] [PASSED] 0x7D55 (METEORLAKE)
[17:22:05] [PASSED] 0x7D60 (METEORLAKE)
[17:22:05] [PASSED] 0x7DD5 (METEORLAKE)
[17:22:05] [PASSED] 0x6420 (LUNARLAKE)
[17:22:05] [PASSED] 0x64A0 (LUNARLAKE)
[17:22:05] [PASSED] 0x64B0 (LUNARLAKE)
[17:22:05] [PASSED] 0xE202 (BATTLEMAGE)
[17:22:05] [PASSED] 0xE209 (BATTLEMAGE)
[17:22:05] [PASSED] 0xE20B (BATTLEMAGE)
[17:22:05] [PASSED] 0xE20C (BATTLEMAGE)
[17:22:05] [PASSED] 0xE20D (BATTLEMAGE)
[17:22:05] [PASSED] 0xE210 (BATTLEMAGE)
[17:22:05] [PASSED] 0xE211 (BATTLEMAGE)
[17:22:05] [PASSED] 0xE212 (BATTLEMAGE)
[17:22:05] [PASSED] 0xE216 (BATTLEMAGE)
[17:22:05] [PASSED] 0xE220 (BATTLEMAGE)
[17:22:05] [PASSED] 0xE221 (BATTLEMAGE)
[17:22:05] [PASSED] 0xE222 (BATTLEMAGE)
[17:22:05] [PASSED] 0xE223 (BATTLEMAGE)
[17:22:05] [PASSED] 0xB080 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB081 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB082 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB083 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB084 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB085 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB086 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB087 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB08F (PANTHERLAKE)
[17:22:05] [PASSED] 0xB090 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB0A1 (PANTHERLAKE)
[17:22:05] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:22:05] [PASSED] 0xFD80 (PANTHERLAKE)
[17:22:05] [PASSED] 0xFD81 (PANTHERLAKE)
[17:22:05] [PASSED] 0xD740 (NOVALAKE_S)
[17:22:05] [PASSED] 0xD741 (NOVALAKE_S)
[17:22:05] [PASSED] 0xD742 (NOVALAKE_S)
[17:22:05] [PASSED] 0xD743 (NOVALAKE_S)
[17:22:05] [PASSED] 0xD745 (NOVALAKE_S)
[17:22:05] [PASSED] 0xD74A (NOVALAKE_S)
[17:22:05] [PASSED] 0xD74B (NOVALAKE_S)
[17:22:05] [PASSED] 0x674C (CRESCENTISLAND)
[17:22:05] [PASSED] 0x674D (CRESCENTISLAND)
[17:22:05] [PASSED] 0x674E (CRESCENTISLAND)
[17:22:05] [PASSED] 0x674F (CRESCENTISLAND)
[17:22:05] [PASSED] 0x6750 (CRESCENTISLAND)
[17:22:05] [PASSED] 0x6751 (CRESCENTISLAND)
[17:22:05] [PASSED] 0x6752 (CRESCENTISLAND)
[17:22:05] [PASSED] 0xD750 (NOVALAKE_P)
[17:22:05] [PASSED] 0xD751 (NOVALAKE_P)
[17:22:05] [PASSED] 0xD752 (NOVALAKE_P)
[17:22:05] [PASSED] 0xD753 (NOVALAKE_P)
[17:22:05] [PASSED] 0xD754 (NOVALAKE_P)
[17:22:05] [PASSED] 0xD755 (NOVALAKE_P)
[17:22:05] [PASSED] 0xD756 (NOVALAKE_P)
[17:22:05] [PASSED] 0xD757 (NOVALAKE_P)
[17:22:05] [PASSED] 0xD75F (NOVALAKE_P)
[17:22:05] =============== [PASSED] check_platform_desc ===============
[17:22:05] ===================== [PASSED] xe_pci ======================
[17:22:05] ============= xe_rtp_tables_test (5 subtests) ==============
[17:22:05] ================== xe_rtp_table_gt_test  ===================
[17:22:05] [PASSED] gt_was/14011060649
[17:22:05] [PASSED] gt_was/14011059788
[17:22:05] [PASSED] gt_was/14015795083
[17:22:05] [PASSED] gt_was/16021867713
[17:22:05] [PASSED] gt_was/14019449301
[17:22:05] [PASSED] gt_was/16028005424
[17:22:05] [PASSED] gt_was/14026578760
[17:22:05] [PASSED] gt_was/1409420604
[17:22:05] [PASSED] gt_was/1408615072
[17:22:05] [PASSED] gt_was/22010523718
[17:22:05] [PASSED] gt_was/14011006942
[17:22:05] [PASSED] gt_was/14014830051
[17:22:05] [PASSED] gt_was/18018781329
[17:22:05] [PASSED] gt_was/1509235366
[17:22:05] [PASSED] gt_was/18018781329
[17:22:05] [PASSED] gt_was/16016694945
[17:22:05] [PASSED] gt_was/14018575942
[17:22:05] [PASSED] gt_was/22016670082
[17:22:05] [PASSED] gt_was/22016670082
[17:22:05] [PASSED] gt_was/14017421178
[17:22:05] [PASSED] gt_was/16025250150
[17:22:05] [PASSED] gt_was/14021871409
[17:22:05] [PASSED] gt_was/16021865536
[17:22:05] [PASSED] gt_was/14021486841
[17:22:05] [PASSED] gt_was/14025160223
[17:22:05] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[17:22:05] [PASSED] gt_was/14025635424
[17:22:05] [PASSED] gt_was/16028005424
[17:22:05] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:22:05] ================== xe_rtp_table_gt_test  ===================
[17:22:05] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[17:22:05] [PASSED] gt_tunings/Tuning: 32B Access Enable
[17:22:05] [PASSED] gt_tunings/Tuning: L3 cache
[17:22:05] [PASSED] gt_tunings/Tuning: L3 cache - media
[17:22:05] [PASSED] gt_tunings/Tuning: Compression Overfetch
[17:22:05] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[17:22:05] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[17:22:05] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[17:22:05] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[17:22:05] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[17:22:05] [PASSED] gt_tunings/Tuning: Stateless compression control
[17:22:05] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[17:22:05] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[17:22:05] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[17:22:05] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[17:22:05] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[17:22:05] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:22:05] ================== xe_rtp_table_oob_test  ==================
[17:22:05] [PASSED] oob_was/1607983814
[17:22:05] [PASSED] oob_was/16010904313
[17:22:05] [PASSED] oob_was/18022495364
[17:22:05] [PASSED] oob_was/22012773006
[17:22:05] [PASSED] oob_was/14014475959
[17:22:05] [PASSED] oob_was/22011391025
[17:22:05] [PASSED] oob_was/22012727170
[17:22:05] [PASSED] oob_was/22012727685
[17:22:05] [PASSED] oob_was/22016596838
[17:22:05] [PASSED] oob_was/18020744125
[17:22:05] [PASSED] oob_was/1409600907
[17:22:05] [PASSED] oob_was/22014953428
[17:22:05] [PASSED] oob_was/16017236439
[17:22:05] [PASSED] oob_was/14019821291
[17:22:05] [PASSED] oob_was/14015076503
[17:22:05] [PASSED] oob_was/22016122933
[17:22:05] [PASSED] oob_was/14018913170
[17:22:05] [PASSED] oob_was/14018094691
[17:22:05] [PASSED] oob_was/18024947630
[17:22:05] [PASSED] oob_was/16022287689
[17:22:05] [PASSED] oob_was/13011645652
[17:22:05] [PASSED] oob_was/14022293748
[17:22:05] [PASSED] oob_was/22019794406
[17:22:05] [PASSED] oob_was/22019338487
[17:22:05] [PASSED] oob_was/16023588340
[17:22:05] [PASSED] oob_was/14019789679
[17:22:05] [PASSED] oob_was/14022866841
[17:22:05] [PASSED] oob_was/16021333562
[17:22:05] [PASSED] oob_was/14016712196
[17:22:05] [PASSED] oob_was/14015568240
[17:22:05] [PASSED] oob_was/18013179988
[17:22:05] [PASSED] oob_was/1508761755
[17:22:05] [PASSED] oob_was/16023105232
[17:22:05] [PASSED] oob_was/16026508708
[17:22:05] [PASSED] oob_was/14020001231
[17:22:05] [PASSED] oob_was/16023683509
[17:22:05] [PASSED] oob_was/14025515070
[17:22:05] [PASSED] oob_was/15015404425_disable
[17:22:05] [PASSED] oob_was/16026007364
[17:22:05] [PASSED] oob_was/14020316580
[17:22:05] [PASSED] oob_was/14025883347
[17:22:05] [PASSED] oob_was/16029380221
[17:22:05] [PASSED] oob_was/22022079272
[17:22:05] [PASSED] oob_was/16029897822
[17:22:05] [PASSED] oob_was/14026539277
[17:22:05] [PASSED] oob_was/14027054324
[17:22:05] [PASSED] oob_was/14025941587
[17:22:05] [PASSED] oob_was/16030224309
[17:22:05] ============== [PASSED] xe_rtp_table_oob_test ==============
[17:22:05] ================ xe_rtp_table_dev_oob_test  ================
[17:22:05] [PASSED] device_oob_was/22010954014
[17:22:05] [PASSED] device_oob_was/15015404425
[17:22:05] [PASSED] device_oob_was/22019338487_display
[17:22:05] [PASSED] device_oob_was/14022085890
[17:22:05] [PASSED] device_oob_was/14026633728
[17:22:05] [PASSED] device_oob_was/14026746987
[17:22:05] [PASSED] device_oob_was/14026779378
[17:22:05] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[17:22:05] ========== xe_rtp_table_missing_upper_bound_test  ==========
[17:22:05] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[17:22:05] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[17:22:05] [PASSED] register_whitelist/1806527549
[17:22:05] [PASSED] register_whitelist/allow_read_ctx_timestamp
[17:22:05] [PASSED] register_whitelist/allow_read_queue_timestamp
[17:22:05] [PASSED] register_whitelist/16014440446
[17:22:05] [PASSED] register_whitelist/16017236439
[17:22:05] [PASSED] register_whitelist/16020183090
[17:22:05] [PASSED] register_whitelist/14024997852
[17:22:05] [PASSED] register_whitelist/14024997852
[17:22:05] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[17:22:05] =============== [PASSED] xe_rtp_tables_test ================
[17:22:05] =================== xe_rtp (3 subtests) ====================
[17:22:05] =================== xe_rtp_rules_tests  ====================
[17:22:05] [PASSED] no
[17:22:05] [PASSED] yes
[17:22:05] [PASSED] no-and-no
[17:22:05] [PASSED] no-and-yes
[17:22:05] [PASSED] yes-and-no
[17:22:05] [PASSED] yes-and-yes
[17:22:05] [PASSED] no-or-no
[17:22:05] [PASSED] no-or-yes
[17:22:05] [PASSED] yes-or-no
[17:22:05] [PASSED] yes-or-yes
[17:22:05] [PASSED] no-yes-or-yes-no
[17:22:05] [PASSED] no-yes-or-yes-yes
[17:22:05] [PASSED] yes-yes-or-no-yes
[17:22:05] [PASSED] yes-yes-or-yes-yes
[17:22:05] [PASSED] no-no-or-yes-or-no
[17:22:05] [PASSED] or
[17:22:05] [PASSED] or-yes
[17:22:05] [PASSED] or-no
[17:22:05] [PASSED] yes-or
[17:22:05] [PASSED] no-or
[17:22:05] [PASSED] no-or-or-yes
[17:22:05] [PASSED] yes-or-or-no
[17:22:05] [PASSED] no-or-or-no
[17:22:05] [PASSED] missing-context-engine-class
[17:22:05] [PASSED] missing-context-engine-class-or-yes
[17:22:05] [PASSED] missing-context-engine-class-or-or-yes
[17:22:05] =============== [PASSED] xe_rtp_rules_tests ================
[17:22:05] =============== xe_rtp_process_to_sr_tests  ================
[17:22:05] [PASSED] coalesce-same-reg
[17:22:05] [PASSED] coalesce-same-reg-literal-and-func
[17:22:05] [PASSED] no-match-no-add
[17:22:05] [PASSED] two-regs-two-entries
[17:22:05] [PASSED] clr-one-set-other
[17:22:05] [PASSED] set-field
[17:22:05] [PASSED] conflict-duplicate
[17:22:05] [PASSED] conflict-not-disjoint
[17:22:05] [PASSED] conflict-not-disjoint-literal-and-func
[17:22:05] [PASSED] conflict-reg-type
[17:22:05] [PASSED] bad-mcr-reg-forced-to-regular
[17:22:05] [PASSED] bad-regular-reg-forced-to-mcr
[17:22:05] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:22:05] ================== xe_rtp_process_tests  ===================
[17:22:05] [PASSED] active1
[17:22:05] [PASSED] active2
[17:22:05] [PASSED] active-inactive
[17:22:05] [PASSED] inactive-active
[17:22:05] [PASSED] inactive-active-inactive
[17:22:05] [PASSED] inactive-inactive-inactive
[17:22:05] ============== [PASSED] xe_rtp_process_tests ===============
[17:22:05] ===================== [PASSED] xe_rtp ======================
[17:22:05] ==================== xe_wa (1 subtest) =====================
[17:22:05] ======================== xe_wa_gt  =========================
[17:22:05] [PASSED] TIGERLAKE B0
[17:22:05] [PASSED] DG1 A0
[17:22:05] [PASSED] DG1 B0
[17:22:05] [PASSED] ALDERLAKE_S A0
[17:22:05] [PASSED] ALDERLAKE_S B0
[17:22:05] [PASSED] ALDERLAKE_S C0
[17:22:05] [PASSED] ALDERLAKE_S D0
[17:22:05] [PASSED] ALDERLAKE_P A0
[17:22:05] [PASSED] ALDERLAKE_P B0
[17:22:05] [PASSED] ALDERLAKE_P C0
[17:22:05] [PASSED] ALDERLAKE_S RPLS D0
[17:22:05] [PASSED] ALDERLAKE_P RPLU E0
[17:22:05] [PASSED] DG2 G10 C0
[17:22:05] [PASSED] DG2 G11 B1
[17:22:05] [PASSED] DG2 G12 A1
[17:22:05] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:22:05] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:22:05] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:22:05] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:22:05] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:22:05] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:22:05] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:22:05] ==================== [PASSED] xe_wa_gt =====================
[17:22:05] ====================== [PASSED] xe_wa ======================
[17:22:05] ============================================================
[17:22:05] Testing complete. Ran 839 tests: passed: 810, skipped: 29
[17:22:05] Elapsed time: 41.887s total, 1.874s configuring, 39.247s building, 0.723s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:22:06] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:22:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:22:33] Starting KUnit Kernel (1/1)...
[17:22:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:22:33] ============ drm_test_pick_cmdline (2 subtests) ============
[17:22:33] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:22:33] =============== drm_test_pick_cmdline_named  ===============
[17:22:33] [PASSED] NTSC
[17:22:33] [PASSED] NTSC-J
[17:22:33] [PASSED] PAL
[17:22:33] [PASSED] PAL-M
[17:22:33] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:22:33] ============== [PASSED] drm_test_pick_cmdline ==============
[17:22:33] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:22:33] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:22:33] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:22:33] =========== drm_validate_clone_mode (2 subtests) ===========
[17:22:33] ============== drm_test_check_in_clone_mode  ===============
[17:22:33] [PASSED] in_clone_mode
[17:22:33] [PASSED] not_in_clone_mode
[17:22:33] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:22:33] =============== drm_test_check_valid_clones  ===============
[17:22:33] [PASSED] not_in_clone_mode
[17:22:33] [PASSED] valid_clone
[17:22:33] [PASSED] invalid_clone
[17:22:33] =========== [PASSED] drm_test_check_valid_clones ===========
[17:22:33] ============= [PASSED] drm_validate_clone_mode =============
[17:22:33] ============= drm_validate_modeset (1 subtest) =============
[17:22:33] [PASSED] drm_test_check_connector_changed_modeset
[17:22:33] ============== [PASSED] drm_validate_modeset ===============
[17:22:33] ====== drm_test_bridge_get_current_state (1 subtest) =======
[17:22:33] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:22:33] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:22:33] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:22:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:22:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:22:33] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[17:22:33] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:22:33] ============== drm_bridge_alloc (2 subtests) ===============
[17:22:33] [PASSED] drm_test_drm_bridge_alloc_basic
[17:22:33] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:22:33] ================ [PASSED] drm_bridge_alloc =================
[17:22:33] ============= drm_bridge_bus_fmt (5 subtests) ==============
[17:22:33] [PASSED] drm_test_bridge_rgb_yuv_rgb
[17:22:33] [PASSED] drm_test_bridge_must_convert_to_yuv444
[17:22:33] [PASSED] drm_test_bridge_hdmi_auto_rgb
[17:22:33] [PASSED] drm_test_bridge_auto_first
[17:22:33] [PASSED] drm_test_bridge_rgb_yuv_no_path
[17:22:33] =============== [PASSED] drm_bridge_bus_fmt ================
[17:22:33] ============= drm_cmdline_parser (40 subtests) =============
[17:22:33] [PASSED] drm_test_cmdline_force_d_only
[17:22:33] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:22:33] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:22:33] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:22:33] [PASSED] drm_test_cmdline_force_e_only
[17:22:33] [PASSED] drm_test_cmdline_res
[17:22:33] [PASSED] drm_test_cmdline_res_vesa
[17:22:33] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:22:33] [PASSED] drm_test_cmdline_res_rblank
[17:22:33] [PASSED] drm_test_cmdline_res_bpp
[17:22:33] [PASSED] drm_test_cmdline_res_refresh
[17:22:33] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:22:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:22:33] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:22:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:22:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:22:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:22:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:22:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:22:33] [PASSED] drm_test_cmdline_res_margins_force_on
[17:22:33] [PASSED] drm_test_cmdline_res_vesa_margins
[17:22:33] [PASSED] drm_test_cmdline_name
[17:22:33] [PASSED] drm_test_cmdline_name_bpp
[17:22:33] [PASSED] drm_test_cmdline_name_option
[17:22:33] [PASSED] drm_test_cmdline_name_bpp_option
[17:22:33] [PASSED] drm_test_cmdline_rotate_0
[17:22:33] [PASSED] drm_test_cmdline_rotate_90
[17:22:33] [PASSED] drm_test_cmdline_rotate_180
[17:22:33] [PASSED] drm_test_cmdline_rotate_270
[17:22:33] [PASSED] drm_test_cmdline_hmirror
[17:22:33] [PASSED] drm_test_cmdline_vmirror
[17:22:33] [PASSED] drm_test_cmdline_margin_options
[17:22:33] [PASSED] drm_test_cmdline_multiple_options
[17:22:33] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:22:33] [PASSED] drm_test_cmdline_extra_and_option
[17:22:33] [PASSED] drm_test_cmdline_freestanding_options
[17:22:33] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:22:33] [PASSED] drm_test_cmdline_panel_orientation
[17:22:33] ================ drm_test_cmdline_invalid  =================
[17:22:33] [PASSED] margin_only
[17:22:33] [PASSED] interlace_only
[17:22:33] [PASSED] res_missing_x
[17:22:33] [PASSED] res_missing_y
[17:22:33] [PASSED] res_bad_y
[17:22:33] [PASSED] res_missing_y_bpp
[17:22:33] [PASSED] res_bad_bpp
[17:22:33] [PASSED] res_bad_refresh
[17:22:33] [PASSED] res_bpp_refresh_force_on_off
[17:22:33] [PASSED] res_invalid_mode
[17:22:33] [PASSED] res_bpp_wrong_place_mode
[17:22:33] [PASSED] name_bpp_refresh
[17:22:33] [PASSED] name_refresh
[17:22:33] [PASSED] name_refresh_wrong_mode
[17:22:33] [PASSED] name_refresh_invalid_mode
[17:22:33] [PASSED] rotate_multiple
[17:22:33] [PASSED] rotate_invalid_val
[17:22:33] [PASSED] rotate_truncated
[17:22:33] [PASSED] invalid_option
[17:22:33] [PASSED] invalid_tv_option
[17:22:33] [PASSED] truncated_tv_option
[17:22:33] ============ [PASSED] drm_test_cmdline_invalid =============
[17:22:33] =============== drm_test_cmdline_tv_options  ===============
[17:22:33] [PASSED] NTSC
[17:22:33] [PASSED] NTSC_443
[17:22:33] [PASSED] NTSC_J
[17:22:33] [PASSED] PAL
[17:22:33] [PASSED] PAL_M
[17:22:33] [PASSED] PAL_N
[17:22:33] [PASSED] SECAM
[17:22:33] [PASSED] MONO_525
[17:22:33] [PASSED] MONO_625
[17:22:33] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:22:33] =============== [PASSED] drm_cmdline_parser ================
[17:22:33] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:22:33] [PASSED] drm_test_connector_hdmi_init_valid
[17:22:33] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:22:33] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:22:33] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:22:33] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:22:33] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:22:33] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:22:33] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:22:33] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:22:33] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:22:33] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:22:33] [PASSED] supported_formats=0x5 yuv420_allowed=1
[17:22:33] [PASSED] supported_formats=0x5 yuv420_allowed=0
[17:22:33] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:22:33] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:22:33] [PASSED] drm_test_connector_hdmi_init_null_product
[17:22:33] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:22:33] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:22:33] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:22:33] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:22:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:22:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:22:33] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:22:33] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:22:33] [PASSED] HDMI-A
[17:22:33] [PASSED] HDMI-B
[17:22:33] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:22:33] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:22:33] [PASSED] Unknown
[17:22:33] [PASSED] VGA
[17:22:33] [PASSED] DVI-I
[17:22:33] [PASSED] DVI-D
[17:22:33] [PASSED] DVI-A
[17:22:33] [PASSED] Composite
[17:22:33] [PASSED] SVIDEO
[17:22:33] [PASSED] LVDS
[17:22:33] [PASSED] Component
[17:22:33] [PASSED] DIN
[17:22:33] [PASSED] DP
[17:22:33] [PASSED] TV
[17:22:33] [PASSED] eDP
[17:22:33] [PASSED] Virtual
[17:22:33] [PASSED] DSI
[17:22:33] [PASSED] DPI
[17:22:33] [PASSED] Writeback
[17:22:33] [PASSED] SPI
[17:22:33] [PASSED] USB
[17:22:33] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:22:33] ============ [PASSED] drmm_connector_hdmi_init =============
[17:22:33] ============= drmm_connector_init (3 subtests) =============
[17:22:33] [PASSED] drm_test_drmm_connector_init
[17:22:33] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:22:33] ========= drm_test_drmm_connector_init_type_valid  =========
[17:22:33] [PASSED] Unknown
[17:22:33] [PASSED] VGA
[17:22:33] [PASSED] DVI-I
[17:22:33] [PASSED] DVI-D
[17:22:33] [PASSED] DVI-A
[17:22:33] [PASSED] Composite
[17:22:33] [PASSED] SVIDEO
[17:22:33] [PASSED] LVDS
[17:22:33] [PASSED] Component
[17:22:33] [PASSED] DIN
[17:22:33] [PASSED] DP
[17:22:33] [PASSED] HDMI-A
[17:22:33] [PASSED] HDMI-B
[17:22:33] [PASSED] TV
[17:22:33] [PASSED] eDP
[17:22:33] [PASSED] Virtual
[17:22:33] [PASSED] DSI
[17:22:33] [PASSED] DPI
[17:22:33] [PASSED] Writeback
[17:22:33] [PASSED] SPI
[17:22:33] [PASSED] USB
[17:22:33] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:22:33] =============== [PASSED] drmm_connector_init ===============
[17:22:33] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_init
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:22:33] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:22:33] [PASSED] Unknown
[17:22:33] [PASSED] VGA
[17:22:33] [PASSED] DVI-I
[17:22:33] [PASSED] DVI-D
[17:22:33] [PASSED] DVI-A
[17:22:33] [PASSED] Composite
[17:22:33] [PASSED] SVIDEO
[17:22:33] [PASSED] LVDS
[17:22:33] [PASSED] Component
[17:22:33] [PASSED] DIN
[17:22:33] [PASSED] DP
[17:22:33] [PASSED] HDMI-A
[17:22:33] [PASSED] HDMI-B
[17:22:33] [PASSED] TV
[17:22:33] [PASSED] eDP
[17:22:33] [PASSED] Virtual
[17:22:33] [PASSED] DSI
[17:22:33] [PASSED] DPI
[17:22:33] [PASSED] Writeback
[17:22:33] [PASSED] SPI
[17:22:33] [PASSED] USB
[17:22:33] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:22:33] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:22:33] [PASSED] Unknown
[17:22:33] [PASSED] VGA
[17:22:33] [PASSED] DVI-I
[17:22:33] [PASSED] DVI-D
[17:22:33] [PASSED] DVI-A
[17:22:33] [PASSED] Composite
[17:22:33] [PASSED] SVIDEO
[17:22:33] [PASSED] LVDS
[17:22:33] [PASSED] Component
[17:22:33] [PASSED] DIN
[17:22:33] [PASSED] DP
[17:22:33] [PASSED] HDMI-A
[17:22:33] [PASSED] HDMI-B
[17:22:33] [PASSED] TV
[17:22:33] [PASSED] eDP
[17:22:33] [PASSED] Virtual
[17:22:33] [PASSED] DSI
[17:22:33] [PASSED] DPI
[17:22:33] [PASSED] Writeback
[17:22:33] [PASSED] SPI
[17:22:33] [PASSED] USB
[17:22:33] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:22:33] =========== [PASSED] drm_connector_dynamic_init ============
[17:22:33] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:22:33] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:22:33] ======= drm_connector_dynamic_register (7 subtests) ========
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:22:33] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:22:33] ========= [PASSED] drm_connector_dynamic_register ==========
[17:22:33] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:22:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:22:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:22:33] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:22:33] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:22:33] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:22:33] [PASSED] NTSC
[17:22:33] [PASSED] NTSC-443
[17:22:33] [PASSED] NTSC-J
[17:22:33] [PASSED] PAL
[17:22:33] [PASSED] PAL-M
[17:22:33] [PASSED] PAL-N
[17:22:33] [PASSED] SECAM
[17:22:33] [PASSED] Mono
[17:22:33] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:22:33] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:22:33] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:22:33] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:22:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:22:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:22:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:22:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:22:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:22:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:22:33] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:22:33] [PASSED] VIC 96
[17:22:33] [PASSED] VIC 97
[17:22:33] [PASSED] VIC 101
[17:22:33] [PASSED] VIC 102
[17:22:33] [PASSED] VIC 106
[17:22:33] [PASSED] VIC 107
[17:22:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:22:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:22:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:22:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:22:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:22:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:22:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:22:33] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:22:33] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:22:33] [PASSED] Automatic
[17:22:33] [PASSED] Full
[17:22:33] [PASSED] Limited 16:235
[17:22:33] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:22:33] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:22:33] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:22:33] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:22:33] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:22:33] [PASSED] RGB
[17:22:33] [PASSED] YUV 4:2:0
[17:22:33] [PASSED] YUV 4:2:2
[17:22:33] [PASSED] YUV 4:4:4
[17:22:33] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:22:33] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:22:33] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:22:33] ============= drm_damage_helper (21 subtests) ==============
[17:22:33] [PASSED] drm_test_damage_iter_no_damage
[17:22:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:22:33] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:22:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:22:33] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:22:33] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:22:33] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:22:33] [PASSED] drm_test_damage_iter_simple_damage
[17:22:33] [PASSED] drm_test_damage_iter_single_damage
[17:22:33] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:22:33] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:22:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:22:33] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:22:33] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:22:33] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:22:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:22:33] [PASSED] drm_test_damage_iter_damage
[17:22:33] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:22:33] [PASSED] drm_test_damage_iter_damage_one_outside
[17:22:33] [PASSED] drm_test_damage_iter_damage_src_moved
[17:22:33] [PASSED] drm_test_damage_iter_damage_not_visible
[17:22:33] ================ [PASSED] drm_damage_helper ================
[17:22:33] ============== drm_dp_mst_helper (3 subtests) ==============
[17:22:33] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:22:33] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:22:33] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:22:33] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:22:33] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:22:33] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:22:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:22:33] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:22:33] [PASSED] Link rate 2000000 lane count 4
[17:22:33] [PASSED] Link rate 2000000 lane count 2
[17:22:33] [PASSED] Link rate 2000000 lane count 1
[17:22:33] [PASSED] Link rate 1350000 lane count 4
[17:22:33] [PASSED] Link rate 1350000 lane count 2
[17:22:33] [PASSED] Link rate 1350000 lane count 1
[17:22:33] [PASSED] Link rate 1000000 lane count 4
[17:22:33] [PASSED] Link rate 1000000 lane count 2
[17:22:33] [PASSED] Link rate 1000000 lane count 1
[17:22:33] [PASSED] Link rate 810000 lane count 4
[17:22:33] [PASSED] Link rate 810000 lane count 2
[17:22:33] [PASSED] Link rate 810000 lane count 1
[17:22:33] [PASSED] Link rate 540000 lane count 4
[17:22:33] [PASSED] Link rate 540000 lane count 2
[17:22:33] [PASSED] Link rate 540000 lane count 1
[17:22:33] [PASSED] Link rate 270000 lane count 4
[17:22:33] [PASSED] Link rate 270000 lane count 2
[17:22:33] [PASSED] Link rate 270000 lane count 1
[17:22:33] [PASSED] Link rate 162000 lane count 4
[17:22:33] [PASSED] Link rate 162000 lane count 2
[17:22:33] [PASSED] Link rate 162000 lane count 1
[17:22:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:22:33] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:22:33] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:22:33] [PASSED] DP_POWER_UP_PHY with port number
[17:22:33] [PASSED] DP_POWER_DOWN_PHY with port number
[17:22:33] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:22:33] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:22:33] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:22:33] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:22:33] [PASSED] DP_QUERY_PAYLOAD with port number
[17:22:33] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:22:33] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:22:33] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:22:33] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:22:33] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:22:33] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:22:33] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:22:33] [PASSED] DP_REMOTE_I2C_READ with port number
[17:22:33] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:22:33] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:22:33] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:22:33] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:22:33] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:22:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:22:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:22:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:22:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:22:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:22:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:22:33] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:22:33] ================ [PASSED] drm_dp_mst_helper ================
[17:22:33] ================== drm_exec (7 subtests) ===================
[17:22:33] [PASSED] sanitycheck
[17:22:33] [PASSED] test_lock
[17:22:33] [PASSED] test_lock_unlock
[17:22:33] [PASSED] test_duplicates
[17:22:33] [PASSED] test_prepare
[17:22:33] [PASSED] test_prepare_array
[17:22:33] [PASSED] test_multiple_loops
[17:22:33] ==================== [PASSED] drm_exec =====================
[17:22:33] =========== drm_format_helper_test (17 subtests) ===========
[17:22:33] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:22:33] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:22:33] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:22:33] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:22:33] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:22:33] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:22:33] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:22:33] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:22:33] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:22:33] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:22:33] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:22:33] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:22:33] ==================== drm_test_fb_swab  =====================
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ================ [PASSED] drm_test_fb_swab =================
[17:22:33] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:22:33] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:22:33] [PASSED] single_pixel_source_buffer
[17:22:33] [PASSED] single_pixel_clip_rectangle
[17:22:33] [PASSED] well_known_colors
[17:22:33] [PASSED] destination_pitch
[17:22:33] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:22:33] ================= drm_test_fb_clip_offset  =================
[17:22:33] [PASSED] pass through
[17:22:33] [PASSED] horizontal offset
[17:22:33] [PASSED] vertical offset
[17:22:33] [PASSED] horizontal and vertical offset
[17:22:33] [PASSED] horizontal offset (custom pitch)
[17:22:33] [PASSED] vertical offset (custom pitch)
[17:22:33] [PASSED] horizontal and vertical offset (custom pitch)
[17:22:33] ============= [PASSED] drm_test_fb_clip_offset =============
[17:22:33] =================== drm_test_fb_memcpy  ====================
[17:22:33] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:22:33] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:22:33] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:22:33] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:22:33] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:22:33] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:22:33] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:22:33] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:22:33] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:22:33] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:22:33] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:22:33] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:22:33] =============== [PASSED] drm_test_fb_memcpy ================
[17:22:33] ============= [PASSED] drm_format_helper_test ==============
[17:22:33] ================= drm_format (18 subtests) =================
[17:22:33] [PASSED] drm_test_format_block_width_invalid
[17:22:33] [PASSED] drm_test_format_block_width_one_plane
[17:22:33] [PASSED] drm_test_format_block_width_two_plane
[17:22:33] [PASSED] drm_test_format_block_width_three_plane
[17:22:33] [PASSED] drm_test_format_block_width_tiled
[17:22:33] [PASSED] drm_test_format_block_height_invalid
[17:22:33] [PASSED] drm_test_format_block_height_one_plane
[17:22:33] [PASSED] drm_test_format_block_height_two_plane
[17:22:33] [PASSED] drm_test_format_block_height_three_plane
[17:22:33] [PASSED] drm_test_format_block_height_tiled
[17:22:33] [PASSED] drm_test_format_min_pitch_invalid
[17:22:33] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:22:33] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:22:33] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:22:33] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:22:33] [PASSED] drm_test_format_min_pitch_two_plane
[17:22:33] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:22:33] [PASSED] drm_test_format_min_pitch_tiled
[17:22:33] =================== [PASSED] drm_format ====================
[17:22:33] ============== drm_framebuffer (10 subtests) ===============
[17:22:33] ========== drm_test_framebuffer_check_src_coords  ==========
[17:22:33] [PASSED] Success: source fits into fb
[17:22:33] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:22:33] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:22:33] [PASSED] Fail: overflowing fb with source width
[17:22:33] [PASSED] Fail: overflowing fb with source height
[17:22:33] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:22:33] [PASSED] drm_test_framebuffer_cleanup
[17:22:33] =============== drm_test_framebuffer_create  ===============
[17:22:33] [PASSED] ABGR8888 normal sizes
[17:22:33] [PASSED] ABGR8888 max sizes
[17:22:33] [PASSED] ABGR8888 pitch greater than min required
[17:22:33] [PASSED] ABGR8888 pitch less than min required
[17:22:33] [PASSED] ABGR8888 Invalid width
[17:22:33] [PASSED] ABGR8888 Invalid buffer handle
[17:22:33] [PASSED] No pixel format
[17:22:33] [PASSED] ABGR8888 Width 0
[17:22:33] [PASSED] ABGR8888 Height 0
[17:22:33] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:22:33] [PASSED] ABGR8888 Large buffer offset
[17:22:33] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:22:33] [PASSED] ABGR8888 Invalid flag
[17:22:33] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:22:33] [PASSED] ABGR8888 Valid buffer modifier
[17:22:33] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:22:33] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:22:33] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:22:33] [PASSED] NV12 Normal sizes
[17:22:33] [PASSED] NV12 Max sizes
[17:22:33] [PASSED] NV12 Invalid pitch
[17:22:33] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:22:33] [PASSED] NV12 different  modifier per-plane
[17:22:33] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:22:33] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:22:33] [PASSED] NV12 Modifier for inexistent plane
[17:22:33] [PASSED] NV12 Handle for inexistent plane
[17:22:33] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:22:33] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:22:33] [PASSED] YVU420 Normal sizes
[17:22:33] [PASSED] YVU420 Max sizes
[17:22:33] [PASSED] YVU420 Invalid pitch
[17:22:33] [PASSED] YVU420 Different pitches
[17:22:33] [PASSED] YVU420 Different buffer offsets/pitches
[17:22:33] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:22:33] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:22:33] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:22:33] [PASSED] YVU420 Valid modifier
[17:22:33] [PASSED] YVU420 Different modifiers per plane
[17:22:33] [PASSED] YVU420 Modifier for inexistent plane
[17:22:33] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:22:33] [PASSED] X0L2 Normal sizes
[17:22:33] [PASSED] X0L2 Max sizes
[17:22:33] [PASSED] X0L2 Invalid pitch
[17:22:33] [PASSED] X0L2 Pitch greater than minimum required
[17:22:33] [PASSED] X0L2 Handle for inexistent plane
[17:22:33] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:22:33] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:22:33] [PASSED] X0L2 Valid modifier
[17:22:33] [PASSED] X0L2 Modifier for inexistent plane
[17:22:33] =========== [PASSED] drm_test_framebuffer_create ===========
[17:22:33] [PASSED] drm_test_framebuffer_free
[17:22:33] [PASSED] drm_test_framebuffer_init
[17:22:33] [PASSED] drm_test_framebuffer_init_bad_format
[17:22:33] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:22:33] [PASSED] drm_test_framebuffer_lookup
[17:22:33] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:22:33] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:22:33] ================= [PASSED] drm_framebuffer =================
[17:22:33] ================ drm_gem_shmem (8 subtests) ================
[17:22:33] [PASSED] drm_gem_shmem_test_obj_create
[17:22:33] [PASSED] drm_gem_shmem_test_obj_create_private
[17:22:33] [PASSED] drm_gem_shmem_test_pin_pages
[17:22:33] [PASSED] drm_gem_shmem_test_vmap
[17:22:33] [PASSED] drm_gem_shmem_test_get_sg_table
[17:22:33] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:22:33] [PASSED] drm_gem_shmem_test_madvise
[17:22:33] [PASSED] drm_gem_shmem_test_purge
[17:22:33] ================== [PASSED] drm_gem_shmem ==================
[17:22:33] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[17:22:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:22:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:22:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:22:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:22:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:22:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:22:33] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:22:33] [PASSED] Automatic
[17:22:33] [PASSED] Full
[17:22:33] [PASSED] Limited 16:235
[17:22:33] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:22:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:22:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:22:33] [PASSED] drm_test_check_disable_connector
[17:22:33] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:22:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:22:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:22:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:22:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:22:33] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:22:33] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:22:33] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:22:33] [PASSED] drm_test_check_output_bpc_dvi
[17:22:33] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:22:33] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:22:33] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:22:33] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:22:33] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:22:33] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:22:33] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:22:33] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:22:33] ============ drm_test_check_hdmi_color_format  =============
[17:22:33] [PASSED] AUTO -> RGB
[17:22:33] [PASSED] YCBCR422 -> YUV422
[17:22:33] [PASSED] YCBCR420 -> YUV420
[17:22:33] [PASSED] YCBCR444 -> YUV444
[17:22:33] [PASSED] RGB -> RGB
[17:22:33] ======== [PASSED] drm_test_check_hdmi_color_format =========
[17:22:33] ======== drm_test_check_hdmi_color_format_420_only  ========
[17:22:33] [PASSED] RGB should fail
[17:22:33] [PASSED] YUV444 should fail
[17:22:33] [PASSED] YUV422 should fail
[17:22:33] [PASSED] YUV420 should work
[17:22:33] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[17:22:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:22:33] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:22:33] [PASSED] drm_test_check_broadcast_rgb_value
[17:22:33] [PASSED] drm_test_check_bpc_8_value
[17:22:33] [PASSED] drm_test_check_bpc_10_value
[17:22:33] [PASSED] drm_test_check_bpc_12_value
[17:22:33] [PASSED] drm_test_check_format_value
[17:22:33] [PASSED] drm_test_check_tmds_char_value
[17:22:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:22:33] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[17:22:33] [PASSED] drm_test_check_mode_valid
[17:22:33] [PASSED] drm_test_check_mode_valid_reject
[17:22:33] [PASSED] drm_test_check_mode_valid_reject_rate
[17:22:33] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:22:33] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[17:22:33] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[17:22:33] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[17:22:33] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:22:33] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[17:22:33] [PASSED] drm_test_check_infoframes
[17:22:33] [PASSED] drm_test_check_reject_avi_infoframe
[17:22:33] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[17:22:33] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[17:22:33] [PASSED] drm_test_check_reject_audio_infoframe
[17:22:33] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[17:22:33] ================= drm_managed (2 subtests) =================
[17:22:33] [PASSED] drm_test_managed_release_action
[17:22:33] [PASSED] drm_test_managed_run_action
[17:22:33] =================== [PASSED] drm_managed ===================
[17:22:33] =================== drm_mm (6 subtests) ====================
[17:22:33] [PASSED] drm_test_mm_init
[17:22:33] [PASSED] drm_test_mm_debug
[17:22:33] [PASSED] drm_test_mm_align32
[17:22:33] [PASSED] drm_test_mm_align64
[17:22:33] [PASSED] drm_test_mm_lowest
[17:22:33] [PASSED] drm_test_mm_highest
[17:22:33] ===================== [PASSED] drm_mm ======================
[17:22:33] ============= drm_modes_analog_tv (5 subtests) =============
[17:22:33] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:22:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:22:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:22:33] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:22:33] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:22:33] =============== [PASSED] drm_modes_analog_tv ===============
[17:22:33] ============== drm_panic_helper (3 subtests) ===============
[17:22:33] ============= drm_test_panic_screen_user_map  ==============
[17:22:33] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[17:22:33] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[17:22:33] ========= [PASSED] drm_test_panic_screen_user_map ==========
[17:22:33] ============= drm_test_panic_screen_user_page  =============
[17:22:33] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[17:22:33] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[17:22:33] ========= [PASSED] drm_test_panic_screen_user_page =========
[17:22:33] ========== drm_test_panic_screen_user_set_pixel  ===========
[17:22:33] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[17:22:33] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[17:22:33] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[17:22:33] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[17:22:33] ================ [PASSED] drm_panic_helper =================
[17:22:33] ============== drm_plane_helper (2 subtests) ===============
[17:22:33] =============== drm_test_check_plane_state  ================
[17:22:33] [PASSED] clipping_simple
[17:22:33] [PASSED] clipping_rotate_reflect
[17:22:33] [PASSED] positioning_simple
[17:22:33] [PASSED] upscaling
[17:22:33] [PASSED] downscaling
[17:22:33] [PASSED] rounding1
[17:22:33] [PASSED] rounding2
[17:22:33] [PASSED] rounding3
[17:22:33] [PASSED] rounding4
[17:22:33] =========== [PASSED] drm_test_check_plane_state ============
[17:22:33] =========== drm_test_check_invalid_plane_state  ============
[17:22:33] [PASSED] positioning_invalid
[17:22:33] [PASSED] upscaling_invalid
[17:22:33] [PASSED] downscaling_invalid
[17:22:33] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:22:33] ================ [PASSED] drm_plane_helper =================
[17:22:33] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:22:33] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:22:33] [PASSED] None
[17:22:33] [PASSED] PAL
[17:22:33] [PASSED] NTSC
[17:22:33] [PASSED] Both, NTSC Default
[17:22:33] [PASSED] Both, PAL Default
[17:22:33] [PASSED] Both, NTSC Default, with PAL on command-line
[17:22:33] [PASSED] Both, PAL Default, with NTSC on command-line
[17:22:33] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:22:33] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:22:33] ================== drm_rect (9 subtests) ===================
[17:22:33] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:22:33] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:22:33] [PASSED] drm_test_rect_clip_scaled_clipped
[17:22:33] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:22:33] ================= drm_test_rect_intersect  =================
[17:22:33] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:22:33] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:22:33] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:22:33] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:22:33] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:22:33] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:22:33] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:22:33] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:22:33] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:22:33] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:22:33] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:22:33] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:22:33] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:22:33] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:22:33] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:22:33] ============= [PASSED] drm_test_rect_intersect =============
[17:22:33] ================ drm_test_rect_calc_hscale  ================
[17:22:33] [PASSED] normal use
[17:22:33] [PASSED] out of max range
[17:22:33] [PASSED] out of min range
[17:22:33] [PASSED] zero dst
[17:22:33] [PASSED] negative src
[17:22:33] [PASSED] negative dst
[17:22:33] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:22:33] ================ drm_test_rect_calc_vscale  ================
[17:22:33] [PASSED] normal use
[17:22:33] [PASSED] out of max range
[17:22:33] [PASSED] out of min range
[17:22:33] [PASSED] zero dst
[17:22:33] [PASSED] negative src
[17:22:33] [PASSED] negative dst
[17:22:33] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:22:33] ================== drm_test_rect_rotate  ===================
[17:22:33] [PASSED] reflect-x
[17:22:33] [PASSED] reflect-y
[17:22:33] [PASSED] rotate-0
[17:22:33] [PASSED] rotate-90
[17:22:33] [PASSED] rotate-180
[17:22:33] [PASSED] rotate-270
[17:22:33] ============== [PASSED] drm_test_rect_rotate ===============
[17:22:33] ================ drm_test_rect_rotate_inv  =================
[17:22:33] [PASSED] reflect-x
[17:22:33] [PASSED] reflect-y
[17:22:33] [PASSED] rotate-0
[17:22:33] [PASSED] rotate-90
[17:22:33] [PASSED] rotate-180
[17:22:33] [PASSED] rotate-270
[17:22:33] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:22:33] ==================== [PASSED] drm_rect =====================
[17:22:33] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:22:33] ============ drm_test_sysfb_build_fourcc_list  =============
[17:22:33] [PASSED] no native formats
[17:22:33] [PASSED] XRGB8888 as native format
[17:22:33] [PASSED] remove duplicates
[17:22:33] [PASSED] convert alpha formats
[17:22:33] [PASSED] random formats
[17:22:33] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:22:33] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:22:33] ================== drm_fixp (2 subtests) ===================
[17:22:33] [PASSED] drm_test_int2fixp
[17:22:33] [PASSED] drm_test_sm2fixp
[17:22:33] ==================== [PASSED] drm_fixp =====================
[17:22:33] ============================================================
[17:22:33] Testing complete. Ran 667 tests: passed: 667
[17:22:33] Elapsed time: 27.803s total, 1.860s configuring, 25.528s building, 0.411s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:22:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:22:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:22:45] Starting KUnit Kernel (1/1)...
[17:22:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:22:45] ================= ttm_device (5 subtests) ==================
[17:22:45] [PASSED] ttm_device_init_basic
[17:22:45] [PASSED] ttm_device_init_multiple
[17:22:45] [PASSED] ttm_device_fini_basic
[17:22:45] [PASSED] ttm_device_init_no_vma_man
[17:22:45] ================== ttm_device_init_pools  ==================
[17:22:45] [PASSED] No DMA allocations, no DMA32 required
[17:22:45] [PASSED] DMA allocations, DMA32 required
[17:22:45] [PASSED] No DMA allocations, DMA32 required
[17:22:45] [PASSED] DMA allocations, no DMA32 required
[17:22:46] ============== [PASSED] ttm_device_init_pools ==============
[17:22:46] =================== [PASSED] ttm_device ====================
[17:22:46] ================== ttm_pool (8 subtests) ===================
[17:22:46] ================== ttm_pool_alloc_basic  ===================
[17:22:46] [PASSED] One page
[17:22:46] [PASSED] More than one page
[17:22:46] [PASSED] Above the allocation limit
[17:22:46] [PASSED] One page, with coherent DMA mappings enabled
[17:22:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:22:46] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:22:46] ============== ttm_pool_alloc_basic_dma_addr  ==============
[17:22:46] [PASSED] One page
[17:22:46] [PASSED] More than one page
[17:22:46] [PASSED] Above the allocation limit
[17:22:46] [PASSED] One page, with coherent DMA mappings enabled
[17:22:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:22:46] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:22:46] [PASSED] ttm_pool_alloc_order_caching_match
[17:22:46] [PASSED] ttm_pool_alloc_caching_mismatch
[17:22:46] [PASSED] ttm_pool_alloc_order_mismatch
[17:22:46] [PASSED] ttm_pool_free_dma_alloc
[17:22:46] [PASSED] ttm_pool_free_no_dma_alloc
[17:22:46] [PASSED] ttm_pool_fini_basic
[17:22:46] ==================== [PASSED] ttm_pool =====================
[17:22:46] ================ ttm_resource (8 subtests) =================
[17:22:46] ================= ttm_resource_init_basic  =================
[17:22:46] [PASSED] Init resource in TTM_PL_SYSTEM
[17:22:46] [PASSED] Init resource in TTM_PL_VRAM
[17:22:46] [PASSED] Init resource in a private placement
[17:22:46] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:22:46] ============= [PASSED] ttm_resource_init_basic =============
[17:22:46] [PASSED] ttm_resource_init_pinned
[17:22:46] [PASSED] ttm_resource_fini_basic
[17:22:46] [PASSED] ttm_resource_manager_init_basic
[17:22:46] [PASSED] ttm_resource_manager_usage_basic
[17:22:46] [PASSED] ttm_resource_manager_set_used_basic
[17:22:46] [PASSED] ttm_sys_man_alloc_basic
[17:22:46] [PASSED] ttm_sys_man_free_basic
[17:22:46] ================== [PASSED] ttm_resource ===================
[17:22:46] =================== ttm_tt (15 subtests) ===================
[17:22:46] ==================== ttm_tt_init_basic  ====================
[17:22:46] [PASSED] Page-aligned size
[17:22:46] [PASSED] Extra pages requested
[17:22:46] ================ [PASSED] ttm_tt_init_basic ================
[17:22:46] [PASSED] ttm_tt_init_misaligned
[17:22:46] [PASSED] ttm_tt_fini_basic
[17:22:46] [PASSED] ttm_tt_fini_sg
[17:22:46] [PASSED] ttm_tt_fini_shmem
[17:22:46] [PASSED] ttm_tt_create_basic
[17:22:46] [PASSED] ttm_tt_create_invalid_bo_type
[17:22:46] [PASSED] ttm_tt_create_ttm_exists
[17:22:46] [PASSED] ttm_tt_create_failed
[17:22:46] [PASSED] ttm_tt_destroy_basic
[17:22:46] [PASSED] ttm_tt_populate_null_ttm
[17:22:46] [PASSED] ttm_tt_populate_populated_ttm
[17:22:46] [PASSED] ttm_tt_unpopulate_basic
[17:22:46] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:22:46] [PASSED] ttm_tt_swapin_basic
[17:22:46] ===================== [PASSED] ttm_tt ======================
[17:22:46] =================== ttm_bo (14 subtests) ===================
[17:22:46] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[17:22:46] [PASSED] Cannot be interrupted and sleeps
[17:22:46] [PASSED] Cannot be interrupted, locks straight away
[17:22:46] [PASSED] Can be interrupted, sleeps
[17:22:46] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:22:46] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:22:46] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:22:46] [PASSED] ttm_bo_reserve_double_resv
[17:22:46] [PASSED] ttm_bo_reserve_interrupted
[17:22:46] [PASSED] ttm_bo_reserve_deadlock
[17:22:46] [PASSED] ttm_bo_unreserve_basic
[17:22:46] [PASSED] ttm_bo_unreserve_pinned
[17:22:46] [PASSED] ttm_bo_unreserve_bulk
[17:22:46] [PASSED] ttm_bo_fini_basic
[17:22:46] [PASSED] ttm_bo_fini_shared_resv
[17:22:46] [PASSED] ttm_bo_pin_basic
[17:22:46] [PASSED] ttm_bo_pin_unpin_resource
[17:22:46] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:22:46] ===================== [PASSED] ttm_bo ======================
[17:22:46] ============== ttm_bo_validate (22 subtests) ===============
[17:22:46] ============== ttm_bo_init_reserved_sys_man  ===============
[17:22:46] [PASSED] Buffer object for userspace
[17:22:46] [PASSED] Kernel buffer object
[17:22:46] [PASSED] Shared buffer object
[17:22:46] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:22:46] ============== ttm_bo_init_reserved_mock_man  ==============
[17:22:46] [PASSED] Buffer object for userspace
[17:22:46] [PASSED] Kernel buffer object
[17:22:46] [PASSED] Shared buffer object
[17:22:46] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:22:46] [PASSED] ttm_bo_init_reserved_resv
[17:22:46] ================== ttm_bo_validate_basic  ==================
[17:22:46] [PASSED] Buffer object for userspace
[17:22:46] [PASSED] Kernel buffer object
[17:22:46] [PASSED] Shared buffer object
[17:22:46] ============== [PASSED] ttm_bo_validate_basic ==============
[17:22:46] [PASSED] ttm_bo_validate_invalid_placement
[17:22:46] ============= ttm_bo_validate_same_placement  ==============
[17:22:46] [PASSED] System manager
[17:22:46] [PASSED] VRAM manager
[17:22:46] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:22:46] [PASSED] ttm_bo_validate_failed_alloc
[17:22:46] [PASSED] ttm_bo_validate_pinned
[17:22:46] [PASSED] ttm_bo_validate_busy_placement
[17:22:46] ================ ttm_bo_validate_multihop  =================
[17:22:46] [PASSED] Buffer object for userspace
[17:22:46] [PASSED] Kernel buffer object
[17:22:46] [PASSED] Shared buffer object
[17:22:46] ============ [PASSED] ttm_bo_validate_multihop =============
[17:22:46] ========== ttm_bo_validate_no_placement_signaled  ==========
[17:22:46] [PASSED] Buffer object in system domain, no page vector
[17:22:46] [PASSED] Buffer object in system domain with an existing page vector
[17:22:46] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:22:46] ======== ttm_bo_validate_no_placement_not_signaled  ========
[17:22:46] [PASSED] Buffer object for userspace
[17:22:46] [PASSED] Kernel buffer object
[17:22:46] [PASSED] Shared buffer object
[17:22:46] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:22:46] [PASSED] ttm_bo_validate_move_fence_signaled
[17:22:46] ========= ttm_bo_validate_move_fence_not_signaled  =========
[17:22:46] [PASSED] Waits for GPU
[17:22:46] [PASSED] Tries to lock straight away
[17:22:46] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:22:46] [PASSED] ttm_bo_validate_swapout
[17:22:46] [PASSED] ttm_bo_validate_happy_evict
[17:22:46] [PASSED] ttm_bo_validate_all_pinned_evict
[17:22:46] [PASSED] ttm_bo_validate_allowed_only_evict
[17:22:46] [PASSED] ttm_bo_validate_deleted_evict
[17:22:46] [PASSED] ttm_bo_validate_busy_domain_evict
[17:22:46] [PASSED] ttm_bo_validate_evict_gutting
[17:22:46] [PASSED] ttm_bo_validate_recrusive_evict
[17:22:46] ================= [PASSED] ttm_bo_validate =================
[17:22:46] ============================================================
[17:22:46] Testing complete. Ran 102 tests: passed: 102
[17:22:46] Elapsed time: 12.135s total, 1.837s configuring, 10.033s building, 0.225s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[17:22:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:22:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:22:56] Starting KUnit Kernel (1/1)...
[17:22:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:22:56] =============== dma-buf-fence (12 subtests) ================
[17:22:56] [PASSED] test_sanitycheck
[17:22:56] [PASSED] test_signaling
[17:22:56] [PASSED] test_add_callback
[17:22:56] [PASSED] test_late_add_callback
[17:22:56] [PASSED] test_rm_callback
[17:22:56] [PASSED] test_late_rm_callback
[17:22:56] [PASSED] test_status
[17:22:56] [PASSED] test_error
[17:22:56] [PASSED] test_wait
[17:22:56] [PASSED] test_wait_timeout
[17:22:56] [PASSED] test_stub
[17:22:56] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[17:22:56] ================== [PASSED] dma-buf-fence ==================
[17:22:56] ============ dma-buf-fence-chain (11 subtests) =============
[17:22:56] [PASSED] test_sanitycheck
[17:22:56] [PASSED] test_find_seqno
[17:22:56] [PASSED] test_find_signaled
[17:22:56] [PASSED] test_find_out_of_order
[17:23:02] [PASSED] test_find_gap
[17:23:02] [PASSED] test_find_race
[17:23:02] [PASSED] test_signal_forward
[17:23:02] [PASSED] test_signal_backward
[17:23:02] [PASSED] test_wait_forward
[17:23:02] [PASSED] test_wait_backward
[17:23:02] [PASSED] test_wait_random
[17:23:02] =============== [PASSED] dma-buf-fence-chain ===============
[17:23:02] ============ dma-buf-fence-unwrap (11 subtests) ============
[17:23:02] [PASSED] test_sanitycheck
[17:23:02] [PASSED] test_unwrap_array
[17:23:02] [PASSED] test_unwrap_chain
[17:23:02] [PASSED] test_unwrap_chain_array
[17:23:02] [PASSED] test_unwrap_merge
[17:23:02] [PASSED] test_unwrap_merge_duplicate
[17:23:02] [PASSED] test_unwrap_merge_seqno
[17:23:02] [PASSED] test_unwrap_merge_order
[17:23:02] [PASSED] test_unwrap_merge_complex
[17:23:02] [PASSED] test_unwrap_merge_complex_seqno
[17:23:02] [PASSED] test_dedup_empty
[17:23:02] ============== [PASSED] dma-buf-fence-unwrap ===============
[17:23:02] ================ dma-buf-resv (5 subtests) =================
[17:23:02] [PASSED] test_sanitycheck
[17:23:02] ===================== test_signaling  ======================
[17:23:02] [PASSED] kernel
[17:23:02] [PASSED] write
[17:23:02] [PASSED] read
[17:23:02] [PASSED] bookkeep
[17:23:02] ================= [PASSED] test_signaling ==================
[17:23:02] ====================== test_for_each  ======================
[17:23:02] [PASSED] kernel
[17:23:02] [PASSED] write
[17:23:02] [PASSED] read
[17:23:02] [PASSED] bookkeep
[17:23:02] ================== [PASSED] test_for_each ==================
[17:23:02] ================= test_for_each_unlocked  ==================
[17:23:02] [PASSED] kernel
[17:23:02] [PASSED] write
[17:23:02] [PASSED] read
[17:23:02] [PASSED] bookkeep
[17:23:02] ============= [PASSED] test_for_each_unlocked ==============
[17:23:02] ===================== test_get_fences  =====================
[17:23:02] [PASSED] kernel
[17:23:02] [PASSED] write
[17:23:02] [PASSED] read
[17:23:02] [PASSED] bookkeep
[17:23:02] ================= [PASSED] test_get_fences =================
[17:23:02] ================== [PASSED] dma-buf-resv ===================
[17:23:02] ============================================================
[17:23:02] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[17:23:02] Elapsed time: 15.874s total, 1.856s configuring, 8.746s building, 5.262s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH 03/10] drm/i915: Handle joined pipes inside intel_crtc_vblank_{on, off}()

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915: NULL state dereference in intel_crtc_vblank_off()
--

commit c6499a1bf58e345d4e50ee3b23d7821c66712bdd
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915: Handle joined pipes inside intel_crtc_vblank_{on, off}()

This commit moves the joined-pipe iteration into intel_crtc_vblank_on()
and intel_crtc_vblank_off(), renaming the single-pipe helpers to
intel_pipe_vblank_on() and intel_pipe_vblank_off(). Callers are updated to
pass struct intel_atomic_state alongside the CRTC state.

> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ea0cdb7822f39..381cdf7d5131c 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c

[ ... ]

> @@ -1455,7 +1455,7 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state,
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  
> -	intel_crtc_vblank_off(old_crtc_state);
> +	intel_crtc_vblank_off(state, old_crtc_state);
>  
>  	/* step2d,e: disable transcoder and wait */
>  	gen11_dsi_disable_transcoder(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 5b8968197fbcf..b814b84c650fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -265,7 +265,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
>  	struct intel_display *display = to_intel_display(encoder);
>  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  
> -	intel_crtc_vblank_off(old_crtc_state);
> +	intel_crtc_vblank_off(state, old_crtc_state);
>  
>  	intel_disable_transcoder(old_crtc_state);
>  

[ ... ]

> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 10ed9bdfee763..a28f4a088e587 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c

[ ... ]

> @@ -165,6 +165,34 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
>  	flush_work(&display->irq.vblank_notify_work);
>  }
>  
> +void intel_crtc_vblank_on(struct intel_atomic_state *state,
> +			  const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_crtc *pipe_crtc;
> +
> +	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
> +		const struct intel_crtc_state *pipe_crtc_state =
> +			intel_atomic_get_new_crtc_state(state, pipe_crtc);
> +
> +		intel_pipe_vblank_on(pipe_crtc_state);
> +	}
> +}
> +
> +void intel_crtc_vblank_off(struct intel_atomic_state *state,
> +			   const struct intel_crtc_state *old_crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_crtc *pipe_crtc;
> +
> +	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
> +		const struct intel_crtc_state *old_pipe_crtc_state =
> +			intel_atomic_get_old_crtc_state(state, pipe_crtc);
> +
> +		intel_pipe_vblank_off(old_pipe_crtc_state);
> +	}
> +}

[Severity: High]
Can state be NULL when intel_crtc_vblank_off() is called from
encoder->post_disable()?

During initial hardware readout or resume in
intel_modeset_setup_hw_state(), intel_sanitize_encoder() disables an
encoder whose connector is active while its pipe is inactive by invoking
the disable hooks with a NULL atomic state:

drivers/gpu/drm/i915/display/intel_modeset_setup.c:intel_sanitize_encoder() {
	...
	if (connector && !has_active_crtc) {
		...
		if (crtc_state) {
			...
			/* FIXME NULL atomic state passed! */
			if (encoder->disable)
				encoder->disable(NULL, encoder, crtc_state,
						 connector->base.state);
			if (encoder->post_disable)
				encoder->post_disable(NULL, encoder, crtc_state,
						      connector->base.state);
		}
	}
}

Previously, gen11_dsi_post_disable(), intel_dsi_post_disable() (on
Broxton and Geminilake), and hsw_post_disable_crt() did not dereference
state and passed old_crtc_state directly to intel_crtc_vblank_off(). With
this change, those callbacks pass state = NULL to intel_crtc_vblank_off(),
which dereferences state in both to_intel_display(state) and
intel_atomic_get_old_crtc_state(state, pipe_crtc).

Would it make sense to keep using intel_pipe_vblank_off(old_crtc_state) in
the non-joiner post_disable callbacks, or handle a NULL state inside
intel_crtc_vblank_off()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030171327.29829-1-ville.syrjala@linux.intel.com?part=3

Re: [PATCH 09/10] drm/i915: Fix FEC wait with port sync on pre-LNL

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/ddi: LNL vs PTL version mismatch in FEC status wait comment and check
--

commit c0a68d9ab06674ed868f492b35dc93f1dc05b1bf
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915: Fix FEC wait with port sync on pre-LNL

This commit defers waiting for FEC status in intel_ddi_enable() until after
the timing generators have started, and adds a helper to wait for FEC status
across all synced transcoders when port sync is enabled.

> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9939fa43e8f73..2e7f278a1b6c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c

[ ... ]

> @@ -3623,6 +3654,16 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
>  	else
>  		intel_crtc_vblank_on(state, crtc_state);
>  
> +	/*
> +	 * On pre-LNL FEC_DECODE_EN will only be sent when the timing
> +	 * generator starts. Also note that FEC_DECODE_EN cannot be
> +	 * re-sent without restarting the timing generator.
> +	 */
> +	if (is_trans_port_sync_mode(crtc_state))
> +		trans_port_sync_wait_for_fec_status(state, encoder, crtc_state, true);
> +	else
> +		intel_ddi_wait_for_fec_status(encoder, crtc_state, true);

[Severity: Medium]
Should the comment here (and the commit message) refer to pre-PTL and PTL+
rather than pre-LNL and LNL+, or should the version check in
intel_ddi_enable_fec() be updated?

The commit message and the comment in intel_ddi_enable() state that on LNL+
FEC_DECODE_EN is sent immediately when enabling FEC in DP_TP_CTL, and that
LNL+ therefore checks FEC status immediately in intel_ddi_enable_fec() and
then a second time here in intel_ddi_enable().

However, intel_ddi_enable_fec() skips the immediate check and retry loop on
DISPLAY_VER < 30:

drivers/gpu/drm/i915/display/intel_ddi.c:intel_ddi_enable_fec() {
	...
	intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
		     0, DP_TP_CTL_FEC_ENABLE);

	if (DISPLAY_VER(display) < 30)
		return;

	ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
	...
}

Since LNL is DISPLAY_VER 20 and PTL is DISPLAY_VER 30, LNL returns early in
intel_ddi_enable_fec() without waiting for FEC status, and port sync is also
enabled up through DISPLAY_VER 20 in intel_ddi_port_sync_transcoders():

drivers/gpu/drm/i915/display/intel_ddi.c:intel_ddi_port_sync_transcoders() {
	/*
	 * We don't enable port sync on BDW due to missing w/as and
	 * due to not having adjusted the modeset sequence appropriately.
	 */
	if (!IS_DISPLAY_VER(display, 9, 20))
		return 0;
	...
}

Is intel_ddi_enable_fec() supposed to check DISPLAY_VER(display) < 20 for
LNL+, or was the description intended to say pre-PTL / PTL+?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030171327.29829-1-ville.syrjala@linux.intel.com?part=9

Re: [PATCH 06/10] drm/i915: Wait for timing generator to start in intel_crtc_vblank_on() on HSW+

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915: intel_pipe_vblank_on() scanline wait times out on DSI
--

commit a024447aed84d4ab8f0e7bb2ee11d21475e5b408
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915: Wait for timing generator to start in intel_crtc_vblank_on() on HSW+

This commit waits for the pipe scanline counter to start moving inside
intel_pipe_vblank_on() on Haswell and newer platforms before enabling
vblank interrupts.

> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index a28f4a088e587..209d5a18ee8d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -128,8 +128,21 @@ u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
>  
>  void intel_pipe_vblank_on(const struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
> +	/*
> +	 * Make sure the timing generator has really started so
> +	 * the sampled frame/scanline counter values don't jump
> +	 * erratically.
> +	 *
> +	 * TODO do this for older platforms as well after
> +	 * rearranging the modeset sequence a bit.
> +	 */
> +	if (DISPLAY_VER(display) >= 9 ||
> +	    display->platform.broadwell || display->platform.haswell)
> +		intel_wait_for_pipe_scanline_moving(crtc);

[Severity: Medium]
Will calling intel_wait_for_pipe_scanline_moving() unconditionally on
DISPLAY_VER(display) >= 9 time out for 100 ms and log a false error on
Broxton/Geminilake DSI and Gen11+ DSI command mode?

intel_wait_for_pipe_scanline_moving() calls wait_for_pipe_scanline_moving() ->
pipe_scanline_is_moving(), which directly polls PIPEDSL:

drivers/gpu/drm/i915/display/intel_vblank.c:pipe_scanline_is_moving() {
	intel_reg_t reg = PIPEDSL(display, pipe);
	u32 line1, line2;

	line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
	msleep(5);
	line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;

	return line1 != line2;
}

On Broxton (DISPLAY_VER 9) and Geminilake (DISPLAY_VER 10) MIPI DSI, timings
are driven from the port rather than the CPU transcoder, and PIPEDSL does not
increment. Because of this, intel_dsi_compute_config() and
bxt_dsi_get_pipe_config() set I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP, and
__intel_get_crtc_scanline() skips reading PIPEDSL:

drivers/gpu/drm/i915/display/intel_vblank.c:__intel_get_crtc_scanline() {
	if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
		return __intel_get_crtc_scanline_from_timestamp(crtc);

	vtotal = intel_mode_vtotal(mode);

	position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
	...
}

When bxt_dsi_enable() -> intel_crtc_vblank_on() -> intel_pipe_vblank_on() runs
(or during intel_modeset_setup_hw_state()), polling PIPEDSL will see a static
value and time out.

Similarly, on Gen11+ DSI command mode (where I915_MODE_FLAG_DSI_USE_TE0 or
I915_MODE_FLAG_DSI_USE_TE1 is set in crtc_state->mode_flags),
gen11_dsi_configure_transcoder() configures the transcoder in CMD_MODE_TE_GATE
without periodic updates. When gen11_dsi_enable() calls intel_crtc_vblank_on()
during intel_enable_crtc(), no frame update has been requested yet because
icl_dsi_frame_update() is only called later in intel_update_crtc() ->
intel_pipe_update_end():

drivers/gpu/drm/i915/display/intel_crtc.c:intel_pipe_update_end() {
	...
	if (DISPLAY_VER(display) >= 11 &&
	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
		icl_dsi_frame_update(new_crtc_state);
	...
}

Should intel_pipe_vblank_on() skip intel_wait_for_pipe_scanline_moving() when
crtc_state->mode_flags has I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP or
I915_MODE_FLAG_DSI_USE_TE0 / I915_MODE_FLAG_DSI_USE_TE1 set?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030171327.29829-1-ville.syrjala@linux.intel.com?part=6

Re: [PATCH 10/10] drm/i915: Allow joiner with port sync

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915: port sync dropped when joiner secondary CRTC triggers modeset
--

commit e8591be1b66ac026c8025978e792560a0337567b
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915: Allow joiner with port sync

This commit removes the check preventing pipes using joiner from entering
port sync mode now that modeset enable and disable sequences iterate in
pipe/transcoder order.

> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2e7f278a1b6c6..3be5b429ac876 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4675,14 +4675,8 @@ static bool m_n_equal(const struct intel_link_m_n *m_n_1,
>  static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
>  				       const struct intel_crtc_state *crtc_state2)
>  {
> -	/*
> -	 * FIXME the modeset sequence is currently wrong and
> -	 * can't deal with joiner + port sync at the same time.
> -	 *
> -	 * TODO VRR + port sync needs special handling
> -	 */
> +	/* TODO VRR + port sync needs special handling */
>  	return crtc_state1->hw.active && crtc_state2->hw.active &&
> -		!crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes &&

[Severity: High]
Can allowing joiner with port sync here cause port sync to be dropped when an
atomic commit triggers a modeset via a joiner secondary CRTC?

In drivers/gpu/drm/i915/display/intel_display.c:intel_atomic_check(),
drm_atomic_helper_check_modeset() runs connector atomic_check callbacks
before intel_atomic_check_config_and_link() pulls in joined CRTCs:

	ret = drm_atomic_helper_check_modeset(dev, &state->base);
	if (ret)
		goto fail;
	...
	ret = intel_atomic_check_config_and_link(state);

Suppose a joined CRTC pair (primary Pipe A and secondary Pipe B) is active in
port sync mode with a peer CRTC (Pipe C). If userspace submits an atomic
commit targeting the joiner secondary CRTC (Pipe B, which has uapi.enable ==
false and no uapi connectors) that sets uapi.mode_changed = true in
intel_atomic_check() (for example by changing scaling_filter,
sharpness_strength, or vrr_enabled, or clearing inherited on the first
userspace commit), drm_atomic_helper_check_modeset() runs while neither Pipe
A nor its connector is in the atomic state.

Later, intel_atomic_check_config_and_link() -> intel_atomic_check_config() ->
intel_joiner_add_affected_crtcs() adds Pipe A, sets Pipe A's
uapi.mode_changed = true, and adds Pipe A's connector:

	for_each_intel_crtc_in_pipe_mask(display, crtc, modeset_pipes) {
		int ret;

		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

		crtc_state->uapi.mode_changed = true;

		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);

Because drm_atomic_helper_check_modeset() has already finished,
intel_dp_connector_atomic_check() -> intel_modeset_tile_group() and
intel_modeset_synced_crtcs() never run for Pipe A's connector, so Pipe C and
its connector are never added to the atomic state.

When intel_modeset_pipe_config_late() -> intel_ddi_compute_config_late() ->
intel_ddi_port_sync_transcoders() subsequently iterates over connectors in
the atomic state:

	for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
		struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
		const struct intel_crtc_state *crtc_state;

it only sees Pipe A's connector, leaving master_transcoder =
INVALID_TRANSCODER and sync_mode_slaves_mask = 0 on Pipe A.

In intel_crtc_check_fastset(), intel_pipe_config_compare() then sees the
mismatch in master_transcoder or sync_mode_slaves_mask against old_crtc_state
and forces a full modeset on Pipe A and Pipe B without Pipe C in the commit.
If Pipe A was the port sync master, Pipe C's hardware transcoder remains
active and enslaved to TRANSCODER_A while TRANSCODER_A is disabled and
re-enabled, and bdw_get_trans_port_sync_config() during
intel_modeset_verify_crtc() reads back a non-zero sync_mode_slaves_mask,
triggering INTEL_DISPLAY_STATE_WARN in verify_crtc_state().

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030171327.29829-1-ville.syrjala@linux.intel.com?part=10

Re: [PATCH 03/10] drm/i915: Handle joined pipes inside intel_crtc_vblank_{on, off}()

[Ville Syrjälä]

On Fri, Oct 30, 2026 at 05:26:33PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] drm/i915: NULL state dereference in intel_crtc_vblank_off()
> --
> 
> commit c6499a1bf58e345d4e50ee3b23d7821c66712bdd
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> drm/i915: Handle joined pipes inside intel_crtc_vblank_{on, off}()
> 
> This commit moves the joined-pipe iteration into intel_crtc_vblank_on()
> and intel_crtc_vblank_off(), renaming the single-pipe helpers to
> intel_pipe_vblank_on() and intel_pipe_vblank_off(). Callers are updated to
> pass struct intel_atomic_state alongside the CRTC state.
> 
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index ea0cdb7822f39..381cdf7d5131c 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> 
> [ ... ]
> 
> > @@ -1455,7 +1455,7 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state,
> >  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> >  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> >  
> > -	intel_crtc_vblank_off(old_crtc_state);
> > +	intel_crtc_vblank_off(state, old_crtc_state);
> >  
> >  	/* step2d,e: disable transcoder and wait */
> >  	gen11_dsi_disable_transcoder(encoder);
> > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> > index 5b8968197fbcf..b814b84c650fd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> > @@ -265,7 +265,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
> >  	struct intel_display *display = to_intel_display(encoder);
> >  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> >  
> > -	intel_crtc_vblank_off(old_crtc_state);
> > +	intel_crtc_vblank_off(state, old_crtc_state);
> >  
> >  	intel_disable_transcoder(old_crtc_state);
> >  
> 
> [ ... ]
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 10ed9bdfee763..a28f4a088e587 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> 
> [ ... ]
> 
> > @@ -165,6 +165,34 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
> >  	flush_work(&display->irq.vblank_notify_work);
> >  }
> >  
> > +void intel_crtc_vblank_on(struct intel_atomic_state *state,
> > +			  const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_display *display = to_intel_display(state);
> > +	struct intel_crtc *pipe_crtc;
> > +
> > +	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
> > +		const struct intel_crtc_state *pipe_crtc_state =
> > +			intel_atomic_get_new_crtc_state(state, pipe_crtc);
> > +
> > +		intel_pipe_vblank_on(pipe_crtc_state);
> > +	}
> > +}
> > +
> > +void intel_crtc_vblank_off(struct intel_atomic_state *state,
> > +			   const struct intel_crtc_state *old_crtc_state)
> > +{
> > +	struct intel_display *display = to_intel_display(state);
> > +	struct intel_crtc *pipe_crtc;
> > +
> > +	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) {
> > +		const struct intel_crtc_state *old_pipe_crtc_state =
> > +			intel_atomic_get_old_crtc_state(state, pipe_crtc);
> > +
> > +		intel_pipe_vblank_off(old_pipe_crtc_state);
> > +	}
> > +}
> 
> [Severity: High]
> Can state be NULL when intel_crtc_vblank_off() is called from
> encoder->post_disable()?
> 
> During initial hardware readout or resume in
> intel_modeset_setup_hw_state(), intel_sanitize_encoder() disables an
> encoder whose connector is active while its pipe is inactive by invoking
> the disable hooks with a NULL atomic state:
> 
> drivers/gpu/drm/i915/display/intel_modeset_setup.c:intel_sanitize_encoder() {
> 	...
> 	if (connector && !has_active_crtc) {
> 		...
> 		if (crtc_state) {
> 			...
> 			/* FIXME NULL atomic state passed! */
> 			if (encoder->disable)
> 				encoder->disable(NULL, encoder, crtc_state,
> 						 connector->base.state);
> 			if (encoder->post_disable)
> 				encoder->post_disable(NULL, encoder, crtc_state,
> 						      connector->base.state);
> 		}
> 	}
> }
> 
> Previously, gen11_dsi_post_disable(), intel_dsi_post_disable() (on
> Broxton and Geminilake), and hsw_post_disable_crt() did not dereference
> state and passed old_crtc_state directly to intel_crtc_vblank_off(). With
> this change, those callbacks pass state = NULL to intel_crtc_vblank_off(),
> which dereferences state in both to_intel_display(state) and
> intel_atomic_get_old_crtc_state(state, pipe_crtc).
> 
> Would it make sense to keep using intel_pipe_vblank_off(old_crtc_state) in
> the non-joiner post_disable callbacks, or handle a NULL state inside
> intel_crtc_vblank_off()?

I thought about it but apparently forgot to note it in the commit
message; My conclusion was that the encoder sanitize stuff should
never happen on the platforms where we do the vblank_off() from the
encoder hooks. On earlier platforms the vblank_off() is in
.crtc_disable() and intel_crtc_disable_noatomic_begin() creates
a temporary atomic state for that.

I've also occasionally pondered about creating a temporary
atomic state for intel_sanitize_encoder() as well, just to get
rid of even the theoretical possibility of a NULL state. But
that would probably involve some actual thinking...

-- 
Ville Syrjälä
Intel

✓ Xe.CI.BAT: success for drm/i915: Enable vblanks after the timing generator has started

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1450 bytes --]

== Series Details ==

Series: drm/i915: Enable vblanks after the timing generator has started
URL   : https://patchwork.freedesktop.org/series/177276/
State : success

== Summary ==

CI Bug Log - changes from xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6_BAT -> xe-pw-177276v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-177276v1_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-bmg-2:          [ABORT][1] ([Intel XE#9463]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177276v1/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html

  
  [Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463


Build changes
-------------

  * Linux: xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6 -> xe-pw-177276v1

  IGT_9173: 9173
  xe-6036-238c1e3e984e2b7f948cb24165314b8d719a23d6: 238c1e3e984e2b7f948cb24165314b8d719a23d6
  xe-pw-177276v1: 177276v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177276v1/index.html

[-- Attachment #2: Type: text/html, Size: 2015 bytes --]

✓ i915.CI.BAT: success for drm/i915: Enable vblanks after the timing generator has started

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1552 bytes --]

== Series Details ==

Series: drm/i915: Enable vblanks after the timing generator has started
URL   : https://patchwork.freedesktop.org/series/177275/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_19420 -> Patchwork_177275v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_177275v1/index.html

Participating hosts (40 -> 38)
------------------------------

  Missing    (2): bat-dg2-13 bat-adls-6 

Known issues
------------

  Here are the changes found in Patchwork_177275v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-rpls-4:         [PASS][1] -> [DMESG-WARN][2] ([i915#13400])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19420/bat-rpls-4/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_177275v1/bat-rpls-4/igt@core_hotunplug@unbind-rebind.html

  
  [i915#13400]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13400


Build changes
-------------

  * Linux: CI_DRM_19420 -> Patchwork_177275v1

  CI-20190529: 20190529
  CI_DRM_19420: 238c1e3e984e2b7f948cb24165314b8d719a23d6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9172: 9172
  Patchwork_177275v1: 238c1e3e984e2b7f948cb24165314b8d719a23d6 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_177275v1/index.html

[-- Attachment #2: Type: text/html, Size: 2137 bytes --]

Re: [PATCH 06/10] drm/i915: Wait for timing generator to start in intel_crtc_vblank_on() on HSW+

[Ville Syrjälä]

On Fri, Oct 30, 2026 at 05:32:47PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] drm/i915: intel_pipe_vblank_on() scanline wait times out on DSI
> --
> 
> commit a024447aed84d4ab8f0e7bb2ee11d21475e5b408
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> drm/i915: Wait for timing generator to start in intel_crtc_vblank_on() on HSW+
> 
> This commit waits for the pipe scanline counter to start moving inside
> intel_pipe_vblank_on() on Haswell and newer platforms before enabling
> vblank interrupts.
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index a28f4a088e587..209d5a18ee8d9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -128,8 +128,21 @@ u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
> >  
> >  void intel_pipe_vblank_on(const struct intel_crtc_state *crtc_state)
> >  {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  
> > +	/*
> > +	 * Make sure the timing generator has really started so
> > +	 * the sampled frame/scanline counter values don't jump
> > +	 * erratically.
> > +	 *
> > +	 * TODO do this for older platforms as well after
> > +	 * rearranging the modeset sequence a bit.
> > +	 */
> > +	if (DISPLAY_VER(display) >= 9 ||
> > +	    display->platform.broadwell || display->platform.haswell)
> > +		intel_wait_for_pipe_scanline_moving(crtc);
> 
> [Severity: Medium]
> Will calling intel_wait_for_pipe_scanline_moving() unconditionally on
> DISPLAY_VER(display) >= 9 time out for 100 ms and log a false error on
> Broxton/Geminilake DSI and Gen11+ DSI command mode?
> 
> intel_wait_for_pipe_scanline_moving() calls wait_for_pipe_scanline_moving() ->
> pipe_scanline_is_moving(), which directly polls PIPEDSL:
> 
> drivers/gpu/drm/i915/display/intel_vblank.c:pipe_scanline_is_moving() {
> 	intel_reg_t reg = PIPEDSL(display, pipe);
> 	u32 line1, line2;
> 
> 	line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
> 	msleep(5);
> 	line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
> 
> 	return line1 != line2;
> }
> 
> On Broxton (DISPLAY_VER 9) and Geminilake (DISPLAY_VER 10) MIPI DSI, timings
> are driven from the port rather than the CPU transcoder, and PIPEDSL does not
> increment. Because of this, intel_dsi_compute_config() and
> bxt_dsi_get_pipe_config() set I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP, and
> __intel_get_crtc_scanline() skips reading PIPEDSL:
> 
> drivers/gpu/drm/i915/display/intel_vblank.c:__intel_get_crtc_scanline() {
> 	if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
> 		return __intel_get_crtc_scanline_from_timestamp(crtc);
> 
> 	vtotal = intel_mode_vtotal(mode);
> 
> 	position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
> 	...
> }
> 
> When bxt_dsi_enable() -> intel_crtc_vblank_on() -> intel_pipe_vblank_on() runs
> (or during intel_modeset_setup_hw_state()), polling PIPEDSL will see a static
> value and time out.
> 
> Similarly, on Gen11+ DSI command mode (where I915_MODE_FLAG_DSI_USE_TE0 or
> I915_MODE_FLAG_DSI_USE_TE1 is set in crtc_state->mode_flags),
> gen11_dsi_configure_transcoder() configures the transcoder in CMD_MODE_TE_GATE
> without periodic updates. When gen11_dsi_enable() calls intel_crtc_vblank_on()
> during intel_enable_crtc(), no frame update has been requested yet because
> icl_dsi_frame_update() is only called later in intel_update_crtc() ->
> intel_pipe_update_end():
> 
> drivers/gpu/drm/i915/display/intel_crtc.c:intel_pipe_update_end() {
> 	...
> 	if (DISPLAY_VER(display) >= 11 &&
> 	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
> 		icl_dsi_frame_update(new_crtc_state);
> 	...
> }
> 
> Should intel_pipe_vblank_on() skip intel_wait_for_pipe_scanline_moving() when
> crtc_state->mode_flags has I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP or
> I915_MODE_FLAG_DSI_USE_TE0 / I915_MODE_FLAG_DSI_USE_TE1 set?

DSI, sigh. 

I suppose for I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP we could
just wait for the frame timestamp to change. Or perhaps even use
that approach unconditionally for all platforms that have frame
timestamps. But I'll probably need to reverse engineer the actual
behavior of the frame timestamp during timing generator startup...

For now I guess I could just skip this for anything where
the scanline counter supposedly doesn't work.

-- 
Ville Syrjälä
Intel

Re: [PATCH 10/10] drm/i915: Allow joiner with port sync

[Ville Syrjälä]

On Fri, Oct 30, 2026 at 05:38:58PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] drm/i915: port sync dropped when joiner secondary CRTC triggers modeset
> --
> 
> commit e8591be1b66ac026c8025978e792560a0337567b
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> drm/i915: Allow joiner with port sync
> 
> This commit removes the check preventing pipes using joiner from entering
> port sync mode now that modeset enable and disable sequences iterate in
> pipe/transcoder order.
> 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 2e7f278a1b6c6..3be5b429ac876 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4675,14 +4675,8 @@ static bool m_n_equal(const struct intel_link_m_n *m_n_1,
> >  static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
> >  				       const struct intel_crtc_state *crtc_state2)
> >  {
> > -	/*
> > -	 * FIXME the modeset sequence is currently wrong and
> > -	 * can't deal with joiner + port sync at the same time.
> > -	 *
> > -	 * TODO VRR + port sync needs special handling
> > -	 */
> > +	/* TODO VRR + port sync needs special handling */
> >  	return crtc_state1->hw.active && crtc_state2->hw.active &&
> > -		!crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes &&
> 
> [Severity: High]
> Can allowing joiner with port sync here cause port sync to be dropped when an
> atomic commit triggers a modeset via a joiner secondary CRTC?
> 
> In drivers/gpu/drm/i915/display/intel_display.c:intel_atomic_check(),
> drm_atomic_helper_check_modeset() runs connector atomic_check callbacks
> before intel_atomic_check_config_and_link() pulls in joined CRTCs:
> 
> 	ret = drm_atomic_helper_check_modeset(dev, &state->base);
> 	if (ret)
> 		goto fail;
> 	...
> 	ret = intel_atomic_check_config_and_link(state);
> 
> Suppose a joined CRTC pair (primary Pipe A and secondary Pipe B) is active in
> port sync mode with a peer CRTC (Pipe C). If userspace submits an atomic
> commit targeting the joiner secondary CRTC (Pipe B, which has uapi.enable ==
> false and no uapi connectors) that sets uapi.mode_changed = true in
> intel_atomic_check() (for example by changing scaling_filter,
> sharpness_strength, or vrr_enabled, or clearing inherited on the first
> userspace commit), drm_atomic_helper_check_modeset() runs while neither Pipe
> A nor its connector is in the atomic state.
> 
> Later, intel_atomic_check_config_and_link() -> intel_atomic_check_config() ->
> intel_joiner_add_affected_crtcs() adds Pipe A, sets Pipe A's
> uapi.mode_changed = true, and adds Pipe A's connector:
> 
> 	for_each_intel_crtc_in_pipe_mask(display, crtc, modeset_pipes) {
> 		int ret;
> 
> 		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> 
> 		crtc_state->uapi.mode_changed = true;
> 
> 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
> 
> Because drm_atomic_helper_check_modeset() has already finished,
> intel_dp_connector_atomic_check() -> intel_modeset_tile_group() and
> intel_modeset_synced_crtcs() never run for Pipe A's connector, so Pipe C and
> its connector are never added to the atomic state.
> 
> When intel_modeset_pipe_config_late() -> intel_ddi_compute_config_late() ->
> intel_ddi_port_sync_transcoders() subsequently iterates over connectors in
> the atomic state:
> 
> 	for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
> 		struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
> 		const struct intel_crtc_state *crtc_state;
> 
> it only sees Pipe A's connector, leaving master_transcoder =
> INVALID_TRANSCODER and sync_mode_slaves_mask = 0 on Pipe A.
> 
> In intel_crtc_check_fastset(), intel_pipe_config_compare() then sees the
> mismatch in master_transcoder or sync_mode_slaves_mask against old_crtc_state
> and forces a full modeset on Pipe A and Pipe B without Pipe C in the commit.
> If Pipe A was the port sync master, Pipe C's hardware transcoder remains
> active and enslaved to TRANSCODER_A while TRANSCODER_A is disabled and
> re-enabled, and bdw_get_trans_port_sync_config() during
> intel_modeset_verify_crtc() reads back a non-zero sync_mode_slaves_mask,
> triggering INTEL_DISPLAY_STATE_WARN in verify_crtc_state().

Hmm, I think this could even happen without joiner, if the
connectors' tile groups have somehow changed so that they
no longer match.

I suppose what we actually need is a port_sync_add_affected_crtcs().
Need to think if I can do that without causing extra fastsets on
all the synced crtcs when one of them needs a fastset...

-- 
Ville Syrjälä
Intel