[PATCH 0/4] drm/msm/a6xx: Fixes for a680 (SC8180X)

[PATCH 0/4] drm/msm/a6xx: Fixes for a680 (SC8180X)

[Val Packett]

This series includes:

* the missing gbif_cx sequence patch that's been around in a
  Surface Pro X downstream WIP tree for a while;
* new fresh patch based on a (rather slop-py but valid) comment
  on my report about Vulkan texture corruption:
  https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15349
  GMEM starting at 0 did fix it here;
* an import of the hwcg sequence from downstream (kgsl) which
  is just-in-case more than anything, feel free to skip it if
  it's not actually the right thing to do.

Thanks,
~val

Maximilian Luz (1):
  drm/msm/a6xx: Restore GBIF CX config for A640 family

Val Packett (3):
  drm/msm/a6xx: Fix GMEM range on a680
  drm/msm/a6xx: Add GMU_SP_RF_CONTROL registers
  drm/msm/a6xx: Import a680 hwcg sequence from kgsl

 drivers/gpu/drm/msm/adreno/a6xx_catalog.c     | 58 ++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c         |  7 ++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c       |  3 +-
 .../gpu/drm/msm/registers/adreno/a6xx_gmu.xml |  2 +
 4 files changed, 66 insertions(+), 4 deletions(-)

-- 
2.56.0

[PATCH 1/4] drm/msm/a6xx: Restore GBIF CX config for A640 family

[Val Packett]

From: Maximilian Luz <luzmaximilian@gmail.com>

Commit 60a4e18e0e8a ("drm/msm/adreno: Do CX GBIF config before GMU
start") moved the GBIF_QSB_SIDE{0..3} configuration from hw_init() to
the per-GPU catalog entries. Previously, it was applied to all GPUs of
the A610, A640, and A650 families as well as A7xx. However, the A640
family entries (A640 and A680) were not updated with the new gbif_cx
list, so the configuration is no longer applied on these GPUs.

On the Surface Pro X (SC8180X, A680), this results in GMU HFI timeouts
(e.g. for HFI_H2F_MSG_GX_BW_PERF_VOTE) and GPU lockups shortly after
starting a desktop session.

Add the missing gbif_cx entries to restore the previous behavior.

Fixes: 60a4e18e0e8a ("drm/msm/adreno: Do CX GBIF config before GMU start")
Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com>
Signed-off-by: Val Packett <val@packett.cool>
---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 4ef2bd6e7ad2..6c154792cb07 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1041,6 +1041,7 @@ static const struct adreno_info a6xx_gpus[] = {
 		.a6xx = &(const struct a6xx_info) {
 			.hwcg = a640_hwcg,
 			.protect = &a630_protect,
+			.gbif_cx = a640_gbif,
 			.gmu_cgc_mode = 0x00020202,
 			.prim_fifo_threshold = 0x00180000,
 		},
@@ -1164,6 +1165,7 @@ static const struct adreno_info a6xx_gpus[] = {
 		.a6xx = &(const struct a6xx_info) {
 			.hwcg = a640_hwcg,
 			.protect = &a630_protect,
+			.gbif_cx = a640_gbif,
 			.gmu_cgc_mode = 0x00020202,
 			.prim_fifo_threshold = 0x00200200,
 		},
-- 
2.56.0

[PATCH 2/4] drm/msm/a6xx: Fix GMEM range on a680

[Val Packett]

On a680, the GMEM range starts at 0, like on newer generations.
Trying to use the 1M value results in texture corruption in Vulkan.
Fix the wrong range by introducing checks specific to this model.

Link: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15349
Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Signed-off-by: Val Packett <val@packett.cool>
---
I have tried adding it to the if (!(..)) condition i.e. not
touching the REG_A6XX_UCHE_GMEM_RANGE_* at all -- that just
made launching gtk4-demo instantly hang the system..

So the only thing that works and solves the issue
is actually writing the zero for the start.
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 7 +++++--
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 3e4afaa5345f..26440a3ccecb 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1279,8 +1279,11 @@ static int hw_init(struct msm_gpu *gpu)
 	if (!(adreno_is_a650_family(adreno_gpu) ||
 	      adreno_is_a702(adreno_gpu) ||
 	      adreno_is_a730(adreno_gpu))) {
-		gmem_range_min = (adreno_is_a740_family(adreno_gpu) ||
-				  adreno_is_a722(adreno_gpu)) ? SZ_16M : SZ_1M;
+		gmem_range_min = SZ_1M;
+		if (adreno_is_a740_family(adreno_gpu) || adreno_is_a722(adreno_gpu))
+			gmem_range_min = SZ_16M;
+		else if (adreno_is_a680(adreno_gpu))
+			gmem_range_min = 0;
 
 		/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
 		gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index dadfe4c69438..67bd66c78424 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -382,7 +382,8 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
 		*value = adreno_gpu->gmem;
 		return 0;
 	case MSM_PARAM_GMEM_BASE:
-		if (adreno_gpu->info->family >= ADRENO_6XX_GEN3)
+		if (adreno_gpu->info->family >= ADRENO_6XX_GEN3 ||
+		    adreno_is_a680(adreno_gpu))
 			*value = 0;
 		else
 			*value = 0x100000;
-- 
2.56.0

[PATCH 3/4] drm/msm/a6xx: Add GMU_SP_RF_CONTROL registers

[Val Packett]

These registers are used in the a680 hwcg init sequence downstream.
Add them to the XML register list in preparation for importing said
sequence.

Signed-off-by: Val Packett <val@packett.cool>
---
 drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
index 786fd7d2f674..11d57cb52ede 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
@@ -42,6 +42,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
 
 	<reg32 offset="0x1a880" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
 	<reg32 offset="0x1a881" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
+	<reg32 offset="0x1a883" name="GMU_GX_GMU_SP_RF_CONTROL_0"/>
+	<reg32 offset="0x1a884" name="GMU_GX_GMU_SP_RF_CONTROL_1"/>
 	<reg32 offset="0x1b400" name="GMU_CM3_ITCM_START"/>
 	<reg32 offset="0x1c400" name="GMU_CM3_DTCM_START"/>
 	<reg32 offset="0x1cbf0" name="GMU_NMI_CONTROL_STATUS"/>
-- 
2.56.0

[PATCH 4/4] drm/msm/a6xx: Import a680 hwcg sequence from kgsl

[Val Packett]

The initialization sequence for a680 differs from a640 in a few places.
Match downstream by using this a680 specific one.

Signed-off-by: Val Packett <val@packett.cool>
---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 56 ++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 6c154792cb07..48197a54984c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -9,6 +9,7 @@
 #include "adreno_gpu.h"
 #include "a6xx_gpu.h"
 #include "a6xx.xml.h"
+#include "a6xx_gmu.xml.h"
 
 static const struct adreno_reglist a612_hwcg[] = {
 	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
@@ -449,6 +450,59 @@ static const struct adreno_reglist a660_hwcg[] = {
 	{},
 };
 
+static const struct adreno_reglist a680_hwcg[] = {
+	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+	{REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+	{REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+	{REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+	{REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+	{REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+	{REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+	{REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+	{REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+	{REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+	{REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+	{REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
+	{REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+	{REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+	{REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+	{REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+	{REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+	{REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+	{REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+	{REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+	{REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+	{REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+	{REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+	{REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+	{REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+	{REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+	{REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
+	{REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+	{REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+	{REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+	{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+	{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+	{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+	{REG_A6XX_GMU_GX_GMU_SP_RF_CONTROL_0, 0x00000001},
+	{REG_A6XX_GMU_GX_GMU_SP_RF_CONTROL_1, 0x00000001},
+	{},
+};
+
 static const struct adreno_reglist a690_hwcg[] = {
 	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
 	{REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
@@ -1163,7 +1217,7 @@ static const struct adreno_info a6xx_gpus[] = {
 		.funcs = &a6xx_gpu_funcs,
 		.zapfw = "a640_zap.mdt",
 		.a6xx = &(const struct a6xx_info) {
-			.hwcg = a640_hwcg,
+			.hwcg = a680_hwcg,
 			.protect = &a630_protect,
 			.gbif_cx = a640_gbif,
 			.gmu_cgc_mode = 0x00020202,
-- 
2.56.0

Re: [PATCH 4/4] drm/msm/a6xx: Import a680 hwcg sequence from kgsl

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/msm/a6xx: out-of-bounds gpu_write() on GMU registers in a680_hwcg
--

commit f29e5fbd58a4870ae3b815aaaebc1ea0d6ff115a
Author: Val Packett <val@packett.cool>

drm/msm/a6xx: Import a680 hwcg sequence from kgsl

This commit adds an a680_hwcg register table imported from downstream kgsl
and wires it up to the Adreno 680 GPU catalog entry in place of a640_hwcg.

> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 6c154792cb077..48197a54984cf 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -9,6 +9,7 @@
>  #include "adreno_gpu.h"
>  #include "a6xx_gpu.h"
>  #include "a6xx.xml.h"
> +#include "a6xx_gmu.xml.h"
>  
>  static const struct adreno_reglist a612_hwcg[] = {
>  	{REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
> @@ -449,6 +450,59 @@ static const struct adreno_reglist a660_hwcg[] = {
>  	{},
>  };
>  
> +static const struct adreno_reglist a680_hwcg[] = {

[ ... ]

> +	{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
> +	{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
> +	{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
> +	{REG_A6XX_GMU_GX_GMU_SP_RF_CONTROL_0, 0x00000001},
> +	{REG_A6XX_GMU_GX_GMU_SP_RF_CONTROL_1, 0x00000001},

[Severity: High]
Does placing REG_A6XX_GMU_GX_GMU_SP_RF_CONTROL_0 and
REG_A6XX_GMU_GX_GMU_SP_RF_CONTROL_1 into a680_hwcg cause an out-of-bounds
MMIO write past the end of gpu->mmio?

During GPU initialization and suspend (via hw_init() -> a6xx_set_hwcg() and
a6xx_pm_suspend() -> a6xx_set_hwcg()), every entry in the hwcg table is
programmed using gpu_write():

drivers/gpu/drm/msm/adreno/a6xx_gpu.c:a6xx_set_hwcg() {
	...
	for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++)
		gpu_write(gpu, reg->offset, state ? reg->value : 0);
	...
}

In drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml, these two registers are
GMU registers at dword offsets 0x1a883 and 0x1a884 (byte offsets 0x6a20c and
0x6a210 from the GPU base address).

Unlike downstream kgsl, upstream maps the GPU and GMU register spaces
separately. In arch/arm64/boot/dts/qcom/sc8180x.dtsi, the gpu@2c00000 node's
kgsl_3d0_reg_memory region mapped into gpu->mmio is only 0x40000 bytes:

	gpu@2c00000 {
		...
		reg = <0 0x02c00000 0 0x40000>;
		reg-names = "kgsl_3d0_reg_memory";

while the GMU registers at 0x02c6a000 are mapped separately into gmu->mmio by
gmu@2c6a000 and accessed via gmu_write(), which subtracts gmu->mmio_offset
(0x6a000):

drivers/gpu/drm/msm/adreno/a6xx_gmu.h:
#define GMU_BYTE_OFFSET(gmu, offset) (((offset) << 2) - (gmu)->mmio_offset)
...
static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
{
	writel(value, gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));
}

When a6xx_set_hwcg() calls gpu_write() with offsets 0x1a883 and 0x1a884, it
writes to gpu->mmio + 0x6a20c and gpu->mmio + 0x6a210, which is 0x2a20c bytes
past the end of the 0x40000-byte gpu->mmio mapping. Should these GMU register
writes be routed through gmu_write() instead of gpu_write()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261103011358.65398-1-val@packett.cool?part=4

Re: [PATCH 4/4] drm/msm/a6xx: Import a680 hwcg sequence from kgsl

[Val Packett]

On 11/2/26 10:13 PM, Val Packett wrote:

> The initialization sequence for a680 differs from a640 in a few places.
> Match downstream by using this a680 specific one.
>
> Signed-off-by: Val Packett <val@packett.cool>
> ---
>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 56 ++++++++++++++++++++++-
>   1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 6c154792cb07..48197a54984c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -9,6 +9,7 @@
>   #include "adreno_gpu.h"
>   #include "a6xx_gpu.h"
>   #include "a6xx.xml.h"
> +#include "a6xx_gmu.xml.h"
>   [..]

(As sashiko confirms it's not a good idea to try to write the gmu regs 
from here, shouldn't've gotten lazy and assumed it would work anyway..)

I can make the gmu driver write these on init, but would like to know if 
they even do anything interesting, and whether the entire hwcg sequence 
is worth it…

Re: [PATCH 1/4] drm/msm/a6xx: Restore GBIF CX config for A640 family

[Konrad Dybcio]

On 11/3/26 2:13 AM, Val Packett wrote:
> From: Maximilian Luz <luzmaximilian@gmail.com>
> 
> Commit 60a4e18e0e8a ("drm/msm/adreno: Do CX GBIF config before GMU
> start") moved the GBIF_QSB_SIDE{0..3} configuration from hw_init() to
> the per-GPU catalog entries. Previously, it was applied to all GPUs of
> the A610, A640, and A650 families as well as A7xx. However, the A640
> family entries (A640 and A680) were not updated with the new gbif_cx
> list, so the configuration is no longer applied on these GPUs.
> 
> On the Surface Pro X (SC8180X, A680), this results in GMU HFI timeouts
> (e.g. for HFI_H2F_MSG_GX_BW_PERF_VOTE) and GPU lockups shortly after
> starting a desktop session.
> 
> Add the missing gbif_cx entries to restore the previous behavior.
> 
> Fixes: 60a4e18e0e8a ("drm/msm/adreno: Do CX GBIF config before GMU start")
> Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com>
> Signed-off-by: Val Packett <val@packett.cool>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 4/4] drm/msm/a6xx: Import a680 hwcg sequence from kgsl

[Rob Clark]

On Mon, Nov 2, 2026 at 5:39 PM Val Packett <val@packett.cool> wrote:
>
> On 11/2/26 10:13 PM, Val Packett wrote:
>
> > The initialization sequence for a680 differs from a640 in a few places.
> > Match downstream by using this a680 specific one.
> >
> > Signed-off-by: Val Packett <val@packett.cool>
> > ---
> >   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 56 ++++++++++++++++++++++-
> >   1 file changed, 55 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > index 6c154792cb07..48197a54984c 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> > @@ -9,6 +9,7 @@
> >   #include "adreno_gpu.h"
> >   #include "a6xx_gpu.h"
> >   #include "a6xx.xml.h"
> > +#include "a6xx_gmu.xml.h"
> >   [..]
>
> (As sashiko confirms it's not a good idea to try to write the gmu regs
> from here, shouldn't've gotten lazy and assumed it would work anyway..)
>
> I can make the gmu driver write these on init, but would like to know if
> they even do anything interesting, and whether the entire hwcg sequence
> is worth it…

vaguely related to [1].. I guess I'd suggest to do something like that
for now.  Longer term still tbd but dt gmu vs gpu split makes tables
generated from hw view of the world run into these quirks.  Longer
term we'll do something to clean this up, but not sure which route yet

BR,
-R

[1] https://patchwork.freedesktop.org/patch/767327/?series=176505&rev=7