* [PATCH v3 0/5] drm/imagination: RISC-V and META firmware interface updates
@ 2026-11-03 8:36 ` Alexandru Dadu
0 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu,
Matt Coster
Refactor RISC-V and META firmware interface headers to have a more
generic and architecture independent approach:
1. Limits access to the RISC-V and META firmware respective interfaces.
2. Aligns RISC-V and META firmware headers with the other processor
headers.
3. Add "_fw_" component to the headers filename.
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
Changes in v3:
- Fixed remarks raised by Sashiko in pvr_fw_startstop.c.
- Link to v2: https://patch.msgid.link/20261029-prep-meta-fw-arch-independent-v2-0-b9f5d69b7a52@imgtec.com
Changes in v2:
- Update the commit messages to better describe the changes.
- Link to v1: https://patch.msgid.link/20261028-prep-meta-fw-arch-independent-v1-0-73e116f02172@imgtec.com
To: Alessio Belle <alessio.belle@imgtec.com>
To: Luigi Santivetti <luigi.santivetti@imgtec.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: Maxime Ripard <mripard@kernel.org>
To: Thomas Zimmermann <tzimmermann@suse.de>
To: David Airlie <airlied@gmail.com>
To: Simona Vetter <simona@ffwll.ch>
To: Paul Walmsley <pjw@kernel.org>
To: Palmer Dabbelt <palmer@dabbelt.com>
To: Albert Ou <aou@eecs.berkeley.edu>
To: Alexandre Ghiti <alex@ghiti.fr>
Cc: imagination@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
---
Alessio Belle (4):
drm/imagination: Limit access to the RISC-V firmware interface
drm/imagination: Make the RISC-V firmware header arch-independent
drm/imagination: Limit access to the META firmware interface
drm/imagination: Make the META firmware header arch-independent
Alexandru Dadu (1):
drm/imagination: Prepare heap config header for multi-arch support
drivers/gpu/drm/imagination/pvr_fw.c | 7 +-
drivers/gpu/drm/imagination/pvr_fw.h | 26 +++
drivers/gpu/drm/imagination/pvr_fw_meta.c | 104 +++++++-----
drivers/gpu/drm/imagination/pvr_fw_meta.h | 14 --
.../{pvr_rogue_meta.h => pvr_fw_meta_internal.h} | 175 +++++++++++----------
drivers/gpu/drm/imagination/pvr_fw_mips.c | 1 +
drivers/gpu/drm/imagination/pvr_fw_riscv.c | 13 +-
.../gpu/drm/imagination/pvr_fw_riscv_internal.h | 43 +++++
drivers/gpu/drm/imagination/pvr_fw_startstop.c | 61 +++----
drivers/gpu/drm/imagination/pvr_gem.h | 3 +-
.../{pvr_rogue_heap_config.h => pvr_heap_config.h} | 26 +--
drivers/gpu/drm/imagination/pvr_rogue_riscv.h | 39 -----
drivers/gpu/drm/imagination/pvr_vm.c | 18 +--
13 files changed, 289 insertions(+), 241 deletions(-)
---
base-commit: 6e375de99d0c420169481fcd36064177ab55b09d
change-id: 20261028-prep-meta-fw-arch-independent-ffd6dcd626d0
Best regards,
--
Alexandru Dadu <alexandru.dadu@imgtec.com>
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 1/5] drm/imagination: Prepare heap config header for multi-arch support
2026-11-03 8:36 ` Alexandru Dadu
@ 2026-11-03 8:36 ` Alexandru Dadu
-1 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu
Update the name of pvr_rogue_heap_config.h to pvr_heap_config.h to
prepare it for a more generic implementation that will have memory
sections defined for multiple GPU architectures.
Update the multi-arch common define names to a generic format.
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw.c | 7 +++---
drivers/gpu/drm/imagination/pvr_gem.h | 2 +-
.../{pvr_rogue_heap_config.h => pvr_heap_config.h} | 26 +++++++++++-----------
drivers/gpu/drm/imagination/pvr_vm.c | 18 +++++++--------
4 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c
index c6c77b152342..4d5df5272f46 100644
--- a/drivers/gpu/drm/imagination/pvr_fw.c
+++ b/drivers/gpu/drm/imagination/pvr_fw.c
@@ -9,9 +9,8 @@
#include "pvr_fw_startstop.h"
#include "pvr_fw_trace.h"
#include "pvr_gem.h"
+#include "pvr_heap_config.h"
#include "pvr_power.h"
-#include "pvr_rogue_fwif_dev_info.h"
-#include "pvr_rogue_heap_config.h"
#include "pvr_vm.h"
#include <drm/drm_drv.h>
@@ -372,8 +371,8 @@ fw_sysinit_init(void *cpu_ptr, void *priv)
WARN_ON(pvr_fw_object_get_dma_addr(fw_mem->fault_page_obj, 0, &fault_dma_addr));
fwif_sysinit->fault_phys_addr = (u64)fault_dma_addr;
- fwif_sysinit->pds_exec_base = ROGUE_PDSCODEDATA_HEAP_BASE;
- fwif_sysinit->usc_exec_base = ROGUE_USCCODE_HEAP_BASE;
+ fwif_sysinit->pds_exec_base = PVR_PDSCODEDATA_HEAP_BASE;
+ fwif_sysinit->usc_exec_base = PVR_USCCODE_HEAP_BASE;
pvr_fw_object_get_fw_addr(fw_mem->runtime_cfg_obj, &fwif_sysinit->runtime_cfg_fw_addr);
pvr_fw_object_get_fw_addr(fw_dev->fw_trace.tracebuf_ctrl_obj,
diff --git a/drivers/gpu/drm/imagination/pvr_gem.h b/drivers/gpu/drm/imagination/pvr_gem.h
index 4286e047ae24..ae7af82b6f17 100644
--- a/drivers/gpu/drm/imagination/pvr_gem.h
+++ b/drivers/gpu/drm/imagination/pvr_gem.h
@@ -4,7 +4,7 @@
#ifndef PVR_GEM_H
#define PVR_GEM_H
-#include "pvr_rogue_heap_config.h"
+#include "pvr_heap_config.h"
#include "pvr_rogue_meta.h"
#include <uapi/drm/pvr_drm.h>
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h b/drivers/gpu/drm/imagination/pvr_heap_config.h
similarity index 85%
rename from drivers/gpu/drm/imagination/pvr_rogue_heap_config.h
rename to drivers/gpu/drm/imagination/pvr_heap_config.h
index 5c33b342dda5..280bf1ed523b 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h
+++ b/drivers/gpu/drm/imagination/pvr_heap_config.h
@@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
-#ifndef PVR_ROGUE_HEAP_CONFIG_H
-#define PVR_ROGUE_HEAP_CONFIG_H
+#ifndef PVR_HEAP_CONFIG_H
+#define PVR_HEAP_CONFIG_H
#include <linux/sizes.h>
@@ -14,7 +14,7 @@
* fits into this, but the firmware heap is only ever created in the
* kernel driver and never exposed to userspace.
*
- * ROGUE_PDSCODEDATA_HEAP_BASE and ROGUE_USCCODE_HEAP_BASE will be programmed,
+ * PVR_PDSCODEDATA_HEAP_BASE and PVR_USCCODE_HEAP_BASE will be programmed,
* on a global basis, into ROGUE_CR_PDS_EXEC_BASE and ROGUE_CR_USC_CODE_BASE_*
* respectively. Therefore if client drivers use multiple configs they must
* still be consistent with their definitions for these heaps.
@@ -38,9 +38,9 @@
/* 0x80_0000_0000 ************************************************************/
/* 0x80_0000_0000 - 0x9F_FFFF_FFFF **/
-/* 512 GiB to 640 GiB, size of 128 GiB : GENERAL_HEAP */
-#define ROGUE_GENERAL_HEAP_BASE 0x8000000000ull
-#define ROGUE_GENERAL_HEAP_SIZE SZ_128G
+/* 512 GiB to 640 GiB, size of 128 GiB : GENERAL_HEAP **/
+#define PVR_GENERAL_HEAP_BASE 0x8000000000ull
+#define PVR_GENERAL_HEAP_SIZE SZ_128G
/* 0xA0_0000_0000 - 0xAF_FFFF_FFFF */
/* 640 GiB to 704 GiB, size of 64 GiB : FREE */
@@ -58,8 +58,8 @@
/* 0xDA_0000_0000 - 0xDA_FFFF_FFFF */
/* 872 GiB to 876 GiB, size of 4 GiB : PDSCODEDATA_HEAP */
-#define ROGUE_PDSCODEDATA_HEAP_BASE 0xDA00000000ull
-#define ROGUE_PDSCODEDATA_HEAP_SIZE SZ_4G
+#define PVR_PDSCODEDATA_HEAP_BASE 0xDA00000000ull
+#define PVR_PDSCODEDATA_HEAP_SIZE SZ_4G
/* 0xDB_0000_0000 - 0xDB_FFFF_FFFF */
/* 876 GiB to 880 GiB, size of 256 MiB (reserved 4GiB) : BRN */
@@ -76,8 +76,8 @@
/* 0xE0_0000_0000 - 0xE0_FFFF_FFFF */
/* 896 GiB to 900 GiB, size of 4 GiB : USCCODE_HEAP */
-#define ROGUE_USCCODE_HEAP_BASE 0xE000000000ull
-#define ROGUE_USCCODE_HEAP_SIZE SZ_4G
+#define PVR_USCCODE_HEAP_BASE 0xE000000000ull
+#define PVR_USCCODE_HEAP_SIZE SZ_4G
/* 0xE1_0000_0000 - 0xE1_BFFF_FFFF */
/* 900 GiB to 903 GiB, size of 3 GiB : RESERVED */
@@ -99,8 +99,8 @@
/* 0xF2_0000_0000 - 0xF2_001F_FFFF **/
/* 968 GiB to 969 GiB, size of 2 MiB : VISTEST_HEAP */
-#define ROGUE_VISTEST_HEAP_BASE 0xF200000000ull
-#define ROGUE_VISTEST_HEAP_SIZE SZ_2M
+#define PVR_VISTEST_HEAP_BASE 0xF200000000ull
+#define PVR_VISTEST_HEAP_SIZE SZ_2M
/* 0xF2_4000_0000 - 0xF2_FFFF_FFFF */
/* 969 GiB to 972 GiB, size of 3 GiB : FREE */
@@ -110,4 +110,4 @@
/* 0xFF_FFFF_FFFF ************************************************************/
-#endif /* PVR_ROGUE_HEAP_CONFIG_H */
+#endif /* PVR_HEAP_CONFIG_H */
diff --git a/drivers/gpu/drm/imagination/pvr_vm.c b/drivers/gpu/drm/imagination/pvr_vm.c
index ceb78694cd98..ae965043237d 100644
--- a/drivers/gpu/drm/imagination/pvr_vm.c
+++ b/drivers/gpu/drm/imagination/pvr_vm.c
@@ -6,9 +6,9 @@
#include "pvr_device.h"
#include "pvr_drv.h"
#include "pvr_gem.h"
+#include "pvr_heap_config.h"
#include "pvr_mmu.h"
#include "pvr_rogue_fwif.h"
-#include "pvr_rogue_heap_config.h"
#include <drm/drm_exec.h>
#include <drm/drm_gem.h>
@@ -950,20 +950,20 @@ static const struct drm_pvr_static_data_area static_data_areas[] = {
*/
static const struct drm_pvr_heap pvr_heaps[] = {
[DRM_PVR_HEAP_GENERAL] = {
- .base = ROGUE_GENERAL_HEAP_BASE,
- .size = ROGUE_GENERAL_HEAP_SIZE,
+ .base = PVR_GENERAL_HEAP_BASE,
+ .size = PVR_GENERAL_HEAP_SIZE,
.flags = 0,
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
[DRM_PVR_HEAP_PDS_CODE_DATA] = {
- .base = ROGUE_PDSCODEDATA_HEAP_BASE,
- .size = ROGUE_PDSCODEDATA_HEAP_SIZE,
+ .base = PVR_PDSCODEDATA_HEAP_BASE,
+ .size = PVR_PDSCODEDATA_HEAP_SIZE,
.flags = 0,
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
[DRM_PVR_HEAP_USC_CODE] = {
- .base = ROGUE_USCCODE_HEAP_BASE,
- .size = ROGUE_USCCODE_HEAP_SIZE,
+ .base = PVR_USCCODE_HEAP_BASE,
+ .size = PVR_USCCODE_HEAP_SIZE,
.flags = 0,
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
@@ -974,8 +974,8 @@ static const struct drm_pvr_heap pvr_heaps[] = {
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
[DRM_PVR_HEAP_VIS_TEST] = {
- .base = ROGUE_VISTEST_HEAP_BASE,
- .size = ROGUE_VISTEST_HEAP_SIZE,
+ .base = PVR_VISTEST_HEAP_BASE,
+ .size = PVR_VISTEST_HEAP_SIZE,
.flags = 0,
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 1/5] drm/imagination: Prepare heap config header for multi-arch support
@ 2026-11-03 8:36 ` Alexandru Dadu
0 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu
Update the name of pvr_rogue_heap_config.h to pvr_heap_config.h to
prepare it for a more generic implementation that will have memory
sections defined for multiple GPU architectures.
Update the multi-arch common define names to a generic format.
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw.c | 7 +++---
drivers/gpu/drm/imagination/pvr_gem.h | 2 +-
.../{pvr_rogue_heap_config.h => pvr_heap_config.h} | 26 +++++++++++-----------
drivers/gpu/drm/imagination/pvr_vm.c | 18 +++++++--------
4 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c
index c6c77b152342..4d5df5272f46 100644
--- a/drivers/gpu/drm/imagination/pvr_fw.c
+++ b/drivers/gpu/drm/imagination/pvr_fw.c
@@ -9,9 +9,8 @@
#include "pvr_fw_startstop.h"
#include "pvr_fw_trace.h"
#include "pvr_gem.h"
+#include "pvr_heap_config.h"
#include "pvr_power.h"
-#include "pvr_rogue_fwif_dev_info.h"
-#include "pvr_rogue_heap_config.h"
#include "pvr_vm.h"
#include <drm/drm_drv.h>
@@ -372,8 +371,8 @@ fw_sysinit_init(void *cpu_ptr, void *priv)
WARN_ON(pvr_fw_object_get_dma_addr(fw_mem->fault_page_obj, 0, &fault_dma_addr));
fwif_sysinit->fault_phys_addr = (u64)fault_dma_addr;
- fwif_sysinit->pds_exec_base = ROGUE_PDSCODEDATA_HEAP_BASE;
- fwif_sysinit->usc_exec_base = ROGUE_USCCODE_HEAP_BASE;
+ fwif_sysinit->pds_exec_base = PVR_PDSCODEDATA_HEAP_BASE;
+ fwif_sysinit->usc_exec_base = PVR_USCCODE_HEAP_BASE;
pvr_fw_object_get_fw_addr(fw_mem->runtime_cfg_obj, &fwif_sysinit->runtime_cfg_fw_addr);
pvr_fw_object_get_fw_addr(fw_dev->fw_trace.tracebuf_ctrl_obj,
diff --git a/drivers/gpu/drm/imagination/pvr_gem.h b/drivers/gpu/drm/imagination/pvr_gem.h
index 4286e047ae24..ae7af82b6f17 100644
--- a/drivers/gpu/drm/imagination/pvr_gem.h
+++ b/drivers/gpu/drm/imagination/pvr_gem.h
@@ -4,7 +4,7 @@
#ifndef PVR_GEM_H
#define PVR_GEM_H
-#include "pvr_rogue_heap_config.h"
+#include "pvr_heap_config.h"
#include "pvr_rogue_meta.h"
#include <uapi/drm/pvr_drm.h>
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h b/drivers/gpu/drm/imagination/pvr_heap_config.h
similarity index 85%
rename from drivers/gpu/drm/imagination/pvr_rogue_heap_config.h
rename to drivers/gpu/drm/imagination/pvr_heap_config.h
index 5c33b342dda5..280bf1ed523b 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h
+++ b/drivers/gpu/drm/imagination/pvr_heap_config.h
@@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
-#ifndef PVR_ROGUE_HEAP_CONFIG_H
-#define PVR_ROGUE_HEAP_CONFIG_H
+#ifndef PVR_HEAP_CONFIG_H
+#define PVR_HEAP_CONFIG_H
#include <linux/sizes.h>
@@ -14,7 +14,7 @@
* fits into this, but the firmware heap is only ever created in the
* kernel driver and never exposed to userspace.
*
- * ROGUE_PDSCODEDATA_HEAP_BASE and ROGUE_USCCODE_HEAP_BASE will be programmed,
+ * PVR_PDSCODEDATA_HEAP_BASE and PVR_USCCODE_HEAP_BASE will be programmed,
* on a global basis, into ROGUE_CR_PDS_EXEC_BASE and ROGUE_CR_USC_CODE_BASE_*
* respectively. Therefore if client drivers use multiple configs they must
* still be consistent with their definitions for these heaps.
@@ -38,9 +38,9 @@
/* 0x80_0000_0000 ************************************************************/
/* 0x80_0000_0000 - 0x9F_FFFF_FFFF **/
-/* 512 GiB to 640 GiB, size of 128 GiB : GENERAL_HEAP */
-#define ROGUE_GENERAL_HEAP_BASE 0x8000000000ull
-#define ROGUE_GENERAL_HEAP_SIZE SZ_128G
+/* 512 GiB to 640 GiB, size of 128 GiB : GENERAL_HEAP **/
+#define PVR_GENERAL_HEAP_BASE 0x8000000000ull
+#define PVR_GENERAL_HEAP_SIZE SZ_128G
/* 0xA0_0000_0000 - 0xAF_FFFF_FFFF */
/* 640 GiB to 704 GiB, size of 64 GiB : FREE */
@@ -58,8 +58,8 @@
/* 0xDA_0000_0000 - 0xDA_FFFF_FFFF */
/* 872 GiB to 876 GiB, size of 4 GiB : PDSCODEDATA_HEAP */
-#define ROGUE_PDSCODEDATA_HEAP_BASE 0xDA00000000ull
-#define ROGUE_PDSCODEDATA_HEAP_SIZE SZ_4G
+#define PVR_PDSCODEDATA_HEAP_BASE 0xDA00000000ull
+#define PVR_PDSCODEDATA_HEAP_SIZE SZ_4G
/* 0xDB_0000_0000 - 0xDB_FFFF_FFFF */
/* 876 GiB to 880 GiB, size of 256 MiB (reserved 4GiB) : BRN */
@@ -76,8 +76,8 @@
/* 0xE0_0000_0000 - 0xE0_FFFF_FFFF */
/* 896 GiB to 900 GiB, size of 4 GiB : USCCODE_HEAP */
-#define ROGUE_USCCODE_HEAP_BASE 0xE000000000ull
-#define ROGUE_USCCODE_HEAP_SIZE SZ_4G
+#define PVR_USCCODE_HEAP_BASE 0xE000000000ull
+#define PVR_USCCODE_HEAP_SIZE SZ_4G
/* 0xE1_0000_0000 - 0xE1_BFFF_FFFF */
/* 900 GiB to 903 GiB, size of 3 GiB : RESERVED */
@@ -99,8 +99,8 @@
/* 0xF2_0000_0000 - 0xF2_001F_FFFF **/
/* 968 GiB to 969 GiB, size of 2 MiB : VISTEST_HEAP */
-#define ROGUE_VISTEST_HEAP_BASE 0xF200000000ull
-#define ROGUE_VISTEST_HEAP_SIZE SZ_2M
+#define PVR_VISTEST_HEAP_BASE 0xF200000000ull
+#define PVR_VISTEST_HEAP_SIZE SZ_2M
/* 0xF2_4000_0000 - 0xF2_FFFF_FFFF */
/* 969 GiB to 972 GiB, size of 3 GiB : FREE */
@@ -110,4 +110,4 @@
/* 0xFF_FFFF_FFFF ************************************************************/
-#endif /* PVR_ROGUE_HEAP_CONFIG_H */
+#endif /* PVR_HEAP_CONFIG_H */
diff --git a/drivers/gpu/drm/imagination/pvr_vm.c b/drivers/gpu/drm/imagination/pvr_vm.c
index ceb78694cd98..ae965043237d 100644
--- a/drivers/gpu/drm/imagination/pvr_vm.c
+++ b/drivers/gpu/drm/imagination/pvr_vm.c
@@ -6,9 +6,9 @@
#include "pvr_device.h"
#include "pvr_drv.h"
#include "pvr_gem.h"
+#include "pvr_heap_config.h"
#include "pvr_mmu.h"
#include "pvr_rogue_fwif.h"
-#include "pvr_rogue_heap_config.h"
#include <drm/drm_exec.h>
#include <drm/drm_gem.h>
@@ -950,20 +950,20 @@ static const struct drm_pvr_static_data_area static_data_areas[] = {
*/
static const struct drm_pvr_heap pvr_heaps[] = {
[DRM_PVR_HEAP_GENERAL] = {
- .base = ROGUE_GENERAL_HEAP_BASE,
- .size = ROGUE_GENERAL_HEAP_SIZE,
+ .base = PVR_GENERAL_HEAP_BASE,
+ .size = PVR_GENERAL_HEAP_SIZE,
.flags = 0,
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
[DRM_PVR_HEAP_PDS_CODE_DATA] = {
- .base = ROGUE_PDSCODEDATA_HEAP_BASE,
- .size = ROGUE_PDSCODEDATA_HEAP_SIZE,
+ .base = PVR_PDSCODEDATA_HEAP_BASE,
+ .size = PVR_PDSCODEDATA_HEAP_SIZE,
.flags = 0,
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
[DRM_PVR_HEAP_USC_CODE] = {
- .base = ROGUE_USCCODE_HEAP_BASE,
- .size = ROGUE_USCCODE_HEAP_SIZE,
+ .base = PVR_USCCODE_HEAP_BASE,
+ .size = PVR_USCCODE_HEAP_SIZE,
.flags = 0,
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
@@ -974,8 +974,8 @@ static const struct drm_pvr_heap pvr_heaps[] = {
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
[DRM_PVR_HEAP_VIS_TEST] = {
- .base = ROGUE_VISTEST_HEAP_BASE,
- .size = ROGUE_VISTEST_HEAP_SIZE,
+ .base = PVR_VISTEST_HEAP_BASE,
+ .size = PVR_VISTEST_HEAP_SIZE,
.flags = 0,
.page_size_log2 = PVR_DEVICE_PAGE_SHIFT,
},
--
2.43.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 2/5] drm/imagination: Limit access to the RISC-V firmware interface
2026-11-03 8:36 ` Alexandru Dadu
@ 2026-11-03 8:36 ` Alexandru Dadu
-1 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu
From: Alessio Belle <alessio.belle@imgtec.com>
- Rename the RISC-V firmware processor header adding an "internal"
suffix.
- Add guard to the RISC-V firmware processor header to prevent
accidental inclusion outside of the RISC-V firmware specific logic.
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw_riscv.c | 4 +++-
.../{pvr_rogue_riscv.h => pvr_rogue_riscv_internal.h} | 10 +++++++---
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
index cd84635bb88d..0d4dd45520a9 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_riscv.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
@@ -7,7 +7,9 @@
#include "pvr_fw_mips.h"
#include "pvr_gem.h"
#include "pvr_rogue_cr_defs.h"
-#include "pvr_rogue_riscv.h"
+#define PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
+#include "pvr_rogue_riscv_internal.h"
+#undef PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_vm.h"
#include <linux/compiler.h>
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_riscv.h b/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
similarity index 81%
rename from drivers/gpu/drm/imagination/pvr_rogue_riscv.h
rename to drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
index d971729e18a4..ba18c2a82205 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_riscv.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
@@ -1,8 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/* Copyright (c) 2024 Imagination Technologies Ltd. */
-#ifndef PVR_ROGUE_RISCV_H
-#define PVR_ROGUE_RISCV_H
+#ifndef PVR_ROGUE_RISCV_INTERNAL_H
+#define PVR_ROGUE_RISCV_INTERNAL_H
+
+#ifndef PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
+#error This file may only be included if explicitly defined
+#endif
#include "pvr_rogue_cr_defs.h"
@@ -36,4 +40,4 @@ enum rogue_riscvfw_region {
#define ROGUE_RISCVFW_REGION_BASE(r) ((u32)(ROGUE_RISCV_REGION_##r) << ROGUE_RISCVFW_REGION_SHIFT)
-#endif /* PVR_ROGUE_RISCV_H */
+#endif /* PVR_ROGUE_RISCV_INTERNAL_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 2/5] drm/imagination: Limit access to the RISC-V firmware interface
@ 2026-11-03 8:36 ` Alexandru Dadu
0 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu
From: Alessio Belle <alessio.belle@imgtec.com>
- Rename the RISC-V firmware processor header adding an "internal"
suffix.
- Add guard to the RISC-V firmware processor header to prevent
accidental inclusion outside of the RISC-V firmware specific logic.
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw_riscv.c | 4 +++-
.../{pvr_rogue_riscv.h => pvr_rogue_riscv_internal.h} | 10 +++++++---
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
index cd84635bb88d..0d4dd45520a9 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_riscv.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
@@ -7,7 +7,9 @@
#include "pvr_fw_mips.h"
#include "pvr_gem.h"
#include "pvr_rogue_cr_defs.h"
-#include "pvr_rogue_riscv.h"
+#define PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
+#include "pvr_rogue_riscv_internal.h"
+#undef PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_vm.h"
#include <linux/compiler.h>
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_riscv.h b/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
similarity index 81%
rename from drivers/gpu/drm/imagination/pvr_rogue_riscv.h
rename to drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
index d971729e18a4..ba18c2a82205 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_riscv.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
@@ -1,8 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/* Copyright (c) 2024 Imagination Technologies Ltd. */
-#ifndef PVR_ROGUE_RISCV_H
-#define PVR_ROGUE_RISCV_H
+#ifndef PVR_ROGUE_RISCV_INTERNAL_H
+#define PVR_ROGUE_RISCV_INTERNAL_H
+
+#ifndef PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
+#error This file may only be included if explicitly defined
+#endif
#include "pvr_rogue_cr_defs.h"
@@ -36,4 +40,4 @@ enum rogue_riscvfw_region {
#define ROGUE_RISCVFW_REGION_BASE(r) ((u32)(ROGUE_RISCV_REGION_##r) << ROGUE_RISCVFW_REGION_SHIFT)
-#endif /* PVR_ROGUE_RISCV_H */
+#endif /* PVR_ROGUE_RISCV_INTERNAL_H */
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 3/5] drm/imagination: Make the RISC-V firmware header arch-independent
2026-11-03 8:36 ` Alexandru Dadu
@ 2026-11-03 8:36 ` Alexandru Dadu
-1 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu,
Matt Coster
From: Alessio Belle <alessio.belle@imgtec.com>
This header file contains definitions common to all PowerVR
architectures starting from Rogue, so rename both the file and its
contents to reflect this.
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw_riscv.c | 14 +++----
.../gpu/drm/imagination/pvr_fw_riscv_internal.h | 43 ++++++++++++++++++++++
.../gpu/drm/imagination/pvr_rogue_riscv_internal.h | 43 ----------------------
3 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
index 0d4dd45520a9..2b24c40bc20f 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_riscv.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
@@ -6,10 +6,10 @@
#include "pvr_fw_info.h"
#include "pvr_fw_mips.h"
#include "pvr_gem.h"
+#define PVR_FW_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
+#include "pvr_fw_riscv_internal.h"
+#undef PVR_FW_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_rogue_cr_defs.h"
-#define PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
-#include "pvr_rogue_riscv_internal.h"
-#undef PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_vm.h"
#include <linux/compiler.h>
@@ -43,13 +43,13 @@ pvr_riscv_wrapper_init(struct pvr_device *pvr_dev)
pvr_cr_write64(pvr_dev,
PVR_CR_REPEAT_X(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG,
- ROGUE_RISCV_REGION_BOOTLDR_CODE),
+ PVR_RISCV_REGION_BOOTLDR_CODE),
code_addr | common_opts |
ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_FETCH_EN_EN);
pvr_cr_write64(pvr_dev,
PVR_CR_REPEAT_X(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG,
- ROGUE_RISCV_REGION_BOOTLDR_DATA),
+ PVR_RISCV_REGION_BOOTLDR_DATA),
data_addr | common_opts |
ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_LOAD_STORE_EN_EN);
@@ -132,9 +132,9 @@ pvr_riscv_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
/* RISC-V cacheability is determined by address. */
if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED)
- fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_UNCACHED_DATA);
+ fw_addr |= PVR_RISCVFW_REGION_BASE(SHARED_UNCACHED_DATA);
else
- fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_CACHED_DATA);
+ fw_addr |= PVR_RISCVFW_REGION_BASE(SHARED_CACHED_DATA);
return fw_addr;
}
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv_internal.h b/drivers/gpu/drm/imagination/pvr_fw_riscv_internal.h
new file mode 100644
index 000000000000..abcbb4ef06fe
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv_internal.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/* Copyright (c) 2024 Imagination Technologies Ltd. */
+
+#ifndef PVR_FW_RISCV_INTERNAL_H
+#define PVR_FW_RISCV_INTERNAL_H
+
+#ifndef PVR_FW_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
+#error This file may only be included if explicitly defined
+#endif
+
+#include "pvr_rogue_cr_defs.h"
+
+#include <linux/bitops.h>
+#include <linux/sizes.h>
+#include <linux/types.h>
+
+#define PVR_RISCVFW_REGION_SIZE SZ_256M
+#define PVR_RISCVFW_REGION_SHIFT __ffs(PVR_RISCVFW_REGION_SIZE)
+
+enum pvr_riscvfw_region {
+ PVR_RISCV_REGION__RESERVED_0 = 0,
+ PVR_RISCV_REGION__RESERVED_1,
+ PVR_RISCV_REGION_SOCIF,
+ PVR_RISCV_REGION__RESERVED_3,
+ PVR_RISCV_REGION__RESERVED_4,
+ PVR_RISCV_REGION_BOOTLDR_DATA,
+ PVR_RISCV_REGION_SHARED_CACHED_DATA,
+ PVR_RISCV_REGION__RESERVED_7,
+ PVR_RISCV_REGION_COREMEM,
+ PVR_RISCV_REGION__RESERVED_9,
+ PVR_RISCV_REGION__RESERVED_A,
+ PVR_RISCV_REGION__RESERVED_B,
+ PVR_RISCV_REGION_BOOTLDR_CODE,
+ PVR_RISCV_REGION_SHARED_UNCACHED_DATA,
+ PVR_RISCV_REGION__RESERVED_E,
+ PVR_RISCV_REGION__RESERVED_F,
+
+ PVR_RISCV_REGION__COUNT,
+};
+
+#define PVR_RISCVFW_REGION_BASE(r) ((u32)(PVR_RISCV_REGION_##r) << PVR_RISCVFW_REGION_SHIFT)
+
+#endif /* PVR_FW_RISCV_INTERNAL_H */
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h b/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
deleted file mode 100644
index ba18c2a82205..000000000000
--- a/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/* Copyright (c) 2024 Imagination Technologies Ltd. */
-
-#ifndef PVR_ROGUE_RISCV_INTERNAL_H
-#define PVR_ROGUE_RISCV_INTERNAL_H
-
-#ifndef PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
-#error This file may only be included if explicitly defined
-#endif
-
-#include "pvr_rogue_cr_defs.h"
-
-#include <linux/bitops.h>
-#include <linux/sizes.h>
-#include <linux/types.h>
-
-#define ROGUE_RISCVFW_REGION_SIZE SZ_256M
-#define ROGUE_RISCVFW_REGION_SHIFT __ffs(ROGUE_RISCVFW_REGION_SIZE)
-
-enum rogue_riscvfw_region {
- ROGUE_RISCV_REGION__RESERVED_0 = 0,
- ROGUE_RISCV_REGION__RESERVED_1,
- ROGUE_RISCV_REGION_SOCIF,
- ROGUE_RISCV_REGION__RESERVED_3,
- ROGUE_RISCV_REGION__RESERVED_4,
- ROGUE_RISCV_REGION_BOOTLDR_DATA,
- ROGUE_RISCV_REGION_SHARED_CACHED_DATA,
- ROGUE_RISCV_REGION__RESERVED_7,
- ROGUE_RISCV_REGION_COREMEM,
- ROGUE_RISCV_REGION__RESERVED_9,
- ROGUE_RISCV_REGION__RESERVED_A,
- ROGUE_RISCV_REGION__RESERVED_B,
- ROGUE_RISCV_REGION_BOOTLDR_CODE,
- ROGUE_RISCV_REGION_SHARED_UNCACHED_DATA,
- ROGUE_RISCV_REGION__RESERVED_E,
- ROGUE_RISCV_REGION__RESERVED_F,
-
- ROGUE_RISCV_REGION__COUNT,
-};
-
-#define ROGUE_RISCVFW_REGION_BASE(r) ((u32)(ROGUE_RISCV_REGION_##r) << ROGUE_RISCVFW_REGION_SHIFT)
-
-#endif /* PVR_ROGUE_RISCV_INTERNAL_H */
--
2.43.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 3/5] drm/imagination: Make the RISC-V firmware header arch-independent
@ 2026-11-03 8:36 ` Alexandru Dadu
0 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu,
Matt Coster
From: Alessio Belle <alessio.belle@imgtec.com>
This header file contains definitions common to all PowerVR
architectures starting from Rogue, so rename both the file and its
contents to reflect this.
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw_riscv.c | 14 +++----
.../gpu/drm/imagination/pvr_fw_riscv_internal.h | 43 ++++++++++++++++++++++
.../gpu/drm/imagination/pvr_rogue_riscv_internal.h | 43 ----------------------
3 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
index 0d4dd45520a9..2b24c40bc20f 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_riscv.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
@@ -6,10 +6,10 @@
#include "pvr_fw_info.h"
#include "pvr_fw_mips.h"
#include "pvr_gem.h"
+#define PVR_FW_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
+#include "pvr_fw_riscv_internal.h"
+#undef PVR_FW_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_rogue_cr_defs.h"
-#define PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
-#include "pvr_rogue_riscv_internal.h"
-#undef PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_vm.h"
#include <linux/compiler.h>
@@ -43,13 +43,13 @@ pvr_riscv_wrapper_init(struct pvr_device *pvr_dev)
pvr_cr_write64(pvr_dev,
PVR_CR_REPEAT_X(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG,
- ROGUE_RISCV_REGION_BOOTLDR_CODE),
+ PVR_RISCV_REGION_BOOTLDR_CODE),
code_addr | common_opts |
ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_FETCH_EN_EN);
pvr_cr_write64(pvr_dev,
PVR_CR_REPEAT_X(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG,
- ROGUE_RISCV_REGION_BOOTLDR_DATA),
+ PVR_RISCV_REGION_BOOTLDR_DATA),
data_addr | common_opts |
ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_LOAD_STORE_EN_EN);
@@ -132,9 +132,9 @@ pvr_riscv_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
/* RISC-V cacheability is determined by address. */
if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED)
- fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_UNCACHED_DATA);
+ fw_addr |= PVR_RISCVFW_REGION_BASE(SHARED_UNCACHED_DATA);
else
- fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_CACHED_DATA);
+ fw_addr |= PVR_RISCVFW_REGION_BASE(SHARED_CACHED_DATA);
return fw_addr;
}
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv_internal.h b/drivers/gpu/drm/imagination/pvr_fw_riscv_internal.h
new file mode 100644
index 000000000000..abcbb4ef06fe
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv_internal.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/* Copyright (c) 2024 Imagination Technologies Ltd. */
+
+#ifndef PVR_FW_RISCV_INTERNAL_H
+#define PVR_FW_RISCV_INTERNAL_H
+
+#ifndef PVR_FW_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
+#error This file may only be included if explicitly defined
+#endif
+
+#include "pvr_rogue_cr_defs.h"
+
+#include <linux/bitops.h>
+#include <linux/sizes.h>
+#include <linux/types.h>
+
+#define PVR_RISCVFW_REGION_SIZE SZ_256M
+#define PVR_RISCVFW_REGION_SHIFT __ffs(PVR_RISCVFW_REGION_SIZE)
+
+enum pvr_riscvfw_region {
+ PVR_RISCV_REGION__RESERVED_0 = 0,
+ PVR_RISCV_REGION__RESERVED_1,
+ PVR_RISCV_REGION_SOCIF,
+ PVR_RISCV_REGION__RESERVED_3,
+ PVR_RISCV_REGION__RESERVED_4,
+ PVR_RISCV_REGION_BOOTLDR_DATA,
+ PVR_RISCV_REGION_SHARED_CACHED_DATA,
+ PVR_RISCV_REGION__RESERVED_7,
+ PVR_RISCV_REGION_COREMEM,
+ PVR_RISCV_REGION__RESERVED_9,
+ PVR_RISCV_REGION__RESERVED_A,
+ PVR_RISCV_REGION__RESERVED_B,
+ PVR_RISCV_REGION_BOOTLDR_CODE,
+ PVR_RISCV_REGION_SHARED_UNCACHED_DATA,
+ PVR_RISCV_REGION__RESERVED_E,
+ PVR_RISCV_REGION__RESERVED_F,
+
+ PVR_RISCV_REGION__COUNT,
+};
+
+#define PVR_RISCVFW_REGION_BASE(r) ((u32)(PVR_RISCV_REGION_##r) << PVR_RISCVFW_REGION_SHIFT)
+
+#endif /* PVR_FW_RISCV_INTERNAL_H */
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h b/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
deleted file mode 100644
index ba18c2a82205..000000000000
--- a/drivers/gpu/drm/imagination/pvr_rogue_riscv_internal.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/* Copyright (c) 2024 Imagination Technologies Ltd. */
-
-#ifndef PVR_ROGUE_RISCV_INTERNAL_H
-#define PVR_ROGUE_RISCV_INTERNAL_H
-
-#ifndef PVR_ROGUE_RISCV_INTERNAL_H_EXPLICIT_INCLUDE
-#error This file may only be included if explicitly defined
-#endif
-
-#include "pvr_rogue_cr_defs.h"
-
-#include <linux/bitops.h>
-#include <linux/sizes.h>
-#include <linux/types.h>
-
-#define ROGUE_RISCVFW_REGION_SIZE SZ_256M
-#define ROGUE_RISCVFW_REGION_SHIFT __ffs(ROGUE_RISCVFW_REGION_SIZE)
-
-enum rogue_riscvfw_region {
- ROGUE_RISCV_REGION__RESERVED_0 = 0,
- ROGUE_RISCV_REGION__RESERVED_1,
- ROGUE_RISCV_REGION_SOCIF,
- ROGUE_RISCV_REGION__RESERVED_3,
- ROGUE_RISCV_REGION__RESERVED_4,
- ROGUE_RISCV_REGION_BOOTLDR_DATA,
- ROGUE_RISCV_REGION_SHARED_CACHED_DATA,
- ROGUE_RISCV_REGION__RESERVED_7,
- ROGUE_RISCV_REGION_COREMEM,
- ROGUE_RISCV_REGION__RESERVED_9,
- ROGUE_RISCV_REGION__RESERVED_A,
- ROGUE_RISCV_REGION__RESERVED_B,
- ROGUE_RISCV_REGION_BOOTLDR_CODE,
- ROGUE_RISCV_REGION_SHARED_UNCACHED_DATA,
- ROGUE_RISCV_REGION__RESERVED_E,
- ROGUE_RISCV_REGION__RESERVED_F,
-
- ROGUE_RISCV_REGION__COUNT,
-};
-
-#define ROGUE_RISCVFW_REGION_BASE(r) ((u32)(ROGUE_RISCV_REGION_##r) << ROGUE_RISCVFW_REGION_SHIFT)
-
-#endif /* PVR_ROGUE_RISCV_INTERNAL_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 4/5] drm/imagination: Limit access to the META firmware interface
2026-11-03 8:36 ` Alexandru Dadu
@ 2026-11-03 8:36 ` Alexandru Dadu
-1 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu
From: Alessio Belle <alessio.belle@imgtec.com>
Ensure all accesses to the META firmware interface are done via the
generic firmware interface.
To achieve this:
- Introduce a new function to the firmware processor table to remove
the last direct access to the META firmware interface from
outside of the generic firmware logic.
- Remove the META firmware interface header.
- Rename the META firmware processor header adding an "internal" suffix.
- Add guard to the META firmware processor header to prevent accidental
inclusion outside of the META firmware specific logic.
- Add a multi_dm_thread_assoc property to struct pvr_fw_defs to isolate
that behaviour from the architecture.
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw.h | 26 +++++++++
drivers/gpu/drm/imagination/pvr_fw_meta.c | 28 ++++++++--
drivers/gpu/drm/imagination/pvr_fw_meta.h | 14 -----
drivers/gpu/drm/imagination/pvr_fw_mips.c | 1 +
drivers/gpu/drm/imagination/pvr_fw_riscv.c | 1 +
drivers/gpu/drm/imagination/pvr_fw_startstop.c | 61 ++++++++++++----------
drivers/gpu/drm/imagination/pvr_gem.h | 1 -
...{pvr_rogue_meta.h => pvr_rogue_meta_internal.h} | 10 ++--
8 files changed, 93 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h
index 4b25291135b6..610406668bbb 100644
--- a/drivers/gpu/drm/imagination/pvr_fw.h
+++ b/drivers/gpu/drm/imagination/pvr_fw.h
@@ -184,6 +184,23 @@ struct pvr_fw_defs {
*/
void (*irq_clear)(struct pvr_device *pvr_dev);
+ /**
+ * @must_wait_fw_idle: Check if the FW stop sequence should wait for hardware
+ * to report FW idle before proceeding.
+ *
+ * @pvr_dev: Target PowerVR device.
+ * @wait[out]: Whether the FW stop sequence should wait for FW idle.
+ *
+ * This function is optional. The assumption is that we must always wait
+ * for the firmware to reach idle; implement this function and return
+ * %false to alter this behavior.
+ *
+ * Returns:
+ * * 0 on success.
+ * * Any appropriate error on failure.
+ */
+ int (*must_wait_fw_idle)(struct pvr_device *pvr_dev, bool *wait);
+
/**
* @has_fixed_data_addr: Specify whether the firmware fixed data must be loaded at the
* address given by the firmware layout table.
@@ -191,6 +208,15 @@ struct pvr_fw_defs {
* This value is mandatory.
*/
bool has_fixed_data_addr;
+
+ /**
+ * @multi_dm_thread_assoc: Specify that all threads must be associated
+ * with the DM separately rather than just the
+ * first thread (the default behaviour).
+ *
+ * This value is mandatory.
+ */
+ bool multi_dm_thread_assoc;
};
/**
diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c
index 84f568b5510f..f451f97a4f2f 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_meta.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c
@@ -4,10 +4,11 @@
#include "pvr_device.h"
#include "pvr_fw.h"
#include "pvr_fw_info.h"
-#include "pvr_fw_meta.h"
#include "pvr_gem.h"
#include "pvr_rogue_cr_defs.h"
-#include "pvr_rogue_meta.h"
+#define PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
+#include "pvr_rogue_meta_internal.h"
+#undef PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_vm.h"
#include <linux/compiler.h>
@@ -32,7 +33,7 @@
* * 0 on success, or
* * Any error returned by pvr_cr_poll_reg32().
*/
-int
+static int
pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out)
{
int err;
@@ -563,6 +564,25 @@ pvr_meta_irq_clear(struct pvr_device *pvr_dev)
ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK);
}
+static int
+pvr_meta_must_wait_fw_idle(struct pvr_device *pvr_dev, bool *wait)
+{
+ u32 reg_value;
+ int err;
+
+ err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value);
+ if (err)
+ return err;
+
+ /*
+ * Wait for Sidekick/Jones to signal IDLE including the Garten
+ * Wrapper if there is no debugger attached (TxVECINT_BHALT = 0x0).
+ */
+ *wait = !reg_value;
+
+ return 0;
+}
+
const struct pvr_fw_defs pvr_fw_defs_meta = {
.init = pvr_meta_init,
.fini = pvr_meta_fini,
@@ -573,5 +593,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta = {
.wrapper_init = pvr_meta_wrapper_init,
.irq_pending = pvr_meta_irq_pending,
.irq_clear = pvr_meta_irq_clear,
+ .must_wait_fw_idle = pvr_meta_must_wait_fw_idle,
.has_fixed_data_addr = false,
+ .multi_dm_thread_assoc = true,
};
diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.h b/drivers/gpu/drm/imagination/pvr_fw_meta.h
deleted file mode 100644
index 911ad700cba6..000000000000
--- a/drivers/gpu/drm/imagination/pvr_fw_meta.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-/* Copyright (c) 2023 Imagination Technologies Ltd. */
-
-#ifndef PVR_FW_META_H
-#define PVR_FW_META_H
-
-#include <linux/types.h>
-
-/* Forward declaration from pvr_device.h */
-struct pvr_device;
-
-int pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out);
-
-#endif /* PVR_FW_META_H */
diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c
index 6914fc46db50..ec0dad1692c3 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_mips.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c
@@ -196,4 +196,5 @@ const struct pvr_fw_defs pvr_fw_defs_mips = {
.irq_pending = pvr_mips_irq_pending,
.irq_clear = pvr_mips_irq_clear,
.has_fixed_data_addr = true,
+ .multi_dm_thread_assoc = false,
};
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
index 2b24c40bc20f..ef2801276252 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_riscv.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
@@ -182,4 +182,5 @@ const struct pvr_fw_defs pvr_fw_defs_riscv = {
.irq_pending = pvr_riscv_irq_pending,
.irq_clear = pvr_riscv_irq_clear,
.has_fixed_data_addr = false,
+ .multi_dm_thread_assoc = false,
};
diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
index 98ca2692239d..ab637ba7d108 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
@@ -3,10 +3,8 @@
#include "pvr_device.h"
#include "pvr_fw.h"
-#include "pvr_fw_meta.h"
#include "pvr_fw_startstop.h"
#include "pvr_rogue_cr_defs.h"
-#include "pvr_rogue_meta.h"
#include "pvr_vm.h"
#include <linux/compiler.h>
@@ -199,6 +197,30 @@ pvr_fw_start(struct pvr_device *pvr_dev)
return err;
}
+static inline bool layout_is_mars(struct pvr_device *pvr_dev)
+{
+ u64 layout_mars_value = 0;
+
+ if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value))
+ return false;
+
+ return layout_mars_value == 0;
+}
+
+static inline int must_wait_fw_idle_before_stop(struct pvr_device *pvr_dev)
+{
+ bool wait_fw_idle = true;
+ int err;
+
+ if (pvr_dev->fw_dev.defs->must_wait_fw_idle) {
+ err = pvr_dev->fw_dev.defs->must_wait_fw_idle(pvr_dev, &wait_fw_idle);
+ if (err)
+ return err;
+ }
+
+ return wait_fw_idle;
+}
+
/**
* pvr_fw_stop() - Stop FW processor
* @pvr_dev: Target PowerVR device.
@@ -214,15 +236,9 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
~(ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN |
ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN |
ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN);
- bool skip_garten_idle = false;
- u64 layout_mars_value = 0;
- bool layout_mars = false;
- bool meta_fw = pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META;
- u32 reg_value;
- int err;
- if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value) == 0)
- layout_mars = layout_mars_value > 0;
+ bool layout_mars = layout_is_mars(pvr_dev);
+ int err;
/*
* For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been
@@ -250,7 +266,7 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL &
ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK);
- if (meta_fw) {
+ if (pvr_dev->fw_dev.defs->multi_dm_thread_assoc) {
pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC,
ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL &
ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
@@ -297,6 +313,8 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
* powered down by the FW.
*/
if (!layout_mars) {
+ int wait_fw_idle;
+
/* Wait for SLC to signal IDLE. */
err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE,
ROGUE_CR_SLC_IDLE_MASKFULL,
@@ -309,24 +327,12 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
sidekick_idle_mask, POLL_TIMEOUT_USEC);
if (err)
return err;
- }
- if (meta_fw) {
- err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value);
- if (err)
- return err;
-
- /*
- * Wait for Sidekick/Jones to signal IDLE including the Garten
- * Wrapper if there is no debugger attached (TxVECINT_BHALT =
- * 0x0).
- */
- if (reg_value)
- skip_garten_idle = true;
- }
+ wait_fw_idle = must_wait_fw_idle_before_stop(pvr_dev);
+ if (wait_fw_idle < 0)
+ return wait_fw_idle;
- if (meta_fw || !layout_mars) {
- if (!skip_garten_idle) {
+ if (wait_fw_idle) {
err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE,
ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
@@ -346,7 +352,6 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
ROGUE_CR_MARS_IDLE_CPU_EN |
ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN,
POLL_TIMEOUT_USEC);
-
if (err)
return err;
}
diff --git a/drivers/gpu/drm/imagination/pvr_gem.h b/drivers/gpu/drm/imagination/pvr_gem.h
index ae7af82b6f17..e84be25f8576 100644
--- a/drivers/gpu/drm/imagination/pvr_gem.h
+++ b/drivers/gpu/drm/imagination/pvr_gem.h
@@ -5,7 +5,6 @@
#define PVR_GEM_H
#include "pvr_heap_config.h"
-#include "pvr_rogue_meta.h"
#include <uapi/drm/pvr_drm.h>
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_meta.h b/drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
similarity index 98%
rename from drivers/gpu/drm/imagination/pvr_rogue_meta.h
rename to drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
index 3020e6582daa..dd978988ed40 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_meta.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
@@ -1,8 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
-#ifndef PVR_ROGUE_META_H
-#define PVR_ROGUE_META_H
+#ifndef PVR_ROGUE_META_INTERNAL_H
+#define PVR_ROGUE_META_INTERNAL_H
+
+#ifndef PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
+#error This file may only be included if explicitly defined
+#endif
/***** The META HW register definitions in the file are updated manually *****/
@@ -353,4 +357,4 @@ struct rogue_meta_ldr_cfg_blk {
#define ROGUE_FW_PROCESSOR_META "META"
-#endif /* PVR_ROGUE_META_H */
+#endif /* PVR_ROGUE_META_INTERNAL_H */
--
2.43.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 4/5] drm/imagination: Limit access to the META firmware interface
@ 2026-11-03 8:36 ` Alexandru Dadu
0 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu
From: Alessio Belle <alessio.belle@imgtec.com>
Ensure all accesses to the META firmware interface are done via the
generic firmware interface.
To achieve this:
- Introduce a new function to the firmware processor table to remove
the last direct access to the META firmware interface from
outside of the generic firmware logic.
- Remove the META firmware interface header.
- Rename the META firmware processor header adding an "internal" suffix.
- Add guard to the META firmware processor header to prevent accidental
inclusion outside of the META firmware specific logic.
- Add a multi_dm_thread_assoc property to struct pvr_fw_defs to isolate
that behaviour from the architecture.
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw.h | 26 +++++++++
drivers/gpu/drm/imagination/pvr_fw_meta.c | 28 ++++++++--
drivers/gpu/drm/imagination/pvr_fw_meta.h | 14 -----
drivers/gpu/drm/imagination/pvr_fw_mips.c | 1 +
drivers/gpu/drm/imagination/pvr_fw_riscv.c | 1 +
drivers/gpu/drm/imagination/pvr_fw_startstop.c | 61 ++++++++++++----------
drivers/gpu/drm/imagination/pvr_gem.h | 1 -
...{pvr_rogue_meta.h => pvr_rogue_meta_internal.h} | 10 ++--
8 files changed, 93 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h
index 4b25291135b6..610406668bbb 100644
--- a/drivers/gpu/drm/imagination/pvr_fw.h
+++ b/drivers/gpu/drm/imagination/pvr_fw.h
@@ -184,6 +184,23 @@ struct pvr_fw_defs {
*/
void (*irq_clear)(struct pvr_device *pvr_dev);
+ /**
+ * @must_wait_fw_idle: Check if the FW stop sequence should wait for hardware
+ * to report FW idle before proceeding.
+ *
+ * @pvr_dev: Target PowerVR device.
+ * @wait[out]: Whether the FW stop sequence should wait for FW idle.
+ *
+ * This function is optional. The assumption is that we must always wait
+ * for the firmware to reach idle; implement this function and return
+ * %false to alter this behavior.
+ *
+ * Returns:
+ * * 0 on success.
+ * * Any appropriate error on failure.
+ */
+ int (*must_wait_fw_idle)(struct pvr_device *pvr_dev, bool *wait);
+
/**
* @has_fixed_data_addr: Specify whether the firmware fixed data must be loaded at the
* address given by the firmware layout table.
@@ -191,6 +208,15 @@ struct pvr_fw_defs {
* This value is mandatory.
*/
bool has_fixed_data_addr;
+
+ /**
+ * @multi_dm_thread_assoc: Specify that all threads must be associated
+ * with the DM separately rather than just the
+ * first thread (the default behaviour).
+ *
+ * This value is mandatory.
+ */
+ bool multi_dm_thread_assoc;
};
/**
diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c
index 84f568b5510f..f451f97a4f2f 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_meta.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c
@@ -4,10 +4,11 @@
#include "pvr_device.h"
#include "pvr_fw.h"
#include "pvr_fw_info.h"
-#include "pvr_fw_meta.h"
#include "pvr_gem.h"
#include "pvr_rogue_cr_defs.h"
-#include "pvr_rogue_meta.h"
+#define PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
+#include "pvr_rogue_meta_internal.h"
+#undef PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_vm.h"
#include <linux/compiler.h>
@@ -32,7 +33,7 @@
* * 0 on success, or
* * Any error returned by pvr_cr_poll_reg32().
*/
-int
+static int
pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out)
{
int err;
@@ -563,6 +564,25 @@ pvr_meta_irq_clear(struct pvr_device *pvr_dev)
ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK);
}
+static int
+pvr_meta_must_wait_fw_idle(struct pvr_device *pvr_dev, bool *wait)
+{
+ u32 reg_value;
+ int err;
+
+ err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value);
+ if (err)
+ return err;
+
+ /*
+ * Wait for Sidekick/Jones to signal IDLE including the Garten
+ * Wrapper if there is no debugger attached (TxVECINT_BHALT = 0x0).
+ */
+ *wait = !reg_value;
+
+ return 0;
+}
+
const struct pvr_fw_defs pvr_fw_defs_meta = {
.init = pvr_meta_init,
.fini = pvr_meta_fini,
@@ -573,5 +593,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta = {
.wrapper_init = pvr_meta_wrapper_init,
.irq_pending = pvr_meta_irq_pending,
.irq_clear = pvr_meta_irq_clear,
+ .must_wait_fw_idle = pvr_meta_must_wait_fw_idle,
.has_fixed_data_addr = false,
+ .multi_dm_thread_assoc = true,
};
diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.h b/drivers/gpu/drm/imagination/pvr_fw_meta.h
deleted file mode 100644
index 911ad700cba6..000000000000
--- a/drivers/gpu/drm/imagination/pvr_fw_meta.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-/* Copyright (c) 2023 Imagination Technologies Ltd. */
-
-#ifndef PVR_FW_META_H
-#define PVR_FW_META_H
-
-#include <linux/types.h>
-
-/* Forward declaration from pvr_device.h */
-struct pvr_device;
-
-int pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out);
-
-#endif /* PVR_FW_META_H */
diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c
index 6914fc46db50..ec0dad1692c3 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_mips.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c
@@ -196,4 +196,5 @@ const struct pvr_fw_defs pvr_fw_defs_mips = {
.irq_pending = pvr_mips_irq_pending,
.irq_clear = pvr_mips_irq_clear,
.has_fixed_data_addr = true,
+ .multi_dm_thread_assoc = false,
};
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
index 2b24c40bc20f..ef2801276252 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_riscv.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
@@ -182,4 +182,5 @@ const struct pvr_fw_defs pvr_fw_defs_riscv = {
.irq_pending = pvr_riscv_irq_pending,
.irq_clear = pvr_riscv_irq_clear,
.has_fixed_data_addr = false,
+ .multi_dm_thread_assoc = false,
};
diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
index 98ca2692239d..ab637ba7d108 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
@@ -3,10 +3,8 @@
#include "pvr_device.h"
#include "pvr_fw.h"
-#include "pvr_fw_meta.h"
#include "pvr_fw_startstop.h"
#include "pvr_rogue_cr_defs.h"
-#include "pvr_rogue_meta.h"
#include "pvr_vm.h"
#include <linux/compiler.h>
@@ -199,6 +197,30 @@ pvr_fw_start(struct pvr_device *pvr_dev)
return err;
}
+static inline bool layout_is_mars(struct pvr_device *pvr_dev)
+{
+ u64 layout_mars_value = 0;
+
+ if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value))
+ return false;
+
+ return layout_mars_value == 0;
+}
+
+static inline int must_wait_fw_idle_before_stop(struct pvr_device *pvr_dev)
+{
+ bool wait_fw_idle = true;
+ int err;
+
+ if (pvr_dev->fw_dev.defs->must_wait_fw_idle) {
+ err = pvr_dev->fw_dev.defs->must_wait_fw_idle(pvr_dev, &wait_fw_idle);
+ if (err)
+ return err;
+ }
+
+ return wait_fw_idle;
+}
+
/**
* pvr_fw_stop() - Stop FW processor
* @pvr_dev: Target PowerVR device.
@@ -214,15 +236,9 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
~(ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN |
ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN |
ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN);
- bool skip_garten_idle = false;
- u64 layout_mars_value = 0;
- bool layout_mars = false;
- bool meta_fw = pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META;
- u32 reg_value;
- int err;
- if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value) == 0)
- layout_mars = layout_mars_value > 0;
+ bool layout_mars = layout_is_mars(pvr_dev);
+ int err;
/*
* For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been
@@ -250,7 +266,7 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL &
ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK);
- if (meta_fw) {
+ if (pvr_dev->fw_dev.defs->multi_dm_thread_assoc) {
pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC,
ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL &
ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
@@ -297,6 +313,8 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
* powered down by the FW.
*/
if (!layout_mars) {
+ int wait_fw_idle;
+
/* Wait for SLC to signal IDLE. */
err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE,
ROGUE_CR_SLC_IDLE_MASKFULL,
@@ -309,24 +327,12 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
sidekick_idle_mask, POLL_TIMEOUT_USEC);
if (err)
return err;
- }
- if (meta_fw) {
- err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value);
- if (err)
- return err;
-
- /*
- * Wait for Sidekick/Jones to signal IDLE including the Garten
- * Wrapper if there is no debugger attached (TxVECINT_BHALT =
- * 0x0).
- */
- if (reg_value)
- skip_garten_idle = true;
- }
+ wait_fw_idle = must_wait_fw_idle_before_stop(pvr_dev);
+ if (wait_fw_idle < 0)
+ return wait_fw_idle;
- if (meta_fw || !layout_mars) {
- if (!skip_garten_idle) {
+ if (wait_fw_idle) {
err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE,
ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
@@ -346,7 +352,6 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
ROGUE_CR_MARS_IDLE_CPU_EN |
ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN,
POLL_TIMEOUT_USEC);
-
if (err)
return err;
}
diff --git a/drivers/gpu/drm/imagination/pvr_gem.h b/drivers/gpu/drm/imagination/pvr_gem.h
index ae7af82b6f17..e84be25f8576 100644
--- a/drivers/gpu/drm/imagination/pvr_gem.h
+++ b/drivers/gpu/drm/imagination/pvr_gem.h
@@ -5,7 +5,6 @@
#define PVR_GEM_H
#include "pvr_heap_config.h"
-#include "pvr_rogue_meta.h"
#include <uapi/drm/pvr_drm.h>
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_meta.h b/drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
similarity index 98%
rename from drivers/gpu/drm/imagination/pvr_rogue_meta.h
rename to drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
index 3020e6582daa..dd978988ed40 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_meta.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
@@ -1,8 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
-#ifndef PVR_ROGUE_META_H
-#define PVR_ROGUE_META_H
+#ifndef PVR_ROGUE_META_INTERNAL_H
+#define PVR_ROGUE_META_INTERNAL_H
+
+#ifndef PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
+#error This file may only be included if explicitly defined
+#endif
/***** The META HW register definitions in the file are updated manually *****/
@@ -353,4 +357,4 @@ struct rogue_meta_ldr_cfg_blk {
#define ROGUE_FW_PROCESSOR_META "META"
-#endif /* PVR_ROGUE_META_H */
+#endif /* PVR_ROGUE_META_INTERNAL_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v3 4/5] drm/imagination: Limit access to the META firmware interface
2026-11-03 8:36 ` Alexandru Dadu
(?)
@ 2026-11-03 8:46 ` sashiko-bot
-1 siblings, 0 replies; 13+ messages in thread
From: sashiko-bot @ 2026-11-03 8:46 UTC (permalink / raw)
To: Alexandru Dadu; +Cc: dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/imagination: inverted layout_mars_value check in layout_is_mars()
--
commit 4207fc7502d043d11f6874d92c1ba51c38ade0fe
Author: Alessio Belle <alessio.belle@imgtec.com>
drm/imagination: Limit access to the META firmware interface
This commit isolates access to the META firmware interface behind the
generic firmware processor table in struct pvr_fw_defs, removes
pvr_fw_meta.h, and renames pvr_rogue_meta.h to pvr_rogue_meta_internal.h.
> diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
> index 98ca2692239d0..ab637ba7d108c 100644
> --- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c
> +++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
[ ... ]
> @@ -199,6 +197,30 @@ pvr_fw_start(struct pvr_device *pvr_dev)
> return err;
> }
>
> +static inline bool layout_is_mars(struct pvr_device *pvr_dev)
> +{
> + u64 layout_mars_value = 0;
> +
> + if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value))
> + return false;
> +
> + return layout_mars_value == 0;
> +}
[Severity: High]
As reported by Sashiko on v2 [1], does layout_is_mars() invert the check on
layout_mars_value when PVR_FEATURE_VALUE() succeeds?
Prior to this change, pvr_fw_stop() checked:
if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value) == 0)
layout_mars = layout_mars_value > 0;
In layout_is_mars(), when PVR_FEATURE_VALUE() returns 0 (feature present),
it evaluates layout_mars_value == 0 instead of layout_mars_value > 0.
On cores with the layout_mars feature enabled (layout_mars_value > 0),
layout_is_mars() will return false, causing pvr_fw_stop() to poll
ROGUE_CR_SIDEKICK_IDLE and ROGUE_CR_SLC_IDLE (which are already powered
down by the firmware on MARS cores) and skip polling ROGUE_CR_MARS_IDLE
before asserting ROGUE_CR_SOFT_RESET. Should this return
layout_mars_value > 0 instead?
[1] https://lore.kernel.org/r/20261029-prep-meta-fw-arch-independent-v2-4-b9f5d69b7a52@imgtec.com
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261103-prep-meta-fw-arch-independent-v3-0-563dbaf1b779@imgtec.com?part=4
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 5/5] drm/imagination: Make the META firmware header arch-independent
2026-11-03 8:36 ` Alexandru Dadu
@ 2026-11-03 8:36 ` Alexandru Dadu
-1 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu,
Matt Coster
From: Alessio Belle <alessio.belle@imgtec.com>
This header file contains definitions common to all PowerVR
architectures starting from Rogue, so rename both the file and its
contents to reflect this.
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw_meta.c | 82 +++++-----
...ogue_meta_internal.h => pvr_fw_meta_internal.h} | 173 +++++++++++----------
2 files changed, 127 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c
index f451f97a4f2f..7f48b23b5c75 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_meta.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c
@@ -5,10 +5,10 @@
#include "pvr_fw.h"
#include "pvr_fw_info.h"
#include "pvr_gem.h"
+#define PVR_FW_META_INTERNAL_H_EXPLICIT_INCLUDE
+#include "pvr_fw_meta_internal.h"
+#undef PVR_FW_META_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_rogue_cr_defs.h"
-#define PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
-#include "pvr_rogue_meta_internal.h"
-#undef PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_vm.h"
#include <linux/compiler.h>
@@ -91,7 +91,7 @@ pvr_meta_wrapper_init(struct pvr_device *pvr_dev)
<< ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT;
/* Set SLC DM=META. */
- garten_config |= ((u64)ROGUE_FW_SEGMMU_META_BIFDM_ID)
+ garten_config |= ((u64)PVR_FW_SEGMMU_META_BIFDM_ID)
<< ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT;
pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, garten_config);
@@ -108,11 +108,11 @@ add_boot_arg(u32 **boot_conf, u32 param, u32 data)
static int
meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw,
- struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size, u8 *fw_code_ptr,
+ struct pvr_meta_ldr_l1_data_blk *l1_data, u32 coremem_size, u8 *fw_code_ptr,
u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr, const u32 fw_size)
{
- struct rogue_meta_ldr_l2_data_blk *l2_block =
- (struct rogue_meta_ldr_l2_data_blk *)(fw +
+ struct pvr_meta_ldr_l2_data_blk *l2_block =
+ (struct pvr_meta_ldr_l2_data_blk *)(fw +
l1_data->cmd_data[1]);
struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
u32 offset = l1_data->cmd_data[0];
@@ -131,8 +131,8 @@ meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw,
((((u8 *)l2_block->block_data) + data_size) - fw) >= fw_size)
return -EINVAL;
- if (!ROGUE_META_IS_COREMEM_CODE(offset, coremem_size) &&
- !ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
+ if (!PVR_META_IS_COREMEM_CODE(offset, coremem_size) &&
+ !PVR_META_IS_COREMEM_DATA(offset, coremem_size)) {
/* Global range is aliased to local range */
offset &= ~META_MEM_GLOBAL_RANGE_BIT;
}
@@ -153,7 +153,7 @@ meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw,
static int
meta_ldr_cmd_zeromem(struct drm_device *drm_dev,
- struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size,
+ struct pvr_meta_ldr_l1_data_blk *l1_data, u32 coremem_size,
u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr)
{
struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
@@ -162,7 +162,7 @@ meta_ldr_cmd_zeromem(struct drm_device *drm_dev,
void *write_addr;
int err;
- if (ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
+ if (PVR_META_IS_COREMEM_DATA(offset, coremem_size)) {
/* cannot zero coremem directly */
return 0;
}
@@ -186,13 +186,12 @@ meta_ldr_cmd_zeromem(struct drm_device *drm_dev,
static int
meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw,
- struct rogue_meta_ldr_l1_data_blk *l1_data,
+ struct pvr_meta_ldr_l1_data_blk *l1_data,
const u32 fw_size, u32 **boot_conf_ptr)
{
- struct rogue_meta_ldr_l2_data_blk *l2_block =
- (struct rogue_meta_ldr_l2_data_blk *)(fw +
- l1_data->cmd_data[0]);
- struct rogue_meta_ldr_cfg_blk *config_command;
+ struct pvr_meta_ldr_l2_data_blk *l2_block =
+ (struct pvr_meta_ldr_l2_data_blk *)(fw + l1_data->cmd_data[0]);
+ struct pvr_meta_ldr_cfg_blk *config_command;
u32 l2_block_size;
u32 curr_block_size = 0;
u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL;
@@ -202,14 +201,14 @@ meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw,
return -EINVAL;
l2_block_size = l2_block->length - 6 /* L2 Tag length and checksum */;
- config_command = (struct rogue_meta_ldr_cfg_blk *)l2_block->block_data;
+ config_command = (struct pvr_meta_ldr_cfg_blk *)l2_block->block_data;
if (((u8 *)config_command - fw) >= fw_size ||
((((u8 *)config_command) + l2_block_size) - fw) >= fw_size)
return -EINVAL;
while (l2_block_size >= 12) {
- if (config_command->type != ROGUE_META_LDR_CFG_WRITE)
+ if (config_command->type != PVR_META_LDR_CFG_WRITE)
return -EINVAL;
/*
@@ -227,7 +226,7 @@ meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw,
curr_block_size = 12;
l2_block_size -= curr_block_size;
- config_command = (struct rogue_meta_ldr_cfg_blk
+ config_command = (struct pvr_meta_ldr_cfg_blk
*)((uintptr_t)config_command +
curr_block_size);
}
@@ -259,10 +258,10 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
u8 *fw_core_data_ptr, u32 **boot_conf_ptr)
{
struct drm_device *drm_dev = from_pvr_device(pvr_dev);
- struct rogue_meta_ldr_block_hdr *ldr_header =
- (struct rogue_meta_ldr_block_hdr *)fw;
- struct rogue_meta_ldr_l1_data_blk *l1_data =
- (struct rogue_meta_ldr_l1_data_blk *)(fw + ldr_header->sl_data);
+ struct pvr_meta_ldr_block_hdr *ldr_header =
+ (struct pvr_meta_ldr_block_hdr *)fw;
+ struct pvr_meta_ldr_l1_data_blk *l1_data =
+ (struct pvr_meta_ldr_l1_data_blk *)(fw + ldr_header->sl_data);
const u32 fw_size = pvr_dev->fw_dev.firmware->size;
int err;
@@ -280,13 +279,13 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
if (((u8 *)l1_data - fw) >= fw_size || ((u8 *)(l1_data + 1) - fw) >= fw_size)
return -EINVAL;
- if (ROGUE_META_LDR_BLK_IS_COMMENT(l1_data->cmd)) {
+ if (PVR_META_LDR_BLK_IS_COMMENT(l1_data->cmd)) {
/* Don't process comment blocks */
goto next_block;
}
- switch (l1_data->cmd & ROGUE_META_LDR_CMD_MASK)
- case ROGUE_META_LDR_CMD_LOADMEM: {
+ switch (l1_data->cmd & PVR_META_LDR_CMD_MASK)
+ case PVR_META_LDR_CMD_LOADMEM: {
err = meta_ldr_cmd_loadmem(drm_dev, fw, l1_data,
coremem_size,
fw_code_ptr, fw_data_ptr,
@@ -296,11 +295,11 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
return err;
break;
- case ROGUE_META_LDR_CMD_START_THREADS:
+ case PVR_META_LDR_CMD_START_THREADS:
/* Don't process this block */
break;
- case ROGUE_META_LDR_CMD_ZEROMEM:
+ case PVR_META_LDR_CMD_ZEROMEM:
err = meta_ldr_cmd_zeromem(drm_dev, l1_data,
coremem_size,
fw_code_ptr, fw_data_ptr,
@@ -310,7 +309,7 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
return err;
break;
- case ROGUE_META_LDR_CMD_CONFIG:
+ case PVR_META_LDR_CMD_CONFIG:
err = meta_ldr_cmd_config(drm_dev, fw, l1_data, fw_size,
&boot_conf);
if (err)
@@ -325,8 +324,7 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
if (l1_data->next == 0xFFFFFFFF)
break;
- l1_data = (struct rogue_meta_ldr_l1_data_blk *)(fw +
- l1_data->next);
+ l1_data = (struct pvr_meta_ldr_l1_data_blk *)(fw + l1_data->next);
}
if (boot_conf_ptr)
@@ -344,12 +342,12 @@ configure_seg_id(u64 seg_out_addr, u32 seg_base, u32 seg_limit, u32 seg_id,
u32 *boot_conf = *boot_conf_ptr;
/* META segments have a minimum size. */
- u32 limit_off = max(seg_limit, ROGUE_FW_SEGMMU_ALIGN);
+ u32 limit_off = max(seg_limit, PVR_FW_SEGMMU_ALIGN);
/* The limit is an offset, therefore off = size - 1. */
limit_off -= 1;
- seg_base |= ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE;
+ seg_base |= PVR_FW_SEGMMU_ALLTHRS_WRITEABLE;
add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_BASE(seg_id), seg_base);
add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_LIMIT(seg_id), limit_off);
@@ -375,8 +373,8 @@ configure_seg_mmu(struct pvr_device *pvr_dev, u32 **boot_conf_ptr)
u64 seg_out_addr_top;
seg_out_addr_top =
- ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(MMU_CONTEXT_MAPPING_FWPRIV,
- ROGUE_FW_SEGMMU_META_BIFDM_ID);
+ PVR_FW_SEGMMU_OUTADDR_TOP_SLC(MMU_CONTEXT_MAPPING_FWPRIV,
+ PVR_FW_SEGMMU_META_BIFDM_ID);
for (u32 i = 0; i < num_layout_entries; i++) {
/*
@@ -385,7 +383,7 @@ configure_seg_mmu(struct pvr_device *pvr_dev, u32 **boot_conf_ptr)
* segment MMU. Only the FW data segment needs to be configured.
*/
if (layout_entries[i].type == FW_DATA) {
- u32 seg_id = ROGUE_FW_SEGMMU_DATA_ID;
+ u32 seg_id = PVR_FW_SEGMMU_DATA_ID;
u64 seg_out_addr = get_fw_obj_gpu_addr(pvr_dev->fw_dev.mem.data_obj);
seg_out_addr += layout_entries[i].alloc_offset;
@@ -463,7 +461,7 @@ pvr_meta_fw_process(struct pvr_device *pvr_dev, const u8 *fw,
u32 *boot_conf;
int err;
- boot_conf = ((u32 *)fw_code_ptr) + ROGUE_FW_BOOTLDR_CONF_OFFSET;
+ boot_conf = ((u32 *)fw_code_ptr) + PVR_FW_BOOTLDR_CONF_OFFSET;
/* Slave port and JTAG accesses are privileged. */
add_boot_arg(&boot_conf, META_CR_SYSC_JTAG_THREAD,
@@ -518,15 +516,15 @@ pvr_meta_fini(struct pvr_device *pvr_dev)
static u32
pvr_meta_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
{
- u32 fw_addr = fw_obj->fw_addr_offset + offset + ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS;
+ u32 fw_addr = fw_obj->fw_addr_offset + offset + PVR_FW_SEGMMU_DATA_BASE_ADDRESS;
/* META cacheability is determined by address. */
if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED) {
- fw_addr |= ROGUE_FW_SEGMMU_DATA_META_UNCACHED |
- ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED;
+ fw_addr |= PVR_FW_SEGMMU_DATA_META_UNCACHED |
+ PVR_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED;
} else {
- fw_addr |= ROGUE_FW_SEGMMU_DATA_META_CACHED |
- ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHED;
+ fw_addr |= PVR_FW_SEGMMU_DATA_META_CACHED |
+ PVR_FW_SEGMMU_DATA_VIVT_SLC_CACHED;
}
return fw_addr;
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h b/drivers/gpu/drm/imagination/pvr_fw_meta_internal.h
similarity index 69%
rename from drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
rename to drivers/gpu/drm/imagination/pvr_fw_meta_internal.h
index dd978988ed40..7d288a377bbb 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
+++ b/drivers/gpu/drm/imagination/pvr_fw_meta_internal.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
-#ifndef PVR_ROGUE_META_INTERNAL_H
-#define PVR_ROGUE_META_INTERNAL_H
+#ifndef PVR_FW_META_INTERNAL_H
+#define PVR_FW_META_INTERNAL_H
-#ifndef PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
+#ifndef PVR_FW_META_INTERNAL_H_EXPLICIT_INCLUDE
#error This file may only be included if explicitly defined
#endif
@@ -45,7 +45,7 @@
#define META_CR_PERF_ICORE1 (0x0480FFD8)
#define META_CR_PERF_ICORE_DCACHEMISS (0x8)
-#define META_CR_PERF_COUNT(ctrl, thr) \
+#define META_CR_PERF_COUNT(ctrl, thr) \
((META_CR_PERF_COUNT_CTRL_##ctrl << META_CR_PERF_COUNT_CTRL_SHIFT) | \
((thr) << META_CR_PERF_COUNT_THR_SHIFT))
@@ -74,8 +74,8 @@
#define META_CR_TXUPC_ID (0x5)
/* Macros to calculate register access values. */
-#define META_CR_CORE_REG(thr, reg_num, unit) \
- (((u32)(thr) << META_CR_TXUXXRXRQ_TX_S) | \
+#define META_CR_CORE_REG(thr, reg_num, unit) \
+ (((u32)(thr) << META_CR_TXUXXRXRQ_TX_S) | \
((u32)(reg_num) << META_CR_TXUXXRXRQ_RX_S) | \
((u32)(unit) << META_CR_TXUXXRXRQ_UXX_S))
@@ -140,7 +140,7 @@
******************************************************************************
*/
/* Block header structure. */
-struct rogue_meta_ldr_block_hdr {
+struct pvr_meta_ldr_block_hdr {
u32 dev_id;
u32 sl_code;
u32 sl_data;
@@ -149,7 +149,7 @@ struct rogue_meta_ldr_block_hdr {
};
/* High level data stream block structure. */
-struct rogue_meta_ldr_l1_data_blk {
+struct pvr_meta_ldr_l1_data_blk {
u16 cmd;
u16 length;
u32 next;
@@ -157,21 +157,21 @@ struct rogue_meta_ldr_l1_data_blk {
};
/* High level data stream block structure. */
-struct rogue_meta_ldr_l2_data_blk {
+struct pvr_meta_ldr_l2_data_blk {
u16 tag;
u16 length;
u32 block_data[4];
};
/* Config command structure. */
-struct rogue_meta_ldr_cfg_blk {
+struct pvr_meta_ldr_cfg_blk {
u32 type;
u32 block_data[4];
};
/* Block type definitions */
-#define ROGUE_META_LDR_COMMENT_TYPE_MASK (0x0010U)
-#define ROGUE_META_LDR_BLK_IS_COMMENT(x) (((x) & ROGUE_META_LDR_COMMENT_TYPE_MASK) != 0U)
+#define PVR_META_LDR_COMMENT_TYPE_MASK (0x0010U)
+#define PVR_META_LDR_BLK_IS_COMMENT(x) (((x) & PVR_META_LDR_COMMENT_TYPE_MASK) != 0U)
/*
* Command definitions
@@ -183,14 +183,14 @@ struct rogue_meta_ldr_cfg_blk {
* 4 ZeroMem Zeros a memory region.
* 5 Config Perform a configuration command.
*/
-#define ROGUE_META_LDR_CMD_MASK (0x000FU)
+#define PVR_META_LDR_CMD_MASK (0x000FU)
-#define ROGUE_META_LDR_CMD_LOADMEM (0x0000U)
-#define ROGUE_META_LDR_CMD_LOADCORE (0x0001U)
-#define ROGUE_META_LDR_CMD_LOADMMREG (0x0002U)
-#define ROGUE_META_LDR_CMD_START_THREADS (0x0003U)
-#define ROGUE_META_LDR_CMD_ZEROMEM (0x0004U)
-#define ROGUE_META_LDR_CMD_CONFIG (0x0005U)
+#define PVR_META_LDR_CMD_LOADMEM (0x0000U)
+#define PVR_META_LDR_CMD_LOADCORE (0x0001U)
+#define PVR_META_LDR_CMD_LOADMMREG (0x0002U)
+#define PVR_META_LDR_CMD_START_THREADS (0x0003U)
+#define PVR_META_LDR_CMD_ZEROMEM (0x0004U)
+#define PVR_META_LDR_CMD_CONFIG (0x0005U)
/*
* Config Command definitions
@@ -202,61 +202,61 @@ struct rogue_meta_ldr_cfg_blk {
* 3 MemSet Set mem to value
* 4 MemCheck check mem for specific value.
*/
-#define ROGUE_META_LDR_CFG_PAUSE (0x0000)
-#define ROGUE_META_LDR_CFG_READ (0x0001)
-#define ROGUE_META_LDR_CFG_WRITE (0x0002)
-#define ROGUE_META_LDR_CFG_MEMSET (0x0003)
-#define ROGUE_META_LDR_CFG_MEMCHECK (0x0004)
+#define PVR_META_LDR_CFG_PAUSE (0x0000)
+#define PVR_META_LDR_CFG_READ (0x0001)
+#define PVR_META_LDR_CFG_WRITE (0x0002)
+#define PVR_META_LDR_CFG_MEMSET (0x0003)
+#define PVR_META_LDR_CFG_MEMCHECK (0x0004)
/*
******************************************************************************
- * ROGUE FW segmented MMU definitions
+ * META segmented MMU definitions
******************************************************************************
*/
/* All threads can access the segment. */
-#define ROGUE_FW_SEGMMU_ALLTHRS (0xf << 8U)
+#define PVR_FW_SEGMMU_ALLTHRS (0xf << 8U)
/* Writable. */
-#define ROGUE_FW_SEGMMU_WRITEABLE (0x1U << 1U)
+#define PVR_FW_SEGMMU_WRITEABLE (0x1U << 1U)
/* All threads can access and writable. */
-#define ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE \
- (ROGUE_FW_SEGMMU_ALLTHRS | ROGUE_FW_SEGMMU_WRITEABLE)
+#define PVR_FW_SEGMMU_ALLTHRS_WRITEABLE \
+ (PVR_FW_SEGMMU_ALLTHRS | PVR_FW_SEGMMU_WRITEABLE)
/* Direct map region 10 used for mapping GPU memory - max 8MB. */
-#define ROGUE_FW_SEGMMU_DMAP_GPU_ID (10U)
-#define ROGUE_FW_SEGMMU_DMAP_GPU_ADDR_START (0x07000000U)
-#define ROGUE_FW_SEGMMU_DMAP_GPU_MAX_SIZE (0x00800000U)
+#define PVR_FW_SEGMMU_DMAP_GPU_ID (10U)
+#define PVR_FW_SEGMMU_DMAP_GPU_ADDR_START (0x07000000U)
+#define PVR_FW_SEGMMU_DMAP_GPU_MAX_SIZE (0x00800000U)
/* Segment IDs. */
-#define ROGUE_FW_SEGMMU_DATA_ID (1U)
-#define ROGUE_FW_SEGMMU_BOOTLDR_ID (2U)
-#define ROGUE_FW_SEGMMU_TEXT_ID (ROGUE_FW_SEGMMU_BOOTLDR_ID)
+#define PVR_FW_SEGMMU_DATA_ID (1U)
+#define PVR_FW_SEGMMU_BOOTLDR_ID (2U)
+#define PVR_FW_SEGMMU_TEXT_ID (PVR_FW_SEGMMU_BOOTLDR_ID)
/*
* SLC caching strategy in S7 and volcanic is emitted through the segment MMU.
- * All the segments configured through the macro ROGUE_FW_SEGMMU_OUTADDR_TOP are
+ * All the segments configured through the macro PVR_FW_SEGMMU_OUTADDR_TOP are
* CACHED in the SLC.
* The interface has been kept the same to simplify the code changes.
* The bifdm argument is ignored (no longer relevant) in S7 and volcanic.
*/
-#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) \
+#define PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) \
((((u64)((pers) & 0x3)) << 52) | (((u64)((mmu_ctx) & 0xFF)) << 44) | \
(((u64)((slc_policy) & 0x1)) << 40))
-#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) \
- ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3, 0x0, mmu_ctx)
-#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) \
- ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0, 0x1, mmu_ctx)
+#define PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) \
+ PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3, 0x0, mmu_ctx)
+#define PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) \
+ PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0, 0x1, mmu_ctx)
/*
* To configure the Page Catalog and BIF-DM fed into the BIF for Garten
* accesses through this segment.
*/
-#define ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(pc, bifdm) \
+#define PVR_FW_SEGMMU_OUTADDR_TOP_SLC(pc, bifdm) \
(((u64)((u64)(pc) & 0xFU) << 44U) | ((u64)((u64)(bifdm) & 0xFU) << 40U))
-#define ROGUE_FW_SEGMMU_META_BIFDM_ID (0x7U)
+#define PVR_FW_SEGMMU_META_BIFDM_ID (0x7U)
/* META segments have 4kB minimum size. */
-#define ROGUE_FW_SEGMMU_ALIGN (0x1000U)
+#define PVR_FW_SEGMMU_ALIGN (0x1000U)
/* Segmented MMU registers (n = segment id). */
#define META_CR_MMCU_SEGMENT_N_BASE(n) (0x04850000U + ((n) * 0x10U))
@@ -273,72 +273,73 @@ struct rogue_meta_ldr_cfg_blk {
* - SLC cached, META cached, FW base address 0x10000000
* - SLC cached, META uncached, FW base address 0x90000000
*/
-#define ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS (0x10000000U)
-#define ROGUE_FW_SEGMMU_DATA_META_CACHED (0x0U)
-#define ROGUE_FW_SEGMMU_DATA_META_UNCACHED (META_MEM_GLOBAL_RANGE_BIT)
-#define ROGUE_FW_SEGMMU_DATA_META_CACHE_MASK (META_MEM_GLOBAL_RANGE_BIT)
+#define PVR_FW_SEGMMU_DATA_BASE_ADDRESS (0x10000000U)
+#define PVR_FW_SEGMMU_DATA_META_CACHED (0x0U)
+#define PVR_FW_SEGMMU_DATA_META_UNCACHED (META_MEM_GLOBAL_RANGE_BIT)
+#define PVR_FW_SEGMMU_DATA_META_CACHE_MASK (META_MEM_GLOBAL_RANGE_BIT)
/*
* For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
* the PTEs for the FW data, not in the Meta Segment MMU, which means these
* defines have no real effect in those cases.
*/
-#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHED (0x0U)
-#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED (0x60000000U)
-#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK (0x60000000U)
+#define PVR_FW_SEGMMU_DATA_VIVT_SLC_CACHED (0x0U)
+#define PVR_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED (0x60000000U)
+#define PVR_FW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK (0x60000000U)
/*
******************************************************************************
- * ROGUE FW Bootloader defaults
+ * META Bootloader defaults
******************************************************************************
*/
-#define ROGUE_FW_BOOTLDR_META_ADDR (0x40000000U)
-#define ROGUE_FW_BOOTLDR_DEVV_ADDR_0 (0xC0000000U)
-#define ROGUE_FW_BOOTLDR_DEVV_ADDR_1 (0x000000E1)
-#define ROGUE_FW_BOOTLDR_DEVV_ADDR \
- ((((u64)ROGUE_FW_BOOTLDR_DEVV_ADDR_1) << 32) | \
- ROGUE_FW_BOOTLDR_DEVV_ADDR_0)
-#define ROGUE_FW_BOOTLDR_LIMIT (0x1FFFF000)
-#define ROGUE_FW_MAX_BOOTLDR_OFFSET (0x1000)
+#define PVR_FW_BOOTLDR_META_ADDR (0x40000000U)
+#define PVR_FW_BOOTLDR_DEVV_ADDR_0 (0xC0000000U)
+#define PVR_FW_BOOTLDR_DEVV_ADDR_1 (0x000000E1)
+#define PVR_FW_BOOTLDR_DEVV_ADDR \
+ ((((u64)PVR_FW_BOOTLDR_DEVV_ADDR_1) << 32) | \
+ PVR_FW_BOOTLDR_DEVV_ADDR_0)
+#define PVR_FW_BOOTLDR_LIMIT (0x1FFFF000)
+#define PVR_FW_MAX_BOOTLDR_OFFSET (0x1000)
/* Bootloader configuration offset is in dwords (512 bytes) */
-#define ROGUE_FW_BOOTLDR_CONF_OFFSET (0x80)
+#define PVR_FW_BOOTLDR_CONF_OFFSET (0x80)
/*
******************************************************************************
- * ROGUE META Stack
+ * META Stack
******************************************************************************
*/
-#define ROGUE_META_STACK_SIZE (0x1000U)
+#define PVR_META_STACK_SIZE (0x1000U)
/*
******************************************************************************
- * ROGUE META Core memory
+ * META Core memory
******************************************************************************
*/
/* Code and data both map to the same physical memory. */
-#define ROGUE_META_COREMEM_CODE_ADDR (0x80000000U)
-#define ROGUE_META_COREMEM_DATA_ADDR (0x82000000U)
-#define ROGUE_META_COREMEM_OFFSET_MASK (0x01ffffffU)
-
-#define ROGUE_META_IS_COREMEM_CODE(a, b) \
- ({ \
- u32 _a = (a), _b = (b); \
- ((_a) >= ROGUE_META_COREMEM_CODE_ADDR) && \
- ((_a) < (ROGUE_META_COREMEM_CODE_ADDR + (_b))); \
+#define PVR_META_COREMEM_CODE_ADDR (0x80000000U)
+#define PVR_META_COREMEM_DATA_ADDR (0x82000000U)
+#define PVR_META_COREMEM_OFFSET_MASK (0x01ffffffU)
+
+#define PVR_META_IS_COREMEM_CODE(a, b) \
+ ({ \
+ u32 _a = (a), _b = (b); \
+ ((_a) >= PVR_META_COREMEM_CODE_ADDR) && \
+ ((_a) < (PVR_META_COREMEM_CODE_ADDR + (_b))); \
})
-#define ROGUE_META_IS_COREMEM_DATA(a, b) \
- ({ \
- u32 _a = (a), _b = (b); \
- ((_a) >= ROGUE_META_COREMEM_DATA_ADDR) && \
- ((_a) < (ROGUE_META_COREMEM_DATA_ADDR + (_b))); \
+#define PVR_META_IS_COREMEM_DATA(a, b) \
+ ({ \
+ u32 _a = (a), _b = (b); \
+ ((_a) >= PVR_META_COREMEM_DATA_ADDR) && \
+ ((_a) < (PVR_META_COREMEM_DATA_ADDR + (_b))); \
})
+
/*
******************************************************************************
* 2nd thread
******************************************************************************
*/
-#define ROGUE_FW_THR1_PC (0x18930000)
-#define ROGUE_FW_THR1_SP (0x78890000)
+#define PVR_FW_THR1_PC (0x18930000)
+#define PVR_FW_THR1_SP (0x78890000)
/*
******************************************************************************
@@ -350,11 +351,11 @@ struct rogue_meta_ldr_cfg_blk {
#define META_CR_CORE_ID_VER_SHIFT (16U)
#define META_CR_CORE_ID_VER_CLRMSK (0XFF00FFFFU)
-#define ROGUE_CR_META_MTP218_CORE_ID_VALUE 0x19
-#define ROGUE_CR_META_MTP219_CORE_ID_VALUE 0x1E
-#define ROGUE_CR_META_LTP218_CORE_ID_VALUE 0x1C
-#define ROGUE_CR_META_LTP217_CORE_ID_VALUE 0x1F
+#define PVR_CR_META_MTP218_CORE_ID_VALUE 0x19
+#define PVR_CR_META_MTP219_CORE_ID_VALUE 0x1E
+#define PVR_CR_META_LTP218_CORE_ID_VALUE 0x1C
+#define PVR_CR_META_LTP217_CORE_ID_VALUE 0x1F
-#define ROGUE_FW_PROCESSOR_META "META"
+#define PVR_FW_PROCESSOR_META "META"
-#endif /* PVR_ROGUE_META_INTERNAL_H */
+#endif /* PVR_FW_META_INTERNAL_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v3 5/5] drm/imagination: Make the META firmware header arch-independent
@ 2026-11-03 8:36 ` Alexandru Dadu
0 siblings, 0 replies; 13+ messages in thread
From: Alexandru Dadu @ 2026-11-03 8:36 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-riscv, linux-kernel, Alexandru Dadu,
Matt Coster
From: Alessio Belle <alessio.belle@imgtec.com>
This header file contains definitions common to all PowerVR
architectures starting from Rogue, so rename both the file and its
contents to reflect this.
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw_meta.c | 82 +++++-----
...ogue_meta_internal.h => pvr_fw_meta_internal.h} | 173 +++++++++++----------
2 files changed, 127 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c
index f451f97a4f2f..7f48b23b5c75 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_meta.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c
@@ -5,10 +5,10 @@
#include "pvr_fw.h"
#include "pvr_fw_info.h"
#include "pvr_gem.h"
+#define PVR_FW_META_INTERNAL_H_EXPLICIT_INCLUDE
+#include "pvr_fw_meta_internal.h"
+#undef PVR_FW_META_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_rogue_cr_defs.h"
-#define PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
-#include "pvr_rogue_meta_internal.h"
-#undef PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
#include "pvr_vm.h"
#include <linux/compiler.h>
@@ -91,7 +91,7 @@ pvr_meta_wrapper_init(struct pvr_device *pvr_dev)
<< ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT;
/* Set SLC DM=META. */
- garten_config |= ((u64)ROGUE_FW_SEGMMU_META_BIFDM_ID)
+ garten_config |= ((u64)PVR_FW_SEGMMU_META_BIFDM_ID)
<< ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT;
pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, garten_config);
@@ -108,11 +108,11 @@ add_boot_arg(u32 **boot_conf, u32 param, u32 data)
static int
meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw,
- struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size, u8 *fw_code_ptr,
+ struct pvr_meta_ldr_l1_data_blk *l1_data, u32 coremem_size, u8 *fw_code_ptr,
u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr, const u32 fw_size)
{
- struct rogue_meta_ldr_l2_data_blk *l2_block =
- (struct rogue_meta_ldr_l2_data_blk *)(fw +
+ struct pvr_meta_ldr_l2_data_blk *l2_block =
+ (struct pvr_meta_ldr_l2_data_blk *)(fw +
l1_data->cmd_data[1]);
struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
u32 offset = l1_data->cmd_data[0];
@@ -131,8 +131,8 @@ meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw,
((((u8 *)l2_block->block_data) + data_size) - fw) >= fw_size)
return -EINVAL;
- if (!ROGUE_META_IS_COREMEM_CODE(offset, coremem_size) &&
- !ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
+ if (!PVR_META_IS_COREMEM_CODE(offset, coremem_size) &&
+ !PVR_META_IS_COREMEM_DATA(offset, coremem_size)) {
/* Global range is aliased to local range */
offset &= ~META_MEM_GLOBAL_RANGE_BIT;
}
@@ -153,7 +153,7 @@ meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw,
static int
meta_ldr_cmd_zeromem(struct drm_device *drm_dev,
- struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size,
+ struct pvr_meta_ldr_l1_data_blk *l1_data, u32 coremem_size,
u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr)
{
struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
@@ -162,7 +162,7 @@ meta_ldr_cmd_zeromem(struct drm_device *drm_dev,
void *write_addr;
int err;
- if (ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
+ if (PVR_META_IS_COREMEM_DATA(offset, coremem_size)) {
/* cannot zero coremem directly */
return 0;
}
@@ -186,13 +186,12 @@ meta_ldr_cmd_zeromem(struct drm_device *drm_dev,
static int
meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw,
- struct rogue_meta_ldr_l1_data_blk *l1_data,
+ struct pvr_meta_ldr_l1_data_blk *l1_data,
const u32 fw_size, u32 **boot_conf_ptr)
{
- struct rogue_meta_ldr_l2_data_blk *l2_block =
- (struct rogue_meta_ldr_l2_data_blk *)(fw +
- l1_data->cmd_data[0]);
- struct rogue_meta_ldr_cfg_blk *config_command;
+ struct pvr_meta_ldr_l2_data_blk *l2_block =
+ (struct pvr_meta_ldr_l2_data_blk *)(fw + l1_data->cmd_data[0]);
+ struct pvr_meta_ldr_cfg_blk *config_command;
u32 l2_block_size;
u32 curr_block_size = 0;
u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL;
@@ -202,14 +201,14 @@ meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw,
return -EINVAL;
l2_block_size = l2_block->length - 6 /* L2 Tag length and checksum */;
- config_command = (struct rogue_meta_ldr_cfg_blk *)l2_block->block_data;
+ config_command = (struct pvr_meta_ldr_cfg_blk *)l2_block->block_data;
if (((u8 *)config_command - fw) >= fw_size ||
((((u8 *)config_command) + l2_block_size) - fw) >= fw_size)
return -EINVAL;
while (l2_block_size >= 12) {
- if (config_command->type != ROGUE_META_LDR_CFG_WRITE)
+ if (config_command->type != PVR_META_LDR_CFG_WRITE)
return -EINVAL;
/*
@@ -227,7 +226,7 @@ meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw,
curr_block_size = 12;
l2_block_size -= curr_block_size;
- config_command = (struct rogue_meta_ldr_cfg_blk
+ config_command = (struct pvr_meta_ldr_cfg_blk
*)((uintptr_t)config_command +
curr_block_size);
}
@@ -259,10 +258,10 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
u8 *fw_core_data_ptr, u32 **boot_conf_ptr)
{
struct drm_device *drm_dev = from_pvr_device(pvr_dev);
- struct rogue_meta_ldr_block_hdr *ldr_header =
- (struct rogue_meta_ldr_block_hdr *)fw;
- struct rogue_meta_ldr_l1_data_blk *l1_data =
- (struct rogue_meta_ldr_l1_data_blk *)(fw + ldr_header->sl_data);
+ struct pvr_meta_ldr_block_hdr *ldr_header =
+ (struct pvr_meta_ldr_block_hdr *)fw;
+ struct pvr_meta_ldr_l1_data_blk *l1_data =
+ (struct pvr_meta_ldr_l1_data_blk *)(fw + ldr_header->sl_data);
const u32 fw_size = pvr_dev->fw_dev.firmware->size;
int err;
@@ -280,13 +279,13 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
if (((u8 *)l1_data - fw) >= fw_size || ((u8 *)(l1_data + 1) - fw) >= fw_size)
return -EINVAL;
- if (ROGUE_META_LDR_BLK_IS_COMMENT(l1_data->cmd)) {
+ if (PVR_META_LDR_BLK_IS_COMMENT(l1_data->cmd)) {
/* Don't process comment blocks */
goto next_block;
}
- switch (l1_data->cmd & ROGUE_META_LDR_CMD_MASK)
- case ROGUE_META_LDR_CMD_LOADMEM: {
+ switch (l1_data->cmd & PVR_META_LDR_CMD_MASK)
+ case PVR_META_LDR_CMD_LOADMEM: {
err = meta_ldr_cmd_loadmem(drm_dev, fw, l1_data,
coremem_size,
fw_code_ptr, fw_data_ptr,
@@ -296,11 +295,11 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
return err;
break;
- case ROGUE_META_LDR_CMD_START_THREADS:
+ case PVR_META_LDR_CMD_START_THREADS:
/* Don't process this block */
break;
- case ROGUE_META_LDR_CMD_ZEROMEM:
+ case PVR_META_LDR_CMD_ZEROMEM:
err = meta_ldr_cmd_zeromem(drm_dev, l1_data,
coremem_size,
fw_code_ptr, fw_data_ptr,
@@ -310,7 +309,7 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
return err;
break;
- case ROGUE_META_LDR_CMD_CONFIG:
+ case PVR_META_LDR_CMD_CONFIG:
err = meta_ldr_cmd_config(drm_dev, fw, l1_data, fw_size,
&boot_conf);
if (err)
@@ -325,8 +324,7 @@ process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code
if (l1_data->next == 0xFFFFFFFF)
break;
- l1_data = (struct rogue_meta_ldr_l1_data_blk *)(fw +
- l1_data->next);
+ l1_data = (struct pvr_meta_ldr_l1_data_blk *)(fw + l1_data->next);
}
if (boot_conf_ptr)
@@ -344,12 +342,12 @@ configure_seg_id(u64 seg_out_addr, u32 seg_base, u32 seg_limit, u32 seg_id,
u32 *boot_conf = *boot_conf_ptr;
/* META segments have a minimum size. */
- u32 limit_off = max(seg_limit, ROGUE_FW_SEGMMU_ALIGN);
+ u32 limit_off = max(seg_limit, PVR_FW_SEGMMU_ALIGN);
/* The limit is an offset, therefore off = size - 1. */
limit_off -= 1;
- seg_base |= ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE;
+ seg_base |= PVR_FW_SEGMMU_ALLTHRS_WRITEABLE;
add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_BASE(seg_id), seg_base);
add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_LIMIT(seg_id), limit_off);
@@ -375,8 +373,8 @@ configure_seg_mmu(struct pvr_device *pvr_dev, u32 **boot_conf_ptr)
u64 seg_out_addr_top;
seg_out_addr_top =
- ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(MMU_CONTEXT_MAPPING_FWPRIV,
- ROGUE_FW_SEGMMU_META_BIFDM_ID);
+ PVR_FW_SEGMMU_OUTADDR_TOP_SLC(MMU_CONTEXT_MAPPING_FWPRIV,
+ PVR_FW_SEGMMU_META_BIFDM_ID);
for (u32 i = 0; i < num_layout_entries; i++) {
/*
@@ -385,7 +383,7 @@ configure_seg_mmu(struct pvr_device *pvr_dev, u32 **boot_conf_ptr)
* segment MMU. Only the FW data segment needs to be configured.
*/
if (layout_entries[i].type == FW_DATA) {
- u32 seg_id = ROGUE_FW_SEGMMU_DATA_ID;
+ u32 seg_id = PVR_FW_SEGMMU_DATA_ID;
u64 seg_out_addr = get_fw_obj_gpu_addr(pvr_dev->fw_dev.mem.data_obj);
seg_out_addr += layout_entries[i].alloc_offset;
@@ -463,7 +461,7 @@ pvr_meta_fw_process(struct pvr_device *pvr_dev, const u8 *fw,
u32 *boot_conf;
int err;
- boot_conf = ((u32 *)fw_code_ptr) + ROGUE_FW_BOOTLDR_CONF_OFFSET;
+ boot_conf = ((u32 *)fw_code_ptr) + PVR_FW_BOOTLDR_CONF_OFFSET;
/* Slave port and JTAG accesses are privileged. */
add_boot_arg(&boot_conf, META_CR_SYSC_JTAG_THREAD,
@@ -518,15 +516,15 @@ pvr_meta_fini(struct pvr_device *pvr_dev)
static u32
pvr_meta_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
{
- u32 fw_addr = fw_obj->fw_addr_offset + offset + ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS;
+ u32 fw_addr = fw_obj->fw_addr_offset + offset + PVR_FW_SEGMMU_DATA_BASE_ADDRESS;
/* META cacheability is determined by address. */
if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED) {
- fw_addr |= ROGUE_FW_SEGMMU_DATA_META_UNCACHED |
- ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED;
+ fw_addr |= PVR_FW_SEGMMU_DATA_META_UNCACHED |
+ PVR_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED;
} else {
- fw_addr |= ROGUE_FW_SEGMMU_DATA_META_CACHED |
- ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHED;
+ fw_addr |= PVR_FW_SEGMMU_DATA_META_CACHED |
+ PVR_FW_SEGMMU_DATA_VIVT_SLC_CACHED;
}
return fw_addr;
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h b/drivers/gpu/drm/imagination/pvr_fw_meta_internal.h
similarity index 69%
rename from drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
rename to drivers/gpu/drm/imagination/pvr_fw_meta_internal.h
index dd978988ed40..7d288a377bbb 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_meta_internal.h
+++ b/drivers/gpu/drm/imagination/pvr_fw_meta_internal.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/* Copyright (c) 2023 Imagination Technologies Ltd. */
-#ifndef PVR_ROGUE_META_INTERNAL_H
-#define PVR_ROGUE_META_INTERNAL_H
+#ifndef PVR_FW_META_INTERNAL_H
+#define PVR_FW_META_INTERNAL_H
-#ifndef PVR_ROGUE_META_INTERNAL_H_EXPLICIT_INCLUDE
+#ifndef PVR_FW_META_INTERNAL_H_EXPLICIT_INCLUDE
#error This file may only be included if explicitly defined
#endif
@@ -45,7 +45,7 @@
#define META_CR_PERF_ICORE1 (0x0480FFD8)
#define META_CR_PERF_ICORE_DCACHEMISS (0x8)
-#define META_CR_PERF_COUNT(ctrl, thr) \
+#define META_CR_PERF_COUNT(ctrl, thr) \
((META_CR_PERF_COUNT_CTRL_##ctrl << META_CR_PERF_COUNT_CTRL_SHIFT) | \
((thr) << META_CR_PERF_COUNT_THR_SHIFT))
@@ -74,8 +74,8 @@
#define META_CR_TXUPC_ID (0x5)
/* Macros to calculate register access values. */
-#define META_CR_CORE_REG(thr, reg_num, unit) \
- (((u32)(thr) << META_CR_TXUXXRXRQ_TX_S) | \
+#define META_CR_CORE_REG(thr, reg_num, unit) \
+ (((u32)(thr) << META_CR_TXUXXRXRQ_TX_S) | \
((u32)(reg_num) << META_CR_TXUXXRXRQ_RX_S) | \
((u32)(unit) << META_CR_TXUXXRXRQ_UXX_S))
@@ -140,7 +140,7 @@
******************************************************************************
*/
/* Block header structure. */
-struct rogue_meta_ldr_block_hdr {
+struct pvr_meta_ldr_block_hdr {
u32 dev_id;
u32 sl_code;
u32 sl_data;
@@ -149,7 +149,7 @@ struct rogue_meta_ldr_block_hdr {
};
/* High level data stream block structure. */
-struct rogue_meta_ldr_l1_data_blk {
+struct pvr_meta_ldr_l1_data_blk {
u16 cmd;
u16 length;
u32 next;
@@ -157,21 +157,21 @@ struct rogue_meta_ldr_l1_data_blk {
};
/* High level data stream block structure. */
-struct rogue_meta_ldr_l2_data_blk {
+struct pvr_meta_ldr_l2_data_blk {
u16 tag;
u16 length;
u32 block_data[4];
};
/* Config command structure. */
-struct rogue_meta_ldr_cfg_blk {
+struct pvr_meta_ldr_cfg_blk {
u32 type;
u32 block_data[4];
};
/* Block type definitions */
-#define ROGUE_META_LDR_COMMENT_TYPE_MASK (0x0010U)
-#define ROGUE_META_LDR_BLK_IS_COMMENT(x) (((x) & ROGUE_META_LDR_COMMENT_TYPE_MASK) != 0U)
+#define PVR_META_LDR_COMMENT_TYPE_MASK (0x0010U)
+#define PVR_META_LDR_BLK_IS_COMMENT(x) (((x) & PVR_META_LDR_COMMENT_TYPE_MASK) != 0U)
/*
* Command definitions
@@ -183,14 +183,14 @@ struct rogue_meta_ldr_cfg_blk {
* 4 ZeroMem Zeros a memory region.
* 5 Config Perform a configuration command.
*/
-#define ROGUE_META_LDR_CMD_MASK (0x000FU)
+#define PVR_META_LDR_CMD_MASK (0x000FU)
-#define ROGUE_META_LDR_CMD_LOADMEM (0x0000U)
-#define ROGUE_META_LDR_CMD_LOADCORE (0x0001U)
-#define ROGUE_META_LDR_CMD_LOADMMREG (0x0002U)
-#define ROGUE_META_LDR_CMD_START_THREADS (0x0003U)
-#define ROGUE_META_LDR_CMD_ZEROMEM (0x0004U)
-#define ROGUE_META_LDR_CMD_CONFIG (0x0005U)
+#define PVR_META_LDR_CMD_LOADMEM (0x0000U)
+#define PVR_META_LDR_CMD_LOADCORE (0x0001U)
+#define PVR_META_LDR_CMD_LOADMMREG (0x0002U)
+#define PVR_META_LDR_CMD_START_THREADS (0x0003U)
+#define PVR_META_LDR_CMD_ZEROMEM (0x0004U)
+#define PVR_META_LDR_CMD_CONFIG (0x0005U)
/*
* Config Command definitions
@@ -202,61 +202,61 @@ struct rogue_meta_ldr_cfg_blk {
* 3 MemSet Set mem to value
* 4 MemCheck check mem for specific value.
*/
-#define ROGUE_META_LDR_CFG_PAUSE (0x0000)
-#define ROGUE_META_LDR_CFG_READ (0x0001)
-#define ROGUE_META_LDR_CFG_WRITE (0x0002)
-#define ROGUE_META_LDR_CFG_MEMSET (0x0003)
-#define ROGUE_META_LDR_CFG_MEMCHECK (0x0004)
+#define PVR_META_LDR_CFG_PAUSE (0x0000)
+#define PVR_META_LDR_CFG_READ (0x0001)
+#define PVR_META_LDR_CFG_WRITE (0x0002)
+#define PVR_META_LDR_CFG_MEMSET (0x0003)
+#define PVR_META_LDR_CFG_MEMCHECK (0x0004)
/*
******************************************************************************
- * ROGUE FW segmented MMU definitions
+ * META segmented MMU definitions
******************************************************************************
*/
/* All threads can access the segment. */
-#define ROGUE_FW_SEGMMU_ALLTHRS (0xf << 8U)
+#define PVR_FW_SEGMMU_ALLTHRS (0xf << 8U)
/* Writable. */
-#define ROGUE_FW_SEGMMU_WRITEABLE (0x1U << 1U)
+#define PVR_FW_SEGMMU_WRITEABLE (0x1U << 1U)
/* All threads can access and writable. */
-#define ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE \
- (ROGUE_FW_SEGMMU_ALLTHRS | ROGUE_FW_SEGMMU_WRITEABLE)
+#define PVR_FW_SEGMMU_ALLTHRS_WRITEABLE \
+ (PVR_FW_SEGMMU_ALLTHRS | PVR_FW_SEGMMU_WRITEABLE)
/* Direct map region 10 used for mapping GPU memory - max 8MB. */
-#define ROGUE_FW_SEGMMU_DMAP_GPU_ID (10U)
-#define ROGUE_FW_SEGMMU_DMAP_GPU_ADDR_START (0x07000000U)
-#define ROGUE_FW_SEGMMU_DMAP_GPU_MAX_SIZE (0x00800000U)
+#define PVR_FW_SEGMMU_DMAP_GPU_ID (10U)
+#define PVR_FW_SEGMMU_DMAP_GPU_ADDR_START (0x07000000U)
+#define PVR_FW_SEGMMU_DMAP_GPU_MAX_SIZE (0x00800000U)
/* Segment IDs. */
-#define ROGUE_FW_SEGMMU_DATA_ID (1U)
-#define ROGUE_FW_SEGMMU_BOOTLDR_ID (2U)
-#define ROGUE_FW_SEGMMU_TEXT_ID (ROGUE_FW_SEGMMU_BOOTLDR_ID)
+#define PVR_FW_SEGMMU_DATA_ID (1U)
+#define PVR_FW_SEGMMU_BOOTLDR_ID (2U)
+#define PVR_FW_SEGMMU_TEXT_ID (PVR_FW_SEGMMU_BOOTLDR_ID)
/*
* SLC caching strategy in S7 and volcanic is emitted through the segment MMU.
- * All the segments configured through the macro ROGUE_FW_SEGMMU_OUTADDR_TOP are
+ * All the segments configured through the macro PVR_FW_SEGMMU_OUTADDR_TOP are
* CACHED in the SLC.
* The interface has been kept the same to simplify the code changes.
* The bifdm argument is ignored (no longer relevant) in S7 and volcanic.
*/
-#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) \
+#define PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) \
((((u64)((pers) & 0x3)) << 52) | (((u64)((mmu_ctx) & 0xFF)) << 44) | \
(((u64)((slc_policy) & 0x1)) << 40))
-#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) \
- ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3, 0x0, mmu_ctx)
-#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) \
- ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0, 0x1, mmu_ctx)
+#define PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) \
+ PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3, 0x0, mmu_ctx)
+#define PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) \
+ PVR_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0, 0x1, mmu_ctx)
/*
* To configure the Page Catalog and BIF-DM fed into the BIF for Garten
* accesses through this segment.
*/
-#define ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(pc, bifdm) \
+#define PVR_FW_SEGMMU_OUTADDR_TOP_SLC(pc, bifdm) \
(((u64)((u64)(pc) & 0xFU) << 44U) | ((u64)((u64)(bifdm) & 0xFU) << 40U))
-#define ROGUE_FW_SEGMMU_META_BIFDM_ID (0x7U)
+#define PVR_FW_SEGMMU_META_BIFDM_ID (0x7U)
/* META segments have 4kB minimum size. */
-#define ROGUE_FW_SEGMMU_ALIGN (0x1000U)
+#define PVR_FW_SEGMMU_ALIGN (0x1000U)
/* Segmented MMU registers (n = segment id). */
#define META_CR_MMCU_SEGMENT_N_BASE(n) (0x04850000U + ((n) * 0x10U))
@@ -273,72 +273,73 @@ struct rogue_meta_ldr_cfg_blk {
* - SLC cached, META cached, FW base address 0x10000000
* - SLC cached, META uncached, FW base address 0x90000000
*/
-#define ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS (0x10000000U)
-#define ROGUE_FW_SEGMMU_DATA_META_CACHED (0x0U)
-#define ROGUE_FW_SEGMMU_DATA_META_UNCACHED (META_MEM_GLOBAL_RANGE_BIT)
-#define ROGUE_FW_SEGMMU_DATA_META_CACHE_MASK (META_MEM_GLOBAL_RANGE_BIT)
+#define PVR_FW_SEGMMU_DATA_BASE_ADDRESS (0x10000000U)
+#define PVR_FW_SEGMMU_DATA_META_CACHED (0x0U)
+#define PVR_FW_SEGMMU_DATA_META_UNCACHED (META_MEM_GLOBAL_RANGE_BIT)
+#define PVR_FW_SEGMMU_DATA_META_CACHE_MASK (META_MEM_GLOBAL_RANGE_BIT)
/*
* For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
* the PTEs for the FW data, not in the Meta Segment MMU, which means these
* defines have no real effect in those cases.
*/
-#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHED (0x0U)
-#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED (0x60000000U)
-#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK (0x60000000U)
+#define PVR_FW_SEGMMU_DATA_VIVT_SLC_CACHED (0x0U)
+#define PVR_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED (0x60000000U)
+#define PVR_FW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK (0x60000000U)
/*
******************************************************************************
- * ROGUE FW Bootloader defaults
+ * META Bootloader defaults
******************************************************************************
*/
-#define ROGUE_FW_BOOTLDR_META_ADDR (0x40000000U)
-#define ROGUE_FW_BOOTLDR_DEVV_ADDR_0 (0xC0000000U)
-#define ROGUE_FW_BOOTLDR_DEVV_ADDR_1 (0x000000E1)
-#define ROGUE_FW_BOOTLDR_DEVV_ADDR \
- ((((u64)ROGUE_FW_BOOTLDR_DEVV_ADDR_1) << 32) | \
- ROGUE_FW_BOOTLDR_DEVV_ADDR_0)
-#define ROGUE_FW_BOOTLDR_LIMIT (0x1FFFF000)
-#define ROGUE_FW_MAX_BOOTLDR_OFFSET (0x1000)
+#define PVR_FW_BOOTLDR_META_ADDR (0x40000000U)
+#define PVR_FW_BOOTLDR_DEVV_ADDR_0 (0xC0000000U)
+#define PVR_FW_BOOTLDR_DEVV_ADDR_1 (0x000000E1)
+#define PVR_FW_BOOTLDR_DEVV_ADDR \
+ ((((u64)PVR_FW_BOOTLDR_DEVV_ADDR_1) << 32) | \
+ PVR_FW_BOOTLDR_DEVV_ADDR_0)
+#define PVR_FW_BOOTLDR_LIMIT (0x1FFFF000)
+#define PVR_FW_MAX_BOOTLDR_OFFSET (0x1000)
/* Bootloader configuration offset is in dwords (512 bytes) */
-#define ROGUE_FW_BOOTLDR_CONF_OFFSET (0x80)
+#define PVR_FW_BOOTLDR_CONF_OFFSET (0x80)
/*
******************************************************************************
- * ROGUE META Stack
+ * META Stack
******************************************************************************
*/
-#define ROGUE_META_STACK_SIZE (0x1000U)
+#define PVR_META_STACK_SIZE (0x1000U)
/*
******************************************************************************
- * ROGUE META Core memory
+ * META Core memory
******************************************************************************
*/
/* Code and data both map to the same physical memory. */
-#define ROGUE_META_COREMEM_CODE_ADDR (0x80000000U)
-#define ROGUE_META_COREMEM_DATA_ADDR (0x82000000U)
-#define ROGUE_META_COREMEM_OFFSET_MASK (0x01ffffffU)
-
-#define ROGUE_META_IS_COREMEM_CODE(a, b) \
- ({ \
- u32 _a = (a), _b = (b); \
- ((_a) >= ROGUE_META_COREMEM_CODE_ADDR) && \
- ((_a) < (ROGUE_META_COREMEM_CODE_ADDR + (_b))); \
+#define PVR_META_COREMEM_CODE_ADDR (0x80000000U)
+#define PVR_META_COREMEM_DATA_ADDR (0x82000000U)
+#define PVR_META_COREMEM_OFFSET_MASK (0x01ffffffU)
+
+#define PVR_META_IS_COREMEM_CODE(a, b) \
+ ({ \
+ u32 _a = (a), _b = (b); \
+ ((_a) >= PVR_META_COREMEM_CODE_ADDR) && \
+ ((_a) < (PVR_META_COREMEM_CODE_ADDR + (_b))); \
})
-#define ROGUE_META_IS_COREMEM_DATA(a, b) \
- ({ \
- u32 _a = (a), _b = (b); \
- ((_a) >= ROGUE_META_COREMEM_DATA_ADDR) && \
- ((_a) < (ROGUE_META_COREMEM_DATA_ADDR + (_b))); \
+#define PVR_META_IS_COREMEM_DATA(a, b) \
+ ({ \
+ u32 _a = (a), _b = (b); \
+ ((_a) >= PVR_META_COREMEM_DATA_ADDR) && \
+ ((_a) < (PVR_META_COREMEM_DATA_ADDR + (_b))); \
})
+
/*
******************************************************************************
* 2nd thread
******************************************************************************
*/
-#define ROGUE_FW_THR1_PC (0x18930000)
-#define ROGUE_FW_THR1_SP (0x78890000)
+#define PVR_FW_THR1_PC (0x18930000)
+#define PVR_FW_THR1_SP (0x78890000)
/*
******************************************************************************
@@ -350,11 +351,11 @@ struct rogue_meta_ldr_cfg_blk {
#define META_CR_CORE_ID_VER_SHIFT (16U)
#define META_CR_CORE_ID_VER_CLRMSK (0XFF00FFFFU)
-#define ROGUE_CR_META_MTP218_CORE_ID_VALUE 0x19
-#define ROGUE_CR_META_MTP219_CORE_ID_VALUE 0x1E
-#define ROGUE_CR_META_LTP218_CORE_ID_VALUE 0x1C
-#define ROGUE_CR_META_LTP217_CORE_ID_VALUE 0x1F
+#define PVR_CR_META_MTP218_CORE_ID_VALUE 0x19
+#define PVR_CR_META_MTP219_CORE_ID_VALUE 0x1E
+#define PVR_CR_META_LTP218_CORE_ID_VALUE 0x1C
+#define PVR_CR_META_LTP217_CORE_ID_VALUE 0x1F
-#define ROGUE_FW_PROCESSOR_META "META"
+#define PVR_FW_PROCESSOR_META "META"
-#endif /* PVR_ROGUE_META_INTERNAL_H */
+#endif /* PVR_FW_META_INTERNAL_H */
--
2.43.0
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