All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v4 0/7] drm/i915/dp: Add support for the DP symbol based timing generator
@ 2026-11-03  9:58 Arun R Murthy
  2026-11-03  9:58 ` [PATCH v4 1/7] drm/i915/dp: Factor out the DSC slice count and link bpp lookup Arun R Murthy
                   ` (11 more replies)
  0 siblings, 12 replies; 16+ messages in thread
From: Arun R Murthy @ 2026-11-03  9:58 UTC (permalink / raw)
  To: intel-gfx, intel-xe
  Cc: Jani Nikula, chaitanya.kumar.borah, uma.shankar, suraj.kandpal,
	Arun R Murthy

Xe3p adds a DP link layer (LL) symbol based timing generator, as an
alternative to the pixel clock based one. It generates the transcoder
timings in LL symbol cycles instead of pixels, which makes the per-line
symbol insertion for 8b/10b MST and 128b/132b SST/MST compliant with
the DP 2.1 hblank symbol cycle count. This reduces the line-to-line
hblank jitter that some sinks can't handle, and the Min Hblank
mechanism can't be used together with it.

This series computes the LL symbol HACT/HTOTAL/CHUNK_SIZE and the 128
bit Data M/N for the symbol based timing generator, programs and enables
it, and drops the Link M/N ratio limit, which only applies to the pixel
based timing generator. If the symbol based timing generator can't be
used (MSO/eDP splitter, timings out of range, Data M/N above 1.0), the
pixel based one is kept.

Patch overview:
 - Patch 1 factors out the DSC slice count and link bpp lookup, to be
   shared with the Min Hblank computation.
 - Patch 2 adds the symbol based timing generator registers.
 - Patch 3 adds the symbol based timing generator state to the crtc
   state, with its state dump and state checker comparison.
 - Patch 4 adds HAS_DP_SYMBOL_TG().
 - Patch 5 computes the timing generator parameters.
 - Patch 6 programs and enables the timing generator, including the
   state readout.
 - Patch 7 lifts the Link M/N ratio limit when the symbol based timing
   generator is used.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: chaitanya.kumar.borah@intel.com
Cc: uma.shankar@intel.com
Cc: suraj.kandpal@intel.com
To: intel-gfx@lists.freedesktop.org
To: intel-xe@lists.freedesktop.org

Bspec: 68922
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
Changes in v4:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v3: https://lore.kernel.org/r/20261029-vlk-64036-dp-symbol-tg-v3-0-69022424ef17@intel.com

Changes in v3:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v2: https://lore.kernel.org/r/20261028-vlk-64036-dp-symbol-tg-v2-0-43849c325d32@intel.com

Changes in v2:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v1: https://lore.kernel.org/r/20261027-vlk-64036-dp-symbol-tg-v1-0-c46f4ebf67ed@intel.com

---
Arun R Murthy (7):
      drm/i915/dp: Factor out the DSC slice count and link bpp lookup
      drm/i915/display: Add the DP link layer symbol timing generator registers
      drm/i915/display: Add the DP symbol timing generator crtc state
      drm/i915/display: Add HAS_DP_SYMBOL_TG()
      drm/i915/dp: Compute the DP symbol based timing generator parameters
      drm/i915/display: Program and enable the DP symbol based timing generator
      drm/i915/dp: Don't limit the Link M/N ratio with the symbol timing generator

 .../gpu/drm/i915/display/intel_crtc_state_dump.c   |  11 +
 drivers/gpu/drm/i915/display/intel_ddi.c           |   2 +
 drivers/gpu/drm/i915/display/intel_display.c       | 112 +++++++++-
 drivers/gpu/drm/i915/display/intel_display.h       |   1 +
 .../gpu/drm/i915/display/intel_display_device.h    |   1 +
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  38 ++++
 drivers/gpu/drm/i915/display/intel_display_types.h |  13 ++
 drivers/gpu/drm/i915/display/intel_dp.c            | 239 +++++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h            |   3 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c        |  10 +-
 10 files changed, 405 insertions(+), 25 deletions(-)
---
base-commit: d56ff005f0d16ec136ee31fe3238eb447fefdc1a
change-id: 20261027-vlk-64036-dp-symbol-tg-d72c4222856e

Best regards,
-- 
Arun R Murthy <arun.r.murthy@intel.com>


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [PATCH v4 0/7] drm/i915/dp: Add support for the DP symbol based timing generator
@ 2026-11-04  3:24 Arun R Murthy
  2026-11-04  3:24 ` [PATCH v4 6/7] drm/i915/display: Program and enable " Arun R Murthy
  0 siblings, 1 reply; 16+ messages in thread
From: Arun R Murthy @ 2026-11-04  3:24 UTC (permalink / raw)
  To: intel-gfx, intel-xe
  Cc: Jani Nikula, chaitanya.kumar.borah, uma.shankar, suraj.kandpal,
	Arun R Murthy

Xe3p adds a DP link layer (LL) symbol based timing generator, as an
alternative to the pixel clock based one. It generates the transcoder
timings in LL symbol cycles instead of pixels, which makes the per-line
symbol insertion for 8b/10b MST and 128b/132b SST/MST compliant with
the DP 2.1 hblank symbol cycle count. This reduces the line-to-line
hblank jitter that some sinks can't handle, and the Min Hblank
mechanism can't be used together with it.

This series computes the LL symbol HACT/HTOTAL/CHUNK_SIZE and the 128
bit Data M/N for the symbol based timing generator, programs and enables
it, and drops the Link M/N ratio limit, which only applies to the pixel
based timing generator. If the symbol based timing generator can't be
used (MSO/eDP splitter, timings out of range, Data M/N above 1.0), the
pixel based one is kept.

Patch overview:
 - Patch 1 factors out the DSC slice count and link bpp lookup, to be
   shared with the Min Hblank computation.
 - Patch 2 adds the symbol based timing generator registers.
 - Patch 3 adds the symbol based timing generator state to the crtc
   state, with its state dump and state checker comparison.
 - Patch 4 adds HAS_DP_SYMBOL_TG().
 - Patch 5 computes the timing generator parameters.
 - Patch 6 programs and enables the timing generator, including the
   state readout.
 - Patch 7 lifts the Link M/N ratio limit when the symbol based timing
   generator is used.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: chaitanya.kumar.borah@intel.com
Cc: uma.shankar@intel.com
Cc: suraj.kandpal@intel.com
To: intel-gfx@lists.freedesktop.org
To: intel-xe@lists.freedesktop.org

Bspec: 68922
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
Changes in v4:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v3: https://lore.kernel.org/r/20261029-vlk-64036-dp-symbol-tg-v3-0-69022424ef17@intel.com

Changes in v3:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v2: https://lore.kernel.org/r/20261028-vlk-64036-dp-symbol-tg-v2-0-43849c325d32@intel.com

Changes in v2:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v1: https://lore.kernel.org/r/20261027-vlk-64036-dp-symbol-tg-v1-0-c46f4ebf67ed@intel.com

---
Arun R Murthy (7):
      drm/i915/dp: Factor out the DSC slice count and link bpp lookup
      drm/i915/display: Add the DP link layer symbol timing generator registers
      drm/i915/display: Add the DP symbol timing generator crtc state
      drm/i915/display: Add HAS_DP_SYMBOL_TG()
      drm/i915/dp: Compute the DP symbol based timing generator parameters
      drm/i915/display: Program and enable the DP symbol based timing generator
      drm/i915/dp: Don't limit the Link M/N ratio with the symbol timing generator

 .../gpu/drm/i915/display/intel_crtc_state_dump.c   |  11 +
 drivers/gpu/drm/i915/display/intel_ddi.c           |   2 +
 drivers/gpu/drm/i915/display/intel_display.c       | 114 +++++++++-
 drivers/gpu/drm/i915/display/intel_display.h       |   1 +
 .../gpu/drm/i915/display/intel_display_device.h    |   1 +
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  38 ++++
 drivers/gpu/drm/i915/display/intel_display_types.h |  13 ++
 drivers/gpu/drm/i915/display/intel_dp.c            | 240 +++++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h            |   3 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c        |  10 +-
 10 files changed, 408 insertions(+), 25 deletions(-)
---
base-commit: d56ff005f0d16ec136ee31fe3238eb447fefdc1a
change-id: 20261027-vlk-64036-dp-symbol-tg-d72c4222856e

Best regards,
-- 
Arun R Murthy <arun.r.murthy@intel.com>


^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2026-11-04  3:30 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-11-03  9:58 [PATCH v4 0/7] drm/i915/dp: Add support for the DP symbol based timing generator Arun R Murthy
2026-11-03  9:58 ` [PATCH v4 1/7] drm/i915/dp: Factor out the DSC slice count and link bpp lookup Arun R Murthy
2026-11-03  9:58 ` [PATCH v4 2/7] drm/i915/display: Add the DP link layer symbol timing generator registers Arun R Murthy
2026-11-03  9:58 ` [PATCH v4 3/7] drm/i915/display: Add the DP symbol timing generator crtc state Arun R Murthy
2026-11-03  9:58 ` [PATCH v4 4/7] drm/i915/display: Add HAS_DP_SYMBOL_TG() Arun R Murthy
2026-11-03  9:58 ` [PATCH v4 5/7] drm/i915/dp: Compute the DP symbol based timing generator parameters Arun R Murthy
2026-11-03  9:58 ` [PATCH v4 6/7] drm/i915/display: Program and enable the DP symbol based timing generator Arun R Murthy
2026-11-03 10:23   ` sashiko-bot
2026-11-03  9:58 ` [PATCH v4 7/7] drm/i915/dp: Don't limit the Link M/N ratio with the symbol " Arun R Murthy
2026-11-04  1:30   ` Kandpal, Suraj
2026-11-03 10:13 ` ✓ CI.KUnit: success for drm/i915/dp: Add support for the DP symbol based timing generator (rev3) Patchwork
2026-11-03 10:49 ` ✓ Xe.CI.BAT: " Patchwork
2026-11-03 11:21 ` ✓ i915.CI.BAT: " Patchwork
2026-11-03 14:30 ` ✗ i915.CI.Full: failure " Patchwork
2026-11-03 19:18 ` ✗ Xe.CI.FULL: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2026-11-04  3:24 [PATCH v4 0/7] drm/i915/dp: Add support for the DP symbol based timing generator Arun R Murthy
2026-11-04  3:24 ` [PATCH v4 6/7] drm/i915/display: Program and enable " Arun R Murthy

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.