Re: [PATCH v2] clk: meson: s4: keep the PWM clocks off vid_pll

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] clk: meson: s4: unused S4_COMP_SEL macro left behind by
  S4_PWM_SEL
--

commit 5666c90897d1a4bb5320168099b837ca1ef8216b
Author: Christian Stefan Kövér-Draxl <ckoever@outlook.de>

clk: meson: s4: keep the PWM clocks off vid_pll

This commit removes vid_pll from the S4 PWM clock parent list and adds a
mux table to preserve the hardware register indices for the remaining
inputs.

> diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c
> index ba41fcd905881..e5e5ff979efd2 100644
> --- a/drivers/clk/meson/s4-peripherals.c
> +++ b/drivers/clk/meson/s4-peripherals.c
> @@ -2588,51 +2588,61 @@ static struct clk_regmap s4_spicc0_en = {
>  	},
>  };
>  
> -/* PWM Clock */
> +/*
> + * PWM Clock
> + *
> + * vid_pll (mux input 1) is left out: it belongs to the video path and is
> + * reprogrammed on display mode changes.
> + */
> +static u32 s4_pwm_parents_table[] = { 0, 2, 3 };
> +
>  static const struct clk_parent_data s4_pwm_parents[] = {
>  	{ .fw_name = "xtal", },
> -	{ .hw = &s4_vid_pll.hw },
>  	{ .fw_name = "fclk_div4", },
>  	{ .fw_name = "fclk_div3", },
>  };
>  
> -static S4_COMP_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9, 0x3, s4_pwm_parents);
> +#define S4_PWM_SEL(_name, _reg, _shift) \
> +	MESON_COMP_SEL(s4_, _name, _reg, _shift, 0x3, s4_pwm_parents, \
> +		       s4_pwm_parents_table, 0, 0)
> +
> +static S4_PWM_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9);

[Severity: Low]
Does replacing all S4_COMP_SEL() uses with S4_PWM_SEL() leave
S4_COMP_SEL() unused in drivers/clk/meson/s4-peripherals.c, triggering a
-Wunused-macros warning under W=2 builds? Either S4_COMP_SEL() could take
a table argument or the unused macro definition should be removed.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261106101827.46467-1-christian.koever-draxl@student.uibk.ac.at?part=1

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