From: sashiko-bot@kernel.org
To: "Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH 3/5] dt-bindings: mips: mti,mips-cm: add performance counter interrupt
Date: Sun, 08 Nov 2026 13:22:56 +0000 [thread overview]
Message-ID: <sashiko-outbox-203775@kernel.org> (raw)
In-Reply-To: <20261108-i6500-cm3-pmu-v1-3-bd119584891a@mobileye.com>
> The CM3 asserts so_cm_perf_cnt_int when one of its performance counters
> overflows. Whether that output is connected to an interrupt controller
> input is up to the SoC integrator, so describe it as an optional
> 'interrupts' property of the coherency-manager node. When absent, the
> counters have to be polled by software.
>
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-i6500-cm3-pmu-v1-0-bd119584891a@mobileye.com?part=3
next prev parent reply other threads:[~2026-11-08 13:22 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-08 13:20 [PATCH 0/5] perf: add PMU driver for the MIPS Coherence Manager 3 performance counters Vladimir Kondratiev
2026-11-08 13:20 ` [PATCH 1/5] MIPS: CM: add CM3 performance counter GCR definitions Vladimir Kondratiev
2026-11-08 13:24 ` sashiko-bot
2026-11-08 13:20 ` [PATCH 2/5] MIPS: CM: export the symbols needed to access the GCRs from a module Vladimir Kondratiev
2026-11-08 13:28 ` sashiko-bot
2026-11-08 13:20 ` [PATCH 3/5] dt-bindings: mips: mti,mips-cm: add performance counter interrupt Vladimir Kondratiev
2026-11-08 13:22 ` sashiko-bot [this message]
2026-11-08 13:20 ` [PATCH 4/5] perf: add MIPS Coherence Manager 3 (CM3) PMU driver Vladimir Kondratiev
2026-11-08 13:45 ` sashiko-bot
2026-11-08 13:20 ` [PATCH 5/5] MIPS: eyeq6_defconfig: enable the CM3 PMU Vladimir Kondratiev
2026-11-08 13:24 ` sashiko-bot
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