Re: [PATCH 1/5] MIPS: CM: add CM3 performance counter GCR definitions

[sashiko-bot@kernel.org]

> The CM3 implements two programmable 32-bit performance counters and a
> 32-bit cycle counter, controlled through registers in the GCR global
> debug block (GCR_DB_PC_*, offset 0x6100..0x61a8 from GCR_BASE).
> 
> Add GCR_DB_ACCESSOR_{RO,RW} helpers for the debug block and define the
> control, overflow status, event select, cycle counter, qualifier and
> counter registers along with their fields, as described in the I6500
> register reference (MD01189).
> 
> Each accessor comes in two flavours, as the CPC ones do: db_<reg> for
> the local cluster and redir_db_<reg> for the debug block of another
> cluster through the redirect block. GCR_Cx_OTHER.BLOCK value 2 selects
> the debug block in the GCR, where the existing _BLOCK_USER name only
> describes its GIC meaning; add CM_GCR_Cx_OTHER_BLOCK_DEBUG for it.
> 
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>

Sashiko has reviewed this patch and found no issues.

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Sashiko AI review · https://sashiko.dev/#/patchset/20261108-i6500-cm3-pmu-v1-0-bd119584891a@mobileye.com?part=1