Re: [PATCH v8 07/29] drm/msm/dp: add support for MST channel slot allocation

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] drm/msm/dp: unused DP_MAX_TIME_SLOTS macro in
  msm_dp_ctrl_mst_calculate_rg()
--

commit 0628c2c6f6b7a217c52d585875dabea16424021f
Author: Abhinav Kumar <quic_abhinavk@quicinc.com>

drm/msm/dp: add support for MST channel slot allocation

This commit adds DP controller support for programming per-stream MST
timeslot allocations and calculating the rate governor parameters.

> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index 8a2396aec6d5e..0b34db3bd5d22 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -83,6 +83,7 @@
>  #define MR_LINK_PRBS7 0x100
>  #define MR_LINK_CUSTOM80 0x200
>  #define MR_LINK_TRAINING4  0x40
> +#define DP_MAX_TIME_SLOTS 64

[ ... ]

> +static void msm_dp_ctrl_mst_calculate_rg(struct msm_dp_ctrl_private *ctrl,
> +					 struct msm_dp_panel *panel,
> +					 const struct msm_dp_mst_slot_info *slots,
> +					 u32 *p_x_int, u32 *p_y_frac_enum)
> +{
> +	u64 min_slot_cnt, max_slot_cnt;
> +	u64 raw_target_sc, target_sc_fixp, scale_fixp;
> +	u64 pclk = panel->msm_dp_mode.drm_mode.clock;
> +	u64 lclk = 0;
> +	u64 lanes = ctrl->link->link_params.num_lanes;
> +	u64 bpp = panel->msm_dp_mode.bpp;
> +	u64 pbn = slots[panel->stream_id].pbn;
> +	u64 numerator, denominator, temp, temp1, scaled_target_sc;
> +	u32 x_int = 0, y_frac_enum = 0;
> +	u64 target_strm_sym, y_frac_enum_fixp;
> +
> +	lclk = ctrl->link->link_params.rate;
> +
> +	/* min_slot_cnt */
> +	numerator = pclk * bpp * 64 * 1000;

[Severity: Low]
This isn't a bug, but DP_MAX_TIME_SLOTS is defined above and never used;
should this calculation use DP_MAX_TIME_SLOTS instead of 64?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261110-msm-dp-mst-v8-0-d040fb33db5f@oss.qualcomm.com?part=7