Re: [PATCH 2/3] arm64: dts: airoha: add AN7589 SoC dtsi

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Low] arm64: dts: airoha: GICV reg size in an7589.dtsi is 0x1000
  instead of 0x2000
- [Low] arm64: dts: airoha: an7589.dtsi violates DTS node and property
  ordering style
--

commit a54801b37e2982019e19eb5576150babcfa339e8
Author: John Crispin <john@phrozen.org>

arm64: dts: airoha: add AN7589 SoC dtsi

This commit adds the initial device tree include for the Airoha AN7589 SoC,
describing the Cortex-A73 cores, PSCI, GICv3, architected timer, and
console UART.

> diff --git a/arch/arm64/boot/dts/airoha/an7589.dtsi b/arch/arm64/boot/dts/airoha/an7589.dtsi
> new file mode 100644
> index 0000000000000..c0153a00c88ae
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/an7589.dtsi
> @@ -0,0 +1,134 @@
[ ... ]
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		atf@80000000 {
> +			no-map;
> +			reg = <0x0 0x80000000 0x0 0x200000>;
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};

[Severity: Low]
This isn't a bug, but scripts/dtc/dt-check-style --mode=strict reports
several DTS coding style warnings in this file:

- The unaddressed child nodes under / (reserved-memory, psci, cpus,
  clock-1843200, timer, soc) are not ordered alpha-numerically by node
  name.
- reg comes after no-map in atf@80000000.
- ranges comes after #address-cells and #size-cells in soc.
- reg comes after interrupt-controller and #interrupt-cells in
  interrupt-controller@c000000.

[ ... ]

> +		gic: interrupt-controller@c000000 {
> +			compatible = "arm,gic-v3";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			reg = <0x0 0x0c000000 0x0 0x40000>,
> +			      <0x0 0x0c080000 0x0 0x200000>,
> +			      <0x0 0x0c400000 0x0 0x2000>,
> +			      <0x0 0x0c410000 0x0 0x1000>,
> +			      <0x0 0x0c420000 0x0 0x1000>;

[Severity: Low]
Should the fifth reg entry (GICV at 0x0c420000) have a size of 0x2000
instead of 0x1000?

Like GICC at 0x0c400000, the GICv2-compatible virtual CPU interface spans
8 KiB (matching KVM_VGIC_V2_CPU_SIZE), with GICV_DIR at offset 0x1000 in
the second 4 KiB page.  Using 0x1000 causes gic_of_setup_kvm_info() to
record a truncated gic_v3_kvm_info.vcpu resource that omits the second
page.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261110172143.296304-1-john@phrozen.org?part=2