[PATCH 0/3] arm64: dts: airoha: add AN7589 support

[PATCH 0/3] arm64: dts: airoha: add AN7589 support

[John Crispin]

The Airoha AN7589 is a quad Cortex-A73 SoC. This series adds its board
compatibles, a base SoC dtsi with the CPUs, PSCI, the GICv3, the
architected timer and the console UART, and the device tree of the
evaluation board with 2 GiB of DRAM.

The remaining blocks follow with the series of their drivers.

The series applies to next-20261105 and has no dependencies.

John Crispin (3):
  dt-bindings: arm: airoha: add AN7589
  arm64: dts: airoha: add AN7589 SoC dtsi
  arm64: dts: airoha: add AN7589 evaluation board

 .../devicetree/bindings/arm/airoha.yaml       |   4 +
 arch/arm64/boot/dts/airoha/Makefile           |   1 +
 arch/arm64/boot/dts/airoha/an7589-evb.dts     |  22 +++
 arch/arm64/boot/dts/airoha/an7589.dtsi        | 134 ++++++++++++++++++
 4 files changed, 161 insertions(+)
 create mode 100644 arch/arm64/boot/dts/airoha/an7589-evb.dts
 create mode 100644 arch/arm64/boot/dts/airoha/an7589.dtsi


base-commit: ddfe51b0a0f5dc9e415cc2c8ad8db17532dd426b
-- 
2.34.1

[PATCH 1/3] dt-bindings: arm: airoha: add AN7589

[John Crispin]

The AN7589 is the next generation Airoha SoC. Document the SoC compatible
and the compatible for the Airoha evaluation board.

Signed-off-by: John Crispin <john@phrozen.org>
---
 Documentation/devicetree/bindings/arm/airoha.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml
index 7c38c08dbf3f..bf432d256882 100644
--- a/Documentation/devicetree/bindings/arm/airoha.yaml
+++ b/Documentation/devicetree/bindings/arm/airoha.yaml
@@ -26,6 +26,10 @@ properties:
           - enum:
               - airoha,en7581-evb
           - const: airoha,en7581
+      - items:
+          - enum:
+              - airoha,an7589-evb
+          - const: airoha,an7589
 
 additionalProperties: true
 
-- 
2.34.1

[PATCH 2/3] arm64: dts: airoha: add AN7589 SoC dtsi

[John Crispin]

Add the device tree for the Airoha AN7589 SoC. It describes the four
Cortex-A73 cores, which the firmware brings up over PSCI, the GICv3, the
architected timer and the console UART.

The UART runs from a fixed 1.8432 MHz clock, so the console works
before the SCU clock controller probes. The remaining blocks follow later.

Signed-off-by: John Crispin <john@phrozen.org>
---
 arch/arm64/boot/dts/airoha/an7589.dtsi | 134 +++++++++++++++++++++++++
 1 file changed, 134 insertions(+)
 create mode 100644 arch/arm64/boot/dts/airoha/an7589.dtsi

diff --git a/arch/arm64/boot/dts/airoha/an7589.dtsi b/arch/arm64/boot/dts/airoha/an7589.dtsi
new file mode 100644
index 000000000000..c0153a00c88a
--- /dev/null
+++ b/arch/arm64/boot/dts/airoha/an7589.dtsi
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		atf@80000000 {
+			no-map;
+			reg = <0x0 0x80000000 0x0 0x200000>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x1>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x2>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x3>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <64>;
+			cache-level = <2>;
+			cache-unified;
+		};
+	};
+
+	clk1843200: clock-1843200 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1843200>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@c000000 {
+			compatible = "arm,gic-v3";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x0 0x0c000000 0x0 0x40000>,
+			      <0x0 0x0c080000 0x0 0x200000>,
+			      <0x0 0x0c400000 0x0 0x2000>,
+			      <0x0 0x0c410000 0x0 0x1000>,
+			      <0x0 0x0c420000 0x0 0x1000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+
+		uart1: serial@1fbf0000 {
+			compatible = "ns16550";
+			reg = <0x0 0x1fbf0000 0x0 0x30>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk1843200>;
+		};
+	};
+};
-- 
2.34.1

[PATCH 3/3] arm64: dts: airoha: add AN7589 evaluation board

[John Crispin]

Add the device tree for the Airoha AN7589 evaluation board, with 2 GiB
of DRAM and the console on UART1.

Signed-off-by: John Crispin <john@phrozen.org>
---
 arch/arm64/boot/dts/airoha/Makefile       |  1 +
 arch/arm64/boot/dts/airoha/an7589-evb.dts | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)
 create mode 100644 arch/arm64/boot/dts/airoha/an7589-evb.dts

diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile
index ebea112ce1d7..78146871db77 100644
--- a/arch/arm64/boot/dts/airoha/Makefile
+++ b/arch/arm64/boot/dts/airoha/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
+dtb-$(CONFIG_ARCH_AIROHA) += an7589-evb.dtb
 dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
diff --git a/arch/arm64/boot/dts/airoha/an7589-evb.dts b/arch/arm64/boot/dts/airoha/an7589-evb.dts
new file mode 100644
index 000000000000..eadba7154350
--- /dev/null
+++ b/arch/arm64/boot/dts/airoha/an7589-evb.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+#include "an7589.dtsi"
+
+/ {
+	model = "Airoha AN7589 Evaluation Board";
+	compatible = "airoha,an7589-evb", "airoha,an7589";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+};
-- 
2.34.1

Re: [PATCH 2/3] arm64: dts: airoha: add AN7589 SoC dtsi

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Low] arm64: dts: airoha: GICV reg size in an7589.dtsi is 0x1000
  instead of 0x2000
- [Low] arm64: dts: airoha: an7589.dtsi violates DTS node and property
  ordering style
--

commit a54801b37e2982019e19eb5576150babcfa339e8
Author: John Crispin <john@phrozen.org>

arm64: dts: airoha: add AN7589 SoC dtsi

This commit adds the initial device tree include for the Airoha AN7589 SoC,
describing the Cortex-A73 cores, PSCI, GICv3, architected timer, and
console UART.

> diff --git a/arch/arm64/boot/dts/airoha/an7589.dtsi b/arch/arm64/boot/dts/airoha/an7589.dtsi
> new file mode 100644
> index 0000000000000..c0153a00c88ae
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/an7589.dtsi
> @@ -0,0 +1,134 @@
[ ... ]
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		atf@80000000 {
> +			no-map;
> +			reg = <0x0 0x80000000 0x0 0x200000>;
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};

[Severity: Low]
This isn't a bug, but scripts/dtc/dt-check-style --mode=strict reports
several DTS coding style warnings in this file:

- The unaddressed child nodes under / (reserved-memory, psci, cpus,
  clock-1843200, timer, soc) are not ordered alpha-numerically by node
  name.
- reg comes after no-map in atf@80000000.
- ranges comes after #address-cells and #size-cells in soc.
- reg comes after interrupt-controller and #interrupt-cells in
  interrupt-controller@c000000.

[ ... ]

> +		gic: interrupt-controller@c000000 {
> +			compatible = "arm,gic-v3";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			reg = <0x0 0x0c000000 0x0 0x40000>,
> +			      <0x0 0x0c080000 0x0 0x200000>,
> +			      <0x0 0x0c400000 0x0 0x2000>,
> +			      <0x0 0x0c410000 0x0 0x1000>,
> +			      <0x0 0x0c420000 0x0 0x1000>;

[Severity: Low]
Should the fifth reg entry (GICV at 0x0c420000) have a size of 0x2000
instead of 0x1000?

Like GICC at 0x0c400000, the GICv2-compatible virtual CPU interface spans
8 KiB (matching KVM_VGIC_V2_CPU_SIZE), with GICV_DIR at offset 0x1000 in
the second 4 KiB page.  Using 0x1000 causes gic_of_setup_kvm_info() to
record a truncated gic_v3_kvm_info.vcpu resource that omits the second
page.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261110172143.296304-1-john@phrozen.org?part=2

Re: [PATCH 1/3] dt-bindings: arm: airoha: add AN7589

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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