* [PATCH] drm/msm/adreno: Improve AHB error messages
@ 2026-11-11 17:14 Rob Clark
2026-11-11 18:26 ` sashiko-bot
0 siblings, 1 reply; 2+ messages in thread
From: Rob Clark @ 2026-11-11 17:14 UTC (permalink / raw)
To: dri-devel
Cc: linux-arm-msm, freedreno, Rob Clark, Sean Paul, Konrad Dybcio,
Akhil P Oommen, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Marijn Suijten, David Airlie, Simona Vetter, open list
On a7xx/a8xx we can get some details out of the CP_RL_ERROR_DETAILS
registers.
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 20 +++++++++++++++++--
drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 10 ++++++++--
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 11 +++++++++-
3 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index a93e9c960d88..484a78dbc804 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1957,8 +1957,24 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
a6xx_fault_detect_irq(gpu);
- if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
- dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
+ if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) {
+ if (adreno_is_a7xx(to_adreno_gpu(gpu))) {
+ u32 rl0, rl1, addr;
+ const char *mode;
+
+ rl0 = gpu_read(gpu, REG_A7XX_CP_RL_ERROR_DETAILS_0);
+ rl1 = gpu_read(gpu, REG_A7XX_CP_RL_ERROR_DETAILS_1);
+
+ addr = FIELD(rl0, A7XX_CP_RL_ERROR_DETAILS_0_ADDR);
+ mode = (rl0 & A7XX_CP_RL_ERROR_DETAILS_0_WRITE) ? "write" : "read";
+
+ dev_err_ratelimited(&gpu->pdev->dev,
+ "CP | AHB bus error RL_ERROR_0: %x (addr: 0x%05x, %s), RL_ERROR_1: %x\n",
+ rl0, addr, mode, rl1);
+ } else {
+ dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
+ }
+ }
if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
a6xx_cp_hw_err_irq(gpu);
diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index f6afa5b3b0bb..bbf5ca4fb6fc 100644
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -1248,12 +1248,18 @@ irqreturn_t a8xx_irq(struct msm_gpu *gpu)
a8xx_fault_detect_irq(gpu);
if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) {
- u32 rl0, rl1;
+ u32 rl0, rl1, addr;
+ const char *mode;
rl0 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_0);
rl1 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_1);
+
+ addr = FIELD(rl0, A8XX_CP_RL_ERROR_DETAILS_0_ADDR);
+ mode = (rl0 & A8XX_CP_RL_ERROR_DETAILS_0_WRITE) ? "write" : "read";
+
dev_err_ratelimited(&gpu->pdev->dev,
- "CP | AHB bus error RL_ERROR_0: %x, RL_ERROR_1: %x\n", rl0, rl1);
+ "CP | AHB bus error RL_ERROR_0: %x (addr: 0x%05x, %s), RL_ERROR_1: %x\n",
+ rl0, addr, mode, rl1);
}
if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
index b1e7dd26e98a..8d33d9285007 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
@@ -193,7 +193,16 @@ by a particular renderpass/blit.
<reg32 offset="0x0" name="REG"/>
</array>
- <reg32 offset="0x0840" name="CP_RL_ERROR_DETAILS_0" variants="A8XX-"/>
+ <reg32 offset="0x09b4" name="CP_RL_ERROR_DETAILS_0" variants="A7XX">
+ <bitfield name="ADDR" low="0" high="19"/>
+ <bitfield name="WRITE" pos="28" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x09cf" name="CP_RL_ERROR_DETAILS_1" variants="A7XX"/>
+
+ <reg32 offset="0x0840" name="CP_RL_ERROR_DETAILS_0" variants="A8XX-">
+ <bitfield name="ADDR" low="0" high="19"/>
+ <bitfield name="WRITE" pos="28" type="boolean"/>
+ </reg32>
<reg32 offset="0x0841" name="CP_RL_ERROR_DETAILS_1" variants="A8XX-"/>
<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE" variants="A6XX-A7XX"/>
--
2.56.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/msm/adreno: Improve AHB error messages
2026-11-11 17:14 [PATCH] drm/msm/adreno: Improve AHB error messages Rob Clark
@ 2026-11-11 18:26 ` sashiko-bot
0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-11-11 18:26 UTC (permalink / raw)
To: Rob Clark, dri-devel
Thank you for your contribution! Sashiko AI review found no new issues
in this patch, but noticed 1 related pre-existing issue it does not
introduce:
- [Medium] drm/msm/a8xx: status clobbering in a8xx_cp_hw_err_irq() [1]
--
commit 036d732e4c5bd970decdf064cde4d6ff621ef0a9
Author: Rob Clark <robin.clark@oss.qualcomm.com>
drm/msm/adreno: Improve AHB error messages
This commit adds A7XX register definitions and decodes CP_RL_ERROR_DETAILS
registers on A7XX and A8XX GPUs to log detailed AHB bus error messages.
> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> index f892731cd3d3a..f2dcf62be861e 100644
> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> @@ -1232,12 +1232,18 @@ irqreturn_t a8xx_irq(struct msm_gpu *gpu)
> a8xx_fault_detect_irq(gpu);
>
> if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) {
> - u32 rl0, rl1;
> + u32 rl0, rl1, addr;
> + const char *mode;
>
> rl0 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_0);
> rl1 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_1);
> +
> + addr = FIELD(rl0, A8XX_CP_RL_ERROR_DETAILS_0_ADDR);
> + mode = (rl0 & A8XX_CP_RL_ERROR_DETAILS_0_WRITE) ? "write" : "read";
> +
> dev_err_ratelimited(&gpu->pdev->dev,
> - "CP | AHB bus error RL_ERROR_0: %x, RL_ERROR_1: %x\n", rl0, rl1);
> + "CP | AHB bus error RL_ERROR_0: %x (addr: 0x%05x, %s), RL_ERROR_1: %x\n",
> + rl0, addr, mode, rl1);
> }
>
> if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
[Severity: Medium]
This problem wasn't introduced by this patch, but does a8xx_cp_hw_err_irq()
clobber status while iterating over pipes [1]?
drivers/gpu/drm/msm/adreno/a8xx_gpu.c:a8xx_cp_hw_err_irq() {
u32 status = gpu_read(gpu, REG_A8XX_CP_INTERRUPT_STATUS_GLOBAL);
...
for (unsigned int pipe_id = PIPE_NONE; pipe_id <= PIPE_DDE_BV; pipe_id++) {
if (!(BIT(pipe_id) & pipe))
continue;
if (hw_fault_mask & status) {
status = a8xx_read_pipe_slice(gpu, pipe_id, slice,
REG_A8XX_CP_HW_FAULT_STATUS_PIPE);
...
}
if (sw_fault_mask & status) {
status = a8xx_read_pipe_slice(gpu, pipe_id, slice,
REG_A8XX_CP_INTERRUPT_STATUS_PIPE);
...
if (status & BIT(8)) {
a8xx_write_pipe(gpu, pipe_id, REG_A8XX_CP_SQE_STAT_ADDR_PIPE, 1);
status = a8xx_read_pipe_slice(gpu, pipe_id, slice,
REG_A8XX_CP_SQE_STAT_DATA_PIPE);
...
}
if (status & BIT(10)) {
status = a8xx_read_pipe_slice(gpu, pipe_id, slice,
REG_A8XX_CP_PROTECT_STATUS_PIPE);
...
}
}
}
}
Overwriting status with per-pipe fault and opcode register values causes the
subsequent sw_fault_mask check, the BIT(10) register protection check, and
later pipe iterations to test unrelated values instead of the interrupt
status registers, resulting in missed or bogus fault diagnostics.
[1] https://sashiko.dev/#/bug/linux-69f62dbe-1123-4e6d-8506-4fc99ce6cd9b
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261111171417.249152-1-robin.clark@oss.qualcomm.com?part=1
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2026-11-11 18:26 ` sashiko-bot
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