[PATCH v7 0/6] riscv: optimize mode switch latency for Vector

* [PATCH v7 0/6] riscv: optimize mode switch latency for Vector
@ 2026-11-11 18:43 ` Andy Chiu
  0 siblings, 0 replies; 20+ messages in thread
From: Andy Chiu @ 2026-11-11 18:43 UTC (permalink / raw)
  To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
	linux-riscv
  Cc: andybnac, Andy Chiu, dfustini, greentime.hu, linux-kernel, olof

This series provide several optimizations targeting system call latency
regarding vector context management. Before the series, the kernel
handled user's vector context in an conservative way, where registers
were null out and VS is tracked as DIRTY. This introduce excess context
saving and restoring when there is a context swicth.  Also, the kernel
turned off Vector at the exception entry, making all in-kernel vector
usecase take the serialization cost, which includes context switch and
user copies. The cost is not easy to hide as vector code are usually sit
right after enabling V.

Since vector register are set to a known state at syscall exit, the
series set VS to INIT at syscall entry and null out the vector register
at the exit, skipping unnecessary saves and restores. The series also
introduce riscv_novstateopt, when unset, enables vector in the kernel
mode, and do not perform register nulling on the syscall fast path,
where there is no context switch or kernel-mode vector during the
syscall.

With the whole series, nginx request throughput vs base on a four-core
Ascalon-S, by served page size (* = statistically distinct):

       86B     1KB     2KB     4KB     8KB     16KB    32KB
  v5   +0.79%* +1.36%* +2.33%* +2.02%* +0.14%  +0.93%  +2.42%*
  v6   +0.33%* -0.23%  +2.88%* +2.19%* +1.02%  +1.14%  +1.40%*

This series depends on [1], which is now queued in the
linux-riscv/fixes. For those who prefer git, the series is also available
at [3].

Patch summary:
 - New patches: 2, 6
 - Modified patches: 3
 - Unchanged patches: 1, 4, 5

Changelog v7:
 - Resend the series based on unmerged patches from v6
 - Rearange patches so that it does not introduce bug mid-series (2,3)
 - Add a KVM patch that skips duplicate context operations on host vector
   context (6)

Changelog v6:
 - Refactor the context switch of preemptible kernel-mode vector (2)
 - Address checkpatch warnings by reformatting patch 7
 - Drive the optimization with an alternative instead of
   CONFIG_RISCV_VSTATE_OPT, enable it by default (8)
 - Link to v5: https://lore.kernel.org/all/20260810172255.1532787-1-tchiu@tenstorrent.com/

Changelog v5:
 - Rebase on top of the kvm fix
 - Do not read sstatus in vector context swicth (1)
 - Add a test for vectorized user copy (2)
 - Enable vector in the kernel-mode and skip nulling at syscall fast
   path, gurad the optimization in a new config (7)
 - Link to v4: https://patchwork.kernel.org/project/linux-riscv/cover/20260528190927.886558-1-tchiu@tenstorrent.com/

Changelog v4:
 - Fix a build warning (1)
 - Prevent setting INIT when it is already and provide performance
   meassurements (2)
 - Address comments from sashiko (4)
 - Link to v3: https://lore.kernel.org/all/20260521162521.188629-1-tchiu@tenstorrent.com/

Changelog v3:
 - Refactor function names. (1, 2)
 - Merge daichengrong's patch, with a fix and optimzation. (2)
 - Fix ptrace GETREGSET failure. (3)
 - Strengthen ptrace SETREGSET semantics and add a test to cover it. (3,
   4)
 - Fix a potential ABI break in signal and add a test to prevent future
   breaks. (3, 4)
 - Link to v2: https://lore.kernel.org/linux-riscv/20260402043414.2421916-1-andybnac@gmail.com/

Changelog v2: rebase on top of for-next

[1] https://patch.msgid.link/20261020-vector_fpu_regs_status_rmw_fix-v2-1-474a59155e96@intel.com
[3] https://github.com/tchiu-TT/linux/commits/vctxopt/v7/

Andy Chiu (5):
  riscv: vector: refactor vector context operations
  riscv: introduce riscv_v_ucontext_save() for signal and ptrace
  selftests: riscv: Extend vector tests for sigreturn and ptrace
  riscv: vector: optimize vstate operations
  riscv: KVM: do not save host vector context for vcpu

daichengrong (1):
  riscv: clarify vector state semantics on syscall and context switch

 .../admin-guide/kernel-parameters.txt         |  13 ++
 arch/riscv/include/asm/alternative-macros.h   |   6 +
 arch/riscv/include/asm/alternative.h          |   3 -
 arch/riscv/include/asm/cpufeature-macros.h    |   6 +-
 arch/riscv/include/asm/kvm_vcpu_vector.h      |  17 ++-
 arch/riscv/include/asm/vector.h               |  68 +++++++----
 arch/riscv/kernel/cpufeature.c                |  18 +++
 arch/riscv/kernel/entry.S                     |  15 ++-
 arch/riscv/kernel/kernel_mode_vector.c        |   4 +
 arch/riscv/kernel/process.c                   |   3 +
 arch/riscv/kernel/ptrace.c                    |  13 +-
 arch/riscv/kernel/signal.c                    |  11 +-
 arch/riscv/kernel/vector.c                    |  56 ++++++++-
 arch/riscv/kvm/vcpu.c                         |   5 +-
 arch/riscv/kvm/vcpu_vector.c                  |  22 +---
 .../selftests/riscv/sigreturn/sigreturn.c     |  71 +++++++++++
 .../selftests/riscv/vector/vstate_ptrace.c    | 111 +++++++++++++++++-
 17 files changed, 364 insertions(+), 78 deletions(-)

base-commit: d1a8d411533d6be16ac79796c02a9bfc7d7958f1
-- 
2.43.0

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