* [PATCH 00/19] drm/amd/display: refactor DC interfaces to abstract it better.
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
I recently was looking into refactoring some things and noticed
that "struct dc" leaks outside of dc a lot, and this is a large
messy struct and if say someone wanted to use bindgen anywhere
near this code it would be a nightmare.
Then I thought, struct dc isn't meant to be like this, so I spent
some time with an LLM refactoring it so that it's hidden again.
This series does that, it starts by dropping some dead code,
adding some DC accessors, using them in various places.
It then moves dc.h and then a hacky patch to stop dc includes from leaking
out again.
Then it does it all again for some other dc structs that are private.
Some things are a bit messy, especially the ABM calculations, and things
in modules not being quite separated enough, but I've tried to keep the
solutions sane.
Dave.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
Dave Airlie (19):
drm/amd/display: Drop the dead vmid module
drm/amd/display: Add DC accessors as the first step to opaque struct dc
drm/amd/display: Take struct dc in public DSC compute helpers
drm/amd/display/amdgpu_dm: Use DC accessors in audio/color/backlight paths
drm/amd/display/amdgpu_dm: Use DC accessors in psr/replay/dmub/hdcp/irq paths
drm/amd/display/amdgpu_dm: Use DC accessors in plane/crtc/helpers paths
drm/amd/display/amdgpu_dm: Use DC accessors in connector paths
drm/amd/display: Use DC accessors in DAL modules
drm/amd/display/amdgpu_dm: Use DC accessors in debugfs paths
drm/amd/display/amdgpu_dm: Use DC accessors in the DM core paths
drm/amd/display/amdgpu_dm: Finish DC accessor migration for non-test code
drm/amd/display: Migrate amdgpu_dm KUnit tests off struct dc internals
drm/amd/display: Move struct dc out of the public dc.h
drm/amd/display: Restrict the dc directory root to DC-internal builds
drm/amd/display: Add dc_force_max_dramclk for the DP compliance workaround
drm/amd/display: Add DC primitives for ABM hardware programming
drm/amd/display: Replace the dc_get_res_pool accessor with purpose APIs
drm/amd/display: Replace dc_get_config with per-option config reads
drm/amd/display: Replace dc_get_caps with purpose-built capability queries
drivers/gpu/drm/amd/amdgpu/Makefile | 1 -
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 172 ++++----
.../drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c | 8 +-
.../amd/display/amdgpu_dm/amdgpu_dm_backlight.c | 12 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 40 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.h | 4 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 7 +-
.../amd/display/amdgpu_dm/amdgpu_dm_connector.c | 49 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 25 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 132 +++---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 61 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 39 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 30 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 30 +-
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 44 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 33 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 10 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c | 12 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 4 +-
.../gpu/drm/amd/display/amdgpu_dm/tests/Makefile | 1 -
.../display/amdgpu_dm/tests/amdgpu_dm_audio_test.c | 51 +--
.../amdgpu_dm/tests/amdgpu_dm_backlight_test.c | 73 ++--
.../display/amdgpu_dm/tests/amdgpu_dm_color_test.c | 25 +-
.../amdgpu_dm/tests/amdgpu_dm_colorop_test.c | 8 +-
.../amdgpu_dm/tests/amdgpu_dm_connector_test.c | 80 ++--
.../display/amdgpu_dm/tests/amdgpu_dm_crc_test.c | 7 +-
.../display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c | 66 +--
.../display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c | 86 ++--
.../amdgpu_dm/tests/amdgpu_dm_freesync_test.c | 7 +-
.../display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c | 23 +-
.../amdgpu_dm/tests/amdgpu_dm_helpers_test.c | 74 ++--
.../display/amdgpu_dm/tests/amdgpu_dm_irq_test.c | 201 +++++-----
.../display/amdgpu_dm/tests/amdgpu_dm_ism_test.c | 31 +-
.../amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c | 39 +-
.../amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h | 3 +
.../amdgpu_dm/tests/amdgpu_dm_mst_types_test.c | 90 +++--
.../display/amdgpu_dm/tests/amdgpu_dm_plane_test.c | 75 ++--
.../display/amdgpu_dm/tests/amdgpu_dm_psr_test.c | 21 +-
.../amd/display/amdgpu_dm/tests/amdgpu_dm_test.c | 55 ++-
.../display/amdgpu_dm/tests/amdgpu_dm_wb_test.c | 6 +-
drivers/gpu/drm/amd/display/dc/Makefile | 16 +
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c | 1 +
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 +
.../gpu/drm/amd/display/dc/bios/command_table2.c | 1 +
.../drm/amd/display/dc/bls_builder/bls_builder.c | 1 +
.../dc/bls_builder/bls_builder_legacy_init.h | 2 +-
.../display/dc/bls_builder/dcn401_init_builder.c | 1 +
.../dc/bls_builder/dcn401_init_builder_legacy.c | 1 +
.../drm/amd/display/dc/bls_executor/bls_executor.c | 1 +
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 1 +
.../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 1 +
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 23 ++
drivers/gpu/drm/amd/display/dc/core/dc_abm.c | 132 ++++++
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 313 +++++++++++++++
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_link_exports.c | 86 ++++
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 11 +
drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 3 +-
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_test.c | 155 +++++++
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 1 +
drivers/gpu/drm/amd/display/dc/core2/dc_core2.h | 2 +-
.../drm/amd/display/dc/dc_api_dispatch/api_shim.c | 2 +-
.../drm/amd/display/dc/dc_api_dispatch/api_shim.h | 3 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 1 +
drivers/gpu/drm/amd/display/dc/dc_priv.h | 186 +++++++++
drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 1 +
.../gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c | 1 +
.../drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c | 1 +
.../gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 1 +
.../drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c | 1 +
.../gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 2 +-
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 1 +
.../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 1 +
.../gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 1 +
.../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 3 +-
.../drm/amd/display/dc/dce110/dce110_transform_v.c | 1 +
.../display/dc/dcn10/dcn10_hw_sequencer_debug.c | 1 +
.../amd/display/dc/dcn201/dcn201_link_encoder.c | 1 +
.../drm/amd/display/dc/dcn21/dcn21_link_encoder.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c | 3 +-
.../drm/amd/display/dc/dcn31/dcn31_panel_cntl.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c | 3 +-
.../amd/display/dc/dio/dcn10/dcn10_link_encoder.c | 1 +
.../display/dc/dio/dcn10/dcn10_stream_encoder.c | 1 +
.../amd/display/dc/dio/dcn20/dcn20_link_encoder.c | 1 +
.../display/dc/dio/dcn20/dcn20_stream_encoder.c | 1 +
.../display/dc/dio/dcn30/dcn30_dio_link_encoder.c | 1 +
.../dc/dio/dcn30/dcn30_dio_stream_encoder.c | 1 +
.../dc/dio/dcn301/dcn301_dio_link_encoder.c | 1 +
.../display/dc/dio/dcn31/dcn31_dio_link_encoder.c | 1 +
.../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 1 +
.../display/dc/dio/dcn32/dcn32_dio_link_encoder.c | 1 +
.../dc/dio/dcn32/dcn32_dio_stream_encoder.c | 1 +
.../dc/dio/dcn321/dcn321_dio_link_encoder.c | 1 +
.../display/dc/dio/dcn35/dcn35_dio_link_encoder.c | 1 +
.../dc/dio/dcn35/dcn35_dio_stream_encoder.c | 1 +
.../dc/dio/dcn401/dcn401_dio_link_encoder.c | 1 +
.../dc/dio/dcn401/dcn401_dio_stream_encoder.c | 1 +
.../display/dc/dio/dcn42/dcn42_dio_link_encoder.c | 1 +
.../dc/dio/dcn42/dcn42_dio_stream_encoder.c | 1 +
.../display/dc/dio/dcn60/dcn60_dio_link_encoder.c | 1 +
.../dc/dio/dcn60/dcn60_dio_stream_encoder.c | 1 +
.../gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c | 1 +
.../dml21_wrapper/dml21_translation_helper.c | 1 +
.../dc/dml2_wrapper/dml21_wrapper/dml21_utils.c | 1 +
.../dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c | 1 +
.../dc/dml2_wrapper/dml2_dc_resource_mgmt.c | 1 +
.../display/dc/dml2_wrapper/dml2_mall_phantom.c | 1 +
.../dc/dml2_wrapper/dml2_translation_helper.c | 1 +
.../drm/amd/display/dc/dml2_wrapper/dml2_utils.c | 1 +
.../drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c | 1 +
.../amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c | 1 +
.../drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c | 1 +
.../drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c | 1 +
.../gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c | 1 +
.../gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 1 +
.../drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c | 1 +
.../amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 1 +
.../drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c | 1 +
.../drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 18 +-
drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 1 +
.../dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c | 1 +
.../drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c | 1 +
.../amd/display/dc/hubbub/dcn201/dcn201_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c | 1 +
.../amd/display/dc/hubbub/dcn401/dcn401_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c | 1 +
.../gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c | 1 +
.../gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c | 1 +
.../gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce100/dce100_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce112/dce112_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce120/dce120_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce60/dce60_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce80/dce80_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c | 3 +-
.../drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 3 +-
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn201/dcn201_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn301/dcn301_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn302/dcn302_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn303/dcn303_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 3 +-
.../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 3 +-
.../drm/amd/display/dc/hwss/dcn314/dcn314_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 +-
.../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 +-
.../drm/amd/display/dc/hwss/dcn401/dcn401_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h | 2 +-
.../drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c | 1 +
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 16 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 8 +-
drivers/gpu/drm/amd/display/dc/{ => inc}/dc.h | 446 ++++++++++++++-------
.../drm/amd/display/dc/{ => inc}/dc_bios_types.h | 0
.../drm/amd/display/dc/{ => inc}/dc_ddc_types.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_dmub_srv.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_dp_types.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_dsc.h | 4 +-
.../gpu/drm/amd/display/dc/{ => inc}/dc_fused_io.h | 0
.../drm/amd/display/dc/{ => inc}/dc_hdmi_types.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_hw_types.h | 0
.../drm/amd/display/dc/{ => inc}/dc_memory_pool.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_plane.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_probe.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_stat.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_state.h | 2 +-
.../gpu/drm/amd/display/dc/{ => inc}/dc_stream.h | 0
drivers/gpu/drm/amd/display/dc/inc/dc_test.h | 85 ++++
.../gpu/drm/amd/display/dc/{ => inc}/dc_trace.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_types.h | 0
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +-
.../gpu/drm/amd/display/dc/{ => inc}/dm_cp_psp.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dm_helpers.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dm_pp_smu.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dm_services.h | 16 +
.../amd/display/dc/{ => inc}/dm_services_types.h | 0
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 +-
drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +-
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 2 +-
.../gpu/drm/amd/display/dc/{ => inc}/irq_types.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/os_types.h | 0
.../amd/display/dc/irq/dce110/irq_service_dce110.c | 1 +
.../amd/display/dc/link/accessories/link_dp_cts.c | 1 +
.../display/dc/link/accessories/link_dp_trace.c | 1 +
.../drm/amd/display/dc/link/hwss/link_hwss_dio.c | 1 +
.../link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c | 1 +
.../drm/amd/display/dc/link/hwss/link_hwss_dpia.c | 1 +
.../amd/display/dc/link/hwss/link_hwss_hpo_dp.c | 1 +
.../hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 1 +
.../amd/display/dc/link/hwss/link_hwss_hpo_frl.c | 1 +
.../gpu/drm/amd/display/dc/link/link_detection.c | 1 +
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 1 +
drivers/gpu/drm/amd/display/dc/link/link_factory.c | 1 +
.../gpu/drm/amd/display/dc/link/link_resource.c | 1 +
.../gpu/drm/amd/display/dc/link/link_validation.c | 1 +
.../drm/amd/display/dc/link/protocols/link_ddc.c | 1 +
.../display/dc/link/protocols/link_dp_capability.c | 1 +
.../amd/display/dc/link/protocols/link_dp_dpia.c | 2 +-
.../display/dc/link/protocols/link_dp_dpia_bw.c | 1 +
.../dc/link/protocols/link_dp_irq_handler.c | 1 +
.../dc/link/protocols/link_dp_panel_replay.c | 3 +-
.../amd/display/dc/link/protocols/link_dp_phy.c | 1 +
.../display/dc/link/protocols/link_dp_training.c | 1 +
.../dc/link/protocols/link_dp_training_128b_132b.c | 1 +
.../dc/link/protocols/link_dp_training_8b_10b.c | 1 +
.../dc/link/protocols/link_dp_training_dpia.c | 3 +-
.../link_dp_training_fixed_vs_pe_retimer.c | 1 +
.../dc/link/protocols/link_edp_panel_control.c | 3 +-
.../amd/display/dc/link/protocols/link_hdmi_frl.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c | 1 +
.../gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c | 1 +
.../gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 1 +
.../drm/amd/display/dc/optc/dcn401/dcn401_optc.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c | 1 +
.../drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c | 1 +
.../drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c | 1 +
.../display/dc/resource/dce100/dce100_resource.c | 1 +
.../display/dc/resource/dce110/dce110_resource.c | 1 +
.../display/dc/resource/dce112/dce112_resource.c | 1 +
.../display/dc/resource/dce120/dce120_resource.c | 1 +
.../amd/display/dc/resource/dce60/dce60_resource.c | 1 +
.../amd/display/dc/resource/dce80/dce80_resource.c | 1 +
.../amd/display/dc/resource/dcn10/dcn10_resource.c | 1 +
.../amd/display/dc/resource/dcn20/dcn20_resource.c | 1 +
.../display/dc/resource/dcn201/dcn201_resource.c | 1 +
.../amd/display/dc/resource/dcn21/dcn21_resource.c | 1 +
.../amd/display/dc/resource/dcn30/dcn30_resource.c | 1 +
.../display/dc/resource/dcn301/dcn301_resource.c | 1 +
.../display/dc/resource/dcn302/dcn302_resource.c | 1 +
.../display/dc/resource/dcn303/dcn303_resource.c | 1 +
.../amd/display/dc/resource/dcn31/dcn31_resource.c | 1 +
.../display/dc/resource/dcn314/dcn314_resource.c | 1 +
.../display/dc/resource/dcn315/dcn315_resource.c | 1 +
.../display/dc/resource/dcn316/dcn316_resource.c | 1 +
.../amd/display/dc/resource/dcn32/dcn32_resource.c | 1 +
.../dc/resource/dcn32/dcn32_resource_helpers.c | 1 +
.../display/dc/resource/dcn321/dcn321_resource.c | 1 +
.../amd/display/dc/resource/dcn35/dcn35_resource.c | 1 +
.../display/dc/resource/dcn351/dcn351_resource.c | 1 +
.../amd/display/dc/resource/dcn36/dcn36_resource.c | 1 +
.../display/dc/resource/dcn401/dcn401_resource.c | 1 +
.../amd/display/dc/resource/dcn42/dcn42_resource.c | 1 +
.../display/dc/resource/dcn42/dcn42_resource_fpu.c | 1 +
.../display/dc/resource/dcn42b/dcn42b_resource.c | 1 +
.../amd/display/dc/resource/dcn60/dcn60_resource.c | 1 +
.../gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c | 1 +
.../gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c | 1 +
.../dcn401/dcn401_soc_and_ip_translator.c | 1 +
.../dcn42/dcn42_soc_and_ip_translator.c | 1 +
.../dcn60/dcn60_soc_and_ip_translator.c | 1 +
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 +-
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 2 +-
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 2 +-
.../gpu/drm/amd/display/include/logger_interface.h | 13 +-
.../drm/amd/display/modules/color/color_gamma.c | 2 +-
.../drm/amd/display/modules/color/color_gamma.h | 2 +-
.../drm/amd/display/modules/freesync/freesync.c | 14 +-
.../gpu/drm/amd/display/modules/inc/mod_freesync.h | 2 +
.../gpu/drm/amd/display/modules/inc/mod_stats.h | 75 ----
drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h | 46 ---
drivers/gpu/drm/amd/display/modules/power/power.c | 6 +-
.../gpu/drm/amd/display/modules/power/power_abm.c | 168 +++-----
.../drm/amd/display/modules/power/power_helpers.h | 17 +-
.../gpu/drm/amd/display/modules/power/power_psr.c | 12 +-
.../drm/amd/display/modules/power/power_replay.c | 27 +-
drivers/gpu/drm/amd/display/modules/vmid/vmid.c | 178 --------
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
366 files changed, 2633 insertions(+), 1508 deletions(-)
---
base-commit: a6836fcbb5b22968019256025321d655b78bc49c
change-id: 20261112-amdgpu-dc-cleanup-bc5be9190d11
Best regards,
--
Dave Airlie <airlied@redhat.com>
^ permalink raw reply [flat|nested] 52+ messages in thread* [PATCH 01/19] drm/amd/display: Drop the dead vmid module
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
modules/vmid, mod_vmid.h and mod_stats.h are not referenced by any
Makefile; remove the dead code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/modules/inc/mod_stats.h | 75 ---------
drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h | 46 ------
drivers/gpu/drm/amd/display/modules/vmid/vmid.c | 178 ---------------------
3 files changed, 299 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h b/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
deleted file mode 100644
index 8ce6c22e5d04..000000000000
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2016 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef MODULES_INC_MOD_STATS_H_
-#define MODULES_INC_MOD_STATS_H_
-
-#include "dm_services.h"
-
-struct mod_stats {
- int dummy;
-};
-
-struct mod_stats_caps {
- bool dummy;
-};
-
-struct mod_stats_init_params {
- unsigned int stats_enable;
- unsigned int stats_entries;
-};
-
-struct mod_stats *mod_stats_create(struct dc *dc,
- struct mod_stats_init_params *init_params);
-
-void mod_stats_destroy(struct mod_stats *mod_stats);
-
-bool mod_stats_init(struct mod_stats *mod_stats);
-
-void mod_stats_dump(struct mod_stats *mod_stats);
-
-void mod_stats_reset_data(struct mod_stats *mod_stats);
-
-void mod_stats_update_event(struct mod_stats *mod_stats,
- const char *event_string,
- unsigned int length);
-
-void mod_stats_update_flip(struct mod_stats *mod_stats,
- unsigned long long timestamp_in_ns);
-
-void mod_stats_update_vupdate(struct mod_stats *mod_stats,
- unsigned long long timestamp_in_ns);
-
-void mod_stats_update_freesync(struct mod_stats *mod_stats,
- unsigned int v_total_min,
- unsigned int v_total_max,
- unsigned int event_triggers,
- unsigned int window_min,
- unsigned int window_max,
- unsigned int lfc_mid_point_in_us,
- unsigned int inserted_frames,
- unsigned int inserted_frame_duration_in_us);
-
-#endif /* MODULES_INC_MOD_STATS_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h b/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
deleted file mode 100644
index a3787fdf0c08..000000000000
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef MOD_VMID_H_
-#define MOD_VMID_H_
-
-#define MAX_VMID 16
-
-#include "dc.h"
-
-struct mod_vmid {
- int dummy;
-};
-
-uint8_t mod_vmid_get_for_ptb(struct mod_vmid *mod_vmid, uint64_t ptb);
-void mod_vmid_reset(struct mod_vmid *mod_vmid);
-struct mod_vmid *mod_vmid_create(
- struct dc *dc,
- unsigned int num_vmid,
- struct dc_virtual_addr_space_config *va_config);
-
-void mod_vmid_destroy(struct mod_vmid *mod_vmid);
-
-#endif /* MOD_VMID_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
deleted file mode 100644
index 32617893ffb2..000000000000
--- a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "mod_vmid.h"
-
-struct core_vmid {
- struct mod_vmid public;
- struct dc *dc;
-
- unsigned int num_vmid;
- unsigned int num_vmids_available;
- uint64_t ptb_assigned_to_vmid[MAX_VMID];
- struct dc_virtual_addr_space_config base_config;
-};
-
-#define MOD_VMID_TO_CORE(mod_vmid)\
- container_of(mod_vmid, struct core_vmid, public)
-
-static void add_ptb_to_table(struct core_vmid *core_vmid, unsigned int vmid, uint64_t ptb)
-{
- if (vmid < MAX_VMID) {
- core_vmid->ptb_assigned_to_vmid[vmid] = ptb;
- core_vmid->num_vmids_available--;
- }
-}
-
-static void clear_entry_from_vmid_table(struct core_vmid *core_vmid, unsigned int vmid)
-{
- if (vmid < MAX_VMID) {
- core_vmid->ptb_assigned_to_vmid[vmid] = 0;
- core_vmid->num_vmids_available++;
- }
-}
-
-static void evict_vmids(struct core_vmid *core_vmid)
-{
- unsigned int i;
- int ord_int = dc_get_vmid_use_vector(core_vmid->dc);
-
- ASSERT(ord_int >= 0 && ord_int <= 0xFFFF);
- uint16_t ord = (uint16_t)ord_int;
-
- // At this point any positions with value 0 are unused vmids, evict them
- for (i = 1; i < core_vmid->num_vmid; i++) {
- if (!(ord & (1u << i)))
- clear_entry_from_vmid_table(core_vmid, i);
- }
-}
-
-// Return value of -1 indicates vmid table uninitialized or ptb dne in the table
-static int get_existing_vmid_for_ptb(struct core_vmid *core_vmid, uint64_t ptb)
-{
- unsigned int i;
-
- for (i = 0; i < core_vmid->num_vmid; i++) {
- if (core_vmid->ptb_assigned_to_vmid[i] == ptb)
- return i;
- }
-
- return -1;
-}
-
-// Expected to be called only when there's an available vmid
-static int get_next_available_vmid(struct core_vmid *core_vmid)
-{
- unsigned int i;
-
- for (i = 1; i < core_vmid->num_vmid; i++) {
- if (core_vmid->ptb_assigned_to_vmid[i] == 0)
- return i;
- }
-
- return -1;
-}
-
-uint8_t mod_vmid_get_for_ptb(struct mod_vmid *mod_vmid, uint64_t ptb)
-{
- struct core_vmid *core_vmid = MOD_VMID_TO_CORE(mod_vmid);
- int vmid = 0;
-
- // Physical address gets vmid 0
- if (ptb == 0)
- return 0;
-
- vmid = get_existing_vmid_for_ptb(core_vmid, ptb);
-
- if (vmid == -1) {
- struct dc_virtual_addr_space_config va_config = core_vmid->base_config;
-
- va_config.page_table_base_addr = ptb;
-
- if (core_vmid->num_vmids_available == 0)
- evict_vmids(core_vmid);
-
- vmid = get_next_available_vmid(core_vmid);
- if (vmid != -1) {
- add_ptb_to_table(core_vmid, vmid, ptb);
-
- dc_setup_vm_context(core_vmid->dc, &va_config, vmid);
- } else
- ASSERT(0);
- }
-
- ASSERT(vmid >= 0 && vmid <= 0xFF);
- return (uint8_t)vmid;
-}
-
-void mod_vmid_reset(struct mod_vmid *mod_vmid)
-{
- struct core_vmid *core_vmid = MOD_VMID_TO_CORE(mod_vmid);
-
- core_vmid->num_vmids_available = core_vmid->num_vmid - 1;
- memset(core_vmid->ptb_assigned_to_vmid, 0, sizeof(core_vmid->ptb_assigned_to_vmid[0]) * MAX_VMID);
-}
-
-struct mod_vmid *mod_vmid_create(
- struct dc *dc,
- unsigned int num_vmid,
- struct dc_virtual_addr_space_config *va_config)
-{
- struct core_vmid *core_vmid;
-
- if (num_vmid <= 1)
- goto fail_no_vm_ctx;
-
- if (dc == NULL)
- goto fail_dc_null;
-
- core_vmid = kzalloc_obj(struct core_vmid);
-
- if (core_vmid == NULL)
- goto fail_alloc_context;
-
- core_vmid->dc = dc;
- core_vmid->num_vmid = num_vmid;
- core_vmid->num_vmids_available = num_vmid - 1;
- core_vmid->base_config = *va_config;
-
- memset(core_vmid->ptb_assigned_to_vmid, 0, sizeof(core_vmid->ptb_assigned_to_vmid[0]) * MAX_VMID);
-
- return &core_vmid->public;
-
-fail_no_vm_ctx:
-fail_alloc_context:
-fail_dc_null:
- return NULL;
-}
-
-void mod_vmid_destroy(struct mod_vmid *mod_vmid)
-{
- if (mod_vmid != NULL) {
- struct core_vmid *core_vmid = MOD_VMID_TO_CORE(mod_vmid);
-
- kfree(core_vmid);
- }
-}
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 01/19] drm/amd/display: Drop the dead vmid module
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
modules/vmid, mod_vmid.h and mod_stats.h are not referenced by any
Makefile; remove the dead code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/modules/inc/mod_stats.h | 75 ---------
drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h | 46 ------
drivers/gpu/drm/amd/display/modules/vmid/vmid.c | 178 ---------------------
3 files changed, 299 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h b/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
deleted file mode 100644
index 8ce6c22e5d04..000000000000
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2016 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef MODULES_INC_MOD_STATS_H_
-#define MODULES_INC_MOD_STATS_H_
-
-#include "dm_services.h"
-
-struct mod_stats {
- int dummy;
-};
-
-struct mod_stats_caps {
- bool dummy;
-};
-
-struct mod_stats_init_params {
- unsigned int stats_enable;
- unsigned int stats_entries;
-};
-
-struct mod_stats *mod_stats_create(struct dc *dc,
- struct mod_stats_init_params *init_params);
-
-void mod_stats_destroy(struct mod_stats *mod_stats);
-
-bool mod_stats_init(struct mod_stats *mod_stats);
-
-void mod_stats_dump(struct mod_stats *mod_stats);
-
-void mod_stats_reset_data(struct mod_stats *mod_stats);
-
-void mod_stats_update_event(struct mod_stats *mod_stats,
- const char *event_string,
- unsigned int length);
-
-void mod_stats_update_flip(struct mod_stats *mod_stats,
- unsigned long long timestamp_in_ns);
-
-void mod_stats_update_vupdate(struct mod_stats *mod_stats,
- unsigned long long timestamp_in_ns);
-
-void mod_stats_update_freesync(struct mod_stats *mod_stats,
- unsigned int v_total_min,
- unsigned int v_total_max,
- unsigned int event_triggers,
- unsigned int window_min,
- unsigned int window_max,
- unsigned int lfc_mid_point_in_us,
- unsigned int inserted_frames,
- unsigned int inserted_frame_duration_in_us);
-
-#endif /* MODULES_INC_MOD_STATS_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h b/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
deleted file mode 100644
index a3787fdf0c08..000000000000
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_vmid.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef MOD_VMID_H_
-#define MOD_VMID_H_
-
-#define MAX_VMID 16
-
-#include "dc.h"
-
-struct mod_vmid {
- int dummy;
-};
-
-uint8_t mod_vmid_get_for_ptb(struct mod_vmid *mod_vmid, uint64_t ptb);
-void mod_vmid_reset(struct mod_vmid *mod_vmid);
-struct mod_vmid *mod_vmid_create(
- struct dc *dc,
- unsigned int num_vmid,
- struct dc_virtual_addr_space_config *va_config);
-
-void mod_vmid_destroy(struct mod_vmid *mod_vmid);
-
-#endif /* MOD_VMID_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c b/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
deleted file mode 100644
index 32617893ffb2..000000000000
--- a/drivers/gpu/drm/amd/display/modules/vmid/vmid.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "mod_vmid.h"
-
-struct core_vmid {
- struct mod_vmid public;
- struct dc *dc;
-
- unsigned int num_vmid;
- unsigned int num_vmids_available;
- uint64_t ptb_assigned_to_vmid[MAX_VMID];
- struct dc_virtual_addr_space_config base_config;
-};
-
-#define MOD_VMID_TO_CORE(mod_vmid)\
- container_of(mod_vmid, struct core_vmid, public)
-
-static void add_ptb_to_table(struct core_vmid *core_vmid, unsigned int vmid, uint64_t ptb)
-{
- if (vmid < MAX_VMID) {
- core_vmid->ptb_assigned_to_vmid[vmid] = ptb;
- core_vmid->num_vmids_available--;
- }
-}
-
-static void clear_entry_from_vmid_table(struct core_vmid *core_vmid, unsigned int vmid)
-{
- if (vmid < MAX_VMID) {
- core_vmid->ptb_assigned_to_vmid[vmid] = 0;
- core_vmid->num_vmids_available++;
- }
-}
-
-static void evict_vmids(struct core_vmid *core_vmid)
-{
- unsigned int i;
- int ord_int = dc_get_vmid_use_vector(core_vmid->dc);
-
- ASSERT(ord_int >= 0 && ord_int <= 0xFFFF);
- uint16_t ord = (uint16_t)ord_int;
-
- // At this point any positions with value 0 are unused vmids, evict them
- for (i = 1; i < core_vmid->num_vmid; i++) {
- if (!(ord & (1u << i)))
- clear_entry_from_vmid_table(core_vmid, i);
- }
-}
-
-// Return value of -1 indicates vmid table uninitialized or ptb dne in the table
-static int get_existing_vmid_for_ptb(struct core_vmid *core_vmid, uint64_t ptb)
-{
- unsigned int i;
-
- for (i = 0; i < core_vmid->num_vmid; i++) {
- if (core_vmid->ptb_assigned_to_vmid[i] == ptb)
- return i;
- }
-
- return -1;
-}
-
-// Expected to be called only when there's an available vmid
-static int get_next_available_vmid(struct core_vmid *core_vmid)
-{
- unsigned int i;
-
- for (i = 1; i < core_vmid->num_vmid; i++) {
- if (core_vmid->ptb_assigned_to_vmid[i] == 0)
- return i;
- }
-
- return -1;
-}
-
-uint8_t mod_vmid_get_for_ptb(struct mod_vmid *mod_vmid, uint64_t ptb)
-{
- struct core_vmid *core_vmid = MOD_VMID_TO_CORE(mod_vmid);
- int vmid = 0;
-
- // Physical address gets vmid 0
- if (ptb == 0)
- return 0;
-
- vmid = get_existing_vmid_for_ptb(core_vmid, ptb);
-
- if (vmid == -1) {
- struct dc_virtual_addr_space_config va_config = core_vmid->base_config;
-
- va_config.page_table_base_addr = ptb;
-
- if (core_vmid->num_vmids_available == 0)
- evict_vmids(core_vmid);
-
- vmid = get_next_available_vmid(core_vmid);
- if (vmid != -1) {
- add_ptb_to_table(core_vmid, vmid, ptb);
-
- dc_setup_vm_context(core_vmid->dc, &va_config, vmid);
- } else
- ASSERT(0);
- }
-
- ASSERT(vmid >= 0 && vmid <= 0xFF);
- return (uint8_t)vmid;
-}
-
-void mod_vmid_reset(struct mod_vmid *mod_vmid)
-{
- struct core_vmid *core_vmid = MOD_VMID_TO_CORE(mod_vmid);
-
- core_vmid->num_vmids_available = core_vmid->num_vmid - 1;
- memset(core_vmid->ptb_assigned_to_vmid, 0, sizeof(core_vmid->ptb_assigned_to_vmid[0]) * MAX_VMID);
-}
-
-struct mod_vmid *mod_vmid_create(
- struct dc *dc,
- unsigned int num_vmid,
- struct dc_virtual_addr_space_config *va_config)
-{
- struct core_vmid *core_vmid;
-
- if (num_vmid <= 1)
- goto fail_no_vm_ctx;
-
- if (dc == NULL)
- goto fail_dc_null;
-
- core_vmid = kzalloc_obj(struct core_vmid);
-
- if (core_vmid == NULL)
- goto fail_alloc_context;
-
- core_vmid->dc = dc;
- core_vmid->num_vmid = num_vmid;
- core_vmid->num_vmids_available = num_vmid - 1;
- core_vmid->base_config = *va_config;
-
- memset(core_vmid->ptb_assigned_to_vmid, 0, sizeof(core_vmid->ptb_assigned_to_vmid[0]) * MAX_VMID);
-
- return &core_vmid->public;
-
-fail_no_vm_ctx:
-fail_alloc_context:
-fail_dc_null:
- return NULL;
-}
-
-void mod_vmid_destroy(struct mod_vmid *mod_vmid)
-{
- if (mod_vmid != NULL) {
- struct core_vmid *core_vmid = MOD_VMID_TO_CORE(mod_vmid);
-
- kfree(core_vmid);
- }
-}
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 02/19] drm/amd/display: Add DC accessors as the first step to opaque struct dc
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
struct dc is defined in dc.h which is included by DM and DAL modules,
so any of them can dereference dc members directly. As a first step
towards making struct dc private to DC, add an accessor layer:
- Introspection accessors (link count, ctx, caps, config, debug
options, current state, idle optimizations, resource pool, clock
manager) implemented in a new dc/core/dc_accessors.c which is the
single place mapping accessor names onto struct dc fields.
- hwss/cap_funcs wrappers for log_hw_state, get_dcc_en_bits,
prepare_ddc, get_dcc_compression_cap and get_subvp_en.
- FBC and DML2 alternate channel configuration helpers.
- link_service wrappers in dc/core/dc_link_exports.c for the entry
points that DM and DAL modules reach through dc->link_srv today,
violating the link_service.h usage policy.
The accessors are additive; no consumer is migrated yet.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 136 ++++++++++++++++
.../gpu/drm/amd/display/dc/core/dc_link_exports.c | 85 ++++++++++
drivers/gpu/drm/amd/display/dc/dc.h | 174 +++++++++++++++++++++
4 files changed, 396 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 84c68b87210f..0f39a15dfc60 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -68,6 +68,7 @@ FILES += dc_fused_io.o
FILES += dc_helper.o
FILES += dc_memory_pool.o
FILES += core/dc.o
+FILES += core/dc_accessors.o
FILES += dc_api_dispatch/api_shim.o
FILES += core/dc_debug.o
FILES += core/dc_hw_sequencer.o
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
new file mode 100644
index 000000000000..8aa2364b714e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+/* FILE POLICY AND INTENDED USAGE:
+ * This file implements the struct dc accessors declared in dc.h. struct dc
+ * is private to DC; this file is the single place that maps public accessor
+ * names onto struct dc fields. Keep it free of functional behavior so the
+ * mapping stays obvious and auditable.
+ */
+#include "dc.h"
+
+uint8_t dc_get_link_count(const struct dc *dc)
+{
+ return dc->link_count;
+}
+
+struct dc_context *dc_get_ctx(const struct dc *dc)
+{
+ return dc->ctx;
+}
+
+const struct dc_caps *dc_get_caps(const struct dc *dc)
+{
+ return &dc->caps;
+}
+
+const struct dc_config *dc_get_config(const struct dc *dc)
+{
+ return &dc->config;
+}
+
+struct dc_debug_options *dc_get_debug_options(struct dc *dc)
+{
+ return &dc->debug;
+}
+
+struct dc_state *dc_get_current_state(const struct dc *dc)
+{
+ return dc->current_state;
+}
+
+bool dc_is_idle_optimizations_allowed(const struct dc *dc)
+{
+ return dc->idle_optimizations_allowed;
+}
+
+struct resource_pool *dc_get_res_pool(const struct dc *dc)
+{
+ return dc->res_pool;
+}
+
+struct clk_mgr *dc_get_clk_mgr(struct dc *dc)
+{
+ return dc->clk_mgr;
+}
+
+bool dc_get_dcc_compression_cap(const struct dc *dc,
+ const struct dc_dcc_surface_param *input,
+ struct dc_surface_dcc_cap *output)
+{
+ if (!dc->cap_funcs.get_dcc_compression_cap)
+ return false;
+
+ return dc->cap_funcs.get_dcc_compression_cap(dc, input, output);
+}
+
+bool dc_get_subvp_en(struct dc *dc, struct dc_state *context)
+{
+ if (!dc->cap_funcs.get_subvp_en)
+ return false;
+
+ return dc->cap_funcs.get_subvp_en(dc, context);
+}
+
+bool dc_log_hw_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
+{
+ if (!dc->hwss.log_hw_state)
+ return false;
+
+ dc->hwss.log_hw_state(dc, log_ctx);
+ return true;
+}
+
+bool dc_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits)
+{
+ if (!dc->hwss.get_dcc_en_bits)
+ return false;
+
+ dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
+ return true;
+}
+
+void dc_prepare_ddc(struct dc_link *link)
+{
+ if (link->dc->hwss.prepare_ddc)
+ link->dc->hwss.prepare_ddc(link);
+}
+
+bool dc_is_fbc_compressor_available(const struct dc *dc)
+{
+ return dc->fbc_compressor != NULL;
+}
+
+void dc_set_fbc_gpu_addr(struct dc *dc, uint64_t gpu_addr)
+{
+ dc->ctx->fbc_gpu_addr = gpu_addr;
+}
+
+void dc_set_dml2_alt_ch_cfg(struct dc *dc,
+ const struct dml2_soc_alt_ch_info *alt_ch_cfg)
+{
+ dc->dml2_options.alt_ch_cfg = *alt_ch_cfg;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index 5926e8a4f95a..d2f52e4839fe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -545,6 +545,91 @@ void dc_link_edp_replay_residency(const struct dc_link *link,
link->dc->link_srv->edp_replay_residency(link, residency, is_start, mode);
}
+void dc_link_edp_get_psr_residency(const struct dc_link *link,
+ uint32_t *residency, enum psr_residency_mode mode)
+{
+ if (link && link->dc && link->dc->link_srv)
+ link->dc->link_srv->edp_get_psr_residency(link, residency, mode);
+}
+
+bool dc_link_edp_set_sink_vtotal_in_psr_active(const struct dc_link *link,
+ uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_set_sink_vtotal_in_psr_active(
+ link, psr_vtotal_idle, psr_vtotal_su);
+}
+
+bool dc_link_edp_send_replay_cmd(struct dc_link *link,
+ enum replay_FW_Message_type msg,
+ union dmub_replay_cmd_set *cmd_data)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_send_replay_cmd(link, msg, cmd_data);
+}
+
+bool dc_link_edp_set_coasting_vtotal(struct dc_link *link,
+ uint32_t coasting_vtotal, uint16_t frame_skip_number)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_set_coasting_vtotal(
+ link, coasting_vtotal, frame_skip_number);
+}
+
+bool dc_link_edp_replay_get_cumulative_residency(const struct dc_link *link,
+ uint32_t *residency_milli_pct)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_replay_get_cumulative_residency(
+ link, residency_milli_pct);
+}
+
+bool dc_link_edp_set_replay_power_opt_and_coasting_vtotal(
+ struct dc_link *link, const unsigned int *power_opts,
+ uint32_t coasting_vtotal, uint16_t frame_skip_number)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_set_replay_power_opt_and_coasting_vtotal(
+ link, power_opts, coasting_vtotal, frame_skip_number);
+}
+
+bool dc_link_dp_setup_replay(struct dc_link *link,
+ const struct dc_stream_state *stream)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->dp_setup_replay(link, stream);
+}
+
+uint8_t dc_link_get_ddc_aux_inst(const struct dc_link *link)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return 0;
+
+ return link->dc->link_srv->get_ddc_aux_inst(link);
+}
+
+enum dp_link_encoding dc_link_dp_get_encoding_format(
+ const struct dc_link *link)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return DP_8b_10b_ENCODING;
+
+ return link->dc->link_srv->dp_get_encoding_format(
+ &link->verified_link_cap);
+}
+
bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state)
{
return link->dc->link_srv->dp_pr_get_state(link, state);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 916fa87d0dbc..f0c84abab0fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -2464,6 +2464,92 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
const struct dc_crtc_timing *timing,
const enum dc_link_encoding_format link_encoding);
+/*
+ * DC accessors.
+ *
+ * struct dc is private to DC. These accessors are the supported way for
+ * DM and DAL modules to query DC-wide state. Some of them return pointers
+ * to still-public sub-structures; treat those as read-only unless the
+ * documentation says otherwise.
+ */
+
+/* Number of links; valid indices for dc_get_link_at_index(). */
+uint8_t dc_get_link_count(const struct dc *dc);
+
+/* The DC context (logging, register access, dmub service). */
+struct dc_context *dc_get_ctx(const struct dc *dc);
+
+/* Capabilities detected at dc_create() time. Read-only. */
+const struct dc_caps *dc_get_caps(const struct dc *dc);
+
+/* Configuration captured at dc_create() time. Read-only. */
+const struct dc_config *dc_get_config(const struct dc *dc);
+
+/* Debug overrides (module parameters, debugfs). Writable. */
+struct dc_debug_options *dc_get_debug_options(struct dc *dc);
+
+/* The currently committed state. Owned by DC; read-only for DM. */
+struct dc_state *dc_get_current_state(const struct dc *dc);
+
+/* Whether DC may enter idle power optimizations right now. */
+bool dc_is_idle_optimizations_allowed(const struct dc *dc);
+
+/*
+ * The hardware resource pool (DSC engines, audio instances, DMCU/ABM...).
+ * Interim accessor; prefer purpose-built DC interfaces where available.
+ */
+struct resource_pool *dc_get_res_pool(const struct dc *dc);
+
+/* The clock manager. Interim accessor. */
+struct clk_mgr *dc_get_clk_mgr(struct dc *dc);
+
+/*
+ * Query DCC compression support for a surface.
+ * return false - when the asic does not implement the query.
+ */
+bool dc_get_dcc_compression_cap(const struct dc *dc,
+ const struct dc_dcc_surface_param *input,
+ struct dc_surface_dcc_cap *output);
+
+/*
+ * Whether SubVP is enabled in the given state.
+ * return false - when the asic does not support SubVP.
+ */
+bool dc_get_subvp_en(struct dc *dc, struct dc_state *context);
+
+/*
+ * Dump hardware state into the log buffer, or into the kernel log when
+ * log_ctx is NULL.
+ * return false - when the asic does not implement the dump.
+ */
+bool dc_log_hw_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx);
+
+/*
+ * Read the per-pipe DCC enable bits.
+ * return false - when the asic does not implement the query.
+ */
+bool dc_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);
+
+/*
+ * Run the DDC prepare sequence on the link ahead of aux transactions that
+ * require a prepared DDC line. Optional; silently skipped when the asic
+ * does not implement it.
+ */
+void dc_prepare_ddc(struct dc_link *link);
+
+/* Whether an FBC compressor is instantiated for this DC. */
+bool dc_is_fbc_compressor_available(const struct dc *dc);
+
+/*
+ * Provide the GPU address of the FBC compression buffer that DM allocated.
+ * Only meaningful while an FBC compressor is instantiated.
+ */
+void dc_set_fbc_gpu_addr(struct dc *dc, uint64_t gpu_addr);
+
+/* Configure the alternate channel aperture consumed by DML2. */
+void dc_set_dml2_alt_ch_cfg(struct dc *dc,
+ const struct dml2_soc_alt_ch_info *alt_ch_cfg);
+
/* Link Interfaces */
/* Return an enumerated dc_link.
* dc_link order is constant and determined at
@@ -3019,6 +3105,94 @@ bool dc_link_set_pr_general_cmd(struct dc_link *link,
void dc_link_edp_replay_residency(const struct dc_link *link,
unsigned int *residency, bool is_start, enum pr_residency_mode mode);
+/*
+ * Measure PSR residency for the given link.
+ * mode: PSR_RESIDENCY_MODE_PHY, PSR_RESIDENCY_MODE_ALPM, or
+ * PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD
+ */
+void dc_link_edp_get_psr_residency(const struct dc_link *link,
+ uint32_t *residency, enum psr_residency_mode mode);
+
+/*
+ * Set the sink vtotal in psr active to restore sink timing after
+ * exit psr with firmware initiated mode switching.
+ * return false - if the setting is not applied by firmware.
+ */
+bool dc_link_edp_set_sink_vtotal_in_psr_active(const struct dc_link *link,
+ uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
+
+/*
+ * Send general command to Panel Replay firmware:
+ *
+ * @link: link to send the replay command on
+ * @msg: message type which indicates the variable passed to DMUB
+ * @cmd_data: payload for message types that carry one
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_edp_send_replay_cmd(struct dc_link *link,
+ enum replay_FW_Message_type msg,
+ union dmub_replay_cmd_set *cmd_data);
+
+/*
+ * Set panel replay coasting vtotal.
+ *
+ * @link: link to set the coasting vtotal on
+ * @coasting_vtotal: coasting vtotal to program
+ * @frame_skip_number: number of frames to skip
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_edp_set_coasting_vtotal(struct dc_link *link,
+ uint32_t coasting_vtotal, uint16_t frame_skip_number);
+
+/*
+ * Measure cumulative Panel Replay residency for the given link.
+ *
+ * @link: pointer to the dc_link struct instance
+ * @residency_milli_pct: residency in milli-percentage
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_edp_replay_get_cumulative_residency(const struct dc_link *link,
+ uint32_t *residency_milli_pct);
+
+/*
+ * Set panel replay power optimization and coasting vtotal together.
+ *
+ * @link: link to configure
+ * @power_opts: power optimization bits to enable
+ * @coasting_vtotal: coasting vtotal to program
+ * @frame_skip_number: number of frames to skip
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_edp_set_replay_power_opt_and_coasting_vtotal(
+ struct dc_link *link, const unsigned int *power_opts,
+ uint32_t coasting_vtotal, uint16_t frame_skip_number);
+
+/*
+ * Set up the link for panel replay.
+ *
+ * @link: link to configure
+ * @stream: stream to enable panel replay for
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_dp_setup_replay(struct dc_link *link,
+ const struct dc_stream_state *stream);
+
+/*
+ * Get the instance id of the DDC aux service backing the link.
+ */
+uint8_t dc_link_get_ddc_aux_inst(const struct dc_link *link);
+
+/*
+ * Get the DP link encoding format of the link's verified link settings.
+ */
+enum dp_link_encoding dc_link_dp_get_encoding_format(
+ const struct dc_link *link);
+
/*
* Get Panel Replay state:
*
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 02/19] drm/amd/display: Add DC accessors as the first step to opaque struct dc
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
struct dc is defined in dc.h which is included by DM and DAL modules,
so any of them can dereference dc members directly. As a first step
towards making struct dc private to DC, add an accessor layer:
- Introspection accessors (link count, ctx, caps, config, debug
options, current state, idle optimizations, resource pool, clock
manager) implemented in a new dc/core/dc_accessors.c which is the
single place mapping accessor names onto struct dc fields.
- hwss/cap_funcs wrappers for log_hw_state, get_dcc_en_bits,
prepare_ddc, get_dcc_compression_cap and get_subvp_en.
- FBC and DML2 alternate channel configuration helpers.
- link_service wrappers in dc/core/dc_link_exports.c for the entry
points that DM and DAL modules reach through dc->link_srv today,
violating the link_service.h usage policy.
The accessors are additive; no consumer is migrated yet.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 136 ++++++++++++++++
.../gpu/drm/amd/display/dc/core/dc_link_exports.c | 85 ++++++++++
drivers/gpu/drm/amd/display/dc/dc.h | 174 +++++++++++++++++++++
4 files changed, 396 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 84c68b87210f..0f39a15dfc60 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -68,6 +68,7 @@ FILES += dc_fused_io.o
FILES += dc_helper.o
FILES += dc_memory_pool.o
FILES += core/dc.o
+FILES += core/dc_accessors.o
FILES += dc_api_dispatch/api_shim.o
FILES += core/dc_debug.o
FILES += core/dc_hw_sequencer.o
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
new file mode 100644
index 000000000000..8aa2364b714e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+/* FILE POLICY AND INTENDED USAGE:
+ * This file implements the struct dc accessors declared in dc.h. struct dc
+ * is private to DC; this file is the single place that maps public accessor
+ * names onto struct dc fields. Keep it free of functional behavior so the
+ * mapping stays obvious and auditable.
+ */
+#include "dc.h"
+
+uint8_t dc_get_link_count(const struct dc *dc)
+{
+ return dc->link_count;
+}
+
+struct dc_context *dc_get_ctx(const struct dc *dc)
+{
+ return dc->ctx;
+}
+
+const struct dc_caps *dc_get_caps(const struct dc *dc)
+{
+ return &dc->caps;
+}
+
+const struct dc_config *dc_get_config(const struct dc *dc)
+{
+ return &dc->config;
+}
+
+struct dc_debug_options *dc_get_debug_options(struct dc *dc)
+{
+ return &dc->debug;
+}
+
+struct dc_state *dc_get_current_state(const struct dc *dc)
+{
+ return dc->current_state;
+}
+
+bool dc_is_idle_optimizations_allowed(const struct dc *dc)
+{
+ return dc->idle_optimizations_allowed;
+}
+
+struct resource_pool *dc_get_res_pool(const struct dc *dc)
+{
+ return dc->res_pool;
+}
+
+struct clk_mgr *dc_get_clk_mgr(struct dc *dc)
+{
+ return dc->clk_mgr;
+}
+
+bool dc_get_dcc_compression_cap(const struct dc *dc,
+ const struct dc_dcc_surface_param *input,
+ struct dc_surface_dcc_cap *output)
+{
+ if (!dc->cap_funcs.get_dcc_compression_cap)
+ return false;
+
+ return dc->cap_funcs.get_dcc_compression_cap(dc, input, output);
+}
+
+bool dc_get_subvp_en(struct dc *dc, struct dc_state *context)
+{
+ if (!dc->cap_funcs.get_subvp_en)
+ return false;
+
+ return dc->cap_funcs.get_subvp_en(dc, context);
+}
+
+bool dc_log_hw_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
+{
+ if (!dc->hwss.log_hw_state)
+ return false;
+
+ dc->hwss.log_hw_state(dc, log_ctx);
+ return true;
+}
+
+bool dc_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits)
+{
+ if (!dc->hwss.get_dcc_en_bits)
+ return false;
+
+ dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
+ return true;
+}
+
+void dc_prepare_ddc(struct dc_link *link)
+{
+ if (link->dc->hwss.prepare_ddc)
+ link->dc->hwss.prepare_ddc(link);
+}
+
+bool dc_is_fbc_compressor_available(const struct dc *dc)
+{
+ return dc->fbc_compressor != NULL;
+}
+
+void dc_set_fbc_gpu_addr(struct dc *dc, uint64_t gpu_addr)
+{
+ dc->ctx->fbc_gpu_addr = gpu_addr;
+}
+
+void dc_set_dml2_alt_ch_cfg(struct dc *dc,
+ const struct dml2_soc_alt_ch_info *alt_ch_cfg)
+{
+ dc->dml2_options.alt_ch_cfg = *alt_ch_cfg;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index 5926e8a4f95a..d2f52e4839fe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -545,6 +545,91 @@ void dc_link_edp_replay_residency(const struct dc_link *link,
link->dc->link_srv->edp_replay_residency(link, residency, is_start, mode);
}
+void dc_link_edp_get_psr_residency(const struct dc_link *link,
+ uint32_t *residency, enum psr_residency_mode mode)
+{
+ if (link && link->dc && link->dc->link_srv)
+ link->dc->link_srv->edp_get_psr_residency(link, residency, mode);
+}
+
+bool dc_link_edp_set_sink_vtotal_in_psr_active(const struct dc_link *link,
+ uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_set_sink_vtotal_in_psr_active(
+ link, psr_vtotal_idle, psr_vtotal_su);
+}
+
+bool dc_link_edp_send_replay_cmd(struct dc_link *link,
+ enum replay_FW_Message_type msg,
+ union dmub_replay_cmd_set *cmd_data)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_send_replay_cmd(link, msg, cmd_data);
+}
+
+bool dc_link_edp_set_coasting_vtotal(struct dc_link *link,
+ uint32_t coasting_vtotal, uint16_t frame_skip_number)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_set_coasting_vtotal(
+ link, coasting_vtotal, frame_skip_number);
+}
+
+bool dc_link_edp_replay_get_cumulative_residency(const struct dc_link *link,
+ uint32_t *residency_milli_pct)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_replay_get_cumulative_residency(
+ link, residency_milli_pct);
+}
+
+bool dc_link_edp_set_replay_power_opt_and_coasting_vtotal(
+ struct dc_link *link, const unsigned int *power_opts,
+ uint32_t coasting_vtotal, uint16_t frame_skip_number)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->edp_set_replay_power_opt_and_coasting_vtotal(
+ link, power_opts, coasting_vtotal, frame_skip_number);
+}
+
+bool dc_link_dp_setup_replay(struct dc_link *link,
+ const struct dc_stream_state *stream)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return false;
+
+ return link->dc->link_srv->dp_setup_replay(link, stream);
+}
+
+uint8_t dc_link_get_ddc_aux_inst(const struct dc_link *link)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return 0;
+
+ return link->dc->link_srv->get_ddc_aux_inst(link);
+}
+
+enum dp_link_encoding dc_link_dp_get_encoding_format(
+ const struct dc_link *link)
+{
+ if (!link || !link->dc || !link->dc->link_srv)
+ return DP_8b_10b_ENCODING;
+
+ return link->dc->link_srv->dp_get_encoding_format(
+ &link->verified_link_cap);
+}
+
bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state)
{
return link->dc->link_srv->dp_pr_get_state(link, state);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 916fa87d0dbc..f0c84abab0fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -2464,6 +2464,92 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
const struct dc_crtc_timing *timing,
const enum dc_link_encoding_format link_encoding);
+/*
+ * DC accessors.
+ *
+ * struct dc is private to DC. These accessors are the supported way for
+ * DM and DAL modules to query DC-wide state. Some of them return pointers
+ * to still-public sub-structures; treat those as read-only unless the
+ * documentation says otherwise.
+ */
+
+/* Number of links; valid indices for dc_get_link_at_index(). */
+uint8_t dc_get_link_count(const struct dc *dc);
+
+/* The DC context (logging, register access, dmub service). */
+struct dc_context *dc_get_ctx(const struct dc *dc);
+
+/* Capabilities detected at dc_create() time. Read-only. */
+const struct dc_caps *dc_get_caps(const struct dc *dc);
+
+/* Configuration captured at dc_create() time. Read-only. */
+const struct dc_config *dc_get_config(const struct dc *dc);
+
+/* Debug overrides (module parameters, debugfs). Writable. */
+struct dc_debug_options *dc_get_debug_options(struct dc *dc);
+
+/* The currently committed state. Owned by DC; read-only for DM. */
+struct dc_state *dc_get_current_state(const struct dc *dc);
+
+/* Whether DC may enter idle power optimizations right now. */
+bool dc_is_idle_optimizations_allowed(const struct dc *dc);
+
+/*
+ * The hardware resource pool (DSC engines, audio instances, DMCU/ABM...).
+ * Interim accessor; prefer purpose-built DC interfaces where available.
+ */
+struct resource_pool *dc_get_res_pool(const struct dc *dc);
+
+/* The clock manager. Interim accessor. */
+struct clk_mgr *dc_get_clk_mgr(struct dc *dc);
+
+/*
+ * Query DCC compression support for a surface.
+ * return false - when the asic does not implement the query.
+ */
+bool dc_get_dcc_compression_cap(const struct dc *dc,
+ const struct dc_dcc_surface_param *input,
+ struct dc_surface_dcc_cap *output);
+
+/*
+ * Whether SubVP is enabled in the given state.
+ * return false - when the asic does not support SubVP.
+ */
+bool dc_get_subvp_en(struct dc *dc, struct dc_state *context);
+
+/*
+ * Dump hardware state into the log buffer, or into the kernel log when
+ * log_ctx is NULL.
+ * return false - when the asic does not implement the dump.
+ */
+bool dc_log_hw_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx);
+
+/*
+ * Read the per-pipe DCC enable bits.
+ * return false - when the asic does not implement the query.
+ */
+bool dc_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);
+
+/*
+ * Run the DDC prepare sequence on the link ahead of aux transactions that
+ * require a prepared DDC line. Optional; silently skipped when the asic
+ * does not implement it.
+ */
+void dc_prepare_ddc(struct dc_link *link);
+
+/* Whether an FBC compressor is instantiated for this DC. */
+bool dc_is_fbc_compressor_available(const struct dc *dc);
+
+/*
+ * Provide the GPU address of the FBC compression buffer that DM allocated.
+ * Only meaningful while an FBC compressor is instantiated.
+ */
+void dc_set_fbc_gpu_addr(struct dc *dc, uint64_t gpu_addr);
+
+/* Configure the alternate channel aperture consumed by DML2. */
+void dc_set_dml2_alt_ch_cfg(struct dc *dc,
+ const struct dml2_soc_alt_ch_info *alt_ch_cfg);
+
/* Link Interfaces */
/* Return an enumerated dc_link.
* dc_link order is constant and determined at
@@ -3019,6 +3105,94 @@ bool dc_link_set_pr_general_cmd(struct dc_link *link,
void dc_link_edp_replay_residency(const struct dc_link *link,
unsigned int *residency, bool is_start, enum pr_residency_mode mode);
+/*
+ * Measure PSR residency for the given link.
+ * mode: PSR_RESIDENCY_MODE_PHY, PSR_RESIDENCY_MODE_ALPM, or
+ * PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD
+ */
+void dc_link_edp_get_psr_residency(const struct dc_link *link,
+ uint32_t *residency, enum psr_residency_mode mode);
+
+/*
+ * Set the sink vtotal in psr active to restore sink timing after
+ * exit psr with firmware initiated mode switching.
+ * return false - if the setting is not applied by firmware.
+ */
+bool dc_link_edp_set_sink_vtotal_in_psr_active(const struct dc_link *link,
+ uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
+
+/*
+ * Send general command to Panel Replay firmware:
+ *
+ * @link: link to send the replay command on
+ * @msg: message type which indicates the variable passed to DMUB
+ * @cmd_data: payload for message types that carry one
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_edp_send_replay_cmd(struct dc_link *link,
+ enum replay_FW_Message_type msg,
+ union dmub_replay_cmd_set *cmd_data);
+
+/*
+ * Set panel replay coasting vtotal.
+ *
+ * @link: link to set the coasting vtotal on
+ * @coasting_vtotal: coasting vtotal to program
+ * @frame_skip_number: number of frames to skip
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_edp_set_coasting_vtotal(struct dc_link *link,
+ uint32_t coasting_vtotal, uint16_t frame_skip_number);
+
+/*
+ * Measure cumulative Panel Replay residency for the given link.
+ *
+ * @link: pointer to the dc_link struct instance
+ * @residency_milli_pct: residency in milli-percentage
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_edp_replay_get_cumulative_residency(const struct dc_link *link,
+ uint32_t *residency_milli_pct);
+
+/*
+ * Set panel replay power optimization and coasting vtotal together.
+ *
+ * @link: link to configure
+ * @power_opts: power optimization bits to enable
+ * @coasting_vtotal: coasting vtotal to program
+ * @frame_skip_number: number of frames to skip
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_edp_set_replay_power_opt_and_coasting_vtotal(
+ struct dc_link *link, const unsigned int *power_opts,
+ uint32_t coasting_vtotal, uint16_t frame_skip_number);
+
+/*
+ * Set up the link for panel replay.
+ *
+ * @link: link to configure
+ * @stream: stream to enable panel replay for
+ *
+ * return: true if successful, false otherwise
+ */
+bool dc_link_dp_setup_replay(struct dc_link *link,
+ const struct dc_stream_state *stream);
+
+/*
+ * Get the instance id of the DDC aux service backing the link.
+ */
+uint8_t dc_link_get_ddc_aux_inst(const struct dc_link *link);
+
+/*
+ * Get the DP link encoding format of the link's verified link settings.
+ */
+enum dp_link_encoding dc_link_dp_get_encoding_format(
+ const struct dc_link *link);
+
/*
* Get Panel Replay state:
*
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 03/19] drm/amd/display: Take struct dc in public DSC compute helpers
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
dc_dsc_compute_bandwidth_range() and dc_dsc_compute_config() took a
display_stream_compressor pointer that every caller fetched with
dc->res_pool->dscs[0]. The implementations immediately derive the dc
from dsc->ctx->dc anyway, so take struct dc directly and let DC pick
the DSC engine internally.
This removes all res_pool->dscs[0] dereferences from amdgpu_dm and is
a step towards not exposing struct dc outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c | 12 ++++++------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 14 +++++++-------
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 4 ++--
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 17 +++++++++++++++--
4 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index dee06fefdd1d..d334391bcbae 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -1229,7 +1229,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
if (edp_max_bpp_x16 < edp_min_bpp_x16)
edp_min_bpp_x16 = edp_max_bpp_x16;
- if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
+ if (dc_dsc_compute_bandwidth_range(dc,
dc->debug.dsc_min_slice_height_override,
edp_min_bpp_x16, edp_max_bpp_x16,
dsc_caps,
@@ -1238,7 +1238,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
&bw_range)) {
if (bw_range.max_kbps < link_bw_in_kbps) {
- if (dc_dsc_compute_config(dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
0,
@@ -1253,7 +1253,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
}
}
- if (dc_dsc_compute_config(dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
link_bw_in_kbps,
@@ -1309,7 +1309,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
} else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
- if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
link_bandwidth_kbps,
@@ -1339,7 +1339,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
max_supported_bw_in_kbps > 0 &&
dsc_max_supported_bw_in_kbps > 0)
- if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
dsc_max_supported_bw_in_kbps,
@@ -1368,7 +1368,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
if ((timing_bw_in_kbps > link_bandwidth_kbps && dsc_sink_bw_in_kbps > 0) ||
(dsc_policy.enable_dsc_when_not_needed || dsc_options.force_dsc_when_not_needed)) {
- if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
dsc_sink_bw_in_kbps,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 5697645ef7cc..a3877ef767ec 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -980,7 +980,7 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p
memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
- params[i].sink->ctx->dc->res_pool->dscs[0],
+ params[i].sink->ctx->dc,
¶ms[i].sink->dsc_caps.dsc_dec_caps,
&dsc_options,
0,
@@ -1033,7 +1033,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
dc_dsc_compute_config(
- param.sink->ctx->dc->res_pool->dscs[0],
+ param.sink->ctx->dc,
¶m.sink->dsc_caps.dsc_dec_caps,
&dsc_options,
(int) kbps, param.timing,
@@ -1278,7 +1278,7 @@ static void build_frl_mst_dsc_params(struct amdgpu_dm_connector *aconnector,
stream->sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16;
if (dc_dsc_compute_config(
- stream->sink->ctx->dc->res_pool->dscs[0],
+ stream->sink->ctx->dc,
&stream->sink->dsc_caps.dsc_dec_caps,
&dsc_options,
frl_conv_dsc_bw_in_kbps,
@@ -1398,7 +1398,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state,
stream->sink->dsc_caps.dsc_dec_caps.is_frl)
build_frl_mst_dsc_params(aconnector, stream, &dsc_policy, ¶ms[count], frl_conv_dsc_bw_in_kbps);
if (!dc_dsc_compute_bandwidth_range(
- stream->sink->ctx->dc->res_pool->dscs[0],
+ stream->sink->ctx->dc,
stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
min_target_bpp_x16,
max_target_bpp_x16,
@@ -1651,7 +1651,7 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
for (i = 0; i < dc_state->stream_count; i++) {
stream = dc_state->streams[i];
- res_pool = stream->ctx->dc->res_pool;
+ res_pool = dc_get_res_pool(stream->ctx->dc);
if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
continue;
@@ -1943,7 +1943,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
bool is_dsc_possible;
dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
- is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
+ is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc,
stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
dsc_policy.min_target_bpp * 16,
dsc_policy.max_target_bpp * 16,
@@ -2108,7 +2108,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
/*Confirm if we can obtain dsc config*/
dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);
dsc_options.max_target_bpp_limit_override_x16 = aconnector->base.display_info.max_dsc_bpp * 16;
- if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(stream->sink->ctx->dc,
&stream->sink->dsc_caps.dsc_dec_caps,
&dsc_options,
end_to_end_bw_in_kbps,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index de169ed3b3b7..7e1a5cd6d2aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -77,7 +77,7 @@ bool dc_dsc_parse_dsc_edid(const struct dc *dc,
struct dsc_dec_dpcd_caps *dsc_sink_caps);
bool dc_dsc_compute_bandwidth_range(
- const struct display_stream_compressor *dsc,
+ const struct dc *dc,
uint32_t dsc_min_slice_height_override,
uint32_t min_bpp_x16,
uint32_t max_bpp_x16,
@@ -87,7 +87,7 @@ bool dc_dsc_compute_bandwidth_range(
struct dc_dsc_bw_range *range);
bool dc_dsc_compute_config(
- const struct display_stream_compressor *dsc,
+ const struct dc *dc,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dc_dsc_config_options *options,
uint32_t target_bandwidth_kbps,
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 45ef1f745c7d..56db43d1b072 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -924,7 +924,7 @@ bool dc_dsc_parse_dsc_edid(const struct dc *dc, const struct dc_edid_caps *edid_
* If DSC is not possible, leave '*range' untouched.
*/
bool dc_dsc_compute_bandwidth_range(
- const struct display_stream_compressor *dsc,
+ const struct dc *dc,
uint32_t dsc_min_slice_height_override,
uint32_t min_bpp_x16,
uint32_t max_bpp_x16,
@@ -939,6 +939,12 @@ bool dc_dsc_compute_bandwidth_range(
struct dsc_enc_caps dsc_common_caps;
struct dc_dsc_config config = {0};
struct dc_dsc_config_options options = {0};
+ const struct display_stream_compressor *dsc;
+
+ if (!dc || !dc->res_pool)
+ return false;
+
+ dsc = dc->res_pool->dscs[0];
options.dsc_min_slice_height_override = dsc_min_slice_height_override;
options.max_target_bpp_limit_override_x16 = max_bpp_x16;
@@ -2020,7 +2026,7 @@ static bool setup_dsc_config(
}
bool dc_dsc_compute_config(
- const struct display_stream_compressor *dsc,
+ const struct dc *dc,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dc_dsc_config_options *options,
uint32_t target_bandwidth_kbps,
@@ -2031,6 +2037,13 @@ bool dc_dsc_compute_config(
bool is_dsc_possible = false;
struct dsc_enc_caps dsc_enc_caps;
unsigned int min_dsc_slice_count;
+ const struct display_stream_compressor *dsc;
+
+ if (!dc || !dc->res_pool)
+ return false;
+
+ dsc = dc->res_pool->dscs[0];
+
get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);
min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 03/19] drm/amd/display: Take struct dc in public DSC compute helpers
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
dc_dsc_compute_bandwidth_range() and dc_dsc_compute_config() took a
display_stream_compressor pointer that every caller fetched with
dc->res_pool->dscs[0]. The implementations immediately derive the dc
from dsc->ctx->dc anyway, so take struct dc directly and let DC pick
the DSC engine internally.
This removes all res_pool->dscs[0] dereferences from amdgpu_dm and is
a step towards not exposing struct dc outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c | 12 ++++++------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 14 +++++++-------
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 4 ++--
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 17 +++++++++++++++--
4 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index dee06fefdd1d..d334391bcbae 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -1229,7 +1229,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
if (edp_max_bpp_x16 < edp_min_bpp_x16)
edp_min_bpp_x16 = edp_max_bpp_x16;
- if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
+ if (dc_dsc_compute_bandwidth_range(dc,
dc->debug.dsc_min_slice_height_override,
edp_min_bpp_x16, edp_max_bpp_x16,
dsc_caps,
@@ -1238,7 +1238,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
&bw_range)) {
if (bw_range.max_kbps < link_bw_in_kbps) {
- if (dc_dsc_compute_config(dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
0,
@@ -1253,7 +1253,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
}
}
- if (dc_dsc_compute_config(dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
link_bw_in_kbps,
@@ -1309,7 +1309,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
} else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
- if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
link_bandwidth_kbps,
@@ -1339,7 +1339,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
max_supported_bw_in_kbps > 0 &&
dsc_max_supported_bw_in_kbps > 0)
- if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
dsc_max_supported_bw_in_kbps,
@@ -1368,7 +1368,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
if ((timing_bw_in_kbps > link_bandwidth_kbps && dsc_sink_bw_in_kbps > 0) ||
(dsc_policy.enable_dsc_when_not_needed || dsc_options.force_dsc_when_not_needed)) {
- if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(dc,
dsc_caps,
&dsc_options,
dsc_sink_bw_in_kbps,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 5697645ef7cc..a3877ef767ec 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -980,7 +980,7 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p
memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
- params[i].sink->ctx->dc->res_pool->dscs[0],
+ params[i].sink->ctx->dc,
¶ms[i].sink->dsc_caps.dsc_dec_caps,
&dsc_options,
0,
@@ -1033,7 +1033,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
dc_dsc_compute_config(
- param.sink->ctx->dc->res_pool->dscs[0],
+ param.sink->ctx->dc,
¶m.sink->dsc_caps.dsc_dec_caps,
&dsc_options,
(int) kbps, param.timing,
@@ -1278,7 +1278,7 @@ static void build_frl_mst_dsc_params(struct amdgpu_dm_connector *aconnector,
stream->sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16;
if (dc_dsc_compute_config(
- stream->sink->ctx->dc->res_pool->dscs[0],
+ stream->sink->ctx->dc,
&stream->sink->dsc_caps.dsc_dec_caps,
&dsc_options,
frl_conv_dsc_bw_in_kbps,
@@ -1398,7 +1398,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state,
stream->sink->dsc_caps.dsc_dec_caps.is_frl)
build_frl_mst_dsc_params(aconnector, stream, &dsc_policy, ¶ms[count], frl_conv_dsc_bw_in_kbps);
if (!dc_dsc_compute_bandwidth_range(
- stream->sink->ctx->dc->res_pool->dscs[0],
+ stream->sink->ctx->dc,
stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
min_target_bpp_x16,
max_target_bpp_x16,
@@ -1651,7 +1651,7 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
for (i = 0; i < dc_state->stream_count; i++) {
stream = dc_state->streams[i];
- res_pool = stream->ctx->dc->res_pool;
+ res_pool = dc_get_res_pool(stream->ctx->dc);
if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
continue;
@@ -1943,7 +1943,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
bool is_dsc_possible;
dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
- is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
+ is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc,
stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
dsc_policy.min_target_bpp * 16,
dsc_policy.max_target_bpp * 16,
@@ -2108,7 +2108,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
/*Confirm if we can obtain dsc config*/
dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);
dsc_options.max_target_bpp_limit_override_x16 = aconnector->base.display_info.max_dsc_bpp * 16;
- if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],
+ if (dc_dsc_compute_config(stream->sink->ctx->dc,
&stream->sink->dsc_caps.dsc_dec_caps,
&dsc_options,
end_to_end_bw_in_kbps,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index de169ed3b3b7..7e1a5cd6d2aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -77,7 +77,7 @@ bool dc_dsc_parse_dsc_edid(const struct dc *dc,
struct dsc_dec_dpcd_caps *dsc_sink_caps);
bool dc_dsc_compute_bandwidth_range(
- const struct display_stream_compressor *dsc,
+ const struct dc *dc,
uint32_t dsc_min_slice_height_override,
uint32_t min_bpp_x16,
uint32_t max_bpp_x16,
@@ -87,7 +87,7 @@ bool dc_dsc_compute_bandwidth_range(
struct dc_dsc_bw_range *range);
bool dc_dsc_compute_config(
- const struct display_stream_compressor *dsc,
+ const struct dc *dc,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dc_dsc_config_options *options,
uint32_t target_bandwidth_kbps,
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 45ef1f745c7d..56db43d1b072 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -924,7 +924,7 @@ bool dc_dsc_parse_dsc_edid(const struct dc *dc, const struct dc_edid_caps *edid_
* If DSC is not possible, leave '*range' untouched.
*/
bool dc_dsc_compute_bandwidth_range(
- const struct display_stream_compressor *dsc,
+ const struct dc *dc,
uint32_t dsc_min_slice_height_override,
uint32_t min_bpp_x16,
uint32_t max_bpp_x16,
@@ -939,6 +939,12 @@ bool dc_dsc_compute_bandwidth_range(
struct dsc_enc_caps dsc_common_caps;
struct dc_dsc_config config = {0};
struct dc_dsc_config_options options = {0};
+ const struct display_stream_compressor *dsc;
+
+ if (!dc || !dc->res_pool)
+ return false;
+
+ dsc = dc->res_pool->dscs[0];
options.dsc_min_slice_height_override = dsc_min_slice_height_override;
options.max_target_bpp_limit_override_x16 = max_bpp_x16;
@@ -2020,7 +2026,7 @@ static bool setup_dsc_config(
}
bool dc_dsc_compute_config(
- const struct display_stream_compressor *dsc,
+ const struct dc *dc,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dc_dsc_config_options *options,
uint32_t target_bandwidth_kbps,
@@ -2031,6 +2037,13 @@ bool dc_dsc_compute_config(
bool is_dsc_possible = false;
struct dsc_enc_caps dsc_enc_caps;
unsigned int min_dsc_slice_count;
+ const struct display_stream_compressor *dsc;
+
+ if (!dc || !dc->res_pool)
+ return false;
+
+ dsc = dc->res_pool->dscs[0];
+
get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);
min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 04/19] drm/amd/display/amdgpu_dm: Use DC accessors in audio/color/backlight paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_audio.c, amdgpu_dm_color.c, amdgpu_dm_colorop.c
and amdgpu_dm_backlight.c.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c | 6 +++--
.../amd/display/amdgpu_dm/amdgpu_dm_backlight.c | 6 ++---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 28 +++++++++++++---------
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.h | 4 ++--
.../drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 4 ++--
.../drm/amd/display/modules/color/color_gamma.c | 2 +-
.../drm/amd/display/modules/color/color_gamma.h | 2 +-
7 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
index 199f339839b2..97cc52f45a2e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
@@ -140,6 +140,7 @@ EXPORT_IF_KUNIT(amdgpu_dm_audio_init_pins);
int amdgpu_dm_audio_init(struct amdgpu_device *adev)
{
unsigned int inst_array[MAX_AUDIOS];
+ struct resource_pool *res_pool;
int audio_count;
int i, ret;
@@ -148,9 +149,10 @@ int amdgpu_dm_audio_init(struct amdgpu_device *adev)
adev->mode_info.audio.enabled = true;
- audio_count = adev->dm.dc->res_pool->audio_count;
+ res_pool = dc_get_res_pool(adev->dm.dc);
+ audio_count = res_pool->audio_count;
for (i = 0; i < audio_count; i++)
- inst_array[i] = adev->dm.dc->res_pool->audios[i]->inst;
+ inst_array[i] = res_pool->audios[i]->inst;
amdgpu_dm_audio_init_pins(adev, audio_count, inst_array);
ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
index cb74b00723fd..3d268703c551 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
@@ -296,7 +296,7 @@ struct dc_stream_state *dm_find_stream_with_link(
struct amdgpu_display_manager *dm,
struct dc_link *link)
{
- struct dc_state *cur_dc_state = dm->dc->current_state;
+ struct dc_state *cur_dc_state = dc_get_current_state(dm->dc);
struct dc_stream_state *stream = NULL;
int i;
@@ -383,7 +383,7 @@ void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
}
mutex_lock(&dm->dc_lock);
- if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
+ if (dc_get_caps(dm->dc)->ips_support && dc_get_ctx(dm->dc)->dmub_srv->idle_allowed) {
dc_allow_idle_optimizations(dm->dc, false);
reallow_idle = true;
}
@@ -415,7 +415,7 @@ void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
amdgpu_dm_replay_set_event(dm, stream, true,
replay_event_hw_programming, true);
- if (dm->dc->caps.ips_support && reallow_idle)
+ if (dc_get_caps(dm->dc)->ips_support && reallow_idle)
dc_allow_idle_optimizations(dm->dc, true);
mutex_unlock(&dm->dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index f9dc9f46a446..d86b9611568b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -832,7 +832,7 @@ EXPORT_IF_KUNIT(amdgpu_dm_set_atomic_regamma);
* Returns:
* 0 in case of success. -ENOMEM if fails.
*/
-STATIC_IFN_KUNIT int __set_input_tf(struct dc_color_caps *caps,
+STATIC_IFN_KUNIT int __set_input_tf(const struct dc_color_caps *caps,
struct dc_transfer_func *func,
const struct drm_color_lut *lut, uint32_t lut_size)
{
@@ -870,7 +870,7 @@ EXPORT_IF_KUNIT(__set_input_tf);
* Returns:
* 0 in case of success. -ENOMEM if fails.
*/
-STATIC_IFN_KUNIT int __set_input_tf_32(struct dc_color_caps *caps,
+STATIC_IFN_KUNIT int __set_input_tf_32(const struct dc_color_caps *caps,
struct dc_transfer_func *func,
const struct drm_color_lut32 *lut, uint32_t lut_size)
{
@@ -1168,7 +1168,9 @@ int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
const struct drm_color_lut *shaper = NULL, *lut3d = NULL;
uint32_t exp_size, size, dim_size = MAX_COLOR_3DLUT_SIZE;
- bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
+ const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
+ bool has_3dlut =
+ caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
/* shaper LUT is only available if 3D LUT color caps */
exp_size = has_3dlut ? MAX_COLOR_LUT_ENTRIES : 0;
@@ -1403,7 +1405,7 @@ EXPORT_IF_KUNIT(amdgpu_dm_update_crtc_color_mgmt);
static int
map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
struct dc_plane_state *dc_plane_state,
- struct dc_color_caps *caps)
+ const struct dc_color_caps *caps)
{
const struct drm_color_lut *degamma_lut;
enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
@@ -1483,7 +1485,7 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
static int
__set_dm_plane_degamma(struct drm_plane_state *plane_state,
struct dc_plane_state *dc_plane_state,
- struct dc_color_caps *color_caps)
+ const struct dc_color_caps *color_caps)
{
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
const struct drm_color_lut *degamma_lut;
@@ -1551,7 +1553,7 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state,
struct dc_transfer_func *tf = &dc_plane_state->in_transfer_func;
struct drm_colorop *colorop = colorop_state->colorop;
struct drm_device *drm = colorop->dev;
- struct dc_color_caps *color_caps = NULL;
+ const struct dc_color_caps *color_caps = NULL;
bool is_subsampled_format;
if (colorop->type != DRM_COLOROP_1D_CURVE)
@@ -1575,7 +1577,7 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state,
tf->tf = amdgpu_colorop_tf_to_dc_tf(colorop_state->curve_1d_type);
if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
- color_caps = &dc_plane_state->ctx->dc->caps.color;
+ color_caps = &dc_get_caps(dc_plane_state->ctx->dc)->color;
if (!mod_color_calculate_degamma_params(color_caps, tf, NULL,
is_subsampled_format)) {
@@ -1865,7 +1867,9 @@ __set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state,
struct dc_transfer_func *tf = &dc_plane_state->cm.shaper_func;
struct drm_atomic_commit *state = plane_state->state;
const struct amdgpu_device *adev = drm_to_adev(colorop->dev);
- bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
+ const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
+ bool has_3dlut =
+ caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
const struct drm_device *dev = colorop->dev;
const struct drm_color_lut32 *lut3d;
uint32_t lut3d_size;
@@ -2044,7 +2048,9 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,
struct drm_colorop *colorop = plane_state->color_pipeline;
struct drm_device *dev = plane_state->plane->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
+ const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
+ bool has_3dlut =
+ caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
int ret;
/* Fixed Matrix (YUV to RGB) */
@@ -2156,7 +2162,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
struct amdgpu_device *adev = drm_to_adev(crtc->base.state->dev);
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
struct drm_color_ctm_3x4 *ctm = NULL;
- struct dc_color_caps *color_caps = NULL;
+ const struct dc_color_caps *color_caps = NULL;
bool has_crtc_cm_degamma;
int ret;
@@ -2167,7 +2173,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
}
if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
- color_caps = &dc_plane_state->ctx->dc->caps.color;
+ color_caps = &dc_get_caps(dc_plane_state->ctx->dc)->color;
/* Initially, we can just bypass the DGM block. */
dc_plane_state->in_transfer_func.type = TF_TYPE_BYPASS;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.h
index 3e8a3d3fc855..4bda8c47ae09 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.h
@@ -74,9 +74,9 @@ int __set_output_tf_32(struct dc_transfer_func *func,
const struct drm_color_lut32 *lut, uint32_t lut_size,
bool has_rom);
struct dc_color_caps;
-int __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_func *func,
+int __set_input_tf(const struct dc_color_caps *caps, struct dc_transfer_func *func,
const struct drm_color_lut *lut, uint32_t lut_size);
-int __set_input_tf_32(struct dc_color_caps *caps, struct dc_transfer_func *func,
+int __set_input_tf_32(const struct dc_color_caps *caps, struct dc_transfer_func *func,
const struct drm_color_lut32 *lut, uint32_t lut_size);
enum dc_transfer_func_predefined
amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
index c6bb9fec9217..e912256eebb3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
@@ -299,8 +299,8 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr
{
struct drm_device *dev = plane->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- bool hw_3d_lut = adev->dm.dc->caps.color.dpp.hw_3d_lut ||
- adev->dm.dc->caps.color.mpc.preblend;
+ bool hw_3d_lut = dc_get_caps(adev->dm.dc)->color.dpp.hw_3d_lut ||
+ dc_get_caps(adev->dm.dc)->color.mpc.preblend;
return amdgpu_dm_build_default_pipeline(dev, plane, hw_3d_lut, list);
}
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 5786ef5787ac..f654003e3191 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1669,7 +1669,7 @@ static bool map_regamma_hw_to_x_user(
#define _EXTRA_POINTS 3
-bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
+bool mod_color_calculate_degamma_params(const struct dc_color_caps *dc_caps,
struct dc_transfer_func *input_tf,
const struct dc_gamma *ramp, bool map_user_ramp)
{
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
index 97e55278940e..8b7bc41c87df 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
@@ -111,7 +111,7 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
const struct hdr_tm_params *fs_params,
struct calculate_buffer *cal_buffer);
-bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
+bool mod_color_calculate_degamma_params(const struct dc_color_caps *dc_caps,
struct dc_transfer_func *output_tf,
const struct dc_gamma *ramp, bool mapUserRamp);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 04/19] drm/amd/display/amdgpu_dm: Use DC accessors in audio/color/backlight paths
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_audio.c, amdgpu_dm_color.c, amdgpu_dm_colorop.c
and amdgpu_dm_backlight.c.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c | 6 +++--
.../amd/display/amdgpu_dm/amdgpu_dm_backlight.c | 6 ++---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 28 +++++++++++++---------
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.h | 4 ++--
.../drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 4 ++--
.../drm/amd/display/modules/color/color_gamma.c | 2 +-
.../drm/amd/display/modules/color/color_gamma.h | 2 +-
7 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
index 199f339839b2..97cc52f45a2e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
@@ -140,6 +140,7 @@ EXPORT_IF_KUNIT(amdgpu_dm_audio_init_pins);
int amdgpu_dm_audio_init(struct amdgpu_device *adev)
{
unsigned int inst_array[MAX_AUDIOS];
+ struct resource_pool *res_pool;
int audio_count;
int i, ret;
@@ -148,9 +149,10 @@ int amdgpu_dm_audio_init(struct amdgpu_device *adev)
adev->mode_info.audio.enabled = true;
- audio_count = adev->dm.dc->res_pool->audio_count;
+ res_pool = dc_get_res_pool(adev->dm.dc);
+ audio_count = res_pool->audio_count;
for (i = 0; i < audio_count; i++)
- inst_array[i] = adev->dm.dc->res_pool->audios[i]->inst;
+ inst_array[i] = res_pool->audios[i]->inst;
amdgpu_dm_audio_init_pins(adev, audio_count, inst_array);
ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
index cb74b00723fd..3d268703c551 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
@@ -296,7 +296,7 @@ struct dc_stream_state *dm_find_stream_with_link(
struct amdgpu_display_manager *dm,
struct dc_link *link)
{
- struct dc_state *cur_dc_state = dm->dc->current_state;
+ struct dc_state *cur_dc_state = dc_get_current_state(dm->dc);
struct dc_stream_state *stream = NULL;
int i;
@@ -383,7 +383,7 @@ void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
}
mutex_lock(&dm->dc_lock);
- if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
+ if (dc_get_caps(dm->dc)->ips_support && dc_get_ctx(dm->dc)->dmub_srv->idle_allowed) {
dc_allow_idle_optimizations(dm->dc, false);
reallow_idle = true;
}
@@ -415,7 +415,7 @@ void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
amdgpu_dm_replay_set_event(dm, stream, true,
replay_event_hw_programming, true);
- if (dm->dc->caps.ips_support && reallow_idle)
+ if (dc_get_caps(dm->dc)->ips_support && reallow_idle)
dc_allow_idle_optimizations(dm->dc, true);
mutex_unlock(&dm->dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index f9dc9f46a446..d86b9611568b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -832,7 +832,7 @@ EXPORT_IF_KUNIT(amdgpu_dm_set_atomic_regamma);
* Returns:
* 0 in case of success. -ENOMEM if fails.
*/
-STATIC_IFN_KUNIT int __set_input_tf(struct dc_color_caps *caps,
+STATIC_IFN_KUNIT int __set_input_tf(const struct dc_color_caps *caps,
struct dc_transfer_func *func,
const struct drm_color_lut *lut, uint32_t lut_size)
{
@@ -870,7 +870,7 @@ EXPORT_IF_KUNIT(__set_input_tf);
* Returns:
* 0 in case of success. -ENOMEM if fails.
*/
-STATIC_IFN_KUNIT int __set_input_tf_32(struct dc_color_caps *caps,
+STATIC_IFN_KUNIT int __set_input_tf_32(const struct dc_color_caps *caps,
struct dc_transfer_func *func,
const struct drm_color_lut32 *lut, uint32_t lut_size)
{
@@ -1168,7 +1168,9 @@ int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
const struct drm_color_lut *shaper = NULL, *lut3d = NULL;
uint32_t exp_size, size, dim_size = MAX_COLOR_3DLUT_SIZE;
- bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
+ const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
+ bool has_3dlut =
+ caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
/* shaper LUT is only available if 3D LUT color caps */
exp_size = has_3dlut ? MAX_COLOR_LUT_ENTRIES : 0;
@@ -1403,7 +1405,7 @@ EXPORT_IF_KUNIT(amdgpu_dm_update_crtc_color_mgmt);
static int
map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
struct dc_plane_state *dc_plane_state,
- struct dc_color_caps *caps)
+ const struct dc_color_caps *caps)
{
const struct drm_color_lut *degamma_lut;
enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
@@ -1483,7 +1485,7 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
static int
__set_dm_plane_degamma(struct drm_plane_state *plane_state,
struct dc_plane_state *dc_plane_state,
- struct dc_color_caps *color_caps)
+ const struct dc_color_caps *color_caps)
{
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
const struct drm_color_lut *degamma_lut;
@@ -1551,7 +1553,7 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state,
struct dc_transfer_func *tf = &dc_plane_state->in_transfer_func;
struct drm_colorop *colorop = colorop_state->colorop;
struct drm_device *drm = colorop->dev;
- struct dc_color_caps *color_caps = NULL;
+ const struct dc_color_caps *color_caps = NULL;
bool is_subsampled_format;
if (colorop->type != DRM_COLOROP_1D_CURVE)
@@ -1575,7 +1577,7 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state,
tf->tf = amdgpu_colorop_tf_to_dc_tf(colorop_state->curve_1d_type);
if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
- color_caps = &dc_plane_state->ctx->dc->caps.color;
+ color_caps = &dc_get_caps(dc_plane_state->ctx->dc)->color;
if (!mod_color_calculate_degamma_params(color_caps, tf, NULL,
is_subsampled_format)) {
@@ -1865,7 +1867,9 @@ __set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state,
struct dc_transfer_func *tf = &dc_plane_state->cm.shaper_func;
struct drm_atomic_commit *state = plane_state->state;
const struct amdgpu_device *adev = drm_to_adev(colorop->dev);
- bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
+ const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
+ bool has_3dlut =
+ caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
const struct drm_device *dev = colorop->dev;
const struct drm_color_lut32 *lut3d;
uint32_t lut3d_size;
@@ -2044,7 +2048,9 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,
struct drm_colorop *colorop = plane_state->color_pipeline;
struct drm_device *dev = plane_state->plane->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
+ const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
+ bool has_3dlut =
+ caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
int ret;
/* Fixed Matrix (YUV to RGB) */
@@ -2156,7 +2162,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
struct amdgpu_device *adev = drm_to_adev(crtc->base.state->dev);
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
struct drm_color_ctm_3x4 *ctm = NULL;
- struct dc_color_caps *color_caps = NULL;
+ const struct dc_color_caps *color_caps = NULL;
bool has_crtc_cm_degamma;
int ret;
@@ -2167,7 +2173,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
}
if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
- color_caps = &dc_plane_state->ctx->dc->caps.color;
+ color_caps = &dc_get_caps(dc_plane_state->ctx->dc)->color;
/* Initially, we can just bypass the DGM block. */
dc_plane_state->in_transfer_func.type = TF_TYPE_BYPASS;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.h
index 3e8a3d3fc855..4bda8c47ae09 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.h
@@ -74,9 +74,9 @@ int __set_output_tf_32(struct dc_transfer_func *func,
const struct drm_color_lut32 *lut, uint32_t lut_size,
bool has_rom);
struct dc_color_caps;
-int __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_func *func,
+int __set_input_tf(const struct dc_color_caps *caps, struct dc_transfer_func *func,
const struct drm_color_lut *lut, uint32_t lut_size);
-int __set_input_tf_32(struct dc_color_caps *caps, struct dc_transfer_func *func,
+int __set_input_tf_32(const struct dc_color_caps *caps, struct dc_transfer_func *func,
const struct drm_color_lut32 *lut, uint32_t lut_size);
enum dc_transfer_func_predefined
amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
index c6bb9fec9217..e912256eebb3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
@@ -299,8 +299,8 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr
{
struct drm_device *dev = plane->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- bool hw_3d_lut = adev->dm.dc->caps.color.dpp.hw_3d_lut ||
- adev->dm.dc->caps.color.mpc.preblend;
+ bool hw_3d_lut = dc_get_caps(adev->dm.dc)->color.dpp.hw_3d_lut ||
+ dc_get_caps(adev->dm.dc)->color.mpc.preblend;
return amdgpu_dm_build_default_pipeline(dev, plane, hw_3d_lut, list);
}
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 5786ef5787ac..f654003e3191 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1669,7 +1669,7 @@ static bool map_regamma_hw_to_x_user(
#define _EXTRA_POINTS 3
-bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
+bool mod_color_calculate_degamma_params(const struct dc_color_caps *dc_caps,
struct dc_transfer_func *input_tf,
const struct dc_gamma *ramp, bool map_user_ramp)
{
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
index 97e55278940e..8b7bc41c87df 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
@@ -111,7 +111,7 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
const struct hdr_tm_params *fs_params,
struct calculate_buffer *cal_buffer);
-bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
+bool mod_color_calculate_degamma_params(const struct dc_color_caps *dc_caps,
struct dc_transfer_func *output_tf,
const struct dc_gamma *ramp, bool mapUserRamp);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 04/19] drm/amd/display/amdgpu_dm: Use DC accessors in audio/color/backlight paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 1:50 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 1:50 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found no new issues
in this patch, but noticed 2 related pre-existing issues it does not
introduce:
- [Critical] drm/amd/display: race and invalid downcast in
amdgpu_dm_backlight_set_level() [1]
- [Medium] drm/amd/display: swallowed error in
amdgpu_dm_update_plane_color_mgmt() [2]
--
commit c710d624f30d7a2d26cb80389657ac035d1c1f5e
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display/amdgpu_dm: Use DC accessors in audio/color/backlight paths
This commit replaces direct struct dc member accesses with DC accessor
calls in the audio, backlight, and color management paths.
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
> index cb74b00723fda..3d268703c5514 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
> @@ -296,7 +296,7 @@ struct dc_stream_state *dm_find_stream_with_link(
> struct amdgpu_display_manager *dm,
> struct dc_link *link)
> {
> - struct dc_state *cur_dc_state = dm->dc->current_state;
> + struct dc_state *cur_dc_state = dc_get_current_state(dm->dc);
> struct dc_stream_state *stream = NULL;
> int i;
>
> @@ -383,7 +383,7 @@ void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
> }
>
> mutex_lock(&dm->dc_lock);
> - if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
> + if (dc_get_caps(dm->dc)->ips_support && dc_get_ctx(dm->dc)->dmub_srv->idle_allowed) {
> dc_allow_idle_optimizations(dm->dc, false);
> reallow_idle = true;
> }
[Severity: Critical]
This problem wasn't introduced by this patch, but can
amdgpu_dm_backlight_set_level() race with a concurrent atomic commit and
use cur_dc_state or stream after it has been freed [1]?
amdgpu_dm_backlight_set_level() calls dm_find_stream_with_link() before
acquiring dm->dc_lock:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c:amdgpu_dm_backlight_set_level() {
...
list_for_each_entry(connector, &dm->ddev->mode_config.connector_list, head) {
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
...
}
...
link = (struct dc_link *)dm->backlight_link[bl_idx];
stream = dm_find_stream_with_link(dm, link);
if (!stream)
return;
...
mutex_lock(&dm->dc_lock);
}
A concurrent commit can replace current_state and release the old state
and its streams while dm_find_stream_with_link() is walking it or before
dm->dc_lock is taken:
CPU0 CPU1
amdgpu_dm_backlight_set_level()
dm_find_stream_with_link()
cur_dc_state =
dc_get_current_state(dm->dc)
stream = cur_dc_state->streams[i]
amdgpu_dm_commit_streams()
mutex_lock(&dm->dc_lock)
dc_commit_streams()
/* replaces current_state,
releases old state/streams */
mutex_unlock(&dm->dc_lock)
mutex_lock(&dm->dc_lock)
mod_power_set_backlight_nits(...,
stream, ...) <-- use-after-free
In addition, the loop at the start of amdgpu_dm_backlight_set_level()
walks mode_config.connector_list with list_for_each_entry() instead of
drm_connector_list_iter_begin()/end(), which can race with DP MST
connector removal, and unconditionally calls to_amdgpu_dm_connector() on
every entry, which causes type confusion on DRM_MODE_CONNECTOR_WRITEBACK
connectors (allocated as struct amdgpu_dm_wb_connector).
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> index f9dc9f46a4460..d86b9611568b8 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
[ ... ]
> @@ -2156,7 +2162,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
> struct amdgpu_device *adev = drm_to_adev(crtc->base.state->dev);
> struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
> struct drm_color_ctm_3x4 *ctm = NULL;
> - struct dc_color_caps *color_caps = NULL;
> + const struct dc_color_caps *color_caps = NULL;
> bool has_crtc_cm_degamma;
> int ret;
>
> @@ -2167,7 +2173,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
> }
>
> if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
> - color_caps = &dc_plane_state->ctx->dc->caps.color;
> + color_caps = &dc_get_caps(dc_plane_state->ctx->dc)->color;
>
> /* Initially, we can just bypass the DGM block. */
> dc_plane_state->in_transfer_func.type = TF_TYPE_BYPASS;
[Severity: Medium]
This problem wasn't introduced by this patch, but does
amdgpu_dm_update_plane_color_mgmt() swallow errors from
amdgpu_dm_plane_set_colorop_properties() [2]?
At the end of amdgpu_dm_update_plane_color_mgmt():
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c:amdgpu_dm_update_plane_color_mgmt() {
...
if (!amdgpu_dm_plane_set_colorop_properties(plane_state, dc_plane_state))
return 0;
return amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state);
}
When plane_state->color_pipeline is set and
amdgpu_dm_plane_set_colorop_properties() fails with a negative error code
(such as -EINVAL or -ENOMEM), the ! check evaluates to false and execution
falls through to amdgpu_dm_plane_set_color_properties(). Because no legacy
color properties are set on a colorop commit, the fallback bypasses the
color blocks and returns 0, causing the atomic commit to succeed with
plane color management silently disabled.
[1] https://sashiko.dev/#/bug/linux-d25140b3-5901-4689-81c3-c3890f66e5a2
[2] https://sashiko.dev/#/bug/linux-2356891c-983c-48f7-a656-56667766fead
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=4
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 05/19] drm/amd/display/amdgpu_dm: Use DC accessors in psr/replay/dmub/hdcp/irq paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_psr.c, amdgpu_dm_replay.c, amdgpu_dm_dmub.c,
amdgpu_dm_hdcp.c and amdgpu_dm_irq.c.
Add dc_get_dce_version() for the frequent ctx->dce_version reads and
split the debug options accessor into a const read view
(dc_get_debug_options) and an interim writable view
(dc_get_debug_options_mutable) for the remaining module parameter and
debugfs write sites.
Also constify the dc_color_caps consumers in the color module so
dc_get_caps() read views can flow through them.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 41 ++++++++++++----------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 39 ++++++++++----------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 22 ++++++------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 10 +++---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c | 10 +++---
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 12 ++++++-
drivers/gpu/drm/amd/display/dc/dc.h | 10 ++++--
7 files changed, 85 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index 0ea8f9a582cc..af2cda9080d9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -179,6 +179,7 @@ dm_get_alt_channel_pstate_switch_aperture(struct amdgpu_device *adev,
G7_PSTATE_APERTURE2_ID,
};
struct mem_reserved_info apertures[ARRAY_SIZE(region_ids)];
+ struct dml2_soc_alt_ch_info alt_ch_cfg = {0};
u64 aperture_mc_bases[ARRAY_SIZE(region_ids)];
u32 i;
int r;
@@ -214,11 +215,13 @@ dm_get_alt_channel_pstate_switch_aperture(struct amdgpu_device *adev,
hw_params->soc_fb_info.alt_channel_region_size[i] =
apertures[i].reserved_region_size;
/* DML consumes the MC base address bits [47:16]. */
- adev->dm.dc->dml2_options.alt_ch_cfg.region_base_addr_47_16[i] =
+ alt_ch_cfg.region_base_addr_47_16[i] =
(u32)(aperture_mc_bases[i] >> 16);
- adev->dm.dc->dml2_options.alt_ch_cfg.region_size_bytes[i] =
+ alt_ch_cfg.region_size_bytes[i] =
(u32)apertures[i].reserved_region_size;
}
+
+ dc_set_dml2_alt_ch_cfg(adev->dm.dc, &alt_ch_cfg);
}
@@ -229,9 +232,10 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
const struct firmware *dmub_fw = adev->dm.dmub_fw;
struct dc *dc = adev->dm.dc;
- struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
- struct abm *abm = adev->dm.dc->res_pool->abm;
- struct dc_context *ctx = adev->dm.dc->ctx;
+ struct resource_pool *res_pool = dc_get_res_pool(dc);
+ struct dmcu *dmcu = res_pool->dmcu;
+ struct abm *abm = res_pool->abm;
+ struct dc_context *ctx = dc_get_ctx(adev->dm.dc);
struct dmub_srv_hw_params hw_params;
enum dmub_status status;
const unsigned char *fw_inst_const, *fw_bss_data;
@@ -335,14 +339,15 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
hw_params.fb_info = fb_info;
/* Enable usb4 dpia in the FW APU */
- if (dc->caps.is_apu &&
- dc->res_pool->usb4_dpia_count != 0 &&
- !dc->debug.dpia_debug.bits.disable_dpia) {
+ if (dc_get_caps(dc)->is_apu &&
+ dc_get_res_pool(dc)->usb4_dpia_count != 0 &&
+ !dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia) {
hw_params.dpia_supported = true;
- hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;
+ hw_params.disable_dpia = dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia;
hw_params.dpia_hpd_int_enable_supported = false;
- hw_params.enable_non_transparent_setconfig = dc->config.consolidated_dpia_dp_lt;
- hw_params.disable_dpia_bw_allocation = !dc->config.usb4_bw_alloc_support;
+ hw_params.enable_non_transparent_setconfig =
+ dc_get_config(dc)->consolidated_dpia_dp_lt;
+ hw_params.disable_dpia_bw_allocation = !dc_get_config(dc)->usb4_bw_alloc_support;
}
switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
@@ -375,9 +380,9 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
}
- if (!adev->dm.dc->ctx->dmub_srv)
- adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
- if (!adev->dm.dc->ctx->dmub_srv) {
+ if (!dc_get_ctx(adev->dm.dc)->dmub_srv)
+ dc_get_ctx(adev->dm.dc)->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
+ if (!dc_get_ctx(adev->dm.dc)->dmub_srv) {
drm_err(adev_to_drm(adev), "Couldn't allocate DC DMUB server!\n");
return -ENOMEM;
}
@@ -401,13 +406,13 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
if (adev->dm.dmcub_fw_version &&
adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59))
- adev->dm.dc->debug.sanity_checks = true;
+ dc_get_debug_options_mutable(adev->dm.dc)->sanity_checks = true;
break;
case IP_VERSION(3, 1, 4):
if (adev->dm.dmcub_fw_version &&
adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16))
- adev->dm.dc->debug.sanity_checks = true;
+ dc_get_debug_options_mutable(adev->dm.dc)->sanity_checks = true;
break;
default:
break;
@@ -565,7 +570,7 @@ STATIC_IFN_KUNIT uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
{
struct amdgpu_device *adev = ctx;
- return dm_read_reg(adev->dm.dc->ctx, address);
+ return dm_read_reg(dc_get_ctx(adev->dm.dc), address);
}
EXPORT_IF_KUNIT(amdgpu_dm_dmub_reg_read);
@@ -574,7 +579,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
{
struct amdgpu_device *adev = ctx;
- return dm_write_reg(adev->dm.dc->ctx, address, value);
+ return dm_write_reg(dc_get_ctx(adev->dm.dc), address, value);
}
EXPORT_IF_KUNIT(amdgpu_dm_dmub_reg_write);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 47cbc826ed45..73b56e078cbe 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -43,7 +43,7 @@ STATIC_IFN_KUNIT bool lp_write_i2c(void *handle, uint32_t address, const uint8_t
struct dc_link *link = handle;
struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };
struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW,
- link->dc->caps.i2c_speed_in_khz};
+ dc_get_caps(link->dc)->i2c_speed_in_khz};
return dm_helpers_submit_i2c(link->ctx, link, &cmd);
}
@@ -56,7 +56,7 @@ STATIC_IFN_KUNIT bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset
struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset},
{false, address, size, data} };
struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW,
- link->dc->caps.i2c_speed_in_khz};
+ dc_get_caps(link->dc)->i2c_speed_in_khz};
return dm_helpers_submit_i2c(link->ctx, link, &cmd);
}
@@ -308,9 +308,9 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
hdcp_w->aconnector[conn_index] = aconnector;
hdcp_get_link_display_adjustments(enable_encryption, content_type,
- dc->caps.fused_io_supported,
- dc->debug.hdcp_lc_force_fw_enable,
- dc->debug.hdcp_lc_enable_sw_fallback,
+ dc_get_caps(dc)->fused_io_supported,
+ dc_get_debug_options(dc)->hdcp_lc_force_fw_enable,
+ dc_get_debug_options(dc)->hdcp_lc_enable_sw_fallback,
&link_adjust, &display_adjust);
hdcp_update_display_encryption_control(hdcp_work, hdcp_w, conn_index,
enable_encryption);
@@ -676,8 +676,11 @@ void update_config(void *handle, struct cp_psp_stream_config *config)
link->adjust.auth_delay = 2;
link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS;
link->adjust.hdcp1.disable = 0;
- link->adjust.hdcp2.use_fw_locality_check = (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable);
- link->adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback;
+ link->adjust.hdcp2.use_fw_locality_check =
+ (dc_get_caps(dc)->fused_io_supported ||
+ dc_get_debug_options(dc)->hdcp_lc_force_fw_enable);
+ link->adjust.hdcp2.use_sw_locality_fallback =
+ dc_get_debug_options(dc)->hdcp_lc_enable_sw_fallback;
hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index,
@@ -839,7 +842,7 @@ static const struct bin_attribute data_attr = {
struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev,
struct cp_psp *cp_psp, struct dc *dc)
{
- int max_caps = dc->caps.max_links;
+ int max_caps = dc_get_caps(dc)->max_links;
struct hdcp_workqueue *hdcp_work;
int i = 0;
@@ -874,16 +877,16 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev,
struct mod_hdcp_ddc_funcs *ddc_funcs = &config->ddc.funcs;
config->psp.handle = &adev->psp;
- if (dc->ctx->dce_version == DCN_VERSION_3_1 ||
- dc->ctx->dce_version == DCN_VERSION_3_14 ||
- dc->ctx->dce_version == DCN_VERSION_3_15 ||
- dc->ctx->dce_version == DCN_VERSION_3_16 ||
- dc->ctx->dce_version == DCN_VERSION_3_2 ||
- dc->ctx->dce_version == DCN_VERSION_3_21 ||
- dc->ctx->dce_version == DCN_VERSION_3_5 ||
- dc->ctx->dce_version == DCN_VERSION_3_51 ||
- dc->ctx->dce_version == DCN_VERSION_3_6 ||
- dc->ctx->dce_version == DCN_VERSION_4_01)
+ if (dc_get_dce_version(dc) == DCN_VERSION_3_1 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_14 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_15 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_16 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_2 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_21 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_5 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_51 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_6 ||
+ dc_get_dce_version(dc) == DCN_VERSION_4_01)
config->psp.caps.dtm_v3_supported = 1;
config->ddc.handle = dc_get_link_at_index(dc, i);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 5b4ff079cd55..a7ee30c66a48 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -808,7 +808,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
st = (state == AMDGPU_IRQ_STATE_ENABLE);
- if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
+ if (dc && dc_get_caps(dc)->ips_support && dc_is_idle_optimizations_allowed(dc))
dc_allow_idle_optimizations(dc, false);
amdgpu_dm_irq_set(adev, irq_source, st);
@@ -989,8 +989,8 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
* has rather than over the whole enum: the unused slots of the DC
* interrupt table hold dummy handlers that assert when touched.
*/
- for (i = 0; i < adev->dm.dc->link_count; i++) {
- const struct dc_link *link = adev->dm.dc->links[i];
+ for (i = 0; i < dc_get_link_count(adev->dm.dc); i++) {
+ const struct dc_link *link = dc_get_link_at_index(adev->dm.dc, i);
if (link->irq_source_hpd != DC_IRQ_SOURCE_INVALID &&
!amdgpu_dm_irq_set(adev, link->irq_source_hpd, false))
@@ -1226,7 +1226,7 @@ EXPORT_IF_KUNIT(dm_handle_hpd_rx_offload_work);
struct hpd_rx_irq_offload_work_queue *amdgpu_dm_hpd_rx_irq_create_workqueue(struct amdgpu_device *adev)
{
struct dc *dc = adev->dm.dc;
- int max_caps = dc->caps.max_links;
+ int max_caps = dc_get_caps(dc)->max_links;
int i = 0;
struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
@@ -1265,7 +1265,7 @@ void amdgpu_dm_hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
int i;
if (dm->hpd_rx_offload_wq) {
- for (i = 0; i < dm->dc->caps.max_links; i++)
+ for (i = 0; i < dc_get_caps(dm->dc)->max_links; i++)
flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
}
}
@@ -1321,7 +1321,7 @@ void amdgpu_dm_hdmi_hpd_debounce_work(struct work_struct *work)
/* Re-detect the display */
scoped_guard(mutex, &adev->dm.dc_lock) {
- if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) {
+ if (dc_get_caps(dc)->ips_support && dc_get_ctx(dc)->dmub_srv->idle_allowed) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
@@ -1359,7 +1359,7 @@ void amdgpu_dm_hdmi_hpd_debounce_work(struct work_struct *work)
}
scoped_guard(mutex, &adev->dm.dc_lock) {
- if (reallow_idle && dc->caps.ips_support)
+ if (reallow_idle && dc_get_caps(dc)->ips_support)
dc_allow_idle_optimizations(dc, true);
}
}
@@ -1668,7 +1668,7 @@ STATIC_IFN_KUNIT void dmub_hpd_callback(struct amdgpu_device *adev,
}
link_index = notify->link_index;
- link = adev->dm.dc->links[link_index];
+ link = dc_get_link_at_index(adev->dm.dc, link_index);
dev = adev->dm.ddev;
drm_connector_list_iter_begin(dev, &iter);
@@ -2362,7 +2362,7 @@ int amdgpu_dm_dce110_register_irq_handlers(struct amdgpu_device *adev)
unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
/* Use different interrupts for VBLANK on DCE 6 vs. newer. */
const unsigned int vblank_d1 =
- adev->dm.dc->ctx->dce_version >= DCE_VERSION_8_0
+ dc_get_dce_version(adev->dm.dc) >= DCE_VERSION_8_0
? VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 : 1;
if (adev->family >= AMDGPU_FAMILY_AI)
@@ -2413,7 +2413,7 @@ int amdgpu_dm_dce110_register_irq_handlers(struct amdgpu_device *adev)
return -ENOMEM;
}
- if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {
+ if (dc_supports_vrr(dc_get_dce_version(adev->dm.dc))) {
/* Use VUPDATE interrupt */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
src_id = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT + i * 2;
@@ -2626,7 +2626,7 @@ int amdgpu_dm_register_outbox_irq_handlers(struct amdgpu_device *adev)
return r;
}
- if (dc->ctx->dmub_srv) {
+ if (dc_get_ctx(dc)->dmub_srv) {
i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
int_params.irq_source =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index dbad0a6d3a2b..f71f66b04d5e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -37,10 +37,10 @@ bool link_supports_psrsu(struct dc_link *link)
{
struct dc *dc = link->ctx->dc;
- if (!dc->caps.dmcub_support)
+ if (!dc_get_caps(dc)->dmcub_support)
return false;
- if (dc->ctx->dce_version < DCN_VERSION_3_1)
+ if (dc_get_dce_version(dc) < DCN_VERSION_3_1)
return false;
if (!is_psr_su_specific_panel(link))
@@ -111,7 +111,7 @@ bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *ac
/* Reset psr version first */
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
- if (!dc->caps.dmub_caps.psr)
+ if (!dc_get_caps(dc)->dmub_caps.psr)
return false;
if (!(link->connector_signal & SIGNAL_TYPE_EDP))
@@ -148,8 +148,8 @@ bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm)
{
unsigned int i;
- for (i = 0; i < dm->dc->current_state->stream_count; i++) {
- const struct dc_link *link = dm->dc->current_state->streams[i]->link;
+ for (i = 0; i < dc_get_current_state(dm->dc)->stream_count; i++) {
+ const struct dc_link *link = dc_get_current_state(dm->dc)->streams[i]->link;
if (!link)
continue;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
index ee2e4754b089..6441212f93a1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
@@ -97,8 +97,8 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector
if (!amdgpu_dm_link_supports_replay(link, aconnector))
return false;
- if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub ||
- !dc->ctx->dmub_srv->dmub->feature_caps.replay_supported)
+ if (!dc_get_ctx(dc)->dmub_srv || !dc_get_ctx(dc)->dmub_srv->dmub ||
+ !dc_get_ctx(dc)->dmub_srv->dmub->feature_caps.replay_supported)
return false;
/* Mark Replay is supported in link and update related attributes
@@ -121,8 +121,10 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector
debug_flags = (union replay_debug_flags *)&pr_config.debug_flags;
debug_flags->u32All = 0;
- debug_flags->bitfields.visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY;
- debug_flags->bitfields.skip_crtc_disabled = dc->debug.replay_skip_crtc_disabled;
+ debug_flags->bitfields.visual_confirm =
+ dc_get_debug_options(dc)->visual_confirm == VISUAL_CONFIRM_REPLAY;
+ debug_flags->bitfields.skip_crtc_disabled =
+ dc_get_debug_options(dc)->replay_skip_crtc_disabled;
init_replay_config(link, &pr_config);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 8aa2364b714e..15a203fbae81 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -42,6 +42,11 @@ struct dc_context *dc_get_ctx(const struct dc *dc)
return dc->ctx;
}
+enum dce_version dc_get_dce_version(const struct dc *dc)
+{
+ return dc->ctx->dce_version;
+}
+
const struct dc_caps *dc_get_caps(const struct dc *dc)
{
return &dc->caps;
@@ -52,7 +57,12 @@ const struct dc_config *dc_get_config(const struct dc *dc)
return &dc->config;
}
-struct dc_debug_options *dc_get_debug_options(struct dc *dc)
+const struct dc_debug_options *dc_get_debug_options(const struct dc *dc)
+{
+ return &dc->debug;
+}
+
+struct dc_debug_options *dc_get_debug_options_mutable(struct dc *dc)
{
return &dc->debug;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index f0c84abab0fb..9592a95544ea 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -2479,14 +2479,20 @@ uint8_t dc_get_link_count(const struct dc *dc);
/* The DC context (logging, register access, dmub service). */
struct dc_context *dc_get_ctx(const struct dc *dc);
+/* The ASIC display engine version. */
+enum dce_version dc_get_dce_version(const struct dc *dc);
+
/* Capabilities detected at dc_create() time. Read-only. */
const struct dc_caps *dc_get_caps(const struct dc *dc);
/* Configuration captured at dc_create() time. Read-only. */
const struct dc_config *dc_get_config(const struct dc *dc);
-/* Debug overrides (module parameters, debugfs). Writable. */
-struct dc_debug_options *dc_get_debug_options(struct dc *dc);
+/* Debug overrides (module parameters, debugfs). Read-only view. */
+const struct dc_debug_options *dc_get_debug_options(const struct dc *dc);
+
+/* Debug overrides; writable view for module parameter and debugfs writes. */
+struct dc_debug_options *dc_get_debug_options_mutable(struct dc *dc);
/* The currently committed state. Owned by DC; read-only for DM. */
struct dc_state *dc_get_current_state(const struct dc *dc);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 05/19] drm/amd/display/amdgpu_dm: Use DC accessors in psr/replay/dmub/hdcp/irq paths
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_psr.c, amdgpu_dm_replay.c, amdgpu_dm_dmub.c,
amdgpu_dm_hdcp.c and amdgpu_dm_irq.c.
Add dc_get_dce_version() for the frequent ctx->dce_version reads and
split the debug options accessor into a const read view
(dc_get_debug_options) and an interim writable view
(dc_get_debug_options_mutable) for the remaining module parameter and
debugfs write sites.
Also constify the dc_color_caps consumers in the color module so
dc_get_caps() read views can flow through them.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 41 ++++++++++++----------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 39 ++++++++++----------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 22 ++++++------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 10 +++---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c | 10 +++---
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 12 ++++++-
drivers/gpu/drm/amd/display/dc/dc.h | 10 ++++--
7 files changed, 85 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index 0ea8f9a582cc..af2cda9080d9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -179,6 +179,7 @@ dm_get_alt_channel_pstate_switch_aperture(struct amdgpu_device *adev,
G7_PSTATE_APERTURE2_ID,
};
struct mem_reserved_info apertures[ARRAY_SIZE(region_ids)];
+ struct dml2_soc_alt_ch_info alt_ch_cfg = {0};
u64 aperture_mc_bases[ARRAY_SIZE(region_ids)];
u32 i;
int r;
@@ -214,11 +215,13 @@ dm_get_alt_channel_pstate_switch_aperture(struct amdgpu_device *adev,
hw_params->soc_fb_info.alt_channel_region_size[i] =
apertures[i].reserved_region_size;
/* DML consumes the MC base address bits [47:16]. */
- adev->dm.dc->dml2_options.alt_ch_cfg.region_base_addr_47_16[i] =
+ alt_ch_cfg.region_base_addr_47_16[i] =
(u32)(aperture_mc_bases[i] >> 16);
- adev->dm.dc->dml2_options.alt_ch_cfg.region_size_bytes[i] =
+ alt_ch_cfg.region_size_bytes[i] =
(u32)apertures[i].reserved_region_size;
}
+
+ dc_set_dml2_alt_ch_cfg(adev->dm.dc, &alt_ch_cfg);
}
@@ -229,9 +232,10 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
const struct firmware *dmub_fw = adev->dm.dmub_fw;
struct dc *dc = adev->dm.dc;
- struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
- struct abm *abm = adev->dm.dc->res_pool->abm;
- struct dc_context *ctx = adev->dm.dc->ctx;
+ struct resource_pool *res_pool = dc_get_res_pool(dc);
+ struct dmcu *dmcu = res_pool->dmcu;
+ struct abm *abm = res_pool->abm;
+ struct dc_context *ctx = dc_get_ctx(adev->dm.dc);
struct dmub_srv_hw_params hw_params;
enum dmub_status status;
const unsigned char *fw_inst_const, *fw_bss_data;
@@ -335,14 +339,15 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
hw_params.fb_info = fb_info;
/* Enable usb4 dpia in the FW APU */
- if (dc->caps.is_apu &&
- dc->res_pool->usb4_dpia_count != 0 &&
- !dc->debug.dpia_debug.bits.disable_dpia) {
+ if (dc_get_caps(dc)->is_apu &&
+ dc_get_res_pool(dc)->usb4_dpia_count != 0 &&
+ !dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia) {
hw_params.dpia_supported = true;
- hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;
+ hw_params.disable_dpia = dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia;
hw_params.dpia_hpd_int_enable_supported = false;
- hw_params.enable_non_transparent_setconfig = dc->config.consolidated_dpia_dp_lt;
- hw_params.disable_dpia_bw_allocation = !dc->config.usb4_bw_alloc_support;
+ hw_params.enable_non_transparent_setconfig =
+ dc_get_config(dc)->consolidated_dpia_dp_lt;
+ hw_params.disable_dpia_bw_allocation = !dc_get_config(dc)->usb4_bw_alloc_support;
}
switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
@@ -375,9 +380,9 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
}
- if (!adev->dm.dc->ctx->dmub_srv)
- adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
- if (!adev->dm.dc->ctx->dmub_srv) {
+ if (!dc_get_ctx(adev->dm.dc)->dmub_srv)
+ dc_get_ctx(adev->dm.dc)->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
+ if (!dc_get_ctx(adev->dm.dc)->dmub_srv) {
drm_err(adev_to_drm(adev), "Couldn't allocate DC DMUB server!\n");
return -ENOMEM;
}
@@ -401,13 +406,13 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
if (adev->dm.dmcub_fw_version &&
adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59))
- adev->dm.dc->debug.sanity_checks = true;
+ dc_get_debug_options_mutable(adev->dm.dc)->sanity_checks = true;
break;
case IP_VERSION(3, 1, 4):
if (adev->dm.dmcub_fw_version &&
adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16))
- adev->dm.dc->debug.sanity_checks = true;
+ dc_get_debug_options_mutable(adev->dm.dc)->sanity_checks = true;
break;
default:
break;
@@ -565,7 +570,7 @@ STATIC_IFN_KUNIT uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
{
struct amdgpu_device *adev = ctx;
- return dm_read_reg(adev->dm.dc->ctx, address);
+ return dm_read_reg(dc_get_ctx(adev->dm.dc), address);
}
EXPORT_IF_KUNIT(amdgpu_dm_dmub_reg_read);
@@ -574,7 +579,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
{
struct amdgpu_device *adev = ctx;
- return dm_write_reg(adev->dm.dc->ctx, address, value);
+ return dm_write_reg(dc_get_ctx(adev->dm.dc), address, value);
}
EXPORT_IF_KUNIT(amdgpu_dm_dmub_reg_write);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 47cbc826ed45..73b56e078cbe 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -43,7 +43,7 @@ STATIC_IFN_KUNIT bool lp_write_i2c(void *handle, uint32_t address, const uint8_t
struct dc_link *link = handle;
struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };
struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW,
- link->dc->caps.i2c_speed_in_khz};
+ dc_get_caps(link->dc)->i2c_speed_in_khz};
return dm_helpers_submit_i2c(link->ctx, link, &cmd);
}
@@ -56,7 +56,7 @@ STATIC_IFN_KUNIT bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset
struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset},
{false, address, size, data} };
struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW,
- link->dc->caps.i2c_speed_in_khz};
+ dc_get_caps(link->dc)->i2c_speed_in_khz};
return dm_helpers_submit_i2c(link->ctx, link, &cmd);
}
@@ -308,9 +308,9 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
hdcp_w->aconnector[conn_index] = aconnector;
hdcp_get_link_display_adjustments(enable_encryption, content_type,
- dc->caps.fused_io_supported,
- dc->debug.hdcp_lc_force_fw_enable,
- dc->debug.hdcp_lc_enable_sw_fallback,
+ dc_get_caps(dc)->fused_io_supported,
+ dc_get_debug_options(dc)->hdcp_lc_force_fw_enable,
+ dc_get_debug_options(dc)->hdcp_lc_enable_sw_fallback,
&link_adjust, &display_adjust);
hdcp_update_display_encryption_control(hdcp_work, hdcp_w, conn_index,
enable_encryption);
@@ -676,8 +676,11 @@ void update_config(void *handle, struct cp_psp_stream_config *config)
link->adjust.auth_delay = 2;
link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS;
link->adjust.hdcp1.disable = 0;
- link->adjust.hdcp2.use_fw_locality_check = (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable);
- link->adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback;
+ link->adjust.hdcp2.use_fw_locality_check =
+ (dc_get_caps(dc)->fused_io_supported ||
+ dc_get_debug_options(dc)->hdcp_lc_force_fw_enable);
+ link->adjust.hdcp2.use_sw_locality_fallback =
+ dc_get_debug_options(dc)->hdcp_lc_enable_sw_fallback;
hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index,
@@ -839,7 +842,7 @@ static const struct bin_attribute data_attr = {
struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev,
struct cp_psp *cp_psp, struct dc *dc)
{
- int max_caps = dc->caps.max_links;
+ int max_caps = dc_get_caps(dc)->max_links;
struct hdcp_workqueue *hdcp_work;
int i = 0;
@@ -874,16 +877,16 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev,
struct mod_hdcp_ddc_funcs *ddc_funcs = &config->ddc.funcs;
config->psp.handle = &adev->psp;
- if (dc->ctx->dce_version == DCN_VERSION_3_1 ||
- dc->ctx->dce_version == DCN_VERSION_3_14 ||
- dc->ctx->dce_version == DCN_VERSION_3_15 ||
- dc->ctx->dce_version == DCN_VERSION_3_16 ||
- dc->ctx->dce_version == DCN_VERSION_3_2 ||
- dc->ctx->dce_version == DCN_VERSION_3_21 ||
- dc->ctx->dce_version == DCN_VERSION_3_5 ||
- dc->ctx->dce_version == DCN_VERSION_3_51 ||
- dc->ctx->dce_version == DCN_VERSION_3_6 ||
- dc->ctx->dce_version == DCN_VERSION_4_01)
+ if (dc_get_dce_version(dc) == DCN_VERSION_3_1 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_14 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_15 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_16 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_2 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_21 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_5 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_51 ||
+ dc_get_dce_version(dc) == DCN_VERSION_3_6 ||
+ dc_get_dce_version(dc) == DCN_VERSION_4_01)
config->psp.caps.dtm_v3_supported = 1;
config->ddc.handle = dc_get_link_at_index(dc, i);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 5b4ff079cd55..a7ee30c66a48 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -808,7 +808,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
st = (state == AMDGPU_IRQ_STATE_ENABLE);
- if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
+ if (dc && dc_get_caps(dc)->ips_support && dc_is_idle_optimizations_allowed(dc))
dc_allow_idle_optimizations(dc, false);
amdgpu_dm_irq_set(adev, irq_source, st);
@@ -989,8 +989,8 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
* has rather than over the whole enum: the unused slots of the DC
* interrupt table hold dummy handlers that assert when touched.
*/
- for (i = 0; i < adev->dm.dc->link_count; i++) {
- const struct dc_link *link = adev->dm.dc->links[i];
+ for (i = 0; i < dc_get_link_count(adev->dm.dc); i++) {
+ const struct dc_link *link = dc_get_link_at_index(adev->dm.dc, i);
if (link->irq_source_hpd != DC_IRQ_SOURCE_INVALID &&
!amdgpu_dm_irq_set(adev, link->irq_source_hpd, false))
@@ -1226,7 +1226,7 @@ EXPORT_IF_KUNIT(dm_handle_hpd_rx_offload_work);
struct hpd_rx_irq_offload_work_queue *amdgpu_dm_hpd_rx_irq_create_workqueue(struct amdgpu_device *adev)
{
struct dc *dc = adev->dm.dc;
- int max_caps = dc->caps.max_links;
+ int max_caps = dc_get_caps(dc)->max_links;
int i = 0;
struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
@@ -1265,7 +1265,7 @@ void amdgpu_dm_hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
int i;
if (dm->hpd_rx_offload_wq) {
- for (i = 0; i < dm->dc->caps.max_links; i++)
+ for (i = 0; i < dc_get_caps(dm->dc)->max_links; i++)
flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
}
}
@@ -1321,7 +1321,7 @@ void amdgpu_dm_hdmi_hpd_debounce_work(struct work_struct *work)
/* Re-detect the display */
scoped_guard(mutex, &adev->dm.dc_lock) {
- if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) {
+ if (dc_get_caps(dc)->ips_support && dc_get_ctx(dc)->dmub_srv->idle_allowed) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
@@ -1359,7 +1359,7 @@ void amdgpu_dm_hdmi_hpd_debounce_work(struct work_struct *work)
}
scoped_guard(mutex, &adev->dm.dc_lock) {
- if (reallow_idle && dc->caps.ips_support)
+ if (reallow_idle && dc_get_caps(dc)->ips_support)
dc_allow_idle_optimizations(dc, true);
}
}
@@ -1668,7 +1668,7 @@ STATIC_IFN_KUNIT void dmub_hpd_callback(struct amdgpu_device *adev,
}
link_index = notify->link_index;
- link = adev->dm.dc->links[link_index];
+ link = dc_get_link_at_index(adev->dm.dc, link_index);
dev = adev->dm.ddev;
drm_connector_list_iter_begin(dev, &iter);
@@ -2362,7 +2362,7 @@ int amdgpu_dm_dce110_register_irq_handlers(struct amdgpu_device *adev)
unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
/* Use different interrupts for VBLANK on DCE 6 vs. newer. */
const unsigned int vblank_d1 =
- adev->dm.dc->ctx->dce_version >= DCE_VERSION_8_0
+ dc_get_dce_version(adev->dm.dc) >= DCE_VERSION_8_0
? VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 : 1;
if (adev->family >= AMDGPU_FAMILY_AI)
@@ -2413,7 +2413,7 @@ int amdgpu_dm_dce110_register_irq_handlers(struct amdgpu_device *adev)
return -ENOMEM;
}
- if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {
+ if (dc_supports_vrr(dc_get_dce_version(adev->dm.dc))) {
/* Use VUPDATE interrupt */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
src_id = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT + i * 2;
@@ -2626,7 +2626,7 @@ int amdgpu_dm_register_outbox_irq_handlers(struct amdgpu_device *adev)
return r;
}
- if (dc->ctx->dmub_srv) {
+ if (dc_get_ctx(dc)->dmub_srv) {
i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
int_params.irq_source =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index dbad0a6d3a2b..f71f66b04d5e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -37,10 +37,10 @@ bool link_supports_psrsu(struct dc_link *link)
{
struct dc *dc = link->ctx->dc;
- if (!dc->caps.dmcub_support)
+ if (!dc_get_caps(dc)->dmcub_support)
return false;
- if (dc->ctx->dce_version < DCN_VERSION_3_1)
+ if (dc_get_dce_version(dc) < DCN_VERSION_3_1)
return false;
if (!is_psr_su_specific_panel(link))
@@ -111,7 +111,7 @@ bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *ac
/* Reset psr version first */
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
- if (!dc->caps.dmub_caps.psr)
+ if (!dc_get_caps(dc)->dmub_caps.psr)
return false;
if (!(link->connector_signal & SIGNAL_TYPE_EDP))
@@ -148,8 +148,8 @@ bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm)
{
unsigned int i;
- for (i = 0; i < dm->dc->current_state->stream_count; i++) {
- const struct dc_link *link = dm->dc->current_state->streams[i]->link;
+ for (i = 0; i < dc_get_current_state(dm->dc)->stream_count; i++) {
+ const struct dc_link *link = dc_get_current_state(dm->dc)->streams[i]->link;
if (!link)
continue;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
index ee2e4754b089..6441212f93a1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
@@ -97,8 +97,8 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector
if (!amdgpu_dm_link_supports_replay(link, aconnector))
return false;
- if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub ||
- !dc->ctx->dmub_srv->dmub->feature_caps.replay_supported)
+ if (!dc_get_ctx(dc)->dmub_srv || !dc_get_ctx(dc)->dmub_srv->dmub ||
+ !dc_get_ctx(dc)->dmub_srv->dmub->feature_caps.replay_supported)
return false;
/* Mark Replay is supported in link and update related attributes
@@ -121,8 +121,10 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector
debug_flags = (union replay_debug_flags *)&pr_config.debug_flags;
debug_flags->u32All = 0;
- debug_flags->bitfields.visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY;
- debug_flags->bitfields.skip_crtc_disabled = dc->debug.replay_skip_crtc_disabled;
+ debug_flags->bitfields.visual_confirm =
+ dc_get_debug_options(dc)->visual_confirm == VISUAL_CONFIRM_REPLAY;
+ debug_flags->bitfields.skip_crtc_disabled =
+ dc_get_debug_options(dc)->replay_skip_crtc_disabled;
init_replay_config(link, &pr_config);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 8aa2364b714e..15a203fbae81 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -42,6 +42,11 @@ struct dc_context *dc_get_ctx(const struct dc *dc)
return dc->ctx;
}
+enum dce_version dc_get_dce_version(const struct dc *dc)
+{
+ return dc->ctx->dce_version;
+}
+
const struct dc_caps *dc_get_caps(const struct dc *dc)
{
return &dc->caps;
@@ -52,7 +57,12 @@ const struct dc_config *dc_get_config(const struct dc *dc)
return &dc->config;
}
-struct dc_debug_options *dc_get_debug_options(struct dc *dc)
+const struct dc_debug_options *dc_get_debug_options(const struct dc *dc)
+{
+ return &dc->debug;
+}
+
+struct dc_debug_options *dc_get_debug_options_mutable(struct dc *dc)
{
return &dc->debug;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index f0c84abab0fb..9592a95544ea 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -2479,14 +2479,20 @@ uint8_t dc_get_link_count(const struct dc *dc);
/* The DC context (logging, register access, dmub service). */
struct dc_context *dc_get_ctx(const struct dc *dc);
+/* The ASIC display engine version. */
+enum dce_version dc_get_dce_version(const struct dc *dc);
+
/* Capabilities detected at dc_create() time. Read-only. */
const struct dc_caps *dc_get_caps(const struct dc *dc);
/* Configuration captured at dc_create() time. Read-only. */
const struct dc_config *dc_get_config(const struct dc *dc);
-/* Debug overrides (module parameters, debugfs). Writable. */
-struct dc_debug_options *dc_get_debug_options(struct dc *dc);
+/* Debug overrides (module parameters, debugfs). Read-only view. */
+const struct dc_debug_options *dc_get_debug_options(const struct dc *dc);
+
+/* Debug overrides; writable view for module parameter and debugfs writes. */
+struct dc_debug_options *dc_get_debug_options_mutable(struct dc *dc);
/* The currently committed state. Owned by DC; read-only for DM. */
struct dc_state *dc_get_current_state(const struct dc *dc);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 05/19] drm/amd/display/amdgpu_dm: Use DC accessors in psr/replay/dmub/hdcp/irq paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 2:07 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 2:07 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] drm/amd/display: commit message claims dc_color_caps changes
from parent commit
--
commit 343696be48b1784f753cb65b6771fbf97af59e1d
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display/amdgpu_dm: Use DC accessors in psr/replay/dmub/hdcp/irq paths
This commit replaces direct struct dc member accesses with DC accessor
helpers across the psr, replay, dmub, hdcp, and irq paths, adds
dc_get_dce_version(), and splits debug option access into const and
mutable accessors.
> Also constify the dc_color_caps consumers in the color module so
> dc_get_caps() read views can flow through them.
[Severity: Low]
Should this paragraph be dropped from the commit message? This patch
does not touch any color module files; the dc_color_caps consumers were
already constified in the preceding commit "drm/amd/display/amdgpu_dm: Use
DC accessors in audio/color/backlight paths".
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=5
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 06/19] drm/amd/display/amdgpu_dm: Use DC accessors in plane/crtc/helpers paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_plane.c, amdgpu_dm_crtc.c and amdgpu_dm_helpers.c,
including the cap_funcs DCC query (dc_get_dcc_compression_cap), the
hwss prepare_ddc sequence (dc_prepare_ddc) and the clk_mgr use in the
DP compliance test path (dc_get_clk_mgr).
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 16 +++++++--------
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 24 ++++++++++++----------
.../drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 21 ++++++++-----------
3 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 3e0128a29d77..334e33b1c4f4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -180,7 +180,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_idle_worker(struct work_struct *work)
while (idle_work->enable) {
fsleep(HPD_DETECTION_PERIOD_uS);
mutex_lock(&idle_work->dm->dc_lock);
- if (!idle_work->dm->dc->idle_optimizations_allowed) {
+ if (!dc_is_idle_optimizations_allowed(idle_work->dm->dc)) {
mutex_unlock(&idle_work->dm->dc_lock);
break;
}
@@ -308,8 +308,8 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
* Call this function to estimate missed vblanks by using timestamps and
* update the vblank counter in DRM.
*/
- if (dc->caps.ips_support &&
- dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
+ if (dc_get_caps(dc)->ips_support &&
+ dc_get_config(dc)->disable_ips != DMUB_IPS_DISABLE_ALL &&
sr_supported && vblank->config.disable_immediate)
drm_crtc_vblank_restore(crtc);
}
@@ -327,7 +327,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
rc = amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type);
drm_dbg_vbl(crtc->dev, "Put vupdate_irq ret=%d\n", rc);
}
- } else if (dc_supports_vrr(dm->dc->ctx->dce_version)) {
+ } else if (dc_supports_vrr(dc_get_dce_version(dm->dc))) {
if (enable) {
/* vblank irq on -> Only need vupdate irq in vrr mode
* Not ref-counted since we need explicit enable/disable
@@ -530,7 +530,7 @@ dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
{
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
- if (adev->dm.dc->caps.color.mpc.ogam_ram)
+ if (dc_get_caps(adev->dm.dc)->color.mpc.ogam_ram)
drm_object_attach_property(&crtc->base,
adev->mode_info.regamma_tf_property,
AMDGPU_TRANSFER_FUNCTION_DEFAULT);
@@ -813,8 +813,8 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
acrtc->base.state = crtc_state;
}
- acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
- acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
+ acrtc->max_cursor_width = dc_get_caps(dm->adev->dm.dc)->max_cursor_size;
+ acrtc->max_cursor_height = dc_get_caps(dm->adev->dm.dc)->max_cursor_size;
acrtc->crtc_id = crtc_index;
acrtc->base.enabled = false;
@@ -830,7 +830,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
* or the COLOR_PIPELINE property. An atomic commit which attempts to enable
* both is rejected.
*/
- has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&
+ has_degamma = dc_get_caps(dm->adev->dm.dc)->color.dpp.dcn_arch &&
dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 3067ac5bb0cd..02a8cfde9f1a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -136,7 +136,8 @@ STATIC_IFN_KUNIT void apply_edid_quirks(struct dc_link *link, struct edid *edid,
if (dc_is_embedded_signal(link->connector_signal)) {
drm_dbg_driver(dev, "Force PHY power down/up level 2 on panel id %X\n",
panel_id);
- link->ctx->dc->debug.psr_phy_force_phy_power_down_up_level_2 = true;
+ dc_get_debug_options_mutable(link->ctx->dc)->
+ psr_phy_force_phy_power_down_up_level_2 = true;
}
break;
/* Workaround for monitors that get corrupted by the PHY SSC reduction */
@@ -227,7 +228,9 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
if (edid_caps->edid_hdmi) {
edid_caps->qs_bit = connector->display_info.rgb_quant_range_selectable;
- populate_hdmi_info_from_connector(link->dc->config.enable_frl, &connector->display_info.hdmi, edid_caps);
+ populate_hdmi_info_from_connector(
+ dc_get_config(link->dc)->enable_frl,
+ &connector->display_info.hdmi, edid_caps);
drm_dbg_driver(connector->dev, "%s: HDMI_FRL [%s] max_frl_rate %d\n", __func__, connector->name, edid_caps->max_frl_rate);
if (edid_caps->frl_dsc_support)
drm_dbg_driver(connector->dev, "%s: HDMI_FRL_DSC [%s] frl_dsc_10bpc %d, frl_dsc_12bpc %d, frl_dsc_all_bpp %d, frl_dsc_native_420 %d, frl_dsc_max_slices %d, frl_dsc_max_frl_rate %d, frl_dsc_total_chunk_kbytes %d\n",
@@ -236,8 +239,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
edid_caps->frl_dsc_max_frl_rate, edid_caps->frl_dsc_total_chunk_kbytes);
if (aconnector->hdmi_comp_auto) {
edid_caps->panel_patch.hdmi_comp_auto = true;
- link->ctx->dc->debug.force_frl_max = true;
- link->ctx->dc->debug.force_frl_dsc = true;
+ dc_get_debug_options_mutable(link->ctx->dc)->force_frl_max = true;
+ dc_get_debug_options_mutable(link->ctx->dc)->force_frl_dsc = true;
drm_dbg_driver(connector->dev, "%s: HDMI_FRL [%s] hdmi_comp_auto --> enabled\n", __func__, connector->name);
}
}
@@ -1291,8 +1294,7 @@ enum dc_edid_status dm_helpers_read_local_edid(
else
ddc = &aconnector->i2c->base;
- if (link->dc->hwss.prepare_ddc)
- link->dc->hwss.prepare_ddc(link);
+ dc_prepare_ddc(link);
dm_helpers_wait_for_edid_ready(link, ddc);
@@ -1552,12 +1554,12 @@ bool dm_helpers_dp_handle_test_pattern_request(
DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
- struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
+ struct pipe_ctx *pipes = dc_get_current_state(link->dc)->res_ctx.pipe_ctx;
struct pipe_ctx *pipe_ctx = NULL;
struct amdgpu_dm_connector *aconnector = link->priv;
struct drm_device *dev = aconnector->base.dev;
- struct dc_state *dc_state = ctx->dc->current_state;
- struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;
+ struct dc_state *dc_state = dc_get_current_state(ctx->dc);
+ struct clk_mgr *clk_mgr = dc_get_clk_mgr(ctx->dc);
int i;
for (i = 0; i < MAX_PIPES; i++) {
@@ -1663,8 +1665,8 @@ bool dm_helpers_dp_handle_test_pattern_request(
dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?
clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;
dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;
- ctx->dc->clk_mgr->funcs->update_clocks(
- ctx->dc->clk_mgr,
+ dc_get_clk_mgr(ctx->dc)->funcs->update_clocks(
+ dc_get_clk_mgr(ctx->dc),
dc_state,
false);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index b224d9596fd2..eba044bc47df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -306,9 +306,6 @@ STATIC_IFN_KUNIT int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,
format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return -EINVAL;
- if (!dc->cap_funcs.get_dcc_compression_cap)
- return -EINVAL;
-
input.format = format;
input.surface_size.width = plane_size->surface_size.width;
input.surface_size.height = plane_size->surface_size.height;
@@ -319,7 +316,7 @@ STATIC_IFN_KUNIT int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,
else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
input.scan = SCAN_DIRECTION_VERTICAL;
- if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
+ if (!dc_get_dcc_compression_cap(dc, &input, &output))
return -EINVAL;
if (!output.capable)
@@ -1337,7 +1334,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_de
struct amdgpu_device *adev = drm_to_adev(dev);
struct dc *dc = adev->dm.dc;
/* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
- struct dc_plane_cap *plane_cap = &dc->caps.planes[0];
+ const struct dc_plane_cap *plane_cap = &dc_get_caps(dc)->planes[0];
switch (fb->format->format) {
case DRM_FORMAT_P010:
@@ -1697,7 +1694,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
* legacy gamma setup.
*/
if (crtc_state->cm_is_degamma_srgb &&
- adev->dm.dc->caps.color.dpp.gamma_corr)
+ dc_get_caps(adev->dm.dc)->color.dpp.gamma_corr)
attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
if (afb)
@@ -1977,7 +1974,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
struct drm_plane *plane)
{
struct amdgpu_mode_info mode_info = dm->adev->mode_info;
- struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp;
+ struct dpp_color_caps dpp_color_caps = dc_get_caps(dm->dc)->color.dpp;
/* Check HW color pipeline capabilities on DPP block (pre-blending)
* before exposing related properties.
@@ -1999,11 +1996,11 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
AMDGPU_HDR_MULT_DEFAULT);
/* Only enable plane CTM if both DPP and MPC gamut remap is available. */
- if (dm->dc->caps.color.mpc.gamut_remap)
+ if (dc_get_caps(dm->dc)->color.mpc.gamut_remap)
drm_object_attach_property(&plane->base,
dm->adev->mode_info.plane_ctm_property, 0);
- if (dpp_color_caps.hw_3d_lut || dm->dc->caps.color.mpc.preblend) {
+ if (dpp_color_caps.hw_3d_lut || dc_get_caps(dm->dc)->color.mpc.preblend) {
drm_object_attach_property(&plane->base,
mode_info.plane_shaper_lut_property, 0);
drm_object_attach_property(&plane->base,
@@ -2019,7 +2016,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
MAX_COLOR_3DLUT_SIZE);
}
- if (dpp_color_caps.ogam_ram || dm->dc->caps.color.mpc.preblend) {
+ if (dpp_color_caps.ogam_ram || dc_get_caps(dm->dc)->color.mpc.preblend) {
drm_object_attach_property(&plane->base,
mode_info.plane_blend_lut_property, 0);
drm_object_attach_property(&plane->base,
@@ -2171,7 +2168,7 @@ dm_plane_init_colorops(struct drm_plane *plane)
return 0;
/* initialize pipeline */
- if (dc->ctx->dce_version >= DCN_VERSION_3_0) {
+ if (dc_get_dce_version(dc) >= DCN_VERSION_3_0) {
ret = amdgpu_dm_initialize_default_pipeline(plane, &pipelines[len]);
if (ret) {
drm_err(plane->dev, "Failed to create color pipeline for plane %d: %pe\n",
@@ -2218,7 +2215,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
int res = -EPERM;
unsigned int supported_rotations;
uint64_t *modifiers = NULL;
- unsigned int primary_zpos = dm->dc->caps.max_slave_planes;
+ unsigned int primary_zpos = dc_get_caps(dm->dc)->max_slave_planes;
num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,
ARRAY_SIZE(formats));
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 06/19] drm/amd/display/amdgpu_dm: Use DC accessors in plane/crtc/helpers paths
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_plane.c, amdgpu_dm_crtc.c and amdgpu_dm_helpers.c,
including the cap_funcs DCC query (dc_get_dcc_compression_cap), the
hwss prepare_ddc sequence (dc_prepare_ddc) and the clk_mgr use in the
DP compliance test path (dc_get_clk_mgr).
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 16 +++++++--------
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 24 ++++++++++++----------
.../drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 21 ++++++++-----------
3 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 3e0128a29d77..334e33b1c4f4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -180,7 +180,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_idle_worker(struct work_struct *work)
while (idle_work->enable) {
fsleep(HPD_DETECTION_PERIOD_uS);
mutex_lock(&idle_work->dm->dc_lock);
- if (!idle_work->dm->dc->idle_optimizations_allowed) {
+ if (!dc_is_idle_optimizations_allowed(idle_work->dm->dc)) {
mutex_unlock(&idle_work->dm->dc_lock);
break;
}
@@ -308,8 +308,8 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
* Call this function to estimate missed vblanks by using timestamps and
* update the vblank counter in DRM.
*/
- if (dc->caps.ips_support &&
- dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
+ if (dc_get_caps(dc)->ips_support &&
+ dc_get_config(dc)->disable_ips != DMUB_IPS_DISABLE_ALL &&
sr_supported && vblank->config.disable_immediate)
drm_crtc_vblank_restore(crtc);
}
@@ -327,7 +327,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
rc = amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type);
drm_dbg_vbl(crtc->dev, "Put vupdate_irq ret=%d\n", rc);
}
- } else if (dc_supports_vrr(dm->dc->ctx->dce_version)) {
+ } else if (dc_supports_vrr(dc_get_dce_version(dm->dc))) {
if (enable) {
/* vblank irq on -> Only need vupdate irq in vrr mode
* Not ref-counted since we need explicit enable/disable
@@ -530,7 +530,7 @@ dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
{
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
- if (adev->dm.dc->caps.color.mpc.ogam_ram)
+ if (dc_get_caps(adev->dm.dc)->color.mpc.ogam_ram)
drm_object_attach_property(&crtc->base,
adev->mode_info.regamma_tf_property,
AMDGPU_TRANSFER_FUNCTION_DEFAULT);
@@ -813,8 +813,8 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
acrtc->base.state = crtc_state;
}
- acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
- acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
+ acrtc->max_cursor_width = dc_get_caps(dm->adev->dm.dc)->max_cursor_size;
+ acrtc->max_cursor_height = dc_get_caps(dm->adev->dm.dc)->max_cursor_size;
acrtc->crtc_id = crtc_index;
acrtc->base.enabled = false;
@@ -830,7 +830,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
* or the COLOR_PIPELINE property. An atomic commit which attempts to enable
* both is rejected.
*/
- has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&
+ has_degamma = dc_get_caps(dm->adev->dm.dc)->color.dpp.dcn_arch &&
dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 3067ac5bb0cd..02a8cfde9f1a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -136,7 +136,8 @@ STATIC_IFN_KUNIT void apply_edid_quirks(struct dc_link *link, struct edid *edid,
if (dc_is_embedded_signal(link->connector_signal)) {
drm_dbg_driver(dev, "Force PHY power down/up level 2 on panel id %X\n",
panel_id);
- link->ctx->dc->debug.psr_phy_force_phy_power_down_up_level_2 = true;
+ dc_get_debug_options_mutable(link->ctx->dc)->
+ psr_phy_force_phy_power_down_up_level_2 = true;
}
break;
/* Workaround for monitors that get corrupted by the PHY SSC reduction */
@@ -227,7 +228,9 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
if (edid_caps->edid_hdmi) {
edid_caps->qs_bit = connector->display_info.rgb_quant_range_selectable;
- populate_hdmi_info_from_connector(link->dc->config.enable_frl, &connector->display_info.hdmi, edid_caps);
+ populate_hdmi_info_from_connector(
+ dc_get_config(link->dc)->enable_frl,
+ &connector->display_info.hdmi, edid_caps);
drm_dbg_driver(connector->dev, "%s: HDMI_FRL [%s] max_frl_rate %d\n", __func__, connector->name, edid_caps->max_frl_rate);
if (edid_caps->frl_dsc_support)
drm_dbg_driver(connector->dev, "%s: HDMI_FRL_DSC [%s] frl_dsc_10bpc %d, frl_dsc_12bpc %d, frl_dsc_all_bpp %d, frl_dsc_native_420 %d, frl_dsc_max_slices %d, frl_dsc_max_frl_rate %d, frl_dsc_total_chunk_kbytes %d\n",
@@ -236,8 +239,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
edid_caps->frl_dsc_max_frl_rate, edid_caps->frl_dsc_total_chunk_kbytes);
if (aconnector->hdmi_comp_auto) {
edid_caps->panel_patch.hdmi_comp_auto = true;
- link->ctx->dc->debug.force_frl_max = true;
- link->ctx->dc->debug.force_frl_dsc = true;
+ dc_get_debug_options_mutable(link->ctx->dc)->force_frl_max = true;
+ dc_get_debug_options_mutable(link->ctx->dc)->force_frl_dsc = true;
drm_dbg_driver(connector->dev, "%s: HDMI_FRL [%s] hdmi_comp_auto --> enabled\n", __func__, connector->name);
}
}
@@ -1291,8 +1294,7 @@ enum dc_edid_status dm_helpers_read_local_edid(
else
ddc = &aconnector->i2c->base;
- if (link->dc->hwss.prepare_ddc)
- link->dc->hwss.prepare_ddc(link);
+ dc_prepare_ddc(link);
dm_helpers_wait_for_edid_ready(link, ddc);
@@ -1552,12 +1554,12 @@ bool dm_helpers_dp_handle_test_pattern_request(
DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
- struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
+ struct pipe_ctx *pipes = dc_get_current_state(link->dc)->res_ctx.pipe_ctx;
struct pipe_ctx *pipe_ctx = NULL;
struct amdgpu_dm_connector *aconnector = link->priv;
struct drm_device *dev = aconnector->base.dev;
- struct dc_state *dc_state = ctx->dc->current_state;
- struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;
+ struct dc_state *dc_state = dc_get_current_state(ctx->dc);
+ struct clk_mgr *clk_mgr = dc_get_clk_mgr(ctx->dc);
int i;
for (i = 0; i < MAX_PIPES; i++) {
@@ -1663,8 +1665,8 @@ bool dm_helpers_dp_handle_test_pattern_request(
dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?
clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;
dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;
- ctx->dc->clk_mgr->funcs->update_clocks(
- ctx->dc->clk_mgr,
+ dc_get_clk_mgr(ctx->dc)->funcs->update_clocks(
+ dc_get_clk_mgr(ctx->dc),
dc_state,
false);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index b224d9596fd2..eba044bc47df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -306,9 +306,6 @@ STATIC_IFN_KUNIT int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,
format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return -EINVAL;
- if (!dc->cap_funcs.get_dcc_compression_cap)
- return -EINVAL;
-
input.format = format;
input.surface_size.width = plane_size->surface_size.width;
input.surface_size.height = plane_size->surface_size.height;
@@ -319,7 +316,7 @@ STATIC_IFN_KUNIT int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,
else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
input.scan = SCAN_DIRECTION_VERTICAL;
- if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
+ if (!dc_get_dcc_compression_cap(dc, &input, &output))
return -EINVAL;
if (!output.capable)
@@ -1337,7 +1334,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_de
struct amdgpu_device *adev = drm_to_adev(dev);
struct dc *dc = adev->dm.dc;
/* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
- struct dc_plane_cap *plane_cap = &dc->caps.planes[0];
+ const struct dc_plane_cap *plane_cap = &dc_get_caps(dc)->planes[0];
switch (fb->format->format) {
case DRM_FORMAT_P010:
@@ -1697,7 +1694,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
* legacy gamma setup.
*/
if (crtc_state->cm_is_degamma_srgb &&
- adev->dm.dc->caps.color.dpp.gamma_corr)
+ dc_get_caps(adev->dm.dc)->color.dpp.gamma_corr)
attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
if (afb)
@@ -1977,7 +1974,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
struct drm_plane *plane)
{
struct amdgpu_mode_info mode_info = dm->adev->mode_info;
- struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp;
+ struct dpp_color_caps dpp_color_caps = dc_get_caps(dm->dc)->color.dpp;
/* Check HW color pipeline capabilities on DPP block (pre-blending)
* before exposing related properties.
@@ -1999,11 +1996,11 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
AMDGPU_HDR_MULT_DEFAULT);
/* Only enable plane CTM if both DPP and MPC gamut remap is available. */
- if (dm->dc->caps.color.mpc.gamut_remap)
+ if (dc_get_caps(dm->dc)->color.mpc.gamut_remap)
drm_object_attach_property(&plane->base,
dm->adev->mode_info.plane_ctm_property, 0);
- if (dpp_color_caps.hw_3d_lut || dm->dc->caps.color.mpc.preblend) {
+ if (dpp_color_caps.hw_3d_lut || dc_get_caps(dm->dc)->color.mpc.preblend) {
drm_object_attach_property(&plane->base,
mode_info.plane_shaper_lut_property, 0);
drm_object_attach_property(&plane->base,
@@ -2019,7 +2016,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
MAX_COLOR_3DLUT_SIZE);
}
- if (dpp_color_caps.ogam_ram || dm->dc->caps.color.mpc.preblend) {
+ if (dpp_color_caps.ogam_ram || dc_get_caps(dm->dc)->color.mpc.preblend) {
drm_object_attach_property(&plane->base,
mode_info.plane_blend_lut_property, 0);
drm_object_attach_property(&plane->base,
@@ -2171,7 +2168,7 @@ dm_plane_init_colorops(struct drm_plane *plane)
return 0;
/* initialize pipeline */
- if (dc->ctx->dce_version >= DCN_VERSION_3_0) {
+ if (dc_get_dce_version(dc) >= DCN_VERSION_3_0) {
ret = amdgpu_dm_initialize_default_pipeline(plane, &pipelines[len]);
if (ret) {
drm_err(plane->dev, "Failed to create color pipeline for plane %d: %pe\n",
@@ -2218,7 +2215,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
int res = -EPERM;
unsigned int supported_rotations;
uint64_t *modifiers = NULL;
- unsigned int primary_zpos = dm->dc->caps.max_slave_planes;
+ unsigned int primary_zpos = dc_get_caps(dm->dc)->max_slave_planes;
num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,
ARRAY_SIZE(formats));
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 06/19] drm/amd/display/amdgpu_dm: Use DC accessors in plane/crtc/helpers paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 1:58 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 1:58 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found no new issues
in this patch, but noticed 1 related pre-existing issue it does not
introduce:
- [Medium] drm/amd/display: memory leak in dm_helpers_read_local_edid()
[1]
--
commit cb81c7873176d93f0193d77abe7f41c76b00d56d
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display/amdgpu_dm: Use DC accessors in plane/crtc/helpers paths
This commit replaces direct struct dc member dereferences with DC
accessor functions across amdgpu_dm_plane.c, amdgpu_dm_crtc.c, and
amdgpu_dm_helpers.c.
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index 3067ac5bb0cd0..02a8cfde9f1aa 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
[ ... ]
> @@ -1291,8 +1294,7 @@ enum dc_edid_status dm_helpers_read_local_edid(
> else
> ddc = &aconnector->i2c->base;
>
> - if (link->dc->hwss.prepare_ddc)
> - link->dc->hwss.prepare_ddc(link);
> + dc_prepare_ddc(link);
>
> dm_helpers_wait_for_edid_ready(link, ddc);
>
[Severity: Medium]
This problem wasn't introduced by this patch, but does
dm_helpers_read_local_edid() leak drm_edid [1] when returning
EDID_BAD_INPUT?
Later in the retry loop, if the raw EDID check or length validation fails,
the function returns without calling drm_edid_free(drm_edid):
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c:dm_helpers_read_local_edid() {
...
if (!edid || !connector->edid_blob_ptr ||
connector->edid_blob_ptr->length > sizeof(sink->dc_edid.raw_edid))
return EDID_BAD_INPUT;
...
drm_edid_free(drm_edid);
...
}
[1] https://sashiko.dev/#/bug/linux-5db7be8c-2e59-46d2-b3bf-37e1b52f73e4
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=6
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 07/19] drm/amd/display/amdgpu_dm: Use DC accessors in connector paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_connector.c, including the link_service encoding
format query (dc_link_dp_get_encoding_format), link array iteration
(dc_get_link_at_index), the FBC compressor checks and the debug and
caps reads in the DSC policy paths.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index d334391bcbae..134d08207a14 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -266,7 +266,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_fbc_init(struct drm_connector *connector)
struct drm_display_mode *mode;
unsigned long max_size = 0;
- if (adev->dm.dc->fbc_compressor == NULL)
+ if (!dc_is_fbc_compressor_available(adev->dm.dc))
return;
if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
@@ -289,7 +289,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_fbc_init(struct drm_connector *connector)
if (r)
drm_err(adev_to_drm(adev), "DM: Failed to initialize FBC\n");
else {
- adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
+ dc_set_fbc_gpu_addr(adev->dm.dc, compressor->gpu_addr);
drm_info(adev_to_drm(adev), "DM: FBC alloc %lu\n", max_size*4);
}
@@ -1230,7 +1230,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
edp_min_bpp_x16 = edp_max_bpp_x16;
if (dc_dsc_compute_bandwidth_range(dc,
- dc->debug.dsc_min_slice_height_override,
+ dc_get_debug_options(dc)->dsc_min_slice_height_override,
edp_min_bpp_x16, edp_max_bpp_x16,
dsc_caps,
&stream->timing,
@@ -1303,7 +1303,8 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
if (sink->sink_signal == SIGNAL_TYPE_EDP &&
!aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
- dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
+ dc_get_caps(dc)->edp_dsc_support &&
+ aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
@@ -3190,15 +3191,13 @@ STATIC_IFN_KUNIT int amdgpu_dm_connector_get_modes(struct drm_connector *connect
struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
struct drm_encoder *encoder;
const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid;
- struct dc_link_settings *verified_link_cap = &dc_link->verified_link_cap;
- const struct dc *dc = dc_link->dc;
encoder = amdgpu_dm_connector_to_encoder(connector);
if (!drm_edid) {
amdgpu_dm_connector->num_modes =
drm_add_modes_noedid(connector, 640, 480);
- if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
+ if (dc_link_dp_get_encoding_format(dc_link) == DP_128b_132b_ENCODING)
amdgpu_dm_connector->num_modes +=
drm_add_modes_noedid(connector, 1920, 1080);
@@ -3249,7 +3248,7 @@ void hdmi_frl_status_polling_work(struct work_struct *work)
/* Defer to the next cycle rather than block on a busy dc_lock. */
if (mutex_trylock(&dm->dc_lock)) {
for (int i = 0; i < MAX_LINKS; i++) {
- dc_link = dc->links[i];
+ dc_link = dc_get_link_at_index(dc, i);
if (!dc_link || !dc_link->local_sink)
continue;
@@ -4027,13 +4026,15 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
/* Handle MCCS */
if (do_mccs) {
- dm_helpers_read_mccs_caps(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink);
+ dm_helpers_read_mccs_caps(dc_get_ctx(adev->dm.dc),
+ amdgpu_dm_connector->dc_link, sink);
if (sink->edid_caps.freesync_vcp_code && !sink->mccs_caps.freesync_supported)
freesync_capable = false;
if (sink->mccs_caps.freesync_supported && freesync_capable)
- dm_helpers_mccs_vcp_set(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink);
+ dm_helpers_mccs_vcp_set(dc_get_ctx(adev->dm.dc),
+ amdgpu_dm_connector->dc_link, sink);
}
update:
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 07/19] drm/amd/display/amdgpu_dm: Use DC accessors in connector paths
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_connector.c, including the link_service encoding
format query (dc_link_dp_get_encoding_format), link array iteration
(dc_get_link_at_index), the FBC compressor checks and the debug and
caps reads in the DSC policy paths.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index d334391bcbae..134d08207a14 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -266,7 +266,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_fbc_init(struct drm_connector *connector)
struct drm_display_mode *mode;
unsigned long max_size = 0;
- if (adev->dm.dc->fbc_compressor == NULL)
+ if (!dc_is_fbc_compressor_available(adev->dm.dc))
return;
if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
@@ -289,7 +289,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_fbc_init(struct drm_connector *connector)
if (r)
drm_err(adev_to_drm(adev), "DM: Failed to initialize FBC\n");
else {
- adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
+ dc_set_fbc_gpu_addr(adev->dm.dc, compressor->gpu_addr);
drm_info(adev_to_drm(adev), "DM: FBC alloc %lu\n", max_size*4);
}
@@ -1230,7 +1230,7 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
edp_min_bpp_x16 = edp_max_bpp_x16;
if (dc_dsc_compute_bandwidth_range(dc,
- dc->debug.dsc_min_slice_height_override,
+ dc_get_debug_options(dc)->dsc_min_slice_height_override,
edp_min_bpp_x16, edp_max_bpp_x16,
dsc_caps,
&stream->timing,
@@ -1303,7 +1303,8 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
if (sink->sink_signal == SIGNAL_TYPE_EDP &&
!aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
- dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
+ dc_get_caps(dc)->edp_dsc_support &&
+ aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
@@ -3190,15 +3191,13 @@ STATIC_IFN_KUNIT int amdgpu_dm_connector_get_modes(struct drm_connector *connect
struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
struct drm_encoder *encoder;
const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid;
- struct dc_link_settings *verified_link_cap = &dc_link->verified_link_cap;
- const struct dc *dc = dc_link->dc;
encoder = amdgpu_dm_connector_to_encoder(connector);
if (!drm_edid) {
amdgpu_dm_connector->num_modes =
drm_add_modes_noedid(connector, 640, 480);
- if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
+ if (dc_link_dp_get_encoding_format(dc_link) == DP_128b_132b_ENCODING)
amdgpu_dm_connector->num_modes +=
drm_add_modes_noedid(connector, 1920, 1080);
@@ -3249,7 +3248,7 @@ void hdmi_frl_status_polling_work(struct work_struct *work)
/* Defer to the next cycle rather than block on a busy dc_lock. */
if (mutex_trylock(&dm->dc_lock)) {
for (int i = 0; i < MAX_LINKS; i++) {
- dc_link = dc->links[i];
+ dc_link = dc_get_link_at_index(dc, i);
if (!dc_link || !dc_link->local_sink)
continue;
@@ -4027,13 +4026,15 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
/* Handle MCCS */
if (do_mccs) {
- dm_helpers_read_mccs_caps(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink);
+ dm_helpers_read_mccs_caps(dc_get_ctx(adev->dm.dc),
+ amdgpu_dm_connector->dc_link, sink);
if (sink->edid_caps.freesync_vcp_code && !sink->mccs_caps.freesync_supported)
freesync_capable = false;
if (sink->mccs_caps.freesync_supported && freesync_capable)
- dm_helpers_mccs_vcp_set(adev->dm.dc->ctx, amdgpu_dm_connector->dc_link, sink);
+ dm_helpers_mccs_vcp_set(dc_get_ctx(adev->dm.dc),
+ amdgpu_dm_connector->dc_link, sink);
}
update:
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 08/19] drm/amd/display: Use DC accessors in DAL modules
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Migrate modules/freesync, modules/power and the remaining module
users of struct dc members to the DC accessor layer, replacing the
direct link_service calls (edp_get_psr_residency, edp_send_replay_cmd,
edp_set_coasting_vtotal, dp_setup_replay, get_ddc_aux_inst, ...) with
the dc_link_* wrappers.
Add missing struct dc forward declarations to logger_interface.h and
mod_freesync.h.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/include/logger_interface.h | 1 +
.../drm/amd/display/modules/freesync/freesync.c | 14 +++++------
.../gpu/drm/amd/display/modules/inc/mod_freesync.h | 2 ++
drivers/gpu/drm/amd/display/modules/power/power.c | 5 ++--
.../gpu/drm/amd/display/modules/power/power_abm.c | 29 +++++++++++-----------
.../gpu/drm/amd/display/modules/power/power_psr.c | 10 ++++----
.../drm/amd/display/modules/power/power_replay.c | 25 ++++++++-----------
7 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
index 4c01514b926c..7dc738b60162 100644
--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
@@ -28,6 +28,7 @@
#include "logger_types.h"
+struct dc;
struct dc_context;
struct dc_link;
struct dc_surface_update;
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index f154a619b533..dafcb42504f8 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -125,11 +125,10 @@ static unsigned int calc_duration_in_us_from_v_total(
static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)
{
- unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;
+ unsigned int max_hw_v_total = dc_get_caps(stream->ctx->dc)->max_v_total;
- if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {
+ if (dc_get_caps(stream->ctx->dc)->vtotal_limited_by_fp2)
max_hw_v_total -= stream->timing.v_front_porch + 1;
- }
return max_hw_v_total;
}
@@ -1008,7 +1007,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
nominal_field_rate_in_uhz =
mod_freesync_calc_nominal_field_rate(stream);
- if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
+ if (dc_get_caps(stream->ctx->dc)->max_v_total != 0 && stream->timing.h_total != 0) {
min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
(stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));
}
@@ -1196,9 +1195,10 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
if (in_out_vrr->supported == false)
return;
- cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
- cur_timestamp_in_us = (unsigned int)
- div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
+ cur_tick = dm_get_timestamp(dc_get_ctx(core_freesync->dc));
+ cur_timestamp_in_us = (unsigned int)div_u64(
+ dm_get_elapse_time_in_ns(dc_get_ctx(core_freesync->dc), cur_tick, 0),
+ 1000);
in_out_vrr->flip_interval.vsyncs_between_flip++;
in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index c042fb1bf49c..1cf88adb3163 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -28,6 +28,8 @@
#include "mod_shared.h"
+struct dc;
+
// Access structures
struct mod_freesync {
int dummy;
diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c
index d900be8cb5fc..884279696a2d 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power.c
@@ -192,7 +192,8 @@ struct mod_power *mod_power_create(struct dc *dc,
}
// ABM used to contain 4 different configs. There is only 3 since ABM 2.3.
- if ((dc->res_pool->dmcu != NULL) && (dc->res_pool->dmcu->dmcu_version.abm_version < 0x23))
+ if (dc_get_res_pool(dc)->dmcu != NULL &&
+ dc_get_res_pool(dc)->dmcu->dmcu_version.abm_version < 0x23)
abm_max_config = 4;
else
abm_max_config = 3;
@@ -480,7 +481,7 @@ bool mod_power_notify_mode_change(struct mod_power *mod_power,
link = dc_stream_get_link(stream);
if (link != NULL && dc_get_edp_link_panel_inst(dc, link, &panel_inst)) {
- aux_inst = link->dc->link_srv->get_ddc_aux_inst(link);
+ aux_inst = dc_link_get_ddc_aux_inst(link);
mod_power_update_backlight_on_mode_change(core_power, link, panel_inst, aux_inst, is_hdr);
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
index 5f27dea4aa0a..2b420eac5c56 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_abm.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
@@ -712,7 +712,7 @@ void initialize_backlight_caps(struct core_power *core_power, unsigned int inst)
/* Retrieve ACPI extended brightness caps */
if (dm_query_extended_brightness_caps
- (dc->ctx, acpi_display_type, ext_backlight_caps)) {
+ (dc_get_ctx(dc), acpi_display_type, ext_backlight_caps)) {
custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps);
}
@@ -868,7 +868,7 @@ bool mod_power_hw_init_backlight(struct mod_power *mod_power)
params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels;
params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight;
- dmcu = dc->res_pool->dmcu;
+ dmcu = dc_get_res_pool(dc)->dmcu;
// In the case where abm is implemented on dmcub,
// dmcu object will be null.
@@ -876,8 +876,8 @@ bool mod_power_hw_init_backlight(struct mod_power *mod_power)
if (dmcu) {
//DMCU does not support multiple eDP
return dmcu_load_iram(dmcu, params);
- } else if (dc->ctx->dmub_srv) {
- if (!dmub_init_abm_config(dc->res_pool, params, i))
+ } else if (dc_get_ctx(dc)->dmub_srv) {
+ if (!dmub_init_abm_config(dc_get_res_pool(dc), params, i))
return false;
} else
return false;
@@ -935,7 +935,7 @@ static bool set_backlight_millinits_aux(struct core_power *core_power,
// only use internal backlight control if dmub capabilities are not present
if (link->backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX &&
- link->dc->caps.dmub_caps.aux_backlight_support)
+ dc_get_caps(link->dc)->dmub_caps.aux_backlight_support)
return true;
return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR,
@@ -1041,7 +1041,7 @@ bool mod_power_set_backlight_nits(struct mod_power *mod_power,
core_power = MOD_POWER_TO_CORE(mod_power);
link = dc_stream_get_link(stream);
- aux_inst = link->dc->link_srv->get_ddc_aux_inst(link);
+ aux_inst = dc_link_get_ddc_aux_inst(link);
if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
return false;
@@ -1128,7 +1128,7 @@ bool mod_power_set_backlight_percent(struct mod_power *mod_power,
core_power = MOD_POWER_TO_CORE(mod_power);
link = dc_stream_get_link(stream);
- aux_inst = link->dc->link_srv->get_ddc_aux_inst(link);
+ aux_inst = dc_link_get_ddc_aux_inst(link);
if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
return false;
@@ -1658,8 +1658,8 @@ bool mod_power_is_abm_supported(struct mod_power *mod_power,
dc = core_power->dc;
// It's only implemented on dmcub.
- if (dc->ctx->dmub_srv) {
- if (!dmub_is_abm_supported(dc->res_pool, inst))
+ if (dc_get_ctx(dc)->dmub_srv) {
+ if (!dmub_is_abm_supported(dc_get_res_pool(dc), inst))
return false;
} else
return false;
@@ -1682,9 +1682,10 @@ bool mod_power_abm_set_event(struct mod_power *mod_power,
dc = core_power->dc;
// It's only implemented on dmcub.
- if (dc->ctx->dmub_srv) {
- if (!dmub_set_abm_event(dc->res_pool, full_screen, trans_info,
- hdr_mode, scaling_enable, scaling_strength_map, inst))
+ if (dc_get_ctx(dc)->dmub_srv) {
+ if (!dmub_set_abm_event(dc_get_res_pool(dc), full_screen,
+ trans_info, hdr_mode, scaling_enable,
+ scaling_strength_map, inst))
return false;
} else
return false;
@@ -1706,8 +1707,8 @@ bool mod_power_abm_set_strength(struct mod_power *mod_power,
dc = core_power->dc;
// It's only implemented on dmcub.
- if (dc->ctx->dmub_srv) {
- if (!dmub_set_abm_strength(dc->res_pool, strength, inst))
+ if (dc_get_ctx(dc)->dmub_srv) {
+ if (!dmub_set_abm_strength(dc_get_res_pool(dc), strength, inst))
return false;
} else
return false;
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
index 96bb77fff05b..af59cf502297 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_psr.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
@@ -70,13 +70,13 @@ bool mod_power_psr_notify_mode_change(struct mod_power *mod_power,
psr_config.psr_exit_link_training_required =
core_power->map[stream_index].caps->psr_exit_link_training_required;
- if (dc->ctx->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1)
+ if (dc_get_ctx(dc)->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1)
psr_config.allow_smu_optimizations =
core_power->psr_smu_optimizations_support && dc_is_embedded_signal(stream->signal);
else
psr_config.allow_smu_optimizations =
core_power->psr_smu_optimizations_support &&
- mod_power_only_edp(dc->current_state, stream);
+ mod_power_only_edp(dc_get_current_state(dc), stream);
psr_config.allow_multi_disp_optimizations = core_power->multi_disp_optimizations_support;
@@ -455,7 +455,7 @@ void mod_power_psr_residency(struct mod_power *mod_power,
link = dc_stream_get_link(stream);
if (link != NULL)
- link->dc->link_srv->edp_get_psr_residency(link, residency, mode);
+ dc_link_edp_get_psr_residency(link, residency, mode);
}
bool mod_power_psr_get_active_psr_events(struct mod_power *mod_power,
const struct dc_stream_state *stream, unsigned int *active_psr_events)
@@ -510,7 +510,7 @@ bool mod_power_psr_set_sink_vtotal_in_psr_active(struct mod_power *mod_power,
link = dc_stream_get_link(stream);
- return link->dc->link_srv->edp_set_sink_vtotal_in_psr_active(
+ return dc_link_edp_set_sink_vtotal_in_psr_active(
link, psr_vtotal_idle, psr_vtotal_su);
}
/*
@@ -645,7 +645,7 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
config->dsc_slice_height = 0;
if (!(link->connector_signal & SIGNAL_TYPE_EDP) ||
- !dc->caps.edp_dsc_support ||
+ !dc_get_caps(dc)->edp_dsc_support ||
link->panel_config.dsc.disable_dsc_edp ||
!link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
!stream->timing.dsc_cfg.num_slices_v)
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_replay.c b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
index 666585b7e00c..d68f14b18179 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_replay.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
@@ -372,7 +372,7 @@ bool mod_power_replay_set_coasting_vtotal(struct mod_power *mod_power,
if (core_power->num_entities == 0)
return false;
- return link->dc->link_srv->edp_set_coasting_vtotal(link, coasting_vtotal, frame_skip_number);
+ return dc_link_edp_set_coasting_vtotal(link, coasting_vtotal, frame_skip_number);
}
void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power,
@@ -400,7 +400,7 @@ void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power,
cmd_data.sync_data.timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported;
- link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Timing_Sync_Supported,
+ dc_link_edp_send_replay_cmd(link, Replay_Set_Timing_Sync_Supported,
&cmd_data);
}
@@ -429,7 +429,7 @@ void mod_power_replay_disabled_adaptive_sync_sdp(struct mod_power *mod_power,
cmd_data.disabled_adaptive_sync_sdp_data.force_disabled = force_disabled;
- link->dc->link_srv->edp_send_replay_cmd(link, Replay_Disabled_Adaptive_Sync_SDP,
+ dc_link_edp_send_replay_cmd(link, Replay_Disabled_Adaptive_Sync_SDP,
&cmd_data);
}
@@ -461,7 +461,7 @@ static void mod_power_replay_set_general_cmd(struct mod_power *mod_power,
cmd_data.set_general_cmd_data.subtype = general_cmd_type;
cmd_data.set_general_cmd_data.param1 = param1;
cmd_data.set_general_cmd_data.param2 = param2;
- link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_General_Cmd,
+ dc_link_edp_send_replay_cmd(link, Replay_Set_General_Cmd,
&cmd_data);
}
@@ -500,7 +500,7 @@ static void mod_power_replay_set_pseudo_vtotal(struct mod_power *mod_power,
if (link->replay_settings.last_pseudo_vtotal != vtotal) {
link->replay_settings.last_pseudo_vtotal = vtotal;
- link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Pseudo_VTotal, &cmd_data);
+ dc_link_edp_send_replay_cmd(link, Replay_Set_Pseudo_VTotal, &cmd_data);
}
}
@@ -759,8 +759,7 @@ void mod_power_replay_residency(const struct dc_stream_state *stream,
else
mode = PR_RESIDENCY_MODE_PHY;
- if (link && link->dc && link->dc->link_srv)
- link->dc->link_srv->edp_replay_residency(link, residency, is_start, mode);
+ dc_link_edp_replay_residency(link, residency, is_start, mode);
}
bool mod_power_replay_get_cumulative_residency(const struct dc_stream_state *stream,
@@ -768,10 +767,7 @@ bool mod_power_replay_get_cumulative_residency(const struct dc_stream_state *str
{
const struct dc_link *link = dc_stream_get_link(stream);
- if (!link || !link->dc || !link->dc->link_srv)
- return false;
-
- return link->dc->link_srv->edp_replay_get_cumulative_residency(
+ return dc_link_edp_replay_get_cumulative_residency(
link, residency_milli_pct);
}
@@ -802,7 +798,8 @@ bool mod_power_replay_set_power_opt_and_coasting_vtotal(struct mod_power *mod_po
power_opt = mod_power_replay_setup_power_opt(link, active_replay_events, is_ultra_sleep_mode);
- return link->dc->link_srv->edp_set_replay_power_opt_and_coasting_vtotal(link, &power_opt, coasting_vtotal, frame_skip_number);
+ return dc_link_edp_set_replay_power_opt_and_coasting_vtotal(
+ link, &power_opt, coasting_vtotal, frame_skip_number);
}
void mod_power_replay_notify_mode_change(struct mod_power *mod_power,
@@ -829,14 +826,14 @@ void mod_power_replay_notify_mode_change(struct mod_power *mod_power,
link->replay_settings.replay_smu_opt_enable =
(link->replay_settings.config.replay_smu_opt_supported &&
- mod_power_only_edp(dc->current_state, stream));
+ mod_power_only_edp(dc_get_current_state(dc), stream));
if (active_replay_events & replay_event_os_request_force_ffu) {
link->replay_settings.config.os_request_force_ffu = true;
}
if (dc_is_embedded_signal(stream->signal))
- dc->link_srv->dp_setup_replay(link, stream);
+ dc_link_dp_setup_replay(link, stream);
}
void init_replay_config(struct dc_link *link, struct replay_config *pr_config)
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 08/19] drm/amd/display: Use DC accessors in DAL modules
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Migrate modules/freesync, modules/power and the remaining module
users of struct dc members to the DC accessor layer, replacing the
direct link_service calls (edp_get_psr_residency, edp_send_replay_cmd,
edp_set_coasting_vtotal, dp_setup_replay, get_ddc_aux_inst, ...) with
the dc_link_* wrappers.
Add missing struct dc forward declarations to logger_interface.h and
mod_freesync.h.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/include/logger_interface.h | 1 +
.../drm/amd/display/modules/freesync/freesync.c | 14 +++++------
.../gpu/drm/amd/display/modules/inc/mod_freesync.h | 2 ++
drivers/gpu/drm/amd/display/modules/power/power.c | 5 ++--
.../gpu/drm/amd/display/modules/power/power_abm.c | 29 +++++++++++-----------
.../gpu/drm/amd/display/modules/power/power_psr.c | 10 ++++----
.../drm/amd/display/modules/power/power_replay.c | 25 ++++++++-----------
7 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
index 4c01514b926c..7dc738b60162 100644
--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
@@ -28,6 +28,7 @@
#include "logger_types.h"
+struct dc;
struct dc_context;
struct dc_link;
struct dc_surface_update;
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index f154a619b533..dafcb42504f8 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -125,11 +125,10 @@ static unsigned int calc_duration_in_us_from_v_total(
static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)
{
- unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;
+ unsigned int max_hw_v_total = dc_get_caps(stream->ctx->dc)->max_v_total;
- if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {
+ if (dc_get_caps(stream->ctx->dc)->vtotal_limited_by_fp2)
max_hw_v_total -= stream->timing.v_front_porch + 1;
- }
return max_hw_v_total;
}
@@ -1008,7 +1007,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
nominal_field_rate_in_uhz =
mod_freesync_calc_nominal_field_rate(stream);
- if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
+ if (dc_get_caps(stream->ctx->dc)->max_v_total != 0 && stream->timing.h_total != 0) {
min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
(stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));
}
@@ -1196,9 +1195,10 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
if (in_out_vrr->supported == false)
return;
- cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
- cur_timestamp_in_us = (unsigned int)
- div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
+ cur_tick = dm_get_timestamp(dc_get_ctx(core_freesync->dc));
+ cur_timestamp_in_us = (unsigned int)div_u64(
+ dm_get_elapse_time_in_ns(dc_get_ctx(core_freesync->dc), cur_tick, 0),
+ 1000);
in_out_vrr->flip_interval.vsyncs_between_flip++;
in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index c042fb1bf49c..1cf88adb3163 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -28,6 +28,8 @@
#include "mod_shared.h"
+struct dc;
+
// Access structures
struct mod_freesync {
int dummy;
diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c
index d900be8cb5fc..884279696a2d 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power.c
@@ -192,7 +192,8 @@ struct mod_power *mod_power_create(struct dc *dc,
}
// ABM used to contain 4 different configs. There is only 3 since ABM 2.3.
- if ((dc->res_pool->dmcu != NULL) && (dc->res_pool->dmcu->dmcu_version.abm_version < 0x23))
+ if (dc_get_res_pool(dc)->dmcu != NULL &&
+ dc_get_res_pool(dc)->dmcu->dmcu_version.abm_version < 0x23)
abm_max_config = 4;
else
abm_max_config = 3;
@@ -480,7 +481,7 @@ bool mod_power_notify_mode_change(struct mod_power *mod_power,
link = dc_stream_get_link(stream);
if (link != NULL && dc_get_edp_link_panel_inst(dc, link, &panel_inst)) {
- aux_inst = link->dc->link_srv->get_ddc_aux_inst(link);
+ aux_inst = dc_link_get_ddc_aux_inst(link);
mod_power_update_backlight_on_mode_change(core_power, link, panel_inst, aux_inst, is_hdr);
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
index 5f27dea4aa0a..2b420eac5c56 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_abm.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
@@ -712,7 +712,7 @@ void initialize_backlight_caps(struct core_power *core_power, unsigned int inst)
/* Retrieve ACPI extended brightness caps */
if (dm_query_extended_brightness_caps
- (dc->ctx, acpi_display_type, ext_backlight_caps)) {
+ (dc_get_ctx(dc), acpi_display_type, ext_backlight_caps)) {
custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps);
}
@@ -868,7 +868,7 @@ bool mod_power_hw_init_backlight(struct mod_power *mod_power)
params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels;
params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight;
- dmcu = dc->res_pool->dmcu;
+ dmcu = dc_get_res_pool(dc)->dmcu;
// In the case where abm is implemented on dmcub,
// dmcu object will be null.
@@ -876,8 +876,8 @@ bool mod_power_hw_init_backlight(struct mod_power *mod_power)
if (dmcu) {
//DMCU does not support multiple eDP
return dmcu_load_iram(dmcu, params);
- } else if (dc->ctx->dmub_srv) {
- if (!dmub_init_abm_config(dc->res_pool, params, i))
+ } else if (dc_get_ctx(dc)->dmub_srv) {
+ if (!dmub_init_abm_config(dc_get_res_pool(dc), params, i))
return false;
} else
return false;
@@ -935,7 +935,7 @@ static bool set_backlight_millinits_aux(struct core_power *core_power,
// only use internal backlight control if dmub capabilities are not present
if (link->backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX &&
- link->dc->caps.dmub_caps.aux_backlight_support)
+ dc_get_caps(link->dc)->dmub_caps.aux_backlight_support)
return true;
return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR,
@@ -1041,7 +1041,7 @@ bool mod_power_set_backlight_nits(struct mod_power *mod_power,
core_power = MOD_POWER_TO_CORE(mod_power);
link = dc_stream_get_link(stream);
- aux_inst = link->dc->link_srv->get_ddc_aux_inst(link);
+ aux_inst = dc_link_get_ddc_aux_inst(link);
if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
return false;
@@ -1128,7 +1128,7 @@ bool mod_power_set_backlight_percent(struct mod_power *mod_power,
core_power = MOD_POWER_TO_CORE(mod_power);
link = dc_stream_get_link(stream);
- aux_inst = link->dc->link_srv->get_ddc_aux_inst(link);
+ aux_inst = dc_link_get_ddc_aux_inst(link);
if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
return false;
@@ -1658,8 +1658,8 @@ bool mod_power_is_abm_supported(struct mod_power *mod_power,
dc = core_power->dc;
// It's only implemented on dmcub.
- if (dc->ctx->dmub_srv) {
- if (!dmub_is_abm_supported(dc->res_pool, inst))
+ if (dc_get_ctx(dc)->dmub_srv) {
+ if (!dmub_is_abm_supported(dc_get_res_pool(dc), inst))
return false;
} else
return false;
@@ -1682,9 +1682,10 @@ bool mod_power_abm_set_event(struct mod_power *mod_power,
dc = core_power->dc;
// It's only implemented on dmcub.
- if (dc->ctx->dmub_srv) {
- if (!dmub_set_abm_event(dc->res_pool, full_screen, trans_info,
- hdr_mode, scaling_enable, scaling_strength_map, inst))
+ if (dc_get_ctx(dc)->dmub_srv) {
+ if (!dmub_set_abm_event(dc_get_res_pool(dc), full_screen,
+ trans_info, hdr_mode, scaling_enable,
+ scaling_strength_map, inst))
return false;
} else
return false;
@@ -1706,8 +1707,8 @@ bool mod_power_abm_set_strength(struct mod_power *mod_power,
dc = core_power->dc;
// It's only implemented on dmcub.
- if (dc->ctx->dmub_srv) {
- if (!dmub_set_abm_strength(dc->res_pool, strength, inst))
+ if (dc_get_ctx(dc)->dmub_srv) {
+ if (!dmub_set_abm_strength(dc_get_res_pool(dc), strength, inst))
return false;
} else
return false;
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
index 96bb77fff05b..af59cf502297 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_psr.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
@@ -70,13 +70,13 @@ bool mod_power_psr_notify_mode_change(struct mod_power *mod_power,
psr_config.psr_exit_link_training_required =
core_power->map[stream_index].caps->psr_exit_link_training_required;
- if (dc->ctx->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1)
+ if (dc_get_ctx(dc)->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1)
psr_config.allow_smu_optimizations =
core_power->psr_smu_optimizations_support && dc_is_embedded_signal(stream->signal);
else
psr_config.allow_smu_optimizations =
core_power->psr_smu_optimizations_support &&
- mod_power_only_edp(dc->current_state, stream);
+ mod_power_only_edp(dc_get_current_state(dc), stream);
psr_config.allow_multi_disp_optimizations = core_power->multi_disp_optimizations_support;
@@ -455,7 +455,7 @@ void mod_power_psr_residency(struct mod_power *mod_power,
link = dc_stream_get_link(stream);
if (link != NULL)
- link->dc->link_srv->edp_get_psr_residency(link, residency, mode);
+ dc_link_edp_get_psr_residency(link, residency, mode);
}
bool mod_power_psr_get_active_psr_events(struct mod_power *mod_power,
const struct dc_stream_state *stream, unsigned int *active_psr_events)
@@ -510,7 +510,7 @@ bool mod_power_psr_set_sink_vtotal_in_psr_active(struct mod_power *mod_power,
link = dc_stream_get_link(stream);
- return link->dc->link_srv->edp_set_sink_vtotal_in_psr_active(
+ return dc_link_edp_set_sink_vtotal_in_psr_active(
link, psr_vtotal_idle, psr_vtotal_su);
}
/*
@@ -645,7 +645,7 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
config->dsc_slice_height = 0;
if (!(link->connector_signal & SIGNAL_TYPE_EDP) ||
- !dc->caps.edp_dsc_support ||
+ !dc_get_caps(dc)->edp_dsc_support ||
link->panel_config.dsc.disable_dsc_edp ||
!link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
!stream->timing.dsc_cfg.num_slices_v)
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_replay.c b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
index 666585b7e00c..d68f14b18179 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_replay.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
@@ -372,7 +372,7 @@ bool mod_power_replay_set_coasting_vtotal(struct mod_power *mod_power,
if (core_power->num_entities == 0)
return false;
- return link->dc->link_srv->edp_set_coasting_vtotal(link, coasting_vtotal, frame_skip_number);
+ return dc_link_edp_set_coasting_vtotal(link, coasting_vtotal, frame_skip_number);
}
void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power,
@@ -400,7 +400,7 @@ void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power,
cmd_data.sync_data.timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported;
- link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Timing_Sync_Supported,
+ dc_link_edp_send_replay_cmd(link, Replay_Set_Timing_Sync_Supported,
&cmd_data);
}
@@ -429,7 +429,7 @@ void mod_power_replay_disabled_adaptive_sync_sdp(struct mod_power *mod_power,
cmd_data.disabled_adaptive_sync_sdp_data.force_disabled = force_disabled;
- link->dc->link_srv->edp_send_replay_cmd(link, Replay_Disabled_Adaptive_Sync_SDP,
+ dc_link_edp_send_replay_cmd(link, Replay_Disabled_Adaptive_Sync_SDP,
&cmd_data);
}
@@ -461,7 +461,7 @@ static void mod_power_replay_set_general_cmd(struct mod_power *mod_power,
cmd_data.set_general_cmd_data.subtype = general_cmd_type;
cmd_data.set_general_cmd_data.param1 = param1;
cmd_data.set_general_cmd_data.param2 = param2;
- link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_General_Cmd,
+ dc_link_edp_send_replay_cmd(link, Replay_Set_General_Cmd,
&cmd_data);
}
@@ -500,7 +500,7 @@ static void mod_power_replay_set_pseudo_vtotal(struct mod_power *mod_power,
if (link->replay_settings.last_pseudo_vtotal != vtotal) {
link->replay_settings.last_pseudo_vtotal = vtotal;
- link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Pseudo_VTotal, &cmd_data);
+ dc_link_edp_send_replay_cmd(link, Replay_Set_Pseudo_VTotal, &cmd_data);
}
}
@@ -759,8 +759,7 @@ void mod_power_replay_residency(const struct dc_stream_state *stream,
else
mode = PR_RESIDENCY_MODE_PHY;
- if (link && link->dc && link->dc->link_srv)
- link->dc->link_srv->edp_replay_residency(link, residency, is_start, mode);
+ dc_link_edp_replay_residency(link, residency, is_start, mode);
}
bool mod_power_replay_get_cumulative_residency(const struct dc_stream_state *stream,
@@ -768,10 +767,7 @@ bool mod_power_replay_get_cumulative_residency(const struct dc_stream_state *str
{
const struct dc_link *link = dc_stream_get_link(stream);
- if (!link || !link->dc || !link->dc->link_srv)
- return false;
-
- return link->dc->link_srv->edp_replay_get_cumulative_residency(
+ return dc_link_edp_replay_get_cumulative_residency(
link, residency_milli_pct);
}
@@ -802,7 +798,8 @@ bool mod_power_replay_set_power_opt_and_coasting_vtotal(struct mod_power *mod_po
power_opt = mod_power_replay_setup_power_opt(link, active_replay_events, is_ultra_sleep_mode);
- return link->dc->link_srv->edp_set_replay_power_opt_and_coasting_vtotal(link, &power_opt, coasting_vtotal, frame_skip_number);
+ return dc_link_edp_set_replay_power_opt_and_coasting_vtotal(
+ link, &power_opt, coasting_vtotal, frame_skip_number);
}
void mod_power_replay_notify_mode_change(struct mod_power *mod_power,
@@ -829,14 +826,14 @@ void mod_power_replay_notify_mode_change(struct mod_power *mod_power,
link->replay_settings.replay_smu_opt_enable =
(link->replay_settings.config.replay_smu_opt_supported &&
- mod_power_only_edp(dc->current_state, stream));
+ mod_power_only_edp(dc_get_current_state(dc), stream));
if (active_replay_events & replay_event_os_request_force_ffu) {
link->replay_settings.config.os_request_force_ffu = true;
}
if (dc_is_embedded_signal(stream->signal))
- dc->link_srv->dp_setup_replay(link, stream);
+ dc_link_dp_setup_replay(link, stream);
}
void init_replay_config(struct dc_link *link, struct replay_config *pr_config)
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 09/19] drm/amd/display/amdgpu_dm: Use DC accessors in debugfs paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_debugfs.c: dmub context access, current_state and
pipe enumeration, IPS config/idle optimization reads, PSR/Panel
Replay residency queries, hwss state dumps (dc_log_hw_state,
dc_get_dcc_en_bits), the SubVP query and the debug option writes.
Add a purpose-specific setter for the eDP hotplug detection mode
(dc_set_allow_edp_hotplug_detection) instead of writing through
dc->config.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 123 ++++++++++-----------
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 6 +
drivers/gpu/drm/amd/display/dc/dc.h | 7 ++
3 files changed, 73 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 68356cb8e4de..fddb47a32fb9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1028,9 +1028,9 @@ static int replay_capability_show(struct seq_file *m, void *data)
struct dc *dc = link->ctx->dc;
sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
- if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)
+ if (dc_get_ctx(dc)->dmub_srv && dc_get_ctx(dc)->dmub_srv->dmub)
driver_support_replay =
- (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;
+ (bool)dc_get_ctx(dc)->dmub_srv->dmub->feature_caps.replay_supported;
}
seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay));
@@ -1295,7 +1295,7 @@ static int max_downscale_src_width_show(struct seq_file *m, void *unused)
if (!link)
return -ENODEV;
- seq_printf(m, "%d\n", link->dc->debug.max_downscale_src_width);
+ seq_printf(m, "%d\n", dc_get_debug_options(link->dc)->max_downscale_src_width);
return 0;
}
@@ -1313,7 +1313,7 @@ static int odm_combine_segments_show(struct seq_file *m, void *unused)
int i, segments = -EOPNOTSUPP;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == link)
break;
@@ -1594,7 +1594,7 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -1696,7 +1696,7 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
}
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -1780,7 +1780,7 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -1880,7 +1880,7 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
}
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -1964,7 +1964,7 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2064,7 +2064,7 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
}
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2144,7 +2144,7 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2241,7 +2241,7 @@ static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *bu
}
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2319,7 +2319,7 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2373,7 +2373,7 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2442,7 +2442,7 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2511,7 +2511,7 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2701,15 +2701,15 @@ static int ips_status_show(struct seq_file *m, void *unused)
struct dc *dc = adev->dm.dc;
struct dc_dmub_srv *dc_dmub_srv;
- seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);
- seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed);
+ seq_printf(m, "IPS config: %d\n", dc_get_config(dc)->disable_ips);
+ seq_printf(m, "Idle optimization: %d\n", dc_is_idle_optimizations_allowed(dc));
if (adev->dm.idle_workqueue) {
seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable);
seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running);
}
- dc_dmub_srv = dc->ctx->dmub_srv;
+ dc_dmub_srv = dc_get_ctx(dc)->dmub_srv;
if (dc_dmub_srv && dc_dmub_srv->dmub) {
uint32_t rcg_count, ips1_count, ips2_count;
volatile const struct dmub_shared_state_ips_fw *ips_fw =
@@ -2752,7 +2752,7 @@ static int ips_residency_show(struct seq_file *m, void *unused)
mutex_lock(&adev->dm.dc_lock);
mode = IPS_RESIDENCY__IPS1_RCG;
- if (!dc_dmub_srv_ips_query_residency_info(dc->ctx, panel_inst, &info, mode)) {
+ if (!dc_dmub_srv_ips_query_residency_info(dc_get_ctx(dc), panel_inst, &info, mode)) {
seq_printf(m, "ISP query failed\n");
} else {
unsigned int pct, frac;
@@ -2785,7 +2785,7 @@ static int ips_residency_cntl_set(void *data, u64 val)
int ret = 0;
mutex_lock(&adev->dm.dc_lock);
- if (!dc_dmub_srv_ips_residency_cntl(dc->ctx, panel_inst, !!val))
+ if (!dc_dmub_srv_ips_residency_cntl(dc_get_ctx(dc), panel_inst, !!val))
ret = -EIO;
mutex_unlock(&adev->dm.dc_lock);
@@ -3231,7 +3231,7 @@ static int replay_get_state(void *data, u64 *val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
@@ -3263,12 +3263,12 @@ static int replay_set_residency(void *data, u64 val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
- link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);
+ dc_link_edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);
if (reallow_idle)
dc_allow_idle_optimizations(dc, true);
@@ -3292,12 +3292,12 @@ static int replay_get_residency(void *data, u64 *val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
- link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
+ dc_link_edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
if (reallow_idle)
dc_allow_idle_optimizations(dc, true);
@@ -3323,7 +3323,7 @@ static int psr_get(void *data, u64 *val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
@@ -3354,12 +3354,12 @@ static int psr_read_residency(void *data, u64 *val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
- link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
+ dc_link_edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
if (reallow_idle)
dc_allow_idle_optimizations(dc, true);
@@ -3379,7 +3379,7 @@ static int allow_edp_hotplug_detection_get(void *data, u64 *val)
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- *val = adev->dm.dc->config.allow_edp_hotplug_detection;
+ *val = dc_get_config(adev->dm.dc)->allow_edp_hotplug_detection;
return 0;
}
@@ -3392,7 +3392,7 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val)
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
+ dc_set_allow_edp_hotplug_detection(adev->dm.dc, (enum dc_hpd_enable_select)val);
return 0;
}
@@ -3532,10 +3532,10 @@ static int dmub_trace_mask_set(void *data, u64 val)
u32 res;
int i;
- if (!adev->dm.dc || !adev->dm.dc->ctx || !adev->dm.dc->ctx->dmub_srv)
+ if (!adev->dm.dc || !dc_get_ctx(adev->dm.dc) || !dc_get_ctx(adev->dm.dc)->dmub_srv)
return -EINVAL;
- dc_dmub_srv = adev->dm.dc->ctx->dmub_srv;
+ dc_dmub_srv = dc_get_ctx(adev->dm.dc)->dmub_srv;
srv = dc_dmub_srv->dmub;
if (!srv || !srv->fw_version)
return -EINVAL;
@@ -3558,7 +3558,8 @@ static int dmub_trace_mask_set(void *data, u64 val)
break;
}
- if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))
+ if (!dc_wake_and_execute_gpint(dc_get_ctx(adev->dm.dc), cmd, res,
+ NULL, DM_DMUB_WAIT_TYPE_WAIT))
return -EIO;
usleep_range(100, 1000);
@@ -3581,10 +3582,10 @@ static int dmub_trace_mask_show(void *data, u64 *val)
u64 res = 0;
int i = 0;
- if (!adev->dm.dc || !adev->dm.dc->ctx || !adev->dm.dc->ctx->dmub_srv)
+ if (!adev->dm.dc || !dc_get_ctx(adev->dm.dc) || !dc_get_ctx(adev->dm.dc)->dmub_srv)
return -EINVAL;
- dc_dmub_srv = adev->dm.dc->ctx->dmub_srv;
+ dc_dmub_srv = dc_get_ctx(adev->dm.dc)->dmub_srv;
srv = dc_dmub_srv->dmub;
if (!srv || !srv->fw_version)
return -EINVAL;
@@ -3592,7 +3593,9 @@ static int dmub_trace_mask_show(void *data, u64 *val)
while (i < 4) {
uint32_t response;
- if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
+ if (!dc_wake_and_execute_gpint(dc_get_ctx(adev->dm.dc), cmd, 0,
+ &response,
+ DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
return -EIO;
raw = response;
@@ -3715,12 +3718,12 @@ static int cacp_ace_curve_area_show(struct seq_file *m, void *unused)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
- if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd,
+ if (!dc_wake_and_execute_dmub_cmd(dc_get_ctx(dc), &cmd,
DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) ||
cmd.cacp_get_ace_curve_area.header.ret_status)
ret = -EIO;
@@ -4243,11 +4246,9 @@ static ssize_t dtn_log_read(
if (!buf || !size)
return -EINVAL;
- if (!dc->hwss.log_hw_state)
+ if (!dc_log_hw_state(dc, &log_ctx))
return 0;
- dc->hwss.log_hw_state(dc, &log_ctx);
-
if (*pos < log_ctx.pos) {
size_t to_copy = log_ctx.pos - *pos;
@@ -4281,8 +4282,7 @@ static ssize_t dtn_log_write(
if (size == 0)
return 0;
- if (dc->hwss.log_hw_state)
- dc->hwss.log_hw_state(dc, NULL);
+ dc_log_hw_state(dc, NULL);
return size;
}
@@ -4459,18 +4459,17 @@ static int capabilities_show(struct seq_file *m, void *unused)
{
struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
struct dc *dc = adev->dm.dc;
- bool mall_supported = dc->caps.mall_size_total;
- bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
+ bool mall_supported = dc_get_caps(dc)->mall_size_total;
+ bool subvp_supported = dc_get_caps(dc)->subvp_fw_processing_delay_us;
unsigned int mall_in_use = false;
unsigned int subvp_in_use = false;
- struct hubbub *hubbub = dc->res_pool->hubbub;
+ struct hubbub *hubbub = dc_get_res_pool(dc)->hubbub;
if (hubbub && hubbub->funcs->get_mall_en)
hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
- if (dc->cap_funcs.get_subvp_en)
- subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);
+ subvp_in_use = dc_get_subvp_en(dc, dc_get_current_state(dc));
seq_printf(m, "mall supported: %s, enabled: %s\n",
mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
@@ -4490,7 +4489,7 @@ static int dp_force_sst_set(void *data, u64 val)
{
struct amdgpu_device *adev = data;
- adev->dm.dc->debug.set_mst_en_for_sst = val;
+ dc_get_debug_options_mutable(adev->dm.dc)->set_mst_en_for_sst = val;
return 0;
}
@@ -4499,7 +4498,7 @@ static int dp_force_sst_get(void *data, u64 *val)
{
struct amdgpu_device *adev = data;
- *val = adev->dm.dc->debug.set_mst_en_for_sst;
+ *val = dc_get_debug_options(adev->dm.dc)->set_mst_en_for_sst;
return 0;
}
@@ -4514,7 +4513,7 @@ static int dp_ignore_cable_id_set(void *data, u64 val)
{
struct amdgpu_device *adev = data;
- adev->dm.dc->debug.ignore_cable_id = val;
+ dc_get_debug_options_mutable(adev->dm.dc)->ignore_cable_id = val;
return 0;
}
@@ -4523,7 +4522,7 @@ static int dp_ignore_cable_id_get(void *data, u64 *val)
{
struct amdgpu_device *adev = data;
- *val = adev->dm.dc->debug.ignore_cable_id;
+ *val = dc_get_debug_options(adev->dm.dc)->ignore_cable_id;
return 0;
}
@@ -4538,7 +4537,7 @@ static int visual_confirm_set(void *data, u64 val)
{
struct amdgpu_device *adev = data;
- adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
+ dc_get_debug_options_mutable(adev->dm.dc)->visual_confirm = (enum visual_confirm)val;
return 0;
}
@@ -4551,7 +4550,7 @@ static int visual_confirm_get(void *data, u64 *val)
{
struct amdgpu_device *adev = data;
- *val = adev->dm.dc->debug.visual_confirm;
+ *val = dc_get_debug_options(adev->dm.dc)->visual_confirm;
return 0;
}
@@ -4570,9 +4569,9 @@ static int skip_detection_link_training_set(void *data, u64 val)
struct amdgpu_device *adev = data;
if (val == 0)
- adev->dm.dc->debug.skip_detection_link_training = false;
+ dc_get_debug_options_mutable(adev->dm.dc)->skip_detection_link_training = false;
else
- adev->dm.dc->debug.skip_detection_link_training = true;
+ dc_get_debug_options_mutable(adev->dm.dc)->skip_detection_link_training = true;
return 0;
}
@@ -4585,7 +4584,7 @@ static int skip_detection_link_training_get(void *data, u64 *val)
{
struct amdgpu_device *adev = data;
- *val = adev->dm.dc->debug.skip_detection_link_training;
+ *val = dc_get_debug_options(adev->dm.dc)->skip_detection_link_training;
return 0;
}
@@ -4610,7 +4609,7 @@ static ssize_t dcc_en_bits_read(
const uint32_t rd_buf_size = 32;
uint32_t result = 0;
int offset = 0;
- int num_pipes = dc->res_pool->pipe_count;
+ int num_pipes = dc_get_res_pool(dc)->pipe_count;
int *dcc_en_bits;
int i, r;
@@ -4618,13 +4617,11 @@ static ssize_t dcc_en_bits_read(
if (!dcc_en_bits)
return -ENOMEM;
- if (!dc->hwss.get_dcc_en_bits) {
+ if (!dc_get_dcc_en_bits(dc, dcc_en_bits)) {
kfree(dcc_en_bits);
return 0;
}
- dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
-
rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
if (!rd_buf) {
kfree(dcc_en_bits);
@@ -4714,7 +4711,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
&disable_hpd_ops);
- if (adev->dm.dc->caps.ips_support) {
+ if (dc_get_caps(adev->dm.dc)->ips_support) {
debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,
&ips_status_fops);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 15a203fbae81..2803471d7333 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -57,6 +57,12 @@ const struct dc_config *dc_get_config(const struct dc *dc)
return &dc->config;
}
+void dc_set_allow_edp_hotplug_detection(struct dc *dc,
+ enum dc_hpd_enable_select hpd_select)
+{
+ dc->config.allow_edp_hotplug_detection = hpd_select;
+}
+
const struct dc_debug_options *dc_get_debug_options(const struct dc *dc)
{
return &dc->debug;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9592a95544ea..082435846ee9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -2488,6 +2488,13 @@ const struct dc_caps *dc_get_caps(const struct dc *dc);
/* Configuration captured at dc_create() time. Read-only. */
const struct dc_config *dc_get_config(const struct dc *dc);
+/*
+ * Select which eDP connectors get hotplug detection enabled; see
+ * enum dc_hpd_enable_select. Runtime configurable (debugfs).
+ */
+void dc_set_allow_edp_hotplug_detection(struct dc *dc,
+ enum dc_hpd_enable_select hpd_select);
+
/* Debug overrides (module parameters, debugfs). Read-only view. */
const struct dc_debug_options *dc_get_debug_options(const struct dc *dc);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 09/19] drm/amd/display/amdgpu_dm: Use DC accessors in debugfs paths
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm_debugfs.c: dmub context access, current_state and
pipe enumeration, IPS config/idle optimization reads, PSR/Panel
Replay residency queries, hwss state dumps (dc_log_hw_state,
dc_get_dcc_en_bits), the SubVP query and the debug option writes.
Add a purpose-specific setter for the eDP hotplug detection mode
(dc_set_allow_edp_hotplug_detection) instead of writing through
dc->config.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 123 ++++++++++-----------
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 6 +
drivers/gpu/drm/amd/display/dc/dc.h | 7 ++
3 files changed, 73 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 68356cb8e4de..fddb47a32fb9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1028,9 +1028,9 @@ static int replay_capability_show(struct seq_file *m, void *data)
struct dc *dc = link->ctx->dc;
sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
- if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)
+ if (dc_get_ctx(dc)->dmub_srv && dc_get_ctx(dc)->dmub_srv->dmub)
driver_support_replay =
- (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;
+ (bool)dc_get_ctx(dc)->dmub_srv->dmub->feature_caps.replay_supported;
}
seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay));
@@ -1295,7 +1295,7 @@ static int max_downscale_src_width_show(struct seq_file *m, void *unused)
if (!link)
return -ENODEV;
- seq_printf(m, "%d\n", link->dc->debug.max_downscale_src_width);
+ seq_printf(m, "%d\n", dc_get_debug_options(link->dc)->max_downscale_src_width);
return 0;
}
@@ -1313,7 +1313,7 @@ static int odm_combine_segments_show(struct seq_file *m, void *unused)
int i, segments = -EOPNOTSUPP;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == link)
break;
@@ -1594,7 +1594,7 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -1696,7 +1696,7 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
}
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -1780,7 +1780,7 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -1880,7 +1880,7 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
}
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -1964,7 +1964,7 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2064,7 +2064,7 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
}
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2144,7 +2144,7 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2241,7 +2241,7 @@ static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *bu
}
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2319,7 +2319,7 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2373,7 +2373,7 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2442,7 +2442,7 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2511,7 +2511,7 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
return -ENOMEM;
for (i = 0; i < MAX_PIPES; i++) {
- pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+ pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
pipe_ctx->stream->link == aconnector->dc_link &&
pipe_ctx->stream->sink &&
@@ -2701,15 +2701,15 @@ static int ips_status_show(struct seq_file *m, void *unused)
struct dc *dc = adev->dm.dc;
struct dc_dmub_srv *dc_dmub_srv;
- seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);
- seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed);
+ seq_printf(m, "IPS config: %d\n", dc_get_config(dc)->disable_ips);
+ seq_printf(m, "Idle optimization: %d\n", dc_is_idle_optimizations_allowed(dc));
if (adev->dm.idle_workqueue) {
seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable);
seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running);
}
- dc_dmub_srv = dc->ctx->dmub_srv;
+ dc_dmub_srv = dc_get_ctx(dc)->dmub_srv;
if (dc_dmub_srv && dc_dmub_srv->dmub) {
uint32_t rcg_count, ips1_count, ips2_count;
volatile const struct dmub_shared_state_ips_fw *ips_fw =
@@ -2752,7 +2752,7 @@ static int ips_residency_show(struct seq_file *m, void *unused)
mutex_lock(&adev->dm.dc_lock);
mode = IPS_RESIDENCY__IPS1_RCG;
- if (!dc_dmub_srv_ips_query_residency_info(dc->ctx, panel_inst, &info, mode)) {
+ if (!dc_dmub_srv_ips_query_residency_info(dc_get_ctx(dc), panel_inst, &info, mode)) {
seq_printf(m, "ISP query failed\n");
} else {
unsigned int pct, frac;
@@ -2785,7 +2785,7 @@ static int ips_residency_cntl_set(void *data, u64 val)
int ret = 0;
mutex_lock(&adev->dm.dc_lock);
- if (!dc_dmub_srv_ips_residency_cntl(dc->ctx, panel_inst, !!val))
+ if (!dc_dmub_srv_ips_residency_cntl(dc_get_ctx(dc), panel_inst, !!val))
ret = -EIO;
mutex_unlock(&adev->dm.dc_lock);
@@ -3231,7 +3231,7 @@ static int replay_get_state(void *data, u64 *val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
@@ -3263,12 +3263,12 @@ static int replay_set_residency(void *data, u64 val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
- link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);
+ dc_link_edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);
if (reallow_idle)
dc_allow_idle_optimizations(dc, true);
@@ -3292,12 +3292,12 @@ static int replay_get_residency(void *data, u64 *val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
- link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
+ dc_link_edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
if (reallow_idle)
dc_allow_idle_optimizations(dc, true);
@@ -3323,7 +3323,7 @@ static int psr_get(void *data, u64 *val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
@@ -3354,12 +3354,12 @@ static int psr_read_residency(void *data, u64 *val)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
- link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
+ dc_link_edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
if (reallow_idle)
dc_allow_idle_optimizations(dc, true);
@@ -3379,7 +3379,7 @@ static int allow_edp_hotplug_detection_get(void *data, u64 *val)
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- *val = adev->dm.dc->config.allow_edp_hotplug_detection;
+ *val = dc_get_config(adev->dm.dc)->allow_edp_hotplug_detection;
return 0;
}
@@ -3392,7 +3392,7 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val)
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
+ dc_set_allow_edp_hotplug_detection(adev->dm.dc, (enum dc_hpd_enable_select)val);
return 0;
}
@@ -3532,10 +3532,10 @@ static int dmub_trace_mask_set(void *data, u64 val)
u32 res;
int i;
- if (!adev->dm.dc || !adev->dm.dc->ctx || !adev->dm.dc->ctx->dmub_srv)
+ if (!adev->dm.dc || !dc_get_ctx(adev->dm.dc) || !dc_get_ctx(adev->dm.dc)->dmub_srv)
return -EINVAL;
- dc_dmub_srv = adev->dm.dc->ctx->dmub_srv;
+ dc_dmub_srv = dc_get_ctx(adev->dm.dc)->dmub_srv;
srv = dc_dmub_srv->dmub;
if (!srv || !srv->fw_version)
return -EINVAL;
@@ -3558,7 +3558,8 @@ static int dmub_trace_mask_set(void *data, u64 val)
break;
}
- if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))
+ if (!dc_wake_and_execute_gpint(dc_get_ctx(adev->dm.dc), cmd, res,
+ NULL, DM_DMUB_WAIT_TYPE_WAIT))
return -EIO;
usleep_range(100, 1000);
@@ -3581,10 +3582,10 @@ static int dmub_trace_mask_show(void *data, u64 *val)
u64 res = 0;
int i = 0;
- if (!adev->dm.dc || !adev->dm.dc->ctx || !adev->dm.dc->ctx->dmub_srv)
+ if (!adev->dm.dc || !dc_get_ctx(adev->dm.dc) || !dc_get_ctx(adev->dm.dc)->dmub_srv)
return -EINVAL;
- dc_dmub_srv = adev->dm.dc->ctx->dmub_srv;
+ dc_dmub_srv = dc_get_ctx(adev->dm.dc)->dmub_srv;
srv = dc_dmub_srv->dmub;
if (!srv || !srv->fw_version)
return -EINVAL;
@@ -3592,7 +3593,9 @@ static int dmub_trace_mask_show(void *data, u64 *val)
while (i < 4) {
uint32_t response;
- if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
+ if (!dc_wake_and_execute_gpint(dc_get_ctx(adev->dm.dc), cmd, 0,
+ &response,
+ DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
return -EIO;
raw = response;
@@ -3715,12 +3718,12 @@ static int cacp_ace_curve_area_show(struct seq_file *m, void *unused)
mutex_lock(&adev->dm.dc_lock);
- if (dc->idle_optimizations_allowed) {
+ if (dc_is_idle_optimizations_allowed(dc)) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
- if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd,
+ if (!dc_wake_and_execute_dmub_cmd(dc_get_ctx(dc), &cmd,
DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) ||
cmd.cacp_get_ace_curve_area.header.ret_status)
ret = -EIO;
@@ -4243,11 +4246,9 @@ static ssize_t dtn_log_read(
if (!buf || !size)
return -EINVAL;
- if (!dc->hwss.log_hw_state)
+ if (!dc_log_hw_state(dc, &log_ctx))
return 0;
- dc->hwss.log_hw_state(dc, &log_ctx);
-
if (*pos < log_ctx.pos) {
size_t to_copy = log_ctx.pos - *pos;
@@ -4281,8 +4282,7 @@ static ssize_t dtn_log_write(
if (size == 0)
return 0;
- if (dc->hwss.log_hw_state)
- dc->hwss.log_hw_state(dc, NULL);
+ dc_log_hw_state(dc, NULL);
return size;
}
@@ -4459,18 +4459,17 @@ static int capabilities_show(struct seq_file *m, void *unused)
{
struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
struct dc *dc = adev->dm.dc;
- bool mall_supported = dc->caps.mall_size_total;
- bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
+ bool mall_supported = dc_get_caps(dc)->mall_size_total;
+ bool subvp_supported = dc_get_caps(dc)->subvp_fw_processing_delay_us;
unsigned int mall_in_use = false;
unsigned int subvp_in_use = false;
- struct hubbub *hubbub = dc->res_pool->hubbub;
+ struct hubbub *hubbub = dc_get_res_pool(dc)->hubbub;
if (hubbub && hubbub->funcs->get_mall_en)
hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
- if (dc->cap_funcs.get_subvp_en)
- subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);
+ subvp_in_use = dc_get_subvp_en(dc, dc_get_current_state(dc));
seq_printf(m, "mall supported: %s, enabled: %s\n",
mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
@@ -4490,7 +4489,7 @@ static int dp_force_sst_set(void *data, u64 val)
{
struct amdgpu_device *adev = data;
- adev->dm.dc->debug.set_mst_en_for_sst = val;
+ dc_get_debug_options_mutable(adev->dm.dc)->set_mst_en_for_sst = val;
return 0;
}
@@ -4499,7 +4498,7 @@ static int dp_force_sst_get(void *data, u64 *val)
{
struct amdgpu_device *adev = data;
- *val = adev->dm.dc->debug.set_mst_en_for_sst;
+ *val = dc_get_debug_options(adev->dm.dc)->set_mst_en_for_sst;
return 0;
}
@@ -4514,7 +4513,7 @@ static int dp_ignore_cable_id_set(void *data, u64 val)
{
struct amdgpu_device *adev = data;
- adev->dm.dc->debug.ignore_cable_id = val;
+ dc_get_debug_options_mutable(adev->dm.dc)->ignore_cable_id = val;
return 0;
}
@@ -4523,7 +4522,7 @@ static int dp_ignore_cable_id_get(void *data, u64 *val)
{
struct amdgpu_device *adev = data;
- *val = adev->dm.dc->debug.ignore_cable_id;
+ *val = dc_get_debug_options(adev->dm.dc)->ignore_cable_id;
return 0;
}
@@ -4538,7 +4537,7 @@ static int visual_confirm_set(void *data, u64 val)
{
struct amdgpu_device *adev = data;
- adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
+ dc_get_debug_options_mutable(adev->dm.dc)->visual_confirm = (enum visual_confirm)val;
return 0;
}
@@ -4551,7 +4550,7 @@ static int visual_confirm_get(void *data, u64 *val)
{
struct amdgpu_device *adev = data;
- *val = adev->dm.dc->debug.visual_confirm;
+ *val = dc_get_debug_options(adev->dm.dc)->visual_confirm;
return 0;
}
@@ -4570,9 +4569,9 @@ static int skip_detection_link_training_set(void *data, u64 val)
struct amdgpu_device *adev = data;
if (val == 0)
- adev->dm.dc->debug.skip_detection_link_training = false;
+ dc_get_debug_options_mutable(adev->dm.dc)->skip_detection_link_training = false;
else
- adev->dm.dc->debug.skip_detection_link_training = true;
+ dc_get_debug_options_mutable(adev->dm.dc)->skip_detection_link_training = true;
return 0;
}
@@ -4585,7 +4584,7 @@ static int skip_detection_link_training_get(void *data, u64 *val)
{
struct amdgpu_device *adev = data;
- *val = adev->dm.dc->debug.skip_detection_link_training;
+ *val = dc_get_debug_options(adev->dm.dc)->skip_detection_link_training;
return 0;
}
@@ -4610,7 +4609,7 @@ static ssize_t dcc_en_bits_read(
const uint32_t rd_buf_size = 32;
uint32_t result = 0;
int offset = 0;
- int num_pipes = dc->res_pool->pipe_count;
+ int num_pipes = dc_get_res_pool(dc)->pipe_count;
int *dcc_en_bits;
int i, r;
@@ -4618,13 +4617,11 @@ static ssize_t dcc_en_bits_read(
if (!dcc_en_bits)
return -ENOMEM;
- if (!dc->hwss.get_dcc_en_bits) {
+ if (!dc_get_dcc_en_bits(dc, dcc_en_bits)) {
kfree(dcc_en_bits);
return 0;
}
- dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
-
rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
if (!rd_buf) {
kfree(dcc_en_bits);
@@ -4714,7 +4711,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
&disable_hpd_ops);
- if (adev->dm.dc->caps.ips_support) {
+ if (dc_get_caps(adev->dm.dc)->ips_support) {
debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,
&ips_status_fops);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 15a203fbae81..2803471d7333 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -57,6 +57,12 @@ const struct dc_config *dc_get_config(const struct dc *dc)
return &dc->config;
}
+void dc_set_allow_edp_hotplug_detection(struct dc *dc,
+ enum dc_hpd_enable_select hpd_select)
+{
+ dc->config.allow_edp_hotplug_detection = hpd_select;
+}
+
const struct dc_debug_options *dc_get_debug_options(const struct dc *dc)
{
return &dc->debug;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9592a95544ea..082435846ee9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -2488,6 +2488,13 @@ const struct dc_caps *dc_get_caps(const struct dc *dc);
/* Configuration captured at dc_create() time. Read-only. */
const struct dc_config *dc_get_config(const struct dc *dc);
+/*
+ * Select which eDP connectors get hotplug detection enabled; see
+ * enum dc_hpd_enable_select. Runtime configurable (debugfs).
+ */
+void dc_set_allow_edp_hotplug_detection(struct dc *dc,
+ enum dc_hpd_enable_select hpd_select);
+
/* Debug overrides (module parameters, debugfs). Read-only view. */
const struct dc_debug_options *dc_get_debug_options(const struct dc *dc);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 09/19] drm/amd/display/amdgpu_dm: Use DC accessors in debugfs paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 1:53 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 1:53 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found no new issues
in this patch, but noticed 1 related pre-existing issue it does not
introduce:
- [Critical] drm/amd/display: use-after-free in dp_dsc_clock_en_write()
[1]
--
commit 8d9d786f748dd7764b2335ea8779ba852b1d97b2
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display/amdgpu_dm: Use DC accessors in debugfs paths
This commit replaces direct struct dc member dereferences in
amdgpu_dm_debugfs.c with DC accessor functions and adds a setter for the
eDP hotplug detection mode.
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
> index 68356cb8e4dec..fddb47a32fb9e 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
[ ... ]
> @@ -1696,7 +1696,7 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
> }
>
> for (i = 0; i < MAX_PIPES; i++) {
> - pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
> + pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
> if (pipe_ctx->stream &&
> pipe_ctx->stream->link == aconnector->dc_link &&
> pipe_ctx->stream->sink &&
[Severity: Critical]
This problem wasn't introduced by this patch, but can a concurrent atomic
commit free current_state while dp_dsc_clock_en_write() iterates over
res_ctx.pipe_ctx[] [1]?
dp_dsc_clock_en_write() walks dc_get_current_state()->res_ctx.pipe_ctx[]
before taking dev->mode_config.mutex and dev->mode_config.connection_mutex:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:dp_dsc_clock_en_write() {
...
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = &dc_get_current_state(aconnector->dc_link->dc)->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream &&
...
break;
}
if (!pipe_ctx->stream)
goto done;
// Get CRTC state
mutex_lock(&dev->mode_config.mutex);
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
...
}
CPU0 CPU1
dp_dsc_clock_en_write()
state = dc_get_current_state(dc)
amdgpu_dm_atomic_commit_tail()
...
dc_state_release(old_state)
pipe_ctx = &state->res_ctx.pipe_ctx[i]
if (pipe_ctx->stream && ...) <-- use-after-free
If an atomic modeset commit swaps out and frees current_state during the
unlocked loop, dp_dsc_clock_en_write() dereferences freed memory.
[1] https://sashiko.dev/#/bug/linux-3a852cda-9b25-49c2-b119-47f2a71a94c3
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=9
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 10/19] drm/amd/display/amdgpu_dm: Use DC accessors in the DM core paths
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm.c: dmub context access, caps reads (cursor size,
plane/stream/link counts, IPS, planes array), the module parameter
debug overrides, current_state access across suspend/resume and
master-sync, link iteration, and the DMCU/ABM resource pool reads.
With this, no production code outside DC dereferences struct dc
members anymore; only the amdgpu_dm KUnit tests remain.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 141 ++++++++++++----------
1 file changed, 74 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 94d45e5d2a3b..cab39aa4d41f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -150,7 +150,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc)
{
- if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)
+ if (dc_get_ctx(dc)->dmub_srv && !dc_get_ctx(dc)->dmub_srv->idle_exit_counter)
dc_exit_ips_for_hw_access(dc);
}
@@ -204,7 +204,7 @@ STATIC_IFN_KUNIT int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc
return 0;
}
- if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
+ if (dc && dc_get_caps(dc)->ips_support && dc_is_idle_optimizations_allowed(dc))
dc_allow_idle_optimizations(dc, false);
/*
@@ -486,6 +486,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
{
struct dc_init_data init_data;
struct dc_callback_init init_params;
+ struct dc_debug_options *debug_opts;
int r;
adev->dm.ddev = adev_to_drm(adev);
@@ -650,62 +651,65 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (adev->dm.dc) {
drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER,
- dce_version_to_string(adev->dm.dc->ctx->dce_version));
+ dce_version_to_string(dc_get_dce_version(adev->dm.dc)));
} else {
drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER);
goto error;
}
+ debug_opts = dc_get_debug_options_mutable(adev->dm.dc);
+
if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
- adev->dm.dc->debug.force_single_disp_pipe_split = false;
- adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
+ debug_opts->force_single_disp_pipe_split = false;
+ debug_opts->pipe_split_policy = MPC_SPLIT_AVOID;
}
if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
- adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
+ debug_opts->disable_stutter =
+ amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
if (dm_should_disable_stutter(adev->pdev))
- adev->dm.dc->debug.disable_stutter = true;
+ debug_opts->disable_stutter = true;
if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
- adev->dm.dc->debug.disable_stutter = true;
+ debug_opts->disable_stutter = true;
if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
- adev->dm.dc->debug.disable_dsc = true;
+ debug_opts->disable_dsc = true;
if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
- adev->dm.dc->debug.disable_clock_gate = true;
+ debug_opts->disable_clock_gate = true;
if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
- adev->dm.dc->debug.force_subvp_mclk_switch = true;
+ debug_opts->force_subvp_mclk_switch = true;
if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) {
- adev->dm.dc->debug.force_disable_subvp = true;
- adev->dm.dc->debug.fams2_config.bits.enable = false;
+ debug_opts->force_disable_subvp = true;
+ debug_opts->fams2_config.bits.enable = false;
}
if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) {
- adev->dm.dc->debug.using_dml2 = true;
- adev->dm.dc->debug.using_dml21 = true;
+ debug_opts->using_dml2 = true;
+ debug_opts->using_dml21 = true;
}
if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE)
- adev->dm.dc->debug.hdcp_lc_force_fw_enable = true;
+ debug_opts->hdcp_lc_force_fw_enable = true;
if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK)
- adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true;
+ debug_opts->hdcp_lc_enable_sw_fallback = true;
if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT)
- adev->dm.dc->debug.skip_detection_link_training = true;
+ debug_opts->skip_detection_link_training = true;
- adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
+ debug_opts->visual_confirm = amdgpu_dc_visual_confirm;
/* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
- adev->dm.dc->debug.ignore_cable_id = true;
+ debug_opts->ignore_cable_id = true;
/* temporary enable immediate restore for FAMS2 */
- adev->dm.dc->debug.fams2_imm_restore_drr = true;
+ debug_opts->fams2_imm_restore_drr = true;
- if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
+ if (dc_get_caps(adev->dm.dc)->dp_hdmi21_pcon_support)
drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n");
r = dm_dmub_hw_init(adev);
@@ -749,18 +753,18 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
amdgpu_dm_init_color_mod();
- if (adev->dm.dc->caps.max_links > 0) {
+ if (dc_get_caps(adev->dm.dc)->max_links > 0) {
adev->dm.vblank_control_workqueue =
create_singlethread_workqueue("dm_vblank_control_workqueue");
if (!adev->dm.vblank_control_workqueue)
drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n");
}
- if (adev->dm.dc->caps.ips_support &&
- adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL)
+ if (dc_get_caps(adev->dm.dc)->ips_support &&
+ dc_get_config(adev->dm.dc)->disable_ips != DMUB_IPS_DISABLE_ALL)
adev->dm.idle_workqueue = idle_create_workqueue(adev);
- if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
+ if (dc_get_caps(adev->dm.dc)->max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
if (!adev->dm.hdcp_workqueue)
@@ -772,7 +776,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
dc_init_callbacks(adev->dm.dc, &init_params);
}
- if (adev->dm.dc->caps.max_links > 0) {
+ if (dc_get_caps(adev->dm.dc)->max_links > 0) {
adev->dm.hdmi_frl_status_polling_wq =
create_singlethread_workqueue("hdmi_frl_status_polling_wq");
if (!adev->dm.hdmi_frl_status_polling_wq)
@@ -836,8 +840,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
/* TODO: Add_display_info? */
/* TODO use dynamic cursor width */
- adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
- adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
+ adev_to_drm(adev)->mode_config.cursor_width = dc_get_caps(adev->dm.dc)->max_cursor_size;
+ adev_to_drm(adev)->mode_config.cursor_height = dc_get_caps(adev->dm.dc)->max_cursor_size;
if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
drm_err(adev_to_drm(adev),
@@ -925,7 +929,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
if (adev->dm.dc) {
dc_deinit_callbacks(adev->dm.dc);
- dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
+ dc_dmub_srv_destroy(&dc_get_ctx(adev->dm.dc)->dmub_srv);
if (dc_enable_dmub_notifications(adev->dm.dc)) {
kfree(adev->dm.dmub_notify);
adev->dm.dmub_notify = NULL;
@@ -945,7 +949,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
&adev->dm.boot_time_crc_info.cpu_addr);
if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {
- for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
+ for (i = 0; i < dc_get_caps(adev->dm.dc)->max_links; i++) {
if (adev->dm.hpd_rx_offload_wq[i].wq) {
destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
adev->dm.hpd_rx_offload_wq[i].wq = NULL;
@@ -1157,11 +1161,11 @@ static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev)
const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */
if (!adev || !adev->dm.dc || !adev->dm.dc->ctx ||
- !adev->dm.dc->ctx->dmub_srv) {
+ !dc_get_ctx(adev->dm.dc)->dmub_srv) {
return;
}
- dmub = adev->dm.dc->ctx->dmub_srv->dmub;
+ dmub = dc_get_ctx(adev->dm.dc)->dmub_srv->dmub;
bootcrc_info = &adev->dm.boot_time_crc_info;
if (!dmub || !dmub->hw_funcs.get_fw_boot_option) {
@@ -1205,7 +1209,7 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
int i;
struct dmcu *dmcu = NULL;
- dmcu = adev->dm.dc->res_pool->dmcu;
+ dmcu = dc_get_res_pool(adev->dm.dc)->dmcu;
/* Init the boot time CRC (skip in resume) */
if ((adev->in_suspend == 0) &&
@@ -1233,13 +1237,13 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
if (dmcu) {
if (!dmcu_load_iram(dmcu, params))
return -EINVAL;
- } else if (adev->dm.dc->ctx->dmub_srv) {
+ } else if (dc_get_ctx(adev->dm.dc)->dmub_srv) {
struct dc_link *edp_links[MAX_NUM_EDP];
int edp_num;
dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
for (i = 0; i < edp_num; i++) {
- if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
+ if (!dmub_init_abm_config(dc_get_res_pool(adev->dm.dc), params, i))
return -EINVAL;
}
}
@@ -1460,7 +1464,7 @@ STATIC_IFN_KUNIT void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n",
enable ? "enable" : "disable");
- if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {
+ if (dc_supports_vrr(dc_get_dce_version(adev->dm.dc))) {
if (enable) {
if (amdgpu_dm_crtc_vrr_active(
to_dm_crtc_state(acrtc->base.state)))
@@ -1620,7 +1624,7 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block)
amdgpu_dm_ism_force_full_power(dm);
dc_allow_idle_optimizations(adev->dm.dc, false);
- dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);
+ dm->cached_dc_state = dc_state_create_copy(dc_get_current_state(dm->dc));
if (!dm->cached_dc_state) {
drm_err(adev_to_drm(adev),
"Failed to allocate cached DC state during suspend\n");
@@ -1671,10 +1675,10 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block)
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
- if (dm->dc->caps.ips_support && adev->in_s0ix)
+ if (dc_get_caps(dm->dc)->ips_support && adev->in_s0ix)
dc_allow_idle_optimizations(dm->dc, true);
- dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
+ dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
return 0;
}
@@ -1837,8 +1841,8 @@ STATIC_IFN_KUNIT void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev)
if (!dc)
return;
- for (li = 0; li < dc->link_count; li++) {
- struct dc_link *l = dc->links[li];
+ for (li = 0; li < dc_get_link_count(dc); li++) {
+ struct dc_link *l = dc_get_link_at_index(dc, li);
const char *name = NULL;
int rs;
@@ -1896,14 +1900,15 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
int i, r, j;
struct dc_commit_streams_params commit_params = {};
- if (dm->dc->caps.ips_support) {
+ if (dc_get_caps(dm->dc)->ips_support) {
if (!amdgpu_in_reset(adev))
mutex_lock(&dm->dc_lock);
/* Need to set POWER_STATE_D0 first or it will not execute
* idle_power_optimizations command to DMUB.
*/
- dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
+ dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv,
+ DC_ACPI_CM_POWER_STATE_D0);
dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
if (!amdgpu_in_reset(adev))
@@ -1914,7 +1919,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
dc_state = dm->cached_dc_state;
/*
- * The dc->current_state is backed up into dm->cached_dc_state
+ * The dc_get_current_state(dc) is backed up into dm->cached_dc_state
* before we commit 0 streams.
*
* DC will clear link encoder assignments on the real state
@@ -1928,7 +1933,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
* We lose the previous assignments, but we had already
* commit 0 streams anyway.
*/
- link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
+ link_enc_cfg_copy(dc_get_current_state(adev->dm.dc), dc_state);
r = dm_dmub_hw_init(adev);
if (r) {
@@ -1939,7 +1944,8 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
return r;
}
- dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
+ dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv,
+ DC_ACPI_CM_POWER_STATE_D0);
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
dc_resume(dm->dc);
@@ -1998,7 +2004,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
}
/* power on hardware */
- dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
+ dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
/* program HPD filter */
@@ -2340,7 +2346,7 @@ STATIC_IFN_KUNIT int initialize_plane(struct amdgpu_display_manager *dm,
* for a CRTC - like overlay or underlay planes.
*/
possible_crtcs = 1 << plane_id;
- if (plane_id >= dm->dc->caps.max_streams)
+ if (plane_id >= dc_get_caps(dm->dc)->max_streams)
possible_crtcs = 0xff;
ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
@@ -2380,22 +2386,22 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
const struct dc_plane_cap *plane;
bool psr_feature_enabled = false;
bool replay_feature_enabled = false;
- int max_overlay = dm->dc->caps.max_slave_planes;
+ int max_overlay = dc_get_caps(dm->dc)->max_slave_planes;
- dm->display_indexes_num = dm->dc->caps.max_streams;
+ dm->display_indexes_num = dc_get_caps(dm->dc)->max_streams;
/* Update the actual used number of crtc */
adev->mode_info.num_crtc = adev->dm.display_indexes_num;
amdgpu_dm_set_irq_funcs(adev);
- link_cnt = dm->dc->caps.max_links;
+ link_cnt = dc_get_caps(dm->dc)->max_links;
if (amdgpu_dm_mode_config_init(dm->adev)) {
drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n");
return -EINVAL;
}
/* There is one primary plane per CRTC */
- primary_planes = dm->dc->caps.max_streams;
+ primary_planes = dc_get_caps(dm->dc)->max_streams;
if (primary_planes > AMDGPU_MAX_PLANES) {
drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n");
return -EINVAL;
@@ -2406,7 +2412,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
* Order is reversed to match iteration order in atomic check.
*/
for (i = (primary_planes - 1); i >= 0; i--) {
- plane = &dm->dc->caps.planes[i];
+ plane = &dc_get_caps(dm->dc)->planes[i];
if (initialize_plane(dm, mode_info, i,
DRM_PLANE_TYPE_PRIMARY, plane)) {
@@ -2424,8 +2430,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
* Only support DCN for now, and only expose one so we don't encourage
* userspace to use up all the pipes.
*/
- for (i = 0; i < dm->dc->caps.max_planes; ++i) {
- struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
+ for (i = 0; i < dc_get_caps(dm->dc)->max_planes; ++i) {
+ const struct dc_plane_cap *plane = &dc_get_caps(dm->dc)->planes[i];
/* Do not create overlay if MPO disabled */
if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
@@ -2447,7 +2453,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
}
}
- for (i = 0; i < dm->dc->caps.max_streams; i++)
+ for (i = 0; i < dc_get_caps(dm->dc)->max_streams; i++)
if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n");
goto fail;
@@ -3717,7 +3723,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_update_cursor(struct drm_plane *plane,
* legacy gamma setup.
*/
if (crtc_state->cm_is_degamma_srgb &&
- adev->dm.dc->caps.color.dpp.gamma_corr)
+ dc_get_caps(adev->dm.dc)->color.dpp.gamma_corr)
attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
if (afb)
@@ -4843,8 +4849,9 @@ dm_set_writeback(struct amdgpu_display_manager *dm,
}
for (i = 0; i < MAX_PIPES; i++) {
- if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
- pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];
+ if (dc_get_current_state(dm->dc)->res_ctx.pipe_ctx[i].stream ==
+ crtc_state->stream) {
+ pipe = &dc_get_current_state(dm->dc)->res_ctx.pipe_ctx[i];
break;
}
}
@@ -6795,14 +6802,14 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
int i;
mutex_lock(&adev->dm.dc_lock);
- if (dc->current_state) {
- for (i = 0; i < dc->current_state->stream_count; ++i)
- dc->current_state->streams[i]
+ if (dc_get_current_state(dc)) {
+ for (i = 0; i < dc_get_current_state(dc)->stream_count; ++i)
+ dc_get_current_state(dc)->streams[i]
->triggered_crtc_reset.enabled =
adev->dm.force_timing_sync;
- dm_enable_per_frame_crtc_master_sync(dc->current_state);
- dc_trigger_sync(dc, dc->current_state);
+ dm_enable_per_frame_crtc_master_sync(dc_get_current_state(dc));
+ dc_trigger_sync(dc, dc_get_current_state(dc));
}
mutex_unlock(&adev->dm.dc_lock);
}
@@ -6872,8 +6879,8 @@ void amdgpu_dm_update_memclk_states(struct amdgpu_device *adev)
if (!dc)
return;
- if (dc->ctx->dce_version != DCN_VERSION_3_2 &&
- dc->ctx->dce_version != DCN_VERSION_3_21)
+ if (dc_get_dce_version(dc) != DCN_VERSION_3_2 &&
+ dc_get_dce_version(dc) != DCN_VERSION_3_21)
return;
mutex_lock(&adev->dm.dc_lock);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 10/19] drm/amd/display/amdgpu_dm: Use DC accessors in the DM core paths
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Replace direct struct dc member dereferences with the DC accessor
layer in amdgpu_dm.c: dmub context access, caps reads (cursor size,
plane/stream/link counts, IPS, planes array), the module parameter
debug overrides, current_state access across suspend/resume and
master-sync, link iteration, and the DMCU/ABM resource pool reads.
With this, no production code outside DC dereferences struct dc
members anymore; only the amdgpu_dm KUnit tests remain.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 141 ++++++++++++----------
1 file changed, 74 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 94d45e5d2a3b..cab39aa4d41f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -150,7 +150,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc)
{
- if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)
+ if (dc_get_ctx(dc)->dmub_srv && !dc_get_ctx(dc)->dmub_srv->idle_exit_counter)
dc_exit_ips_for_hw_access(dc);
}
@@ -204,7 +204,7 @@ STATIC_IFN_KUNIT int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc
return 0;
}
- if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed)
+ if (dc && dc_get_caps(dc)->ips_support && dc_is_idle_optimizations_allowed(dc))
dc_allow_idle_optimizations(dc, false);
/*
@@ -486,6 +486,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
{
struct dc_init_data init_data;
struct dc_callback_init init_params;
+ struct dc_debug_options *debug_opts;
int r;
adev->dm.ddev = adev_to_drm(adev);
@@ -650,62 +651,65 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (adev->dm.dc) {
drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER,
- dce_version_to_string(adev->dm.dc->ctx->dce_version));
+ dce_version_to_string(dc_get_dce_version(adev->dm.dc)));
} else {
drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER);
goto error;
}
+ debug_opts = dc_get_debug_options_mutable(adev->dm.dc);
+
if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
- adev->dm.dc->debug.force_single_disp_pipe_split = false;
- adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
+ debug_opts->force_single_disp_pipe_split = false;
+ debug_opts->pipe_split_policy = MPC_SPLIT_AVOID;
}
if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
- adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
+ debug_opts->disable_stutter =
+ amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
if (dm_should_disable_stutter(adev->pdev))
- adev->dm.dc->debug.disable_stutter = true;
+ debug_opts->disable_stutter = true;
if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
- adev->dm.dc->debug.disable_stutter = true;
+ debug_opts->disable_stutter = true;
if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
- adev->dm.dc->debug.disable_dsc = true;
+ debug_opts->disable_dsc = true;
if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
- adev->dm.dc->debug.disable_clock_gate = true;
+ debug_opts->disable_clock_gate = true;
if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
- adev->dm.dc->debug.force_subvp_mclk_switch = true;
+ debug_opts->force_subvp_mclk_switch = true;
if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) {
- adev->dm.dc->debug.force_disable_subvp = true;
- adev->dm.dc->debug.fams2_config.bits.enable = false;
+ debug_opts->force_disable_subvp = true;
+ debug_opts->fams2_config.bits.enable = false;
}
if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) {
- adev->dm.dc->debug.using_dml2 = true;
- adev->dm.dc->debug.using_dml21 = true;
+ debug_opts->using_dml2 = true;
+ debug_opts->using_dml21 = true;
}
if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE)
- adev->dm.dc->debug.hdcp_lc_force_fw_enable = true;
+ debug_opts->hdcp_lc_force_fw_enable = true;
if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK)
- adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true;
+ debug_opts->hdcp_lc_enable_sw_fallback = true;
if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT)
- adev->dm.dc->debug.skip_detection_link_training = true;
+ debug_opts->skip_detection_link_training = true;
- adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
+ debug_opts->visual_confirm = amdgpu_dc_visual_confirm;
/* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
- adev->dm.dc->debug.ignore_cable_id = true;
+ debug_opts->ignore_cable_id = true;
/* temporary enable immediate restore for FAMS2 */
- adev->dm.dc->debug.fams2_imm_restore_drr = true;
+ debug_opts->fams2_imm_restore_drr = true;
- if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
+ if (dc_get_caps(adev->dm.dc)->dp_hdmi21_pcon_support)
drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n");
r = dm_dmub_hw_init(adev);
@@ -749,18 +753,18 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
amdgpu_dm_init_color_mod();
- if (adev->dm.dc->caps.max_links > 0) {
+ if (dc_get_caps(adev->dm.dc)->max_links > 0) {
adev->dm.vblank_control_workqueue =
create_singlethread_workqueue("dm_vblank_control_workqueue");
if (!adev->dm.vblank_control_workqueue)
drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n");
}
- if (adev->dm.dc->caps.ips_support &&
- adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL)
+ if (dc_get_caps(adev->dm.dc)->ips_support &&
+ dc_get_config(adev->dm.dc)->disable_ips != DMUB_IPS_DISABLE_ALL)
adev->dm.idle_workqueue = idle_create_workqueue(adev);
- if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
+ if (dc_get_caps(adev->dm.dc)->max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
if (!adev->dm.hdcp_workqueue)
@@ -772,7 +776,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
dc_init_callbacks(adev->dm.dc, &init_params);
}
- if (adev->dm.dc->caps.max_links > 0) {
+ if (dc_get_caps(adev->dm.dc)->max_links > 0) {
adev->dm.hdmi_frl_status_polling_wq =
create_singlethread_workqueue("hdmi_frl_status_polling_wq");
if (!adev->dm.hdmi_frl_status_polling_wq)
@@ -836,8 +840,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
/* TODO: Add_display_info? */
/* TODO use dynamic cursor width */
- adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
- adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
+ adev_to_drm(adev)->mode_config.cursor_width = dc_get_caps(adev->dm.dc)->max_cursor_size;
+ adev_to_drm(adev)->mode_config.cursor_height = dc_get_caps(adev->dm.dc)->max_cursor_size;
if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
drm_err(adev_to_drm(adev),
@@ -925,7 +929,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
if (adev->dm.dc) {
dc_deinit_callbacks(adev->dm.dc);
- dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
+ dc_dmub_srv_destroy(&dc_get_ctx(adev->dm.dc)->dmub_srv);
if (dc_enable_dmub_notifications(adev->dm.dc)) {
kfree(adev->dm.dmub_notify);
adev->dm.dmub_notify = NULL;
@@ -945,7 +949,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
&adev->dm.boot_time_crc_info.cpu_addr);
if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {
- for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
+ for (i = 0; i < dc_get_caps(adev->dm.dc)->max_links; i++) {
if (adev->dm.hpd_rx_offload_wq[i].wq) {
destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
adev->dm.hpd_rx_offload_wq[i].wq = NULL;
@@ -1157,11 +1161,11 @@ static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev)
const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */
if (!adev || !adev->dm.dc || !adev->dm.dc->ctx ||
- !adev->dm.dc->ctx->dmub_srv) {
+ !dc_get_ctx(adev->dm.dc)->dmub_srv) {
return;
}
- dmub = adev->dm.dc->ctx->dmub_srv->dmub;
+ dmub = dc_get_ctx(adev->dm.dc)->dmub_srv->dmub;
bootcrc_info = &adev->dm.boot_time_crc_info;
if (!dmub || !dmub->hw_funcs.get_fw_boot_option) {
@@ -1205,7 +1209,7 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
int i;
struct dmcu *dmcu = NULL;
- dmcu = adev->dm.dc->res_pool->dmcu;
+ dmcu = dc_get_res_pool(adev->dm.dc)->dmcu;
/* Init the boot time CRC (skip in resume) */
if ((adev->in_suspend == 0) &&
@@ -1233,13 +1237,13 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
if (dmcu) {
if (!dmcu_load_iram(dmcu, params))
return -EINVAL;
- } else if (adev->dm.dc->ctx->dmub_srv) {
+ } else if (dc_get_ctx(adev->dm.dc)->dmub_srv) {
struct dc_link *edp_links[MAX_NUM_EDP];
int edp_num;
dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
for (i = 0; i < edp_num; i++) {
- if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
+ if (!dmub_init_abm_config(dc_get_res_pool(adev->dm.dc), params, i))
return -EINVAL;
}
}
@@ -1460,7 +1464,7 @@ STATIC_IFN_KUNIT void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n",
enable ? "enable" : "disable");
- if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {
+ if (dc_supports_vrr(dc_get_dce_version(adev->dm.dc))) {
if (enable) {
if (amdgpu_dm_crtc_vrr_active(
to_dm_crtc_state(acrtc->base.state)))
@@ -1620,7 +1624,7 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block)
amdgpu_dm_ism_force_full_power(dm);
dc_allow_idle_optimizations(adev->dm.dc, false);
- dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state);
+ dm->cached_dc_state = dc_state_create_copy(dc_get_current_state(dm->dc));
if (!dm->cached_dc_state) {
drm_err(adev_to_drm(adev),
"Failed to allocate cached DC state during suspend\n");
@@ -1671,10 +1675,10 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block)
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
- if (dm->dc->caps.ips_support && adev->in_s0ix)
+ if (dc_get_caps(dm->dc)->ips_support && adev->in_s0ix)
dc_allow_idle_optimizations(dm->dc, true);
- dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
+ dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
return 0;
}
@@ -1837,8 +1841,8 @@ STATIC_IFN_KUNIT void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev)
if (!dc)
return;
- for (li = 0; li < dc->link_count; li++) {
- struct dc_link *l = dc->links[li];
+ for (li = 0; li < dc_get_link_count(dc); li++) {
+ struct dc_link *l = dc_get_link_at_index(dc, li);
const char *name = NULL;
int rs;
@@ -1896,14 +1900,15 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
int i, r, j;
struct dc_commit_streams_params commit_params = {};
- if (dm->dc->caps.ips_support) {
+ if (dc_get_caps(dm->dc)->ips_support) {
if (!amdgpu_in_reset(adev))
mutex_lock(&dm->dc_lock);
/* Need to set POWER_STATE_D0 first or it will not execute
* idle_power_optimizations command to DMUB.
*/
- dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
+ dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv,
+ DC_ACPI_CM_POWER_STATE_D0);
dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
if (!amdgpu_in_reset(adev))
@@ -1914,7 +1919,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
dc_state = dm->cached_dc_state;
/*
- * The dc->current_state is backed up into dm->cached_dc_state
+ * The dc_get_current_state(dc) is backed up into dm->cached_dc_state
* before we commit 0 streams.
*
* DC will clear link encoder assignments on the real state
@@ -1928,7 +1933,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
* We lose the previous assignments, but we had already
* commit 0 streams anyway.
*/
- link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
+ link_enc_cfg_copy(dc_get_current_state(adev->dm.dc), dc_state);
r = dm_dmub_hw_init(adev);
if (r) {
@@ -1939,7 +1944,8 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
return r;
}
- dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
+ dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv,
+ DC_ACPI_CM_POWER_STATE_D0);
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
dc_resume(dm->dc);
@@ -1998,7 +2004,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
}
/* power on hardware */
- dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
+ dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
/* program HPD filter */
@@ -2340,7 +2346,7 @@ STATIC_IFN_KUNIT int initialize_plane(struct amdgpu_display_manager *dm,
* for a CRTC - like overlay or underlay planes.
*/
possible_crtcs = 1 << plane_id;
- if (plane_id >= dm->dc->caps.max_streams)
+ if (plane_id >= dc_get_caps(dm->dc)->max_streams)
possible_crtcs = 0xff;
ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
@@ -2380,22 +2386,22 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
const struct dc_plane_cap *plane;
bool psr_feature_enabled = false;
bool replay_feature_enabled = false;
- int max_overlay = dm->dc->caps.max_slave_planes;
+ int max_overlay = dc_get_caps(dm->dc)->max_slave_planes;
- dm->display_indexes_num = dm->dc->caps.max_streams;
+ dm->display_indexes_num = dc_get_caps(dm->dc)->max_streams;
/* Update the actual used number of crtc */
adev->mode_info.num_crtc = adev->dm.display_indexes_num;
amdgpu_dm_set_irq_funcs(adev);
- link_cnt = dm->dc->caps.max_links;
+ link_cnt = dc_get_caps(dm->dc)->max_links;
if (amdgpu_dm_mode_config_init(dm->adev)) {
drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n");
return -EINVAL;
}
/* There is one primary plane per CRTC */
- primary_planes = dm->dc->caps.max_streams;
+ primary_planes = dc_get_caps(dm->dc)->max_streams;
if (primary_planes > AMDGPU_MAX_PLANES) {
drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n");
return -EINVAL;
@@ -2406,7 +2412,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
* Order is reversed to match iteration order in atomic check.
*/
for (i = (primary_planes - 1); i >= 0; i--) {
- plane = &dm->dc->caps.planes[i];
+ plane = &dc_get_caps(dm->dc)->planes[i];
if (initialize_plane(dm, mode_info, i,
DRM_PLANE_TYPE_PRIMARY, plane)) {
@@ -2424,8 +2430,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
* Only support DCN for now, and only expose one so we don't encourage
* userspace to use up all the pipes.
*/
- for (i = 0; i < dm->dc->caps.max_planes; ++i) {
- struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
+ for (i = 0; i < dc_get_caps(dm->dc)->max_planes; ++i) {
+ const struct dc_plane_cap *plane = &dc_get_caps(dm->dc)->planes[i];
/* Do not create overlay if MPO disabled */
if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
@@ -2447,7 +2453,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
}
}
- for (i = 0; i < dm->dc->caps.max_streams; i++)
+ for (i = 0; i < dc_get_caps(dm->dc)->max_streams; i++)
if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n");
goto fail;
@@ -3717,7 +3723,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_update_cursor(struct drm_plane *plane,
* legacy gamma setup.
*/
if (crtc_state->cm_is_degamma_srgb &&
- adev->dm.dc->caps.color.dpp.gamma_corr)
+ dc_get_caps(adev->dm.dc)->color.dpp.gamma_corr)
attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
if (afb)
@@ -4843,8 +4849,9 @@ dm_set_writeback(struct amdgpu_display_manager *dm,
}
for (i = 0; i < MAX_PIPES; i++) {
- if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
- pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i];
+ if (dc_get_current_state(dm->dc)->res_ctx.pipe_ctx[i].stream ==
+ crtc_state->stream) {
+ pipe = &dc_get_current_state(dm->dc)->res_ctx.pipe_ctx[i];
break;
}
}
@@ -6795,14 +6802,14 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
int i;
mutex_lock(&adev->dm.dc_lock);
- if (dc->current_state) {
- for (i = 0; i < dc->current_state->stream_count; ++i)
- dc->current_state->streams[i]
+ if (dc_get_current_state(dc)) {
+ for (i = 0; i < dc_get_current_state(dc)->stream_count; ++i)
+ dc_get_current_state(dc)->streams[i]
->triggered_crtc_reset.enabled =
adev->dm.force_timing_sync;
- dm_enable_per_frame_crtc_master_sync(dc->current_state);
- dc_trigger_sync(dc, dc->current_state);
+ dm_enable_per_frame_crtc_master_sync(dc_get_current_state(dc));
+ dc_trigger_sync(dc, dc_get_current_state(dc));
}
mutex_unlock(&adev->dm.dc_lock);
}
@@ -6872,8 +6879,8 @@ void amdgpu_dm_update_memclk_states(struct amdgpu_device *adev)
if (!dc)
return;
- if (dc->ctx->dce_version != DCN_VERSION_3_2 &&
- dc->ctx->dce_version != DCN_VERSION_3_21)
+ if (dc_get_dce_version(dc) != DCN_VERSION_3_2 &&
+ dc_get_dce_version(dc) != DCN_VERSION_3_21)
return;
mutex_lock(&adev->dm.dc_lock);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 11/19] drm/amd/display/amdgpu_dm: Finish DC accessor migration for non-test code
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Convert the last struct dc member dereferences outside DC (crtc,
irq, mst_types, amdgpu_dm ctx NULL check) to the accessor layer, and
move the PERFORMANCE_TRACE_{START,END} macros, which dereference a
dc-local variable, from the public logger_interface.h into
dc/dm_services.h where their users live.
No production code outside the dc directory dereferences struct dc
members anymore. Only the amdgpu_dm KUnit tests remain to migrate.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 26 +++++++++++++---------
drivers/gpu/drm/amd/display/dc/dm_services.h | 16 +++++++++++++
.../gpu/drm/amd/display/include/logger_interface.h | 12 ----------
6 files changed, 34 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cab39aa4d41f..3458b26846a1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1160,7 +1160,7 @@ static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev)
int ret = 0;
const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */
- if (!adev || !adev->dm.dc || !adev->dm.dc->ctx ||
+ if (!adev || !adev->dm.dc || !dc_get_ctx(adev->dm.dc) ||
!dc_get_ctx(adev->dm.dc)->dmub_srv) {
return;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 334e33b1c4f4..9c607ecc4bd6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -831,7 +831,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
* both is rejected.
*/
has_degamma = dc_get_caps(dm->adev->dm.dc)->color.dpp.dcn_arch &&
- dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
+ dc_get_dce_version(dm->adev->dm.dc) != DCN_VERSION_4_01;
drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
true, MAX_COLOR_LUT_ENTRIES);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index a7ee30c66a48..5c3b83f05d2b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -1656,7 +1656,7 @@ STATIC_IFN_KUNIT void dmub_hpd_callback(struct amdgpu_device *adev,
return;
}
- if (notify->link_index > adev->dm.dc->link_count) {
+ if (notify->link_index > dc_get_link_count(adev->dm.dc)) {
drm_err(adev_to_drm(adev), "DMUB HPD index (%u)is abnormal", notify->link_index);
return;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index a3877ef767ec..2cbe08298706 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1239,7 +1239,7 @@ STATIC_IFN_KUNIT bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector,
unsigned int dsc_max_sink_bw_in_kbps = 0;
if (aconnector->dc_sink &&
- aconnector->dc_link->dc->caps.dp_hdmi21_pcon_support &&
+ dc_get_caps(aconnector->dc_link->dc)->dp_hdmi21_pcon_support &&
aconnector->mst_downstream_port_caps.bytes.byte0.bits.DWN_STRM_PORTX_TYPE == DOWN_STREAM_DETAILED_HDMI) {
max_conv_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(
aconnector->dc_link->dc,
@@ -1399,7 +1399,8 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state,
build_frl_mst_dsc_params(aconnector, stream, &dsc_policy, ¶ms[count], frl_conv_dsc_bw_in_kbps);
if (!dc_dsc_compute_bandwidth_range(
stream->sink->ctx->dc,
- stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
+ dc_get_debug_options(
+ stream->sink->ctx->dc)->dsc_min_slice_height_override,
min_target_bpp_x16,
max_target_bpp_x16,
&stream->sink->dsc_caps.dsc_dec_caps,
@@ -1593,13 +1594,13 @@ STATIC_IFN_KUNIT bool is_dsc_need_re_compute(
}
DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in current dc_state\n",
- __func__, dc->current_state->stream_count);
+ __func__, dc_get_current_state(dc)->stream_count);
/* check current_state if there stream on link but it is not in
* new request state
*/
- for (i = 0; i < dc->current_state->stream_count; i++) {
- stream = dc->current_state->streams[i];
+ for (i = 0; i < dc_get_current_state(dc)->stream_count; i++) {
+ stream = dc_get_current_state(dc)->streams[i];
/* only check stream on the mst hub */
if (stream->link != dc_link)
continue;
@@ -1943,12 +1944,15 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
bool is_dsc_possible;
dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
- is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc,
- stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
- dsc_policy.min_target_bpp * 16,
- dsc_policy.max_target_bpp * 16,
- &stream->sink->dsc_caps.dsc_dec_caps,
- &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);
+ is_dsc_possible = dc_dsc_compute_bandwidth_range(
+ stream->sink->ctx->dc,
+ dc_get_debug_options(
+ stream->sink->ctx->dc)->dsc_min_slice_height_override,
+ dsc_policy.min_target_bpp * 16,
+ dsc_policy.max_target_bpp * 16,
+ &stream->sink->dsc_caps.dsc_dec_caps,
+ &stream->timing,
+ dc_link_get_highest_encoding_format(stream->link), bw_range);
return is_dsc_possible;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 2cf4bcb03cb0..6f54f55d260c 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -262,6 +262,22 @@ void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc
#define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__, CTX)
#define PERF_TRACE_CTX(__CTX) dm_perf_trace_timestamp(__func__, __LINE__, __CTX)
+/*
+ * These macros dereference a dc-local variable and are therefore only
+ * usable from DC-internal code.
+ */
+#define PERFORMANCE_TRACE_START() \
+ unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx)
+
+#define PERFORMANCE_TRACE_END() \
+ do { \
+ unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx); \
+ if (dc->debug.performance_trace) { \
+ DC_LOG_PERF_TRACE("%s duration: %lld ticks\n", __func__, \
+ perf_trc_end_stmp - perf_trc_start_stmp); \
+ } \
+ } while (0)
+
/*
* SMU message tracing
*/
diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
index 7dc738b60162..89869c1b0e6a 100644
--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
@@ -125,18 +125,6 @@ void context_clock_trace(
#define DTN_INFO_END() \
dm_dtn_log_end(dc_ctx, log_ctx)
-#define PERFORMANCE_TRACE_START() \
- unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx)
-
-#define PERFORMANCE_TRACE_END() \
- do { \
- unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx); \
- if (dc->debug.performance_trace) { \
- DC_LOG_PERF_TRACE("%s duration: %lld ticks\n", __func__, \
- perf_trc_end_stmp - perf_trc_start_stmp); \
- } \
- } while (0)
-
#define DISPLAY_STATS_BEGIN(entry) (void)(entry)
#define DISPLAY_STATS(msg, ...) DC_LOG_PERF_TRACE(msg, __VA_ARGS__)
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 11/19] drm/amd/display/amdgpu_dm: Finish DC accessor migration for non-test code
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Convert the last struct dc member dereferences outside DC (crtc,
irq, mst_types, amdgpu_dm ctx NULL check) to the accessor layer, and
move the PERFORMANCE_TRACE_{START,END} macros, which dereference a
dc-local variable, from the public logger_interface.h into
dc/dm_services.h where their users live.
No production code outside the dc directory dereferences struct dc
members anymore. Only the amdgpu_dm KUnit tests remain to migrate.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 2 +-
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 26 +++++++++++++---------
drivers/gpu/drm/amd/display/dc/dm_services.h | 16 +++++++++++++
.../gpu/drm/amd/display/include/logger_interface.h | 12 ----------
6 files changed, 34 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cab39aa4d41f..3458b26846a1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1160,7 +1160,7 @@ static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev)
int ret = 0;
const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */
- if (!adev || !adev->dm.dc || !adev->dm.dc->ctx ||
+ if (!adev || !adev->dm.dc || !dc_get_ctx(adev->dm.dc) ||
!dc_get_ctx(adev->dm.dc)->dmub_srv) {
return;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 334e33b1c4f4..9c607ecc4bd6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -831,7 +831,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
* both is rejected.
*/
has_degamma = dc_get_caps(dm->adev->dm.dc)->color.dpp.dcn_arch &&
- dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
+ dc_get_dce_version(dm->adev->dm.dc) != DCN_VERSION_4_01;
drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
true, MAX_COLOR_LUT_ENTRIES);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index a7ee30c66a48..5c3b83f05d2b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -1656,7 +1656,7 @@ STATIC_IFN_KUNIT void dmub_hpd_callback(struct amdgpu_device *adev,
return;
}
- if (notify->link_index > adev->dm.dc->link_count) {
+ if (notify->link_index > dc_get_link_count(adev->dm.dc)) {
drm_err(adev_to_drm(adev), "DMUB HPD index (%u)is abnormal", notify->link_index);
return;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index a3877ef767ec..2cbe08298706 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1239,7 +1239,7 @@ STATIC_IFN_KUNIT bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector,
unsigned int dsc_max_sink_bw_in_kbps = 0;
if (aconnector->dc_sink &&
- aconnector->dc_link->dc->caps.dp_hdmi21_pcon_support &&
+ dc_get_caps(aconnector->dc_link->dc)->dp_hdmi21_pcon_support &&
aconnector->mst_downstream_port_caps.bytes.byte0.bits.DWN_STRM_PORTX_TYPE == DOWN_STREAM_DETAILED_HDMI) {
max_conv_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(
aconnector->dc_link->dc,
@@ -1399,7 +1399,8 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_commit *state,
build_frl_mst_dsc_params(aconnector, stream, &dsc_policy, ¶ms[count], frl_conv_dsc_bw_in_kbps);
if (!dc_dsc_compute_bandwidth_range(
stream->sink->ctx->dc,
- stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
+ dc_get_debug_options(
+ stream->sink->ctx->dc)->dsc_min_slice_height_override,
min_target_bpp_x16,
max_target_bpp_x16,
&stream->sink->dsc_caps.dsc_dec_caps,
@@ -1593,13 +1594,13 @@ STATIC_IFN_KUNIT bool is_dsc_need_re_compute(
}
DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in current dc_state\n",
- __func__, dc->current_state->stream_count);
+ __func__, dc_get_current_state(dc)->stream_count);
/* check current_state if there stream on link but it is not in
* new request state
*/
- for (i = 0; i < dc->current_state->stream_count; i++) {
- stream = dc->current_state->streams[i];
+ for (i = 0; i < dc_get_current_state(dc)->stream_count; i++) {
+ stream = dc_get_current_state(dc)->streams[i];
/* only check stream on the mst hub */
if (stream->link != dc_link)
continue;
@@ -1943,12 +1944,15 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
bool is_dsc_possible;
dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
- is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc,
- stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
- dsc_policy.min_target_bpp * 16,
- dsc_policy.max_target_bpp * 16,
- &stream->sink->dsc_caps.dsc_dec_caps,
- &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);
+ is_dsc_possible = dc_dsc_compute_bandwidth_range(
+ stream->sink->ctx->dc,
+ dc_get_debug_options(
+ stream->sink->ctx->dc)->dsc_min_slice_height_override,
+ dsc_policy.min_target_bpp * 16,
+ dsc_policy.max_target_bpp * 16,
+ &stream->sink->dsc_caps.dsc_dec_caps,
+ &stream->timing,
+ dc_link_get_highest_encoding_format(stream->link), bw_range);
return is_dsc_possible;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 2cf4bcb03cb0..6f54f55d260c 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -262,6 +262,22 @@ void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc
#define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__, CTX)
#define PERF_TRACE_CTX(__CTX) dm_perf_trace_timestamp(__func__, __LINE__, __CTX)
+/*
+ * These macros dereference a dc-local variable and are therefore only
+ * usable from DC-internal code.
+ */
+#define PERFORMANCE_TRACE_START() \
+ unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx)
+
+#define PERFORMANCE_TRACE_END() \
+ do { \
+ unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx); \
+ if (dc->debug.performance_trace) { \
+ DC_LOG_PERF_TRACE("%s duration: %lld ticks\n", __func__, \
+ perf_trc_end_stmp - perf_trc_start_stmp); \
+ } \
+ } while (0)
+
/*
* SMU message tracing
*/
diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
index 7dc738b60162..89869c1b0e6a 100644
--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
@@ -125,18 +125,6 @@ void context_clock_trace(
#define DTN_INFO_END() \
dm_dtn_log_end(dc_ctx, log_ctx)
-#define PERFORMANCE_TRACE_START() \
- unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx)
-
-#define PERFORMANCE_TRACE_END() \
- do { \
- unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx); \
- if (dc->debug.performance_trace) { \
- DC_LOG_PERF_TRACE("%s duration: %lld ticks\n", __func__, \
- perf_trc_end_stmp - perf_trc_start_stmp); \
- } \
- } while (0)
-
#define DISPLAY_STATS_BEGIN(entry) (void)(entry)
#define DISPLAY_STATS(msg, ...) DC_LOG_PERF_TRACE(msg, __VA_ARGS__)
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 11/19] drm/amd/display/amdgpu_dm: Finish DC accessor migration for non-test code
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 1:53 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 1:53 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found no new issues
in this patch, but noticed 1 related pre-existing issue it does not
introduce:
- [High] drm/amd/display: uninitialized stack memory read in
get_conv_frl_bw() [1]
--
commit 7d52238d02a453de3c024a3c4edfc5cc756f0bed
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display/amdgpu_dm: Finish DC accessor migration for non-test code
This commit converts the remaining struct dc member dereferences in
amdgpu_dm production code to use accessor functions and moves the
PERFORMANCE_TRACE_START and PERFORMANCE_TRACE_END macros into
dc/dm_services.h.
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index a3877ef767eca..2cbe08298706a 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -1239,7 +1239,7 @@ STATIC_IFN_KUNIT bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector,
> unsigned int dsc_max_sink_bw_in_kbps = 0;
>
> if (aconnector->dc_sink &&
> - aconnector->dc_link->dc->caps.dp_hdmi21_pcon_support &&
> + dc_get_caps(aconnector->dc_link->dc)->dp_hdmi21_pcon_support &&
> aconnector->mst_downstream_port_caps.bytes.byte0.bits.DWN_STRM_PORTX_TYPE == DOWN_STREAM_DETAILED_HDMI) {
> max_conv_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(
> aconnector->dc_link->dc,
[Severity: High]
This problem wasn't introduced by this patch, but can get_conv_frl_bw()
read uninitialized stack memory from *bw_in_kbps [1]?
compute_mst_dsc_configs_for_link() declares frl_conv_bw_in_kbps and
frl_conv_dsc_bw_in_kbps on the stack without initializing them and passes
them to get_conv_frl_bw():
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c:get_conv_frl_bw() {
if (aconnector->dc_sink &&
dc_get_caps(aconnector->dc_link->dc)->dp_hdmi21_pcon_support &&
aconnector->mst_downstream_port_caps.bytes.byte0.bits.DWN_STRM_PORTX_TYPE == DOWN_STREAM_DETAILED_HDMI) {
...
if (aconnector->dc_sink->edid_caps.max_frl_rate && max_conv_bw_in_kbps) {
...
*bw_in_kbps = min(max_conv_bw_in_kbps, max_sink_bw_in_kbps);
*dsc_bw_in_kbps = min(*bw_in_kbps, dsc_max_sink_bw_in_kbps);
}
}
return *bw_in_kbps > 0; // Frl endpoint is detected
}
When the downstream port is not HDMI 2.1 PCON or max_frl_rate is 0,
neither output pointer is written before *bw_in_kbps > 0 is evaluated.
If stack contents make *bw_in_kbps non-zero, get_conv_frl_bw() returns
true and compute_mst_dsc_configs_for_link() passes the uninitialized
frl_conv_dsc_bw_in_kbps into build_frl_mst_dsc_params().
[1] https://sashiko.dev/#/bug/linux-04300f5e-3be1-4eaf-ab02-d1aa2df32bb9
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=11
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 12/19] drm/amd/display: Migrate amdgpu_dm KUnit tests off struct dc internals
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
The amdgpu_dm KUnit tests constructed fake struct dc instances with
kunit_kzalloc(sizeof(*dc)) and populated members directly. Add a
KUnit-gated test double API in DC (dc/inc/dc_test.h implemented in
dc/core/dc_test.c) that allocates the fake and exposes setters and
mutable views for the members tests need:
- dc_test_create/destroy for the fake instance
- setters for ctx, current_state, link_srv, res_pool, clk_mgr,
fbc_compressor, links[], link_count, idle_optimizations_allowed
- mutable views for caps, config, debug, hwss and cap_funcs
Rework dm_kunit_alloc_dc* helpers on top of it and convert all test
files to the API plus the public accessors (dc_get_ctx,
dc_get_current_state, dc_get_res_pool, dc_get_clk_mgr, ...), which
are exported for the test modules with EXPORT_IF_KUNIT.
No test logic changes; only how the fakes are built.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../display/amdgpu_dm/tests/amdgpu_dm_audio_test.c | 41 ++---
.../amdgpu_dm/tests/amdgpu_dm_backlight_test.c | 71 ++++----
.../display/amdgpu_dm/tests/amdgpu_dm_color_test.c | 21 +--
.../amdgpu_dm/tests/amdgpu_dm_colorop_test.c | 8 +-
.../amdgpu_dm/tests/amdgpu_dm_connector_test.c | 62 ++++---
.../display/amdgpu_dm/tests/amdgpu_dm_crc_test.c | 5 +-
.../display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c | 59 ++++---
.../display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c | 74 ++++----
.../amdgpu_dm/tests/amdgpu_dm_freesync_test.c | 3 +-
.../display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c | 23 ++-
.../amdgpu_dm/tests/amdgpu_dm_helpers_test.c | 70 ++++----
.../display/amdgpu_dm/tests/amdgpu_dm_irq_test.c | 195 ++++++++++-----------
.../display/amdgpu_dm/tests/amdgpu_dm_ism_test.c | 31 ++--
.../amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c | 26 ++-
.../amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h | 1 +
.../amdgpu_dm/tests/amdgpu_dm_mst_types_test.c | 81 ++++-----
.../display/amdgpu_dm/tests/amdgpu_dm_plane_test.c | 73 ++++----
.../display/amdgpu_dm/tests/amdgpu_dm_psr_test.c | 21 +--
.../amd/display/amdgpu_dm/tests/amdgpu_dm_test.c | 53 +++---
.../display/amdgpu_dm/tests/amdgpu_dm_wb_test.c | 6 +-
drivers/gpu/drm/amd/display/dc/Makefile | 4 +
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 7 +
drivers/gpu/drm/amd/display/dc/core/dc_test.c | 135 ++++++++++++++
drivers/gpu/drm/amd/display/dc/inc/dc_test.h | 81 +++++++++
24 files changed, 689 insertions(+), 462 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
index 281dac959dca..6d8651047ff7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
@@ -18,6 +18,7 @@
#include <drm/drm_probe_helper.h>
#include "dc.h"
+#include "dc_test.h"
#include "dc/inc/core_types.h"
#include "dc/inc/hw/audio.h"
#include "amdgpu.h"
@@ -103,7 +104,7 @@ static void dm_test_audio_init_enabled_success(struct kunit *test)
int saved_audio = amdgpu_dm_audio_get_param();
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
res_pool = kunit_kzalloc(test, sizeof(*res_pool), GFP_KERNEL);
audio0 = kunit_kzalloc(test, sizeof(*audio0), GFP_KERNEL);
audio1 = kunit_kzalloc(test, sizeof(*audio1), GFP_KERNEL);
@@ -121,7 +122,7 @@ static void dm_test_audio_init_enabled_success(struct kunit *test)
res_pool->audio_count = 2;
res_pool->audios[0] = audio0;
res_pool->audios[1] = audio1;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
adev->dm.dc = dc;
adev->dev = dev;
@@ -810,16 +811,16 @@ static void dm_test_commit_audio_notifies_added_connector(struct kunit *test)
adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
- adev->dm.dc->current_state = kunit_kzalloc(test,
- sizeof(*adev->dm.dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
+ sizeof(*dc_get_current_state(adev->dm.dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(adev->dm.dc));
stream->ctx = kunit_kzalloc(test, sizeof(*stream->ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, stream->ctx);
stream->ctx->dc = adev->dm.dc;
- adev->dm.dc->current_state->stream_count = 1;
- adev->dm.dc->current_state->streams[0] = stream;
- adev->dm.dc->current_state->stream_status[0].audio_inst = 8;
+ dc_get_current_state(adev->dm.dc)->stream_count = 1;
+ dc_get_current_state(adev->dm.dc)->streams[0] = stream;
+ dc_get_current_state(adev->dm.dc)->stream_status[0].audio_inst = 8;
mutex_init(&adev->dm.audio_lock);
dm_test_audio_setup_notify_component(test, adev);
@@ -968,10 +969,10 @@ static void dm_test_commit_audio_skips_without_stream_status(struct kunit *test)
adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
- adev->dm.dc->current_state = kunit_kzalloc(test,
- sizeof(*adev->dm.dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
+ sizeof(*dc_get_current_state(adev->dm.dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(adev->dm.dc));
stream->ctx = kunit_kzalloc(test, sizeof(*stream->ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, stream->ctx);
stream->ctx->dc = adev->dm.dc;
@@ -1173,16 +1174,16 @@ static void dm_test_commit_audio_skips_writeback_addition(struct kunit *test)
adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
- adev->dm.dc->current_state = kunit_kzalloc(test,
- sizeof(*adev->dm.dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
+ sizeof(*dc_get_current_state(adev->dm.dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(adev->dm.dc));
stream->ctx = kunit_kzalloc(test, sizeof(*stream->ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, stream->ctx);
stream->ctx->dc = adev->dm.dc;
- adev->dm.dc->current_state->stream_count = 1;
- adev->dm.dc->current_state->streams[0] = stream;
- adev->dm.dc->current_state->stream_status[0].audio_inst = 14;
+ dc_get_current_state(adev->dm.dc)->stream_count = 1;
+ dc_get_current_state(adev->dm.dc)->streams[0] = stream;
+ dc_get_current_state(adev->dm.dc)->stream_status[0].audio_inst = 14;
mutex_init(&adev->dm.audio_lock);
dm_test_audio_setup_notify_component(test, adev);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
index a60c0fbf519d..377b92d84b98 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
@@ -14,6 +14,7 @@
#include <drm/drm_property.h>
#include "dc.h"
+#include "dc_test.h"
#include "dc_dmub_srv.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
@@ -72,8 +73,8 @@ static void dm_test_find_stream_with_link_returns_match(struct kunit *test)
struct dc_link *target_link = dm_kunit_alloc_link(test);
struct dc_stream_state *stream;
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, other_link);
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 1, target_link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, other_link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 1, target_link);
stream = dm_find_stream_with_link(dm, target_link);
KUNIT_ASSERT_NOT_NULL(test, stream);
@@ -90,7 +91,7 @@ static void dm_test_find_stream_with_link_missing(struct kunit *test)
struct dc_link *stream_link = dm_kunit_alloc_link(test);
struct dc_link *missing_link = dm_kunit_alloc_link(test);
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, stream_link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, stream_link);
KUNIT_EXPECT_NULL(test, dm_find_stream_with_link(dm, missing_link));
}
@@ -182,7 +183,7 @@ static void dm_test_backlight_set_level_aux_programs_power_module(struct kunit *
dm->backlight_caps[1].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
dm->backlight_caps[1].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
dm->backlight_link[1] = link;
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, link);
amdgpu_dm_backlight_set_level(dm, 1, 2000);
@@ -227,7 +228,7 @@ static void dm_test_backlight_set_level_pwm_programs_power_module(struct kunit *
dm->backlight_caps[1].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
memcpy(dm->backlight_caps[1].luminance_data, curve, sizeof(curve));
dm->backlight_link[1] = link;
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, link);
amdgpu_dm_set_dc_debug_mask(saved_mask & ~DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE);
for (i = 0; i < ARRAY_SIZE(cases); i++) {
@@ -266,23 +267,23 @@ static void dm_test_backlight_set_level_reallows_idle(struct kunit *test)
mutex_init(&dm->dc_lock);
dm->power_module = NULL;
- /* dm_kunit_alloc_dm() leaves dc->ctx NULL; the idle path dereferences it. */
+ /* dm_kunit_alloc_dm() leaves dc_get_ctx(dc) NULL; the idle path dereferences it. */
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dm->dc->ctx = ctx;
+ dc_test_set_ctx(dm->dc, ctx);
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- dm->dc->ctx->logger = logger;
+ dc_get_ctx(dm->dc)->logger = logger;
dmub_srv = kunit_kzalloc(test, sizeof(*dmub_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dmub_srv);
dmub_srv->idle_allowed = true;
- dm->dc->ctx->dmub_srv = dmub_srv;
- dm->dc->caps.ips_support = true;
+ dc_get_ctx(dm->dc)->dmub_srv = dmub_srv;
+ dc_test_caps(dm->dc)->ips_support = true;
/* Keep dc_allow_idle_optimizations() a safe early return. */
- dm->dc->debug.disable_idle_power_optimizations = true;
+ dc_test_debug_options(dm->dc)->disable_idle_power_optimizations = true;
dm->backlight_caps[1].caps_valid = true;
dm->backlight_caps[1].aux_support = true;
@@ -291,7 +292,7 @@ static void dm_test_backlight_set_level_reallows_idle(struct kunit *test)
dm->backlight_caps[1].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
dm->backlight_caps[1].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
dm->backlight_link[1] = link;
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, link);
amdgpu_dm_backlight_set_level(dm, 1, 2000);
@@ -319,24 +320,25 @@ static void dm_test_backlight_update_status_no_stream(struct kunit *test)
KUNIT_EXPECT_EQ(test, dm->brightness[1], 3456U);
}
-static void setup_test_link_service(struct kunit *test, struct dc_link *link)
+static struct link_service *setup_test_link_service(struct kunit *test, struct dc_link *link)
{
struct link_service *link_srv;
struct dc_context *ctx;
struct dc *dc;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
KUNIT_ASSERT_NOT_NULL(test, ctx);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
+
+ return link_srv;
}
static int dm_test_get_backlight_level_mid(const struct dc_link *link)
@@ -382,9 +384,10 @@ static void dm_test_backlight_get_level_pwm_success(struct kunit *test)
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
u32 hw_level = dm_test_get_backlight_level_mid(link);
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_mid;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_mid;
dm->backlight_link[0] = link;
KUNIT_EXPECT_EQ(test, amdgpu_dm_backlight_get_level(dm, 0),
@@ -399,9 +402,10 @@ static void dm_test_backlight_get_level_pwm_error(struct kunit *test)
{
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
dm->brightness[0] = 4321;
dm->backlight_link[0] = link;
@@ -417,9 +421,10 @@ static void dm_test_backlight_get_level_aux_success(struct kunit *test)
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[0];
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level_nits = dm_test_get_backlight_level_nits;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level_nits = dm_test_get_backlight_level_nits;
dm->backlight_link[0] = link;
caps->caps_valid = true;
caps->aux_support = true;
@@ -439,9 +444,10 @@ static void dm_test_backlight_get_level_aux_error(struct kunit *test)
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[0];
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level_nits = dm_test_get_backlight_level_nits_fail;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level_nits = dm_test_get_backlight_level_nits_fail;
dm->brightness[0] = 6789;
dm->backlight_link[0] = link;
caps->caps_valid = true;
@@ -459,9 +465,10 @@ static void dm_test_backlight_get_brightness_uses_device_index(struct kunit *tes
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
struct backlight_device *bd;
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
bd = kunit_kzalloc(test, sizeof(*bd), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, bd);
dev_set_drvdata(&bd->dev, dm);
@@ -506,9 +513,10 @@ static void dm_test_register_backlight_device_success(struct kunit *test)
struct dc_link *link = dm_kunit_alloc_link(test);
struct drm_minor *primary;
unsigned int max;
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
primary = kunit_kzalloc(test, sizeof(*primary), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, primary);
adev->ddev.primary = primary;
@@ -555,10 +563,11 @@ static void dm_test_register_backlight_device_custom_curve_readback(struct kunit
struct backlight_device *bd;
struct drm_minor *primary;
int ret;
+ struct link_service *link_srv;
amdgpu_dm_set_dc_debug_mask(saved_mask & ~DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE);
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_mid;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_mid;
primary = kunit_kzalloc(test, sizeof(*primary), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, primary);
adev->ddev.primary = primary;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
index 7ad8c56cbcf3..56a47809f302 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
@@ -13,6 +13,7 @@
#include <uapi/drm/drm_mode.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
@@ -1759,7 +1760,7 @@ dm_test_verify_lut3d_alloc_adev(struct kunit *test, bool has_3dlut)
adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
- adev->dm.dc->caps.color.dpp.hw_3d_lut = has_3dlut;
+ dc_test_caps(adev->dm.dc)->color.dpp.hw_3d_lut = has_3dlut;
return adev;
}
@@ -2201,7 +2202,7 @@ static void dm_test_update_plane_color_mgmt_bad_lut3d(struct kunit *test)
{
struct dm_test_color_update_fixture f = dm_test_color_update_setup(test);
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->lut3d = dm_test_make_lut_blob(test, 128);
KUNIT_EXPECT_EQ(test,
@@ -2385,7 +2386,7 @@ static void dm_test_update_plane_color_mgmt_legacy_luts(struct kunit *test)
struct drm_plane_state *plane_state = &f.dm_plane_state->base;
int ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->shaper_lut =
dm_test_make_lut_blob(test, MAX_COLOR_LUT_ENTRIES);
f.dm_plane_state->lut3d = dm_test_make_lut_blob(test, lut3d_entries);
@@ -2537,7 +2538,7 @@ static void dm_test_update_plane_color_mgmt_colorop_bypass_pipeline(struct kunit
};
struct dm_test_color_update_fixture f = dm_test_color_update_setup(test);
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass, ARRAY_SIZE(types));
@@ -2635,7 +2636,7 @@ static void dm_test_update_plane_color_mgmt_colorop_truncated(struct kunit *test
struct dm_crtc_state *crtc_state = f.crtc_state;
int count, ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
for (count = 3; count <= ARRAY_SIZE(types); count++) {
f.dm_plane_state->base.color_pipeline =
@@ -2681,11 +2682,11 @@ static void dm_test_update_plane_color_mgmt_colorop_no_3dlut_hw(struct kunit *te
};
struct dm_test_color_update_fixture f = dm_test_color_update_setup(test);
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass,
ARRAY_SIZE(types));
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = false;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = false;
KUNIT_EXPECT_EQ(test,
amdgpu_dm_update_plane_color_mgmt(f.crtc_state, &f.dm_plane_state->base,
@@ -2729,7 +2730,7 @@ static void dm_test_update_plane_color_mgmt_colorop_shaper(struct kunit *test)
struct drm_property_blob *blob;
int ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass,
ARRAY_SIZE(types));
@@ -2784,7 +2785,7 @@ static void dm_test_update_plane_color_mgmt_colorop_3dlut(struct kunit *test)
struct drm_property_blob *blob;
int ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass,
ARRAY_SIZE(types));
@@ -2839,7 +2840,7 @@ static void dm_test_update_plane_color_mgmt_colorop_3dlut_no_data(struct kunit *
struct drm_plane_state *plane_state = &f.dm_plane_state->base;
int ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass,
ARRAY_SIZE(types));
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_colorop_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_colorop_test.c
index 27cd4b8500e8..de49c54e988e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_colorop_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_colorop_test.c
@@ -10,6 +10,7 @@
#include <drm/drm_kunit_helpers.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_dm_colorop.h"
#include "amdgpu_dm_kunit_test_helpers.h"
@@ -231,11 +232,10 @@ static void dm_test_initialize_default_pipeline_caps(struct kunit *test,
adev = dm_kunit_alloc_adev(test);
drm = &adev->ddev;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
- adev->dm.dc->caps.color.dpp.hw_3d_lut = dpp_hw_3d_lut;
- adev->dm.dc->caps.color.mpc.preblend = mpc_preblend;
+ dc_test_caps(adev->dm.dc)->color.dpp.hw_3d_lut = dpp_hw_3d_lut;
+ dc_test_caps(adev->dm.dc)->color.mpc.preblend = mpc_preblend;
plane = drm_kunit_helper_create_primary_plane(test, drm,
NULL, NULL, NULL, 0, NULL);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
index c0bbb95c4af4..204dc86266a3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
@@ -22,6 +22,7 @@
#include <linux/i2c.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_display.h"
@@ -3052,9 +3053,9 @@ static struct dm_test_fbc_ctx *dm_test_fbc_ctx_alloc(struct kunit *test)
/* Default to the fully-enabled path so each test only flips one knob */
ctx->link->connector_signal = SIGNAL_TYPE_EDP;
- ctx->dc->fbc_compressor =
- (struct compressor *)kunit_kzalloc(test, sizeof(void *), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, ctx->dc->fbc_compressor);
+ dc_test_set_fbc_compressor(ctx->dc,
+ (struct compressor *)kunit_kzalloc(test, sizeof(void *), GFP_KERNEL));
+ KUNIT_ASSERT_TRUE(test, dc_is_fbc_compressor_available(ctx->dc));
return ctx;
}
@@ -3067,7 +3068,7 @@ static void dm_test_fbc_init_no_compressor(struct kunit *test)
{
struct dm_test_fbc_ctx *ctx = dm_test_fbc_ctx_alloc(test);
- ctx->dc->fbc_compressor = NULL;
+ dc_test_set_fbc_compressor(ctx->dc, NULL);
amdgpu_dm_fbc_init(&ctx->aconnector->base);
@@ -5076,7 +5077,7 @@ static struct dm_test_poll_ctx *dm_test_poll_ctx_alloc(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link_srv = kunit_kzalloc(test, sizeof(*ctx->link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link_srv);
- ctx->dc->link_srv = ctx->link_srv;
+ dc_test_install_link_service(ctx->dc, ctx->link_srv);
ctx->dc_ctx = kunit_kzalloc(test, sizeof(*ctx->dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc_ctx);
@@ -5676,7 +5677,7 @@ static void dm_test_atomic_check_mst_scaffold(struct kunit *test,
/* Fake DC link so dm_mst_get_pbn_divider() yields a non-zero divider. */
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -5685,7 +5686,7 @@ static void dm_test_atomic_check_mst_scaffold(struct kunit *test,
dm_test_atomic_check_dp_get_verified_link_cap;
link_srv->dp_link_bandwidth_kbps =
dm_test_atomic_check_dp_link_bandwidth_kbps;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
s->mst_root->dc_link = link;
@@ -6016,7 +6017,7 @@ static enum dc_status dm_test_vs_validate_mode_timing_ok(
static void dm_test_validate_stream_dc_ok_no_pipe(struct kunit *test)
{
struct drm_device *drm = dm_test_alloc_drm(test);
- struct dc *dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ struct dc *dc = dm_kunit_alloc_dc(test);
struct dc_context *ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
struct dal_logger *logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
struct resource_pool *pool = kunit_kzalloc(test, sizeof(*pool), GFP_KERNEL);
@@ -6057,9 +6058,9 @@ static void dm_test_validate_stream_dc_ok_no_pipe(struct kunit *test)
link_srv->validate_mode_timing = dm_test_vs_validate_mode_timing_ok;
- dc->ctx = ctx;
- dc->res_pool = pool;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_set_res_pool(dc, pool);
+ dc_test_install_link_service(dc, link_srv);
link->ep_type = DISPLAY_ENDPOINT_UNKNOWN;
stream->link = link;
@@ -6472,7 +6473,7 @@ static struct dm_test_i2c_ctx *dm_test_i2c_setup(struct kunit *test)
ctx->dc_ctx->dc = ctx->dc;
ctx->link->link_index = 0;
ctx->link->ddc = link_ddc;
- ctx->dc->links[0] = ctx->link;
+ dc_test_set_link(ctx->dc, 0, ctx->link);
ctx->i2c->ddc_service = ctx->ddc;
i2c_set_adapdata(&ctx->i2c->base, ctx->i2c);
@@ -6517,7 +6518,7 @@ static void dm_test_i2c_xfer_oem_no_device(struct kunit *test)
pool = kunit_kzalloc(test, sizeof(*pool), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, pool);
- ctx->dc->res_pool = pool;
+ dc_test_set_res_pool(ctx->dc, pool);
ctx->i2c->oem = true;
KUNIT_EXPECT_EQ(test, amdgpu_dm_i2c_xfer(&ctx->i2c->base, msgs, 1), -EIO);
@@ -7383,9 +7384,9 @@ static struct dm_test_cvs_dc *dm_test_cvs_dc_alloc(struct kunit *test)
c->dc = kunit_kzalloc(test, sizeof(*c->dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, c->dc);
- c->dc->ctx = dcc;
- c->dc->res_pool = pool;
- c->dc->link_srv = c->link_srv;
+ dc_test_set_ctx(c->dc, dcc);
+ dc_test_set_res_pool(c->dc, pool);
+ dc_test_install_link_service(c->dc, c->link_srv);
c->adev->dm.dc = c->dc;
c->dm_state = kunit_kzalloc(test, sizeof(*c->dm_state), GFP_KERNEL);
@@ -8310,12 +8311,11 @@ static void dm_test_ces_setup(struct kunit *test, struct dm_test_edid_ctx *ctx,
i2c->base.lock_ops = &dm_test_force_edid_lock_ops;
ctx->aconnector->i2c = i2c;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link_srv->add_remote_sink = dm_test_ces_add_remote_sink;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
ctx->link->dc = dc;
ctx->link->aux_mode = false;
@@ -8484,7 +8484,7 @@ dm_test_gm_ctx_alloc(struct kunit *test, int connector_type)
KUNIT_ASSERT_NOT_NULL(test, ctx->link);
ctx->link_srv->dp_get_encoding_format = dm_test_gm_enc_8b10b;
- ctx->dc->link_srv = ctx->link_srv;
+ dc_test_install_link_service(ctx->dc, ctx->link_srv);
ctx->adev->dm.dc = ctx->dc;
ctx->link->dc = ctx->dc;
ctx->aconnector->dc_link = ctx->link;
@@ -9079,7 +9079,7 @@ static struct dm_test_frl_ctx *dm_test_frl_ctx_alloc(struct kunit *test)
ctx->link_srv->hdmi_frl_poll_status_flag = dm_test_frl_poll_true;
ctx->link_srv->detect_link = dm_test_frl_detect;
- ctx->dc->link_srv = ctx->link_srv;
+ dc_test_install_link_service(ctx->dc, ctx->link_srv);
ctx->dm->dc = ctx->dc;
mutex_init(&ctx->dm->dc_lock);
INIT_DELAYED_WORK(&ctx->dm->hdmi_frl_status_polling_work, hdmi_frl_status_polling_work);
@@ -9099,7 +9099,7 @@ static struct dc_link *dm_test_frl_add_link(struct kunit *test, struct dm_test_f
KUNIT_ASSERT_NOT_NULL(test, link);
link->dc = ctx->dc;
- ctx->dc->links[0] = link;
+ dc_test_set_link(ctx->dc, 0, link);
return link;
}
@@ -9760,10 +9760,9 @@ dm_test_fs_caps_ctx_alloc(struct kunit *test, enum signal_type sink_signal)
ctx->pool = kunit_kzalloc(test, sizeof(*ctx->pool), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->pool);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
- dc->ctx = dc_ctx;
- dc->res_pool = ctx->pool;
+ dc = dm_kunit_alloc_dc(test);
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_res_pool(dc, ctx->pool);
ctx->adev->dm.dc = dc;
ctx->adev->dm.freesync_module =
@@ -10036,10 +10035,9 @@ dm_test_conn_init_ctx_alloc(struct kunit *test, enum signal_type signal)
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link_srv->dp_get_encoding_format = dm_test_gm_enc_8b10b;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
- dc->ctx = dc_ctx;
- dc->link_srv = link_srv;
+ dc = dm_kunit_alloc_dc(test);
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->link = kunit_kzalloc(test, sizeof(*ctx->link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link);
@@ -10054,8 +10052,8 @@ dm_test_conn_init_ctx_alloc(struct kunit *test, enum signal_type signal)
ddc->link = ctx->link;
ctx->link->ddc = ddc;
- dc->links[0] = ctx->link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, ctx->link);
+ dc_test_set_link_count(dc, 1);
ctx->dm->dc = dc;
/* amdgpu_dm_connector_destroy() and amdgpu_dm_encoder_destroy() kfree() these. */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
index 7f6340702502..8d3123904548 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
@@ -16,6 +16,7 @@
#include <drm/drm_vblank.h>
#include "dc.h"
+#include "dc_test.h"
#include "core_types.h"
#include "logger_types.h"
#include "opp.h"
@@ -137,8 +138,8 @@ static struct dm_test_crc_dc_fixture *dm_test_alloc_crc_dc_fixture(struct kunit
mutex_init(&adev->dm.dc_lock);
adev->dm.dc = fixture->dc;
- fixture->dc->ctx = fixture->dc_ctx;
- fixture->dc->current_state = fixture->dc_state;
+ dc_test_set_ctx(fixture->dc, fixture->dc_ctx);
+ dc_test_set_current_state(fixture->dc, fixture->dc_state);
fixture->dc_ctx->dc = fixture->dc;
fixture->dc_ctx->logger = fixture->logger;
fixture->link->dc = fixture->dc;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
index c130d809098c..96cf015a12d9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
@@ -13,6 +13,7 @@
#include <linux/debugfs.h>
#include "dc.h"
+#include "dc_test.h"
#include "inc/core_types.h"
#include "irq/irq_service.h"
#include "inc/hw/timing_generator.h"
@@ -532,7 +533,7 @@ static void dm_test_crtc_set_vupdate_irq_enable(struct kunit *test)
irqs->info = info;
res_pool->irqs = irqs;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
adev->dm.dc = dc;
acrtc->base.dev = &adev->ddev;
@@ -619,7 +620,7 @@ static void dm_test_idle_worker_enabled_breaks_when_idle_disallowed(struct kunit
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* First loop iteration breaks before any dc_allow_idle_optimizations(). */
- adev->dm.dc->idle_optimizations_allowed = false;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, false);
idle_work = kunit_kzalloc(test, sizeof(*idle_work), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, idle_work);
@@ -658,12 +659,12 @@ static void dm_test_idle_worker_enabled_breaks_when_not_headless(struct kunit *t
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* Allow idle so the first branch is skipped and dc_allow() is exercised. */
- adev->dm.dc->idle_optimizations_allowed = true;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, true);
/* is_apu path avoids DC_LOG_DC()'s NULL-logger dereference. */
- adev->dm.dc->caps.is_apu = true;
+ dc_test_caps(adev->dm.dc)->is_apu = true;
/* Empty stream list -> amdgpu_dm_psr_is_active_allowed() returns false. */
- adev->dm.dc->current_state = dm_kunit_alloc_dc_state(test);
- KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, dm_kunit_alloc_dc_state(test));
+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc_get_current_state(adev->dm.dc));
/* A connected display makes amdgpu_dm_is_headless() false. */
display = kunit_kzalloc(test, sizeof(*display), GFP_KERNEL);
@@ -684,7 +685,7 @@ static void dm_test_idle_worker_enabled_breaks_when_not_headless(struct kunit *t
/*
* Report success only when disabling idle. dc_allow_idle_optimizations() then
- * clears dc->idle_optimizations_allowed on the disable call but leaves it clear
+ * clears dc_is_idle_optimizations_allowed(dc) on the disable call but leaves it clear
* on the re-enable call inside the worker's enable-body, so the next loop
* iteration breaks at the first branch instead of looping forever.
*/
@@ -721,18 +722,18 @@ static void dm_test_idle_worker_enabled_runs_body(struct kunit *test)
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* Allow idle so the first branch is skipped and dc_allow() is exercised. */
- adev->dm.dc->idle_optimizations_allowed = true;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, true);
/* is_apu path avoids DC_LOG_DC()'s NULL-logger dereference. */
- adev->dm.dc->caps.is_apu = true;
+ dc_test_caps(adev->dm.dc)->is_apu = true;
/* dc_allow() logs via DC_LOG_DEBUG() when it flips the flag. */
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- adev->dm.dc->ctx->logger = logger;
+ dc_get_ctx(adev->dm.dc)->logger = logger;
/* dc_allow() only flips the flag when clk_mgr and apply() are present. */
- adev->dm.dc->clk_mgr = dm_kunit_alloc_clk_mgr(test);
- KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc->clk_mgr);
- adev->dm.dc->hwss.apply_idle_power_optimizations = dm_test_idle_apply_flip;
+ dc_test_set_clk_mgr(adev->dm.dc, dm_kunit_alloc_clk_mgr(test));
+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc_get_clk_mgr(adev->dm.dc));
+ dc_test_hwss(adev->dm.dc)->apply_idle_power_optimizations = dm_test_idle_apply_flip;
idle_work = kunit_kzalloc(test, sizeof(*idle_work), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, idle_work);
@@ -743,7 +744,7 @@ static void dm_test_idle_worker_enabled_runs_body(struct kunit *test)
amdgpu_dm_idle_worker(&idle_work->work);
/* Enable-body ran, then the next iteration disabled idle and stopped. */
- KUNIT_EXPECT_FALSE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_FALSE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
KUNIT_EXPECT_FALSE(test, idle_work->running);
}
@@ -963,7 +964,7 @@ dm_test_crtc_setup_enable(struct kunit *test, struct amdgpu_device **adev_out,
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
- adev->dm.dc->ctx->dce_version = dce_version;
+ dc_get_ctx(adev->dm.dc)->dce_version = dce_version;
/* crtc_id 0 maps to a valid IRQ type only when a CRTC is registered. */
adev->mode_info.num_crtc = 1;
@@ -1066,7 +1067,7 @@ static void dm_test_crtc_enable_vblank_vupdate_busy(struct kunit *test)
irqs->info = info;
res_pool->irqs = irqs;
- adev->dm.dc->res_pool = res_pool;
+ dc_test_set_res_pool(adev->dm.dc, res_pool);
KUNIT_EXPECT_EQ(test,
amdgpu_dm_crtc_enable_vblank(&acrtc->base), -EBUSY);
@@ -1193,8 +1194,8 @@ static void dm_test_crtc_enable_vblank_ips_restore(struct kunit *test)
acrtc->base.funcs = &dm_test_crtc_funcs;
/* IPS enabled and not fully disabled -> first restore condition holds. */
- adev->dm.dc->caps.ips_support = true;
- adev->dm.dc->config.disable_ips = DMUB_IPS_ENABLE;
+ dc_test_caps(adev->dm.dc)->ips_support = true;
+ dc_test_config(adev->dm.dc)->disable_ips = DMUB_IPS_ENABLE;
/* Supported PSR version makes self-refresh supported. */
link = acrtc_state->stream->link;
@@ -1240,8 +1241,8 @@ static void dm_test_crtc_enable_vblank_ips_restore_replay(struct kunit *test)
acrtc->base.funcs = &dm_test_crtc_funcs;
/* IPS enabled and not fully disabled -> first restore condition holds. */
- adev->dm.dc->caps.ips_support = true;
- adev->dm.dc->config.disable_ips = DMUB_IPS_ENABLE;
+ dc_test_caps(adev->dm.dc)->ips_support = true;
+ dc_test_config(adev->dm.dc)->disable_ips = DMUB_IPS_ENABLE;
/*
* PSR unsupported but replay supported -> sr_supported is driven by the
@@ -2002,7 +2003,7 @@ static void dm_test_crtc_disable_vblank_no_irq_installed(struct kunit *test)
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* DCE_VERSION_6_0 has no VRR, so the vupdate-irq branch is skipped. */
- adev->dm.dc->ctx->dce_version = DCE_VERSION_6_0;
+ dc_get_ctx(adev->dm.dc)->dce_version = DCE_VERSION_6_0;
adev->dm.active_vblank_irq_count = 0;
/* No CRTCs registered and IRQs not installed -> irq_put returns early. */
@@ -2039,7 +2040,7 @@ static void dm_test_crtc_disable_vblank_vrr(struct kunit *test)
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* DCE_VERSION_8_0 supports VRR -> the vupdate-irq branch is walked. */
- adev->dm.dc->ctx->dce_version = DCE_VERSION_8_0;
+ dc_get_ctx(adev->dm.dc)->dce_version = DCE_VERSION_8_0;
adev->mode_info.num_crtc = 1;
adev->irq.installed = true;
@@ -2089,7 +2090,7 @@ static void dm_test_crtc_disable_vblank_queues_work(struct kunit *test)
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* DCE_VERSION_6_0 has no VRR, so the vupdate-irq branch is skipped. */
- adev->dm.dc->ctx->dce_version = DCE_VERSION_6_0;
+ dc_get_ctx(adev->dm.dc)->dce_version = DCE_VERSION_6_0;
adev->dm.active_vblank_irq_count = 2;
adev->mode_info.num_crtc = 1;
@@ -2187,7 +2188,7 @@ static void dm_test_crtc_init_registers_crtc(struct kunit *test)
dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc);
- dc->caps.max_cursor_size = 256;
+ dc_test_caps(dc)->max_cursor_size = 256;
adev->dm.adev = adev;
adev->dm.ddev = &adev->ddev;
@@ -2249,8 +2250,8 @@ static void dm_test_crtc_init_enables_degamma(struct kunit *test)
dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc);
/* DCN DPP with a non-4.01 ASIC selects the degamma-enabled path. */
- dc->caps.color.dpp.dcn_arch = 1;
- dc->ctx->dce_version = DCN_VERSION_3_0;
+ dc_test_caps(dc)->color.dpp.dcn_arch = 1;
+ dc_get_ctx(dc)->dce_version = DCN_VERSION_3_0;
adev->dm.adev = adev;
adev->dm.ddev = &adev->ddev;
@@ -2520,12 +2521,12 @@ static void dm_test_crtc_atomic_check_valid_stream_passes(struct kunit *test)
tg_funcs->validate_timing = dm_test_atomic_check_validate_timing_ok;
tg->funcs = tg_funcs;
res_pool->timing_generators[0] = tg;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link_srv->validate_mode_timing = dm_test_atomic_check_validate_mode_timing_ok;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
adev->dm.dc = dc;
link = dm_kunit_alloc_link(test);
@@ -2588,7 +2589,7 @@ static void dm_test_crtc_atomic_check_invalid_stream_fails(struct kunit *test)
tg_funcs->validate_timing = dm_test_atomic_check_validate_timing_fail;
tg->funcs = tg_funcs;
res_pool->timing_generators[0] = tg;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
adev->dm.dc = dc;
link = dm_kunit_alloc_link(test);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
index 2e273dea17ef..449fb6d94f75 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
@@ -9,6 +9,8 @@
#include <linux/firmware.h>
#include "dc.h"
+#include "dc_test.h"
+#include "amdgpu_dm_kunit_test_helpers.h"
#include "dc/inc/core_types.h"
#include "dc/inc/hw/dmcu.h"
#include "dc/inc/hw/abm.h"
@@ -524,8 +526,7 @@ static struct amdgpu_device *dm_test_alloc_adev_with_dc(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
res_pool = kunit_kzalloc(test, sizeof(*res_pool), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, res_pool);
@@ -533,8 +534,8 @@ static struct amdgpu_device *dm_test_alloc_adev_with_dc(struct kunit *test)
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc->res_pool = res_pool;
- dc->ctx = ctx;
+ dc_test_set_res_pool(dc, res_pool);
+ dc_test_set_ctx(dc, ctx);
ctx->dc = dc;
ctx->driver_context = adev;
adev->dm.dc = dc;
@@ -647,7 +648,7 @@ static void dm_test_dmub_hw_init_success_fake_dmub(struct kunit *test)
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, adev->dm.dmub_srv->hw_init);
- KUNIT_EXPECT_NOT_NULL(test, adev->dm.dc->ctx->dmub_srv);
+ KUNIT_EXPECT_NOT_NULL(test, dc_get_ctx(adev->dm.dc)->dmub_srv);
}
/**
@@ -664,7 +665,7 @@ static void dm_test_dmub_hw_init_no_hw_support(struct kunit *test)
adev->dm.dmub_srv->hw_funcs.is_supported = dm_test_dmub_unsupported;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
- KUNIT_EXPECT_NULL(test, adev->dm.dc->ctx->dmub_srv);
+ KUNIT_EXPECT_NULL(test, dc_get_ctx(adev->dm.dc)->dmub_srv);
}
/**
@@ -717,7 +718,7 @@ static void dm_test_dmub_hw_init_auto_load_timeout(struct kunit *test)
adev->dm.dmub_srv->hw_funcs.get_fw_status = dm_test_dmub_fw_not_ready;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
- KUNIT_EXPECT_NOT_NULL(test, adev->dm.dc->ctx->dmub_srv);
+ KUNIT_EXPECT_NOT_NULL(test, dc_get_ctx(adev->dm.dc)->dmub_srv);
}
/**
@@ -733,8 +734,8 @@ static void dm_test_dmub_hw_init_apu_dpia_dcn35(struct kunit *test)
struct amdgpu_device *adev = dm_test_alloc_adev_with_dmub(test);
adev->ip_versions[DCE_HWIP][0] = IP_VERSION(3, 5, 0);
- adev->dm.dc->caps.is_apu = true;
- adev->dm.dc->res_pool->usb4_dpia_count = 1;
+ dc_test_caps(adev->dm.dc)->is_apu = true;
+ dc_get_res_pool(adev->dm.dc)->usb4_dpia_count = 1;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, adev->dm.dmub_srv->hw_init);
@@ -755,7 +756,7 @@ static void dm_test_dmub_hw_init_sanity_checks_dcn31(struct kunit *test)
adev->dm.dmcub_fw_version = DMUB_FW_VERSION(4, 0, 10);
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->debug.sanity_checks);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(adev->dm.dc)->sanity_checks);
}
/**
@@ -773,7 +774,7 @@ static void dm_test_dmub_hw_init_sanity_checks_dcn314(struct kunit *test)
adev->dm.dmcub_fw_version = DMUB_FW_VERSION(4, 0, 10);
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->debug.sanity_checks);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(adev->dm.dc)->sanity_checks);
}
/**
@@ -798,8 +799,8 @@ static void dm_test_dmub_hw_init_dmcu_abm(struct kunit *test)
dmcu->funcs = &dm_test_dmcu_funcs;
dmcu->psp_version = 0x12345678;
- adev->dm.dc->res_pool->dmcu = dmcu;
- adev->dm.dc->res_pool->abm = abm;
+ dc_get_res_pool(adev->dm.dc)->dmcu = dmcu;
+ dc_get_res_pool(adev->dm.dc)->abm = abm;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, abm->dmcu_is_running);
@@ -857,7 +858,7 @@ static void dm_test_dmub_hw_resume_full_init(struct kunit *test)
dm_dmub_hw_resume(adev);
- KUNIT_EXPECT_NOT_NULL(test, adev->dm.dc->ctx->dmub_srv);
+ KUNIT_EXPECT_NOT_NULL(test, dc_get_ctx(adev->dm.dc)->dmub_srv);
}
/**
@@ -999,7 +1000,7 @@ static void dm_test_execute_dmub_cmd_null_dmub_srv(struct kunit *test)
* dm_test_process_dmub_aux_transfer_sync_engine_acquire - Test AUX transfer engine-acquire failure
* @test: The KUnit test context
*
- * With dc->link_count == 0, dc_process_dmub_aux_transfer_async() rejects the
+ * With dc_get_link_count(dc) == 0, dc_process_dmub_aux_transfer_async() rejects the
* link index and amdgpu_dm_process_dmub_aux_transfer_sync() reports an
* engine-acquire error and returns -1.
*/
@@ -1019,8 +1020,7 @@ static void dm_test_process_dmub_aux_transfer_sync_engine_acquire(struct kunit *
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
payload = kunit_kzalloc(test, sizeof(*payload), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, payload);
@@ -1028,7 +1028,7 @@ static void dm_test_process_dmub_aux_transfer_sync_engine_acquire(struct kunit *
notify = kunit_kzalloc(test, sizeof(*notify), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, notify);
- dc->link_count = 0;
+ dc_test_set_link_count(dc, 0);
ctx->dc = dc;
ctx->driver_context = adev;
adev->dm.dmub_notify = notify;
@@ -1071,8 +1071,7 @@ static void dm_test_process_dmub_aux_transfer_sync_protocol_error(struct kunit *
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -1087,9 +1086,9 @@ static void dm_test_process_dmub_aux_transfer_sync_protocol_error(struct kunit *
KUNIT_ASSERT_NOT_NULL(test, notify);
link->ddc = ddc;
- dc->ctx = dc_ctx;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
dc_ctx->dc = dc;
dc_ctx->driver_context = adev;
dc_ctx->dmub_srv = NULL;
@@ -1139,8 +1138,7 @@ static void dm_test_process_dmub_aux_transfer_sync_copies_data(struct kunit *tes
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -1155,9 +1153,9 @@ static void dm_test_process_dmub_aux_transfer_sync_copies_data(struct kunit *tes
KUNIT_ASSERT_NOT_NULL(test, notify);
link->ddc = ddc;
- dc->ctx = dc_ctx;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
dc_ctx->dc = dc;
dc_ctx->driver_context = adev;
dc_ctx->dmub_srv = NULL;
@@ -1220,8 +1218,7 @@ static void dm_test_process_dmub_aux_transfer_sync_zero_length(struct kunit *tes
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -1236,9 +1233,9 @@ static void dm_test_process_dmub_aux_transfer_sync_zero_length(struct kunit *tes
KUNIT_ASSERT_NOT_NULL(test, notify);
link->ddc = ddc;
- dc->ctx = dc_ctx;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
dc_ctx->dc = dc;
dc_ctx->driver_context = adev;
dc_ctx->dmub_srv = NULL;
@@ -1294,8 +1291,7 @@ static void dm_test_process_dmub_set_config_sync_unknown_error(struct kunit *tes
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -1306,9 +1302,9 @@ static void dm_test_process_dmub_set_config_sync_unknown_error(struct kunit *tes
notify = kunit_kzalloc(test, sizeof(*notify), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, notify);
- dc->ctx = dc_ctx;
+ dc_test_set_ctx(dc, dc_ctx);
dc_ctx->dmub_srv = NULL;
- dc->links[0] = link;
+ dc_test_set_link(dc, 0, link);
ctx->dc = dc;
ctx->driver_context = adev;
adev->dm.dmub_notify = notify;
@@ -1534,8 +1530,8 @@ static void dm_test_dmub_reg_write_then_read(struct kunit *test)
perf_trace = kunit_kzalloc(test, sizeof(*perf_trace), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, perf_trace);
- adev->dm.dc->ctx->cgs_device = &dm_test_cgs.dev;
- adev->dm.dc->ctx->perf_trace = perf_trace;
+ dc_get_ctx(adev->dm.dc)->cgs_device = &dm_test_cgs.dev;
+ dc_get_ctx(adev->dm.dc)->perf_trace = perf_trace;
amdgpu_dm_dmub_reg_write(adev, 0x1234, 0x0BADF00D);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
index 710cdc7f40bf..a3b9ee396e5c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
@@ -13,6 +13,7 @@
#include <drm/drm_vblank.h>
#include "dc.h"
+#include "dc_test.h"
#include "inc/core_types.h"
#include "amd_shared.h"
#include "amdgpu.h"
@@ -594,7 +595,7 @@ static void dm_test_update_freesync_state_pre_ai_active(struct kunit *test)
stream->timing.v_total = 1125;
adev->dm.adev = adev;
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- adev->dm.dc->current_state = dm_kunit_alloc_dc_state(test);
+ dc_test_set_current_state(adev->dm.dc, dm_kunit_alloc_dc_state(test));
amdgpu_dm_update_freesync_state_on_stream(&adev->dm, &crtc_state, stream, surface, 0);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c
index 5af6ae47bb21..b53aba4153f8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c
@@ -11,6 +11,7 @@
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/i2c.h>
+#include "dc_test.h"
#include <drm/display/drm_dp_helper.h>
@@ -1161,7 +1162,7 @@ static void dm_test_hdcp_update_display_disable_resets_status_and_cancels_valida
* dm_test_hdcp_create_workqueue_zero_max_links_returns_null - zero-link creation fails early
* @test: KUnit test context
*
- * When dc->caps.max_links is zero, hdcp_create_workqueue() should fail
+ * When dc_test_caps(dc)->max_links is zero, hdcp_create_workqueue() should fail
* the initial allocation path and return NULL.
*/
static void dm_test_hdcp_create_workqueue_zero_max_links_returns_null(struct kunit *test)
@@ -1170,10 +1171,9 @@ static void dm_test_hdcp_create_workqueue_zero_max_links_returns_null(struct kun
struct dc *dc;
struct hdcp_workqueue *work;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
- dc->caps.max_links = 0;
+ dc_test_caps(dc)->max_links = 0;
work = hdcp_create_workqueue(NULL, &cp_psp, dc);
@@ -1200,9 +1200,9 @@ static void dm_test_hdcp_create_workqueue_initializes_work(struct kunit *test)
/* sysfs_create_bin_file() needs a real device kobject. */
adev->dev = adev->ddev.dev;
- dc->caps.max_links = 1;
+ dc_test_caps(dc)->max_links = 1;
/* DCE_VERSION_UNKNOWN (0) is not in the DTM v3 list. */
- dc->ctx->dce_version = DCE_VERSION_UNKNOWN;
+ dc_get_ctx(dc)->dce_version = DCE_VERSION_UNKNOWN;
work = hdcp_create_workqueue(adev, &cp_psp, dc);
@@ -1236,8 +1236,8 @@ static void dm_test_hdcp_create_workqueue_sets_dtm_v3_for_dcn31(struct kunit *te
struct hdcp_workqueue *work;
adev->dev = adev->ddev.dev;
- dc->caps.max_links = 1;
- dc->ctx->dce_version = DCN_VERSION_3_1;
+ dc_test_caps(dc)->max_links = 1;
+ dc_get_ctx(dc)->dce_version = DCN_VERSION_3_1;
work = hdcp_create_workqueue(adev, &cp_psp, dc);
@@ -1264,8 +1264,8 @@ static void dm_test_hdcp_create_workqueue_initializes_all_links(struct kunit *te
int i;
adev->dev = adev->ddev.dev;
- dc->caps.max_links = 3;
- dc->ctx->dce_version = DCN_VERSION_3_1;
+ dc_test_caps(dc)->max_links = 3;
+ dc_get_ctx(dc)->dce_version = DCN_VERSION_3_1;
work = hdcp_create_workqueue(adev, &cp_psp, dc);
@@ -2089,8 +2089,7 @@ static struct amdgpu_dm_connector *alloc_test_connector(struct kunit *test,
KUNIT_ASSERT_NOT_NULL(test, aconnector);
dc_link = kunit_kzalloc(test, sizeof(*dc_link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_link);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
kref_init(&aconnector->base.base.refcount);
aconnector->base.index = index;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
index 6e564f60b0df..48e30f1936b5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
@@ -13,6 +13,7 @@
#include <drm/display/drm_dp_mst_helper.h>
#include "dc.h"
+#include "dc_test.h"
#include "core_types.h"
#include "clk_mgr.h"
#include "link_service.h"
@@ -193,15 +194,16 @@ static void dm_test_apply_edid_quirks_psr_phy_power_down(struct kunit *test)
struct edid *embedded = dm_test_edid_with_panel_id(test,
drm_edid_encode_panel_id('S', 'D', 'C', 0x4203));
- link->ctx = dc->ctx;
+ link->ctx = dc_get_ctx(dc);
link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
apply_edid_quirks(link, external, &edid_caps);
- KUNIT_EXPECT_FALSE(test, dc->debug.psr_phy_force_phy_power_down_up_level_2);
+ KUNIT_EXPECT_FALSE(
+ test, dc_test_debug_options(dc)->psr_phy_force_phy_power_down_up_level_2);
link->connector_signal = SIGNAL_TYPE_EDP;
apply_edid_quirks(link, embedded, &edid_caps);
- KUNIT_EXPECT_TRUE(test, dc->debug.psr_phy_force_phy_power_down_up_level_2);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(dc)->psr_phy_force_phy_power_down_up_level_2);
}
/**
@@ -430,11 +432,10 @@ static void dm_test_parse_edid_caps_hdmi_frl(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dc_edid);
edid_caps = kunit_kzalloc(test, sizeof(*edid_caps), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, edid_caps);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link->dc = dc;
- dc->config.enable_frl = true;
+ dc_test_config(dc)->enable_frl = true;
dm_test_fill_base_edid(dc_edid, true);
@@ -473,11 +474,10 @@ static void dm_test_parse_edid_caps_hdmi_frl_dsc(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dc_edid);
edid_caps = kunit_kzalloc(test, sizeof(*edid_caps), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, edid_caps);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link->dc = dc;
- dc->config.enable_frl = true;
+ dc_test_config(dc)->enable_frl = true;
dm_test_fill_base_edid(dc_edid, true);
@@ -512,7 +512,7 @@ static void dm_test_parse_edid_caps_hdmi_comp_auto(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, edid_caps);
link->dc = dc;
- link->ctx = dc->ctx;
+ link->ctx = dc_get_ctx(dc);
dm_test_fill_base_edid(dc_edid, true);
@@ -521,8 +521,8 @@ static void dm_test_parse_edid_caps_hdmi_comp_auto(struct kunit *test)
KUNIT_EXPECT_EQ(test, dm_helpers_parse_edid_caps(link, dc_edid, edid_caps), EDID_OK);
KUNIT_EXPECT_TRUE(test, edid_caps->panel_patch.hdmi_comp_auto);
- KUNIT_EXPECT_TRUE(test, dc->debug.force_frl_max);
- KUNIT_EXPECT_TRUE(test, dc->debug.force_frl_dsc);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(dc)->force_frl_max);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(dc)->force_frl_dsc);
}
/*
@@ -2143,13 +2143,12 @@ static void dm_test_override_panel_settings_debug_mask_disables_dsc(struct kunit
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link = dm_kunit_alloc_link(test);
ctx->dc = dc;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
link_srv->dp_should_enable_fec = dm_test_dp_should_enable_fec;
link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
@@ -2176,21 +2175,20 @@ static void dm_test_override_panel_settings_second_edp_disables_psr(struct kunit
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
first_link = dm_kunit_alloc_link(test);
second_link = dm_kunit_alloc_link(test);
ctx->dc = dc;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link_srv->dp_should_enable_fec = dm_test_dp_should_enable_fec;
first_link->dc = dc;
second_link->dc = dc;
- dc->link_count = 2;
- dc->links[0] = first_link;
- dc->links[1] = second_link;
+ dc_test_set_link_count(dc, 2);
+ dc_test_set_link(dc, 0, first_link);
+ dc_test_set_link(dc, 1, second_link);
first_link->connector_signal = SIGNAL_TYPE_EDP;
second_link->connector_signal = SIGNAL_TYPE_EDP;
@@ -2538,7 +2536,7 @@ static void dm_test_dmub_aux_transfer_sync_hpd_discon(struct kunit *test)
* @test: The KUnit test context
*
* With HPD connected the helper forwards the payload to
- * amdgpu_dm_process_dmub_aux_transfer_sync(). dc->link_count is zero, so the
+ * amdgpu_dm_process_dmub_aux_transfer_sync(). dc_get_link_count(dc) is zero, so the
* async transfer is rejected and the engine-acquire error is reported.
*/
static void dm_test_dmub_aux_transfer_sync_hpd_connected(struct kunit *test)
@@ -4117,15 +4115,14 @@ static void dm_test_dp_handle_test_pattern_no_pipe(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, state);
link = dm_kunit_alloc_link(test);
aconnector = dm_kunit_alloc_connector(test, adev, link);
ctx->dc = dc;
- dc->current_state = state;
+ dc_test_set_current_state(dc, state);
link->dc = dc;
link->priv = aconnector;
@@ -4267,14 +4264,13 @@ static void dm_test_dmub_set_config_sync_unknown_error(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, ctx);
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
notify = kunit_kzalloc(test, sizeof(*notify), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, notify);
link = dm_kunit_alloc_link(test);
- dc->ctx = dc_ctx;
- dc->links[0] = link;
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_link(dc, 0, link);
ctx->dc = dc;
ctx->driver_context = adev;
adev->dm.dmub_notify = notify;
@@ -4309,8 +4305,7 @@ static void dm_test_is_dp_sink_present_queries_link_service(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_NOT_NULL(test, adev);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link = dm_kunit_alloc_link(test);
@@ -4321,7 +4316,7 @@ static void dm_test_is_dp_sink_present_queries_link_service(struct kunit *test)
drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
link_srv->dp_is_sink_present = dm_test_dp_sink_present_true;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
link->priv = aconnector;
@@ -4588,8 +4583,7 @@ static struct dm_test_pattern_fixture dm_test_setup_pattern(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, adev);
fixture.ctx = kunit_kzalloc(test, sizeof(*fixture.ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, fixture.ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, state);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -4607,9 +4601,9 @@ static struct dm_test_pattern_fixture dm_test_setup_pattern(struct kunit *test)
clk_mgr->funcs = &dm_test_clk_mgr_funcs;
clk_mgr->bw_params = bw_params;
- dc->link_srv = link_srv;
- dc->clk_mgr = clk_mgr;
- dc->current_state = state;
+ dc_test_install_link_service(dc, link_srv);
+ dc_test_set_clk_mgr(dc, clk_mgr);
+ dc_test_set_current_state(dc, state);
fixture.ctx->dc = dc;
fixture.link->dc = dc;
fixture.link->priv = fixture.aconnector;
@@ -4794,7 +4788,7 @@ static void dm_test_read_local_edid_i2c_no_response(struct kunit *test)
fixture.link->aux_mode = false;
fixture.link->ddc_hw_inst = 1;
fixture.aconnector->i2c = (struct amdgpu_i2c_adapter *)ddc;
- fixture.dc->hwss.prepare_ddc = dm_test_prepare_ddc;
+ dc_test_hwss(fixture.dc)->prepare_ddc = dm_test_prepare_ddc;
dm_test_prepare_ddc_calls = 0;
KUNIT_EXPECT_EQ(test,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
index 8c112bda46c8..b64d63fe15fd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
@@ -15,6 +15,7 @@
#include <drm/display/drm_dp_helper.h>
#include "dc.h"
+#include "dc_test.h"
#include "inc/core_types.h"
#include "inc/hw/timing_generator.h"
#include "irq/irq_service.h"
@@ -444,7 +445,7 @@ static struct dc *dm_test_alloc_dc_with_irq_service(struct kunit *test,
irqs->funcs = funcs;
irqs->info = info;
res_pool->irqs = irqs;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
return dc;
}
@@ -1532,9 +1533,8 @@ static void dm_test_hpd_rx_irq_create_workqueue(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
- dc->caps.max_links = 4;
+ dc = dm_kunit_alloc_dc(test);
+ dc_test_caps(dc)->max_links = 4;
adev->dm.dc = dc;
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
@@ -1542,10 +1542,10 @@ static void dm_test_hpd_rx_irq_create_workqueue(struct kunit *test)
ctx->wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev);
KUNIT_ASSERT_NOT_NULL(test, ctx->wq);
- ctx->count = dc->caps.max_links;
+ ctx->count = dc_test_caps(dc)->max_links;
KUNIT_ASSERT_EQ(test, kunit_add_action_or_reset(test, dm_test_destroy_hpd_rx_wq, ctx), 0);
- for (i = 0; i < dc->caps.max_links; i++)
+ for (i = 0; i < dc_test_caps(dc)->max_links; i++)
KUNIT_EXPECT_TRUE(test, ctx->wq[i].wq != NULL);
}
@@ -1578,9 +1578,8 @@ static void dm_test_hpd_rx_irq_work_suspend_flushes(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
- dc->caps.max_links = 2;
+ dc = dm_kunit_alloc_dc(test);
+ dc_test_caps(dc)->max_links = 2;
adev->dm.dc = dc;
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
@@ -1588,7 +1587,7 @@ static void dm_test_hpd_rx_irq_work_suspend_flushes(struct kunit *test)
ctx->wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev);
KUNIT_ASSERT_NOT_NULL(test, ctx->wq);
- ctx->count = dc->caps.max_links;
+ ctx->count = dc_test_caps(dc)->max_links;
KUNIT_ASSERT_EQ(test, kunit_add_action_or_reset(test, dm_test_destroy_hpd_rx_wq, ctx), 0);
adev->dm.hpd_rx_offload_wq = ctx->wq;
@@ -1756,12 +1755,12 @@ static void dm_test_set_crtc_irq_state_allows_idle(struct kunit *test)
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- dc->ctx->logger = logger;
+ dc_get_ctx(dc)->logger = logger;
- dc->caps.ips_support = true;
- dc->idle_optimizations_allowed = true;
+ dc_test_caps(dc)->ips_support = true;
+ dc_test_set_idle_optimizations_allowed(dc, true);
/* Keep dc_allow_idle_optimizations() a safe early return. */
- dc->debug.disable_idle_power_optimizations = true;
+ dc_test_debug_options(dc)->disable_idle_power_optimizations = true;
adev->dm.dc = dc;
acrtc->otg_inst = 0;
@@ -2052,8 +2051,8 @@ static void dm_test_hpd_init_empty_connectors(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, link);
link->irq_source_hpd = DC_IRQ_SOURCE_HPD1;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX;
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
amdgpu_dm_hpd_init(adev);
}
@@ -2118,8 +2117,8 @@ static void dm_test_hpd_init_fini_with_connectors(struct kunit *test)
link->irq_source_hpd = DC_IRQ_SOURCE_HPD1;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX;
aconn->dc_link = link;
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
/* The irq service stubs accept the HW writes without register access. */
amdgpu_dm_hpd_init(adev);
@@ -2159,8 +2158,8 @@ static void dm_test_hpd_init_fini_analog_connector(struct kunit *test)
/* An analog connector id makes the loop request polling. */
link->link_id.id = CONNECTOR_ID_VGA;
aconn->dc_link = link;
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
/* use_polling becomes true, so init must enable KMS polling. */
amdgpu_dm_hpd_init(adev);
@@ -2210,8 +2209,8 @@ static void dm_test_hpd_init_fini_irq_ref(struct kunit *test)
link->irq_source_hpd = DC_IRQ_SOURCE_HPD1;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
aconn->dc_link = link;
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
amdgpu_dm_hpd_init(adev);
amdgpu_dm_hpd_fini(adev);
@@ -2310,8 +2309,7 @@ dm_test_setup_hpd_rx_offload_work(struct kunit *test,
mutex_init(&aconn->hpd_lock);
offload_wq->aconnector = aconn;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -2320,8 +2318,8 @@ dm_test_setup_hpd_rx_offload_work(struct kunit *test,
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->detect_connection_type = dm_test_detect_connection_single;
- dc->link_srv = link_srv;
- dc->ctx = ctx;
+ dc_test_install_link_service(dc, link_srv);
+ dc_test_set_ctx(dc, ctx);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -2542,8 +2540,7 @@ static struct amdgpu_dm_connector *dm_test_setup_hdmi_debounce(struct kunit *tes
INIT_DELAYED_WORK(&aconn->hdmi_hpd_debounce_work,
amdgpu_dm_hdmi_hpd_debounce_work);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -2552,8 +2549,8 @@ static struct amdgpu_dm_connector *dm_test_setup_hdmi_debounce(struct kunit *tes
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->detect_link = dm_test_detect_link_false;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -2607,13 +2604,13 @@ static void dm_test_hdmi_hpd_debounce_reallow_idle(struct kunit *test)
/* DC_LOG_* dereferences ctx->logger->dev, so wire a real drm device. */
logger->dev = aconn->base.dev;
- dc->ctx->logger = logger;
+ dc_get_ctx(dc)->logger = logger;
/* Make reallow_idle true and keep dc_allow_idle*() a safe early return. */
dmub_srv->idle_allowed = true;
- dc->ctx->dmub_srv = dmub_srv;
- dc->caps.ips_support = true;
- dc->debug.disable_idle_power_optimizations = true;
+ dc_get_ctx(dc)->dmub_srv = dmub_srv;
+ dc_test_caps(dc)->ips_support = true;
+ dc_test_debug_options(dc)->disable_idle_power_optimizations = true;
/* A cached previous sink must be released and cleared. */
aconn->hdmi_prev_sink = dm_test_sink_create(aconn->dc_link);
@@ -2707,14 +2704,13 @@ static void dm_test_handle_hpd_irq_disabled(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, state);
aconn->base.state = &state->base;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
- dc->ctx = ctx;
+ dc_test_set_ctx(dc, ctx);
ctx->dc = dc;
link->ctx = ctx;
aconn->dc_link = link;
@@ -2756,8 +2752,7 @@ static struct amdgpu_dm_connector *dm_test_setup_hpd_irq_helper(struct kunit *te
KUNIT_ASSERT_NOT_NULL(test, state);
aconn->base.state = &state->base;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -2766,8 +2761,8 @@ static struct amdgpu_dm_connector *dm_test_setup_hpd_irq_helper(struct kunit *te
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->detect_connection_type = dm_test_detect_connection_none;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -3017,8 +3012,7 @@ static void dm_test_handle_hpd_rx_irq_disabled(struct kunit *test)
aconn = dm_kunit_alloc_connector(test, adev, NULL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -3027,8 +3021,8 @@ static void dm_test_handle_hpd_rx_irq_disabled(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->dp_handle_hpd_rx_irq = dm_test_handle_hpd_rx_no_work;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -3101,8 +3095,7 @@ static struct amdgpu_dm_connector *dm_test_setup_hpd_rx_irq(struct kunit *test,
mutex_init(&aconn->hpd_lock);
aconn->mst_mgr.mst_state = true;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -3110,8 +3103,8 @@ static struct amdgpu_dm_connector *dm_test_setup_hpd_rx_irq(struct kunit *test,
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -3332,8 +3325,7 @@ static void dm_test_dmub_hpd_callback_invalid_index(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
notify.link_index = 1;
@@ -3351,11 +3343,10 @@ static void dm_test_dmub_hpd_callback_empty_connectors(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
adev->dm.ddev = &adev->ddev;
- dc->link_count = 1;
+ dc_test_set_link_count(dc, 1);
notify.type = DMUB_NOTIFICATION_HPD_SENSE_NOTIFY;
dmub_hpd_callback(adev, ¬ify);
@@ -3376,11 +3367,10 @@ static void dm_test_dmub_hpd_callback_suspend_skip(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
adev->in_suspend = true;
- dc->link_count = 1;
+ dc_test_set_link_count(dc, 1);
notify.type = DMUB_NOTIFICATION_HPD;
/* adev->dm.ddev is left NULL: reaching the connector walk would crash. */
@@ -3408,15 +3398,14 @@ static void dm_test_dmub_hpd_callback_unknown_type_match(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
adev->dm.ddev = &adev->ddev;
- dc->link_count = 1;
+ dc_test_set_link_count(dc, 1);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
- dc->links[0] = link;
+ dc_test_set_link(dc, 0, link);
/* A writeback connector must be skipped by the loop. */
wbconn = kunit_kzalloc(test, sizeof(*wbconn), GFP_KERNEL);
@@ -3463,8 +3452,7 @@ static void dm_test_dmub_hpd_callback_hpd_type(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
mutex_init(&adev->dm.dc_lock);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -3474,16 +3462,16 @@ static void dm_test_dmub_hpd_callback_hpd_type(struct kunit *test)
link_srv->detect_connection_type = dm_test_detect_connection_none;
link_srv->detect_link = dm_test_detect_link_false;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
adev->dm.dc = dc;
adev->dm.ddev = &adev->ddev;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
aconn = kunit_kzalloc(test, sizeof(*aconn), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, aconn);
@@ -3532,8 +3520,7 @@ static void dm_test_dmub_hpd_callback_hpd_irq_type(struct kunit *test)
spin_lock_init(&offload_wq->offload_lock);
adev->dm.hpd_rx_offload_wq = offload_wq;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -3542,8 +3529,8 @@ static void dm_test_dmub_hpd_callback_hpd_irq_type(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->dp_handle_hpd_rx_irq = dm_test_handle_hpd_rx_no_work;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -3552,8 +3539,8 @@ static void dm_test_dmub_hpd_callback_hpd_irq_type(struct kunit *test)
adev->dm.dc = dc;
adev->dm.ddev = &adev->ddev;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
aconn = kunit_kzalloc(test, sizeof(*aconn), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, aconn);
@@ -3584,8 +3571,7 @@ static void dm_test_register_hpd_handlers_empty(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
KUNIT_EXPECT_EQ(test, amdgpu_dm_register_hpd_handlers(adev), 0);
@@ -3609,8 +3595,7 @@ static void dm_test_register_hpd_handlers_valid(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
wbconn = kunit_kzalloc(test, sizeof(*wbconn), GFP_KERNEL);
@@ -3656,8 +3641,7 @@ static void dm_test_register_hpd_handlers_invalid_hpd(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
aconn = kunit_kzalloc(test, sizeof(*aconn), GFP_KERNEL);
@@ -3691,8 +3675,7 @@ static void dm_test_register_hpd_handlers_invalid_hpd_rx(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
aconn = kunit_kzalloc(test, sizeof(*aconn), GFP_KERNEL);
@@ -3732,8 +3715,8 @@ static void dm_test_register_hpd_handlers_dmub_outbox(struct kunit *test)
adev->dm.dc = dc;
/* Make dc_is_dmub_outbox_supported() return true. */
- dc->caps.dmcub_support = true;
- dc->ctx->asic_id.chip_family = AMDGPU_FAMILY_GC_11_0_1;
+ dc_test_caps(dc)->dmcub_support = true;
+ dc_get_ctx(dc)->asic_id.chip_family = AMDGPU_FAMILY_GC_11_0_1;
KUNIT_EXPECT_EQ(test, amdgpu_dm_register_hpd_handlers(adev), 0);
KUNIT_EXPECT_PTR_EQ(test, adev->dm.dmub_callback[DMUB_NOTIFICATION_HPD],
@@ -3843,18 +3826,18 @@ static struct amdgpu_crtc *dm_test_setup_vrr_pflip_crtc(struct kunit *test,
KUNIT_ASSERT_EQ(test, drm_vblank_init(&adev->ddev, 1), 0);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = kunit_kzalloc(test, sizeof(*dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, kunit_kzalloc(test, sizeof(*dc_get_current_state(dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
adev->dm.dc = dc;
link = dm_kunit_alloc_link(test);
stream = dm_kunit_alloc_stream(test, link);
- stream->ctx = dc->ctx;
+ stream->ctx = dc_get_ctx(dc);
if (tg) {
- dc->current_state->res_ctx.pipe_ctx[0].stream = stream;
- dc->current_state->res_ctx.pipe_ctx[0].stream_res.tg = tg;
+ dc_get_current_state(dc)->res_ctx.pipe_ctx[0].stream = stream;
+ dc_get_current_state(dc)->res_ctx.pipe_ctx[0].stream_res.tg = tg;
}
acrtc = dm_test_add_crtc(test, adev);
@@ -4056,9 +4039,9 @@ static struct amdgpu_crtc *dm_test_setup_vmin_vmax_crtc(struct kunit *test,
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = kunit_kzalloc(test, sizeof(*dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, kunit_kzalloc(test, sizeof(*dc_get_current_state(dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
adev->dm.dc = dc;
link = dm_kunit_alloc_link(test);
@@ -4205,7 +4188,7 @@ static void dm_test_crtc_high_irq_writeback_disables(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, drm_vblank_init(&adev->ddev, 1), 0);
- /* dc_stream_fc_disable_writeback() dereferences dc->res_pool. */
+ /* dc_stream_fc_disable_writeback() dereferences dc_get_res_pool(dc). */
dc = dm_test_alloc_dc_with_irq_service(test,
&dm_test_irq_service_funcs_dcn10);
adev->dm.dc = dc;
@@ -4384,7 +4367,7 @@ static void dm_test_dmub_outbox1_low_irq_empty(struct kunit *test)
dmub->hw_funcs.get_outbox0_wptr = dm_test_dmub_get_outbox0_wptr;
dc_dmub_srv->dmub = dmub;
- dc->ctx->dmub_srv = dc_dmub_srv;
+ dc_get_ctx(dc)->dmub_srv = dc_dmub_srv;
adev->dm.dc = dc;
params.adev = adev;
params.irq_src = DC_IRQ_SOURCE_DMCUB_OUTBOX;
@@ -4422,7 +4405,7 @@ static void dm_test_dmub_outbox1_low_irq_drains_trace(struct kunit *test)
dmub->outbox0_rb.capacity = DM_TEST_OUTBOX0_RB_SIZE;
dmub->hw_funcs.get_outbox0_wptr = dm_test_dmub_get_outbox0_wptr_full;
dc_dmub_srv->dmub = dmub;
- dc->ctx->dmub_srv = dc_dmub_srv;
+ dc_get_ctx(dc)->dmub_srv = dc_dmub_srv;
adev->dm.dc = dc;
params.adev = adev;
params.irq_src = DC_IRQ_SOURCE_DMCUB_OUTBOX;
@@ -4460,11 +4443,11 @@ static struct amdgpu_device *dm_test_alloc_adev_outbox_notify(struct kunit *test
dmub->hw_funcs.get_outbox0_wptr = dm_test_dmub_get_outbox0_wptr;
dmub->hw_funcs.get_outbox1_wptr = dm_test_dmub_get_outbox1_wptr;
dc_dmub_srv->dmub = dmub;
- dc->ctx->dmub_srv = dc_dmub_srv;
+ dc_get_ctx(dc)->dmub_srv = dc_dmub_srv;
/* Make dc_enable_dmub_notifications() return true. */
- dc->caps.dmcub_support = true;
- dc->ctx->asic_id.chip_family = AMDGPU_FAMILY_GC_11_0_1;
+ dc_test_caps(dc)->dmcub_support = true;
+ dc_get_ctx(dc)->asic_id.chip_family = AMDGPU_FAMILY_GC_11_0_1;
adev->dm.dc = dc;
@@ -4578,8 +4561,8 @@ static struct amdgpu_device *dm_test_setup_irq_regs(struct kunit *test,
KUNIT_ASSERT_EQ(test, kunit_add_action_or_reset(test, dm_test_free_irq_sources,
adev), 0);
dc = dm_test_alloc_dc_with_irq_service(test, funcs);
- dc->ctx->dce_version = DCE_VERSION_11_0;
- dc->caps.max_otg_num = 1;
+ dc_get_ctx(dc)->dce_version = DCE_VERSION_11_0;
+ dc_test_caps(dc)->max_otg_num = 1;
adev->dm.dc = dc;
adev->mode_info.num_crtc = 1;
adev->mode_info.num_hpd = 1;
@@ -4663,7 +4646,7 @@ static void dm_test_dce110_register_irq_handlers_crtc_add_id_fails(struct kunit
adev = dm_kunit_alloc_adev(test);
dc = dm_test_alloc_dc_with_irq_service(test, &dm_test_irq_service_funcs_dce110);
- dc->ctx->dce_version = DCE_VERSION_11_0;
+ dc_get_ctx(dc)->dce_version = DCE_VERSION_11_0;
adev->dm.dc = dc;
adev->mode_info.num_crtc = 1;
@@ -4917,7 +4900,7 @@ static void dm_test_register_outbox_irq_handlers_add_id_fails(struct kunit *test
* dm_test_register_outbox_irq_handlers_with_dmub - Test outbox registration with DMUB
* @test: The KUnit test context
*
- * Exercises the dc->ctx->dmub_srv branch which maps the outbox source and
+ * Exercises the dc_get_ctx(dc)->dmub_srv branch which maps the outbox source and
* registers dm_dmub_outbox1_low_irq in the low IRQ context table.
*/
static void dm_test_register_outbox_irq_handlers_with_dmub(struct kunit *test)
@@ -4933,7 +4916,7 @@ static void dm_test_register_outbox_irq_handlers_with_dmub(struct kunit *test)
dc = dm_test_alloc_dc_with_irq_service(test, &dm_test_irq_service_funcs_dcn10);
dc_dmub_srv = kunit_kzalloc(test, sizeof(*dc_dmub_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_dmub_srv);
- dc->ctx->dmub_srv = dc_dmub_srv;
+ dc_get_ctx(dc)->dmub_srv = dc_dmub_srv;
adev->dm.dc = dc;
amdgpu_dm_set_irq_funcs(adev);
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
@@ -5086,9 +5069,9 @@ static void dm_test_handle_vmin_vmax_update(struct kunit *test)
mutex_init(&adev->dm.dc_lock);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = kunit_kzalloc(test, sizeof(*dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, kunit_kzalloc(test, sizeof(*dc_get_current_state(dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
adev->dm.dc = dc;
stream = kunit_kzalloc(test, sizeof(*stream), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
index a9c6485e2a9e..5864147faf1c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
@@ -8,6 +8,7 @@
#include <kunit/test.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
@@ -1191,9 +1192,9 @@ static void dm_test_ism_dispatch_optimized_idle_defers_sso(struct kunit *test)
* ===== Behavioural tests for dm_ism_commit_idle_optimization_state =====
*
* The commit path runs the real DC calls. dc_allow_idle_optimizations() only
- * reaches hardware through dc->hwss.apply_idle_power_optimizations(), so the
+ * reaches hardware through dc_test_hwss(dc)->apply_idle_power_optimizations(), so the
* spy is installed there — DC's own seam — and the outcome is read back from
- * dc->idle_optimizations_allowed. The callback fires only on an actual
+ * dc_is_idle_optimizations_allowed(dc). The callback fires only on an actual
* transition, so the call count is the number of idle state changes requested.
*/
@@ -1236,12 +1237,12 @@ static struct dc_stream_state *setup_commit_test(struct kunit *test,
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- dc->ctx->logger = logger;
+ dc_get_ctx(dc)->logger = logger;
/* is_apu path avoids DC_LOG_DC()'s NULL-logger dereference. */
- dc->caps.is_apu = true;
+ dc_test_caps(dc)->is_apu = true;
/* dc_allow() only calls apply() when clk_mgr is present. */
- dc->clk_mgr = dm_kunit_alloc_clk_mgr(test);
- dc->hwss.apply_idle_power_optimizations = dm_ism_test_apply_idle;
+ dc_test_set_clk_mgr(dc, dm_kunit_alloc_clk_mgr(test));
+ dc_test_hwss(dc)->apply_idle_power_optimizations = dm_ism_test_apply_idle;
dm_ism_test_idle = (typeof(dm_ism_test_idle)){ };
amdgpu_dm_ism_init(&acrtc->ism, config);
@@ -1281,7 +1282,7 @@ static void dm_test_ism_commit_allows_idle_on_optimized_idle(struct kunit *test)
/* vblank disabled + no SSO -> a single allow-idle transition. */
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 1);
KUNIT_EXPECT_TRUE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_TRUE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
cancel_delayed_work(&acrtc->ism.sso_delayed_work);
}
@@ -1308,7 +1309,7 @@ static void dm_test_ism_commit_enables_sso_on_optimized_idle_sso(struct kunit *t
};
setup_commit_test(test, acrtc, &config);
- adev->dm.dc->idle_optimizations_allowed = true;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, true);
scoped_guard(mutex, &adev->dm.dc_lock) {
amdgpu_dm_ism_commit_event(&acrtc->ism,
@@ -1320,7 +1321,7 @@ static void dm_test_ism_commit_enables_sso_on_optimized_idle_sso(struct kunit *t
/* SSO engagement disallows idle, then re-allows it. */
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 2);
KUNIT_EXPECT_TRUE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_TRUE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
}
amdgpu_dm_ism_flush(&acrtc->ism);
@@ -1351,7 +1352,7 @@ static void dm_test_ism_commit_disallows_idle_on_timer_aborted(struct kunit *tes
stream = setup_commit_test(test, acrtc, &config);
setup_idle_delay_history(&acrtc->ism, stream);
- adev->dm.dc->idle_optimizations_allowed = true;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, true);
scoped_guard(mutex, &adev->dm.dc_lock) {
/* Non-zero delay parks the FSM in HYSTERESIS_WAITING. */
@@ -1369,7 +1370,7 @@ static void dm_test_ism_commit_disallows_idle_on_timer_aborted(struct kunit *tes
/* TIMER_ABORTED commit runs with vblank_enabled=true. */
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 1);
KUNIT_EXPECT_FALSE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_FALSE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_FALSE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
}
amdgpu_dm_ism_flush(&acrtc->ism);
@@ -1409,7 +1410,7 @@ static void dm_test_ism_exit_from_optimized_idle_disallows_idle(struct kunit *te
/* Allow on entry, disallow on exit. */
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 2);
KUNIT_EXPECT_FALSE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_FALSE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_FALSE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
/* The idle period was recorded on the way out. */
KUNIT_EXPECT_EQ(test, acrtc->ism.next_record_idx, 1);
}
@@ -1449,7 +1450,7 @@ static void dm_test_ism_exit_from_sso_disallows_idle(struct kunit *test)
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 2);
KUNIT_EXPECT_FALSE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_FALSE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_FALSE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
KUNIT_EXPECT_EQ(test, acrtc->ism.next_record_idx, 1);
}
@@ -1495,7 +1496,7 @@ static void dm_test_ism_delayed_work_runs_timer_elapsed(struct kunit *test)
KUNIT_EXPECT_EQ(test, (int)acrtc->ism.current_state,
(int)DM_ISM_STATE_OPTIMIZED_IDLE_SSO);
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 1);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_TRUE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
amdgpu_dm_ism_flush(&acrtc->ism);
}
@@ -1533,7 +1534,7 @@ static void dm_test_ism_sso_delayed_work_runs_sso_elapsed(struct kunit *test)
KUNIT_EXPECT_EQ(test, (int)acrtc->ism.current_state,
(int)DM_ISM_STATE_OPTIMIZED_IDLE_SSO);
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 3);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_TRUE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
amdgpu_dm_ism_flush(&acrtc->ism);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
index f844b644bb77..9954cbab6541 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
@@ -11,6 +11,7 @@
#include <drm/drm_managed.h>
#include "dc.h"
+#include "dc_test.h"
#include "core_types.h"
#include "clk_mgr.h"
#include "amdgpu.h"
@@ -47,18 +48,29 @@ struct dc_link *dm_kunit_alloc_link(struct kunit *test)
}
EXPORT_SYMBOL(dm_kunit_alloc_link);
+struct dc *dm_kunit_alloc_dc(struct kunit *test)
+{
+ struct dc *dc;
+
+ dc = dc_test_create();
+ KUNIT_ASSERT_NOT_NULL(test, dc);
+ kunit_add_action(test, (kunit_action_t *)dc_test_destroy, dc);
+
+ return dc;
+}
+EXPORT_SYMBOL(dm_kunit_alloc_dc);
+
struct dc *dm_kunit_alloc_dc_with_ctx(struct kunit *test)
{
struct dc_context *ctx;
struct dc *dc;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc->ctx = ctx;
+ dc_test_set_ctx(dc, ctx);
ctx->dc = dc;
return dc;
@@ -72,7 +84,7 @@ struct dc_link *dm_kunit_alloc_link_with_ctx(struct kunit *test)
link = dm_kunit_alloc_link(test);
dc = dm_kunit_alloc_dc_with_ctx(test);
- link->ctx = dc->ctx;
+ link->ctx = dc_get_ctx(dc);
return link;
}
@@ -87,14 +99,12 @@ struct amdgpu_display_manager *dm_kunit_alloc_dm(struct kunit *test)
dm = kunit_kzalloc(test, sizeof(*dm), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
-
+ dc = dm_kunit_alloc_dc(test);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, state);
dm->dc = dc;
- dc->current_state = state;
+ dc_test_set_current_state(dc, state);
return dm;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
index 7d7bcd321775..b4bbf4a3750d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
@@ -21,6 +21,7 @@ struct dc_stream_state;
struct drm_device;
struct amdgpu_device *dm_kunit_alloc_adev(struct kunit *test);
+struct dc *dm_kunit_alloc_dc(struct kunit *test);
struct dc *dm_kunit_alloc_dc_with_ctx(struct kunit *test);
struct dc_link *dm_kunit_alloc_link(struct kunit *test);
struct dc_link *dm_kunit_alloc_link_with_ctx(struct kunit *test);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
index e624eb55cae1..b8ea85846872 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
@@ -23,6 +23,7 @@
#include <drm/display/drm_dp_mst_helper.h>
#include "dc.h"
+#include "dc_test.h"
#include "dpcd_defs.h"
#include "dmub_cmd.h"
#include "amdgpu.h"
@@ -83,7 +84,7 @@ static void dm_mst_test_setup_dm_aux(struct amdgpu_dm_dp_aux *dm_aux,
dm_mst_test_aux_transfer_raw_reply = 0;
dm_mst_test_aux_transfer_raw_operation_result = AUX_RET_SUCCESS;
link_srv->aux_transfer_raw = dm_mst_test_aux_transfer_raw;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
ctx->driver_context = adev;
ddc->link = link;
@@ -137,7 +138,7 @@ static struct amdgpu_dm_connector *dm_mst_test_alloc_sideband_connector(struct k
aconnector = kunit_kzalloc(test, sizeof(*aconnector), GFP_KERNEL);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, aconnector);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -145,7 +146,7 @@ static struct amdgpu_dm_connector *dm_mst_test_alloc_sideband_connector(struct k
mutex_init(&aconnector->handle_mst_msg_ready);
link_srv->get_status = dm_mst_test_get_status;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
link->dpcd_caps.dpcd_rev.raw = DPCD_REV_14;
link->link_status.dpcd_caps = &link->dpcd_caps;
@@ -341,14 +342,14 @@ static void dm_mst_test_pbn_divider_uses_link_bandwidth(struct kunit *test)
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
KUNIT_ASSERT_NOT_NULL(test, link);
KUNIT_ASSERT_NOT_NULL(test, dc);
link_srv->dp_get_verified_link_cap = dm_mst_test_dp_get_verified_link_cap;
link_srv->dp_link_bandwidth_kbps = dm_mst_test_dp_link_bandwidth_kbps;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
KUNIT_EXPECT_EQ(test, dm_mst_get_pbn_divider(link),
@@ -624,7 +625,7 @@ static void dm_mst_test_aux_transfer_native_read(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -675,7 +676,7 @@ static void dm_mst_test_aux_transfer_native_write(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -727,7 +728,7 @@ static void dm_mst_test_aux_transfer_partial_write(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -771,7 +772,7 @@ static void dm_mst_test_aux_transfer_error_result(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -816,7 +817,7 @@ static void dm_mst_test_aux_transfer_hpd_discon_quirk(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -870,7 +871,7 @@ static void dm_mst_test_aux_transfer_non_ack_reply(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -1196,14 +1197,14 @@ static void dm_mst_test_initialize_dp_connector_mst(struct kunit *test)
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = dm_kunit_alloc_link(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ddc);
KUNIT_ASSERT_NOT_NULL(test, dc);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link_srv->dp_get_max_link_enc_cap = dm_mst_test_dp_get_max_link_enc_cap;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
link->ddc = ddc;
@@ -1656,7 +1657,7 @@ static void dm_mst_test_init_child(struct kunit *test, struct dm_mst_test_child
ret = drmm_mode_config_init(&adev->ddev);
KUNIT_ASSERT_EQ(test, ret, 0);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
child->port = kunit_kzalloc(test, sizeof(*child->port), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1665,7 +1666,7 @@ static void dm_mst_test_init_child(struct kunit *test, struct dm_mst_test_child
link_srv->add_remote_sink = dm_mst_test_add_remote_sink;
link_srv->remove_remote_sink = dm_mst_test_remove_remote_sink;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
child->adev = adev;
child->link = dm_kunit_alloc_link(test);
@@ -2519,7 +2520,7 @@ static void dm_mst_test_init_dsc_ctx(struct kunit *test, struct dm_mst_test_dsc_
dc = dm_kunit_alloc_dc_with_ctx(test);
ctx->link = dm_kunit_alloc_link(test);
- ctx->link->ctx = dc->ctx;
+ ctx->link->ctx = dc_get_ctx(dc);
ctx->port = dm_mst_test_alloc_mgr_port(test);
ctx->port->parent = branch;
@@ -2680,14 +2681,14 @@ static void dm_mst_test_init_port_mode_ctx(struct kunit *test,
link_srv->dp_link_bandwidth_kbps = dm_mst_test_root_bandwidth_kbps;
ctx->dc = dm_kunit_alloc_dc_with_ctx(test);
- ctx->dc->link_srv = link_srv;
- ctx->dc->res_pool = res_pool;
+ dc_test_install_link_service(ctx->dc, link_srv);
+ dc_test_set_res_pool(ctx->dc, res_pool);
ctx->link = dm_kunit_alloc_link(test);
ctx->link->dc = ctx->dc;
- ctx->link->ctx = ctx->dc->ctx;
+ ctx->link->ctx = dc_get_ctx(ctx->dc);
- ctx->sink->ctx = ctx->dc->ctx;
+ ctx->sink->ctx = dc_get_ctx(ctx->dc);
ctx->port = dm_mst_test_alloc_mgr_port(test);
ctx->port->full_pbn = full_pbn;
@@ -2789,8 +2790,8 @@ static void dm_mst_test_setup_dsc_caps(struct kunit *test, struct dc *dc, struct
KUNIT_ASSERT_NOT_NULL(test, dsc);
dsc->funcs = &dm_mst_test_dsc_funcs;
- dsc->ctx = dc->ctx;
- dc->res_pool->dscs[0] = dsc;
+ dsc->ctx = dc_get_ctx(dc);
+ dc_get_res_pool(dc)->dscs[0] = dsc;
dec->is_dsc_supported = true;
dec->dsc_version = 0x21;
@@ -3026,8 +3027,8 @@ static struct amdgpu_dm_connector *dm_mst_test_alloc_frl_connector(struct kunit
link_srv->bw_kbps_from_raw_frl_link_rate_data = dm_mst_test_bw_kbps_from_raw_frl;
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->link_srv = link_srv;
- dc->caps.dp_hdmi21_pcon_support = pcon_support;
+ dc_test_install_link_service(dc, link_srv);
+ dc_test_caps(dc)->dp_hdmi21_pcon_support = pcon_support;
link = dm_kunit_alloc_link(test);
link->dc = dc;
@@ -3314,7 +3315,7 @@ static void dm_mst_test_init_recompute_ctx(struct kunit *test,
ctx->adev->ddev.mode_config.num_crtc = 1;
ctx->dc = dm_kunit_alloc_dc_with_ctx(test);
- ctx->dc->current_state = dm_kunit_alloc_dc_state(test);
+ dc_test_set_current_state(ctx->dc, dm_kunit_alloc_dc_state(test));
ctx->dc_state = dm_kunit_alloc_dc_state(test);
ctx->link = dm_kunit_alloc_link(test);
@@ -3444,7 +3445,7 @@ static void dm_mst_test_recompute_unchanged_stream(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- dm_mst_test_add_link_stream(test, ctx.dc->current_state, ctx.link, ctx.aconnector);
+ dm_mst_test_add_link_stream(test, dc_get_current_state(ctx.dc), ctx.link, ctx.aconnector);
ctx.crtc_state->enable = true;
ctx.crtc_state->active = true;
@@ -3466,7 +3467,7 @@ static void dm_mst_test_recompute_stream_removed(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
gone = dm_kunit_alloc_connector(test, ctx.adev, ctx.link);
dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- dm_mst_test_add_link_stream(test, ctx.dc->current_state, ctx.link, gone);
+ dm_mst_test_add_link_stream(test, dc_get_current_state(ctx.dc), ctx.link, gone);
ctx.crtc_state->enable = true;
ctx.crtc_state->active = true;
@@ -3500,7 +3501,7 @@ static void dm_mst_test_recompute_connector_without_crtc(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- dm_mst_test_add_link_stream(test, ctx.dc->current_state, ctx.link, ctx.aconnector);
+ dm_mst_test_add_link_stream(test, dc_get_current_state(ctx.dc), ctx.link, ctx.aconnector);
ctx.conn_state->crtc = NULL;
KUNIT_EXPECT_FALSE(test, is_dsc_need_re_compute(ctx.state, ctx.dc_state, ctx.link));
@@ -3544,13 +3545,13 @@ dm_mst_test_add_mst_dsc_stream(struct kunit *test, struct dm_mst_test_recompute_
funcs->remove_stream_from_ctx = remove_stream;
res_pool->funcs = funcs;
- ctx->dc->res_pool = res_pool;
+ dc_test_set_res_pool(ctx->dc, res_pool);
sink->dsc_caps.dsc_dec_caps.is_dsc_supported = true;
ctx->aconnector->dc_sink = sink;
ctx->aconnector->mst_output_port = port;
stream = dm_mst_test_add_link_stream(test, ctx->dc_state, ctx->link, ctx->aconnector);
- stream->ctx = ctx->dc->ctx;
+ stream->ctx = dc_get_ctx(ctx->dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
return stream;
@@ -3568,7 +3569,7 @@ static void dm_mst_test_compute_configs_skips_sst(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
stream = dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- stream->ctx = ctx.dc->ctx;
+ stream->ctx = dc_get_ctx(ctx.dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT;
KUNIT_EXPECT_EQ(test, compute_mst_dsc_configs_for_state(ctx.state, ctx.dc_state, vars), 0);
@@ -3589,7 +3590,7 @@ static void dm_mst_test_compute_configs_skips_incomplete(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
stream = dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- stream->ctx = ctx.dc->ctx;
+ stream->ctx = dc_get_ctx(ctx.dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
KUNIT_EXPECT_EQ(test, compute_mst_dsc_configs_for_state(ctx.state, ctx.dc_state, vars), 0);
@@ -3663,7 +3664,7 @@ static void dm_mst_test_pre_compute_configs_skips_sst(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
stream = dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- stream->ctx = ctx.dc->ctx;
+ stream->ctx = dc_get_ctx(ctx.dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT;
KUNIT_EXPECT_EQ(test, pre_compute_mst_dsc_configs_for_state(ctx.state, ctx.dc_state, vars), 0);
@@ -3681,7 +3682,7 @@ static void dm_mst_test_pre_compute_configs_skips_incomplete(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
stream = dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- stream->ctx = ctx.dc->ctx;
+ stream->ctx = dc_get_ctx(ctx.dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
KUNIT_EXPECT_EQ(test, pre_compute_mst_dsc_configs_for_state(ctx.state, ctx.dc_state, vars), 0);
@@ -3846,16 +3847,16 @@ dm_mst_test_alloc_dsc_link_ctx(struct kunit *test, int total_avail_slots)
link_srv->mst_decide_link_encoding_format = dm_mst_test_mst_encoding_format;
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->link_srv = link_srv;
- dc->res_pool = res_pool;
- dc->current_state = dm_kunit_alloc_dc_state(test);
+ dc_test_install_link_service(dc, link_srv);
+ dc_test_set_res_pool(dc, res_pool);
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
link = dm_kunit_alloc_link(test);
link->dc = dc;
- link->ctx = dc->ctx;
+ link->ctx = dc_get_ctx(dc);
link->type = dc_connection_mst_branch;
- sink->ctx = dc->ctx;
+ sink->ctx = dc_get_ctx(dc);
dm_mst_test_setup_dsc_caps(test, dc, sink);
/* The payload allocation takes a reference, so start above zero. */
@@ -3870,7 +3871,7 @@ dm_mst_test_alloc_dsc_link_ctx(struct kunit *test, int total_avail_slots)
ctx->dc_state = dm_kunit_alloc_dc_state(test);
ctx->stream = dm_kunit_alloc_stream(test, link);
- ctx->stream->ctx = dc->ctx;
+ ctx->stream->ctx = dc_get_ctx(dc);
ctx->stream->sink = sink;
ctx->stream->dm_stream_context = ctx->aconnector;
ctx->stream->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
index 7422e8ba9564..0d8fd26bb0ac 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
@@ -18,6 +18,7 @@
#include <drm/drm_mode_config.h>
#include <drm/drm_plane.h>
#include <drm/drm_property.h>
+#include "dc_test.h"
struct dm_test_dcc_cap_ctx {
bool callback_ret;
@@ -364,19 +365,19 @@ static void dm_test_get_min_max_dc_plane_scaling(struct kunit *test)
int max_upscale = 0;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
KUNIT_ASSERT_NOT_NULL(test, fb);
adev->dm.dc = dc;
- dc->caps.planes[0].max_upscale_factor.nv12 = 1;
- dc->caps.planes[0].max_downscale_factor.nv12 = 1;
- dc->caps.planes[0].max_upscale_factor.argb8888 = 1600;
- dc->caps.planes[0].max_downscale_factor.argb8888 = 250;
- dc->caps.planes[0].max_upscale_factor.fp16 = 2000;
- dc->caps.planes[0].max_downscale_factor.fp16 = 500;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.nv12 = 1;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.nv12 = 1;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.argb8888 = 1600;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.argb8888 = 250;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.fp16 = 2000;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.fp16 = 500;
fb->format = drm_format_info(DRM_FORMAT_NV12);
KUNIT_ASSERT_NOT_NULL(test, fb->format);
@@ -688,7 +689,7 @@ static void dm_test_validate_dcc_rejects_from_cap(struct kunit *test)
dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
&plane_size, test);
dcc.independent_64b_blks = cases[i].independent_64b_blks;
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
dm_test_dcc_ctx = &ctx;
ret = amdgpu_dm_plane_validate_dcc(adev, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
@@ -723,7 +724,7 @@ static void dm_test_validate_dcc_success_and_scan_mapping(struct kunit *test)
dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
&plane_size, test);
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
dm_test_dcc_ctx = &ctx;
KUNIT_EXPECT_EQ(test,
@@ -1103,7 +1104,7 @@ static void dm_test_setup_gfx9_dcc_device(struct amdgpu_device *adev,
adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
adev->gfx.config.gb_addr_config_fields.num_pkrs = 2;
adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
ctx->callback_ret = true;
ctx->capable = true;
ctx->output_independent_64b_blks = output_independent_64b_blks;
@@ -1406,7 +1407,7 @@ static void dm_test_fill_gfx9_plane_attributes_dcc(struct kunit *test)
int ret;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1417,7 +1418,7 @@ static void dm_test_fill_gfx9_plane_attributes_dcc(struct kunit *test)
adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
adev->gfx.config.gb_addr_config_fields.num_pkrs = 2;
adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
dm_test_dcc_ctx = &ctx;
afb->base.pitches[1] = 256;
@@ -1460,7 +1461,7 @@ static void dm_test_fill_gfx9_plane_attributes_validate_fails(struct kunit *test
int ret;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1511,7 +1512,7 @@ static void dm_test_fill_gfx9_plane_attributes_dcc_ind_blk(struct kunit *test)
unsigned int i;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1575,7 +1576,7 @@ static void dm_test_fill_gfx12_plane_attributes_dcc_blocks(struct kunit *test)
unsigned int i;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1583,7 +1584,7 @@ static void dm_test_fill_gfx12_plane_attributes_dcc_blocks(struct kunit *test)
adev->family = AMDGPU_FAMILY_GC_12_0_0;
adev->dm.dc = dc;
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
plane_size.surface_size.width = 1920;
plane_size.surface_size.height = 1080;
@@ -1635,7 +1636,7 @@ static void dm_test_fill_gfx12_plane_attributes_validate_fails(struct kunit *tes
int ret;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1726,7 +1727,7 @@ static void dm_test_fill_plane_buffer_attributes_gfx12(struct kunit *test)
int ret;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
tiling_info = (struct dc_tiling_info){0};
plane_size = (struct plane_size){0};
@@ -1772,7 +1773,7 @@ static void dm_test_helper_check_state_scaling_caps(struct kunit *test)
struct drm_framebuffer *fb;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
@@ -1787,8 +1788,8 @@ static void dm_test_helper_check_state_scaling_caps(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, fb);
adev->dm.dc = dc;
- dc->caps.planes[0].max_upscale_factor.argb8888 = 1;
- dc->caps.planes[0].max_downscale_factor.argb8888 = 1;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.argb8888 = 1;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.argb8888 = 1;
plane->type = DRM_PLANE_TYPE_OVERLAY;
plane->dev = &adev->ddev;
@@ -1873,7 +1874,7 @@ static void dm_test_fill_dc_scaling_info_plane_caps(struct kunit *test)
struct dc_scaling_info info = {0};
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
@@ -1884,8 +1885,8 @@ static void dm_test_fill_dc_scaling_info_plane_caps(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, fb);
adev->dm.dc = dc;
- dc->caps.planes[0].max_upscale_factor.argb8888 = 16000;
- dc->caps.planes[0].max_downscale_factor.argb8888 = 250;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.argb8888 = 16000;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.argb8888 = 250;
plane->dev = &adev->ddev;
fb->format = drm_format_info(DRM_FORMAT_XRGB8888);
@@ -2025,7 +2026,7 @@ static struct amdgpu_device *dm_test_init_atomic_check_state(struct kunit *test,
struct drm_crtc *crtc;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
*state = kunit_kzalloc(test, sizeof(**state), GFP_KERNEL);
planes = kunit_kzalloc(test, sizeof(*planes), GFP_KERNEL);
crtcs = kunit_kzalloc(test, sizeof(*crtcs), GFP_KERNEL);
@@ -2048,10 +2049,10 @@ static struct amdgpu_device *dm_test_init_atomic_check_state(struct kunit *test,
KUNIT_ASSERT_NOT_NULL(test, *fb);
adev->dm.dc = dc;
- dc->caps.planes[0].max_upscale_factor.argb8888 = 1000;
- dc->caps.planes[0].max_downscale_factor.argb8888 = 1000;
- dc->caps.planes[0].max_upscale_factor.nv12 = 1000;
- dc->caps.planes[0].max_downscale_factor.nv12 = 1000;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.argb8888 = 1000;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.argb8888 = 1000;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.nv12 = 1000;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.nv12 = 1000;
(*plane)->dev = &adev->ddev;
(*plane)->index = 0;
@@ -3009,7 +3010,7 @@ static void dm_test_atomic_check_success(struct kunit *test)
res_pool->funcs = kunit_kzalloc(test, sizeof(*res_pool->funcs), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, res_pool->funcs);
- adev->dm.dc->res_pool = res_pool;
+ dc_test_set_res_pool(adev->dm.dc, res_pool);
dm_plane_state->dc_state->src_rect.width = 100;
dm_plane_state->dc_state->src_rect.height = 100;
@@ -3107,7 +3108,7 @@ static void dm_test_handle_cursor_update_no_stream(struct kunit *test)
struct dm_test_cursor_ctx *ctx = dm_test_alloc_cursor_ctx(test);
ctx->crtc_state->cm_is_degamma_srgb = true;
- ctx->adev->dm.dc->caps.color.dpp.gamma_corr = true;
+ dc_test_caps(ctx->adev->dm.dc)->color.dpp.gamma_corr = true;
amdgpu_dm_plane_handle_cursor_update(ctx->plane, &ctx->old_state);
@@ -3153,11 +3154,11 @@ static void dm_test_panic_flush_disables_dcc(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, res_pool);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = dm_kunit_alloc_dc_state(test);
- dc->hwss.clear_surface_dcc_and_tiling = dm_test_clear_surface_dcc_and_tiling;
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
+ dc_test_hwss(dc)->clear_surface_dcc_and_tiling = dm_test_clear_surface_dcc_and_tiling;
res_pool->pipe_count = 1;
- dc->res_pool = res_pool;
- dc_plane_state->ctx = dc->ctx;
+ dc_test_set_res_pool(dc, res_pool);
+ dc_plane_state->ctx = dc_get_ctx(dc);
fb->modifier = AMD_FMT_MOD;
dm_plane_state->base.fb = fb;
@@ -3231,7 +3232,7 @@ static void dm_test_plane_init_creates_color_pipeline(struct kunit *test)
struct drm_plane *plane;
plane = dm_test_alloc_init_plane(test, &adev);
- adev->dm.dc->ctx->dce_version = DCN_VERSION_3_0;
+ dc_get_ctx(adev->dm.dc)->dce_version = DCN_VERSION_3_0;
KUNIT_ASSERT_EQ(test, amdgpu_dm_plane_init(&adev->dm, plane, 1, NULL), 0);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c
index 0a484ea7c0e8..8b9e34b3c4be 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c
@@ -8,6 +8,7 @@
#include <kunit/test.h>
#include "dc.h"
+#include "dc_test.h"
#include "core_types.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
@@ -50,7 +51,7 @@ static struct dc_link *alloc_test_psrsu_link(struct kunit *test)
struct dc_context *ctx = link->ctx;
struct dc *dc = ctx->dc;
- dc->caps.dmcub_support = true;
+ dc_test_caps(dc)->dmcub_support = true;
ctx->dce_version = DCN_VERSION_3_1;
link->dpcd_caps.edp_rev = DP_EDP_14;
link->dpcd_caps.psr_info.psr_version = DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
@@ -64,7 +65,7 @@ static struct dc_link *alloc_test_psr_caps_link(struct kunit *test)
{
struct dc_link *link = alloc_test_psrsu_link(test);
- link->ctx->dc->caps.dmub_caps.psr = true;
+ dc_test_caps(link->ctx->dc)->dmub_caps.psr = true;
link->connector_signal = SIGNAL_TYPE_EDP;
link->type = dc_connection_single;
@@ -91,7 +92,7 @@ static void dm_test_link_supports_psrsu_no_dmcub(struct kunit *test)
{
struct dc_link *link = alloc_test_psrsu_link(test);
- link->ctx->dc->caps.dmcub_support = false;
+ dc_test_caps(link->ctx->dc)->dmcub_support = false;
KUNIT_EXPECT_FALSE(test, link_supports_psrsu(link));
}
@@ -232,7 +233,7 @@ static void dm_test_set_psr_caps_no_dmub_psr(struct kunit *test)
struct amdgpu_dm_connector *aconnector = alloc_test_aconnector(test);
link->psr_settings.psr_version = DC_PSR_VERSION_1;
- link->ctx->dc->caps.dmub_caps.psr = false;
+ dc_test_caps(link->ctx->dc)->dmub_caps.psr = false;
KUNIT_EXPECT_FALSE(test, amdgpu_dm_set_psr_caps(link, aconnector));
KUNIT_EXPECT_EQ(test, link->psr_settings.psr_version,
@@ -293,9 +294,9 @@ static void dm_test_set_psr_caps_edp1_disabled(struct kunit *test)
struct dc *dc = link->ctx->dc;
edp0->connector_signal = SIGNAL_TYPE_EDP;
- dc->links[0] = edp0;
- dc->links[1] = link;
- dc->link_count = 2;
+ dc_test_set_link(dc, 0, edp0);
+ dc_test_set_link(dc, 1, link);
+ dc_test_set_link_count(dc, 2);
KUNIT_EXPECT_FALSE(test, amdgpu_dm_set_psr_caps(link, aconnector));
}
@@ -647,7 +648,7 @@ static void dm_test_psr_is_active_allowed_no_streams(struct kunit *test)
static void dm_test_psr_is_active_allowed_null_link(struct kunit *test)
{
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
- struct dc_state *state = dm->dc->current_state;
+ struct dc_state *state = dc_get_current_state(dm->dc);
dm_kunit_add_stream_to_state(test, state, 0, NULL);
@@ -662,7 +663,7 @@ static void dm_test_psr_is_active_allowed_null_link(struct kunit *test)
static void dm_test_psr_is_active_allowed_requires_enabled_and_allowed(struct kunit *test)
{
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
- struct dc_state *state = dm->dc->current_state;
+ struct dc_state *state = dc_get_current_state(dm->dc);
struct dc_link *link = dm_kunit_alloc_link(test);
dm_kunit_add_stream_to_state(test, state, 0, link);
@@ -682,7 +683,7 @@ static void dm_test_psr_is_active_allowed_requires_enabled_and_allowed(struct ku
static void dm_test_psr_is_active_allowed_any_stream(struct kunit *test)
{
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
- struct dc_state *state = dm->dc->current_state;
+ struct dc_state *state = dc_get_current_state(dm->dc);
struct dc_link *disabled_link = dm_kunit_alloc_link(test);
struct dc_link *allowed_link = dm_kunit_alloc_link(test);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
index c375ee68778b..c0dbab0b7c46 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
@@ -22,6 +22,7 @@
#include <drm/drm_writeback.h>
#include "dc.h"
+#include "dc_test.h"
#include "dc/dc_dmub_srv.h"
#include "dal_asic_id.h"
#include "dm_services_types.h"
@@ -1279,13 +1280,13 @@ static void dm_test_crtc_with_stream(struct kunit *test,
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- dc->ctx->logger = logger;
+ dc_get_ctx(dc)->logger = logger;
- dc->current_state = dm_kunit_alloc_dc_state(test);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
stream = dm_kunit_alloc_stream(test, NULL);
- stream->ctx = dc->ctx;
+ stream->ctx = dc_get_ctx(dc);
adev->dm.dc = dc;
adev->mode_info.num_crtc = 1;
@@ -1337,8 +1338,8 @@ static void dm_test_crtc_get_scanoutpos_exits_idle(struct kunit *test)
u32 position = 0;
dm_test_crtc_with_stream(test, adev, dc);
- dc->caps.ips_support = true;
- dc->idle_optimizations_allowed = true;
+ dc_test_caps(dc)->ips_support = true;
+ dc_test_set_idle_optimizations_allowed(dc, true);
KUNIT_EXPECT_EQ(test, dm_crtc_get_scanoutpos(adev, 0, &vbl, &position), 0);
}
@@ -2940,8 +2941,8 @@ static struct dc_link *dm_test_dc_with_link(struct kunit *test,
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
struct dc_link *link = dm_kunit_alloc_link(test);
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
adev->dm.dc = dc;
return link;
@@ -2967,7 +2968,7 @@ static void dm_test_dump_links_with_sinks(struct kunit *test)
link->local_sink = local_sink;
link->sink_count = 1;
link->remote_sinks[0] = remote_sink;
- adev->dm.dc->link_count = 2;
+ dc_test_set_link_count(adev->dm.dc, 2);
amdgpu_dm_dump_links_and_sinks(adev);
}
@@ -3328,7 +3329,7 @@ static void dm_test_trigger_timing_sync_streams(struct kunit *test)
context->streams[0] = stream;
context->stream_count = 1;
- dc->current_state = context;
+ dc_test_set_current_state(dc, context);
adev->dm.dc = dc;
adev->dm.force_timing_sync = true;
mutex_init(&adev->dm.dc_lock);
@@ -3387,8 +3388,8 @@ static void dm_test_oem_i2c_hw_init_no_device(struct kunit *test)
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->res_pool = kunit_kzalloc(test, sizeof(*dc->res_pool), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->res_pool);
+ dc_test_set_res_pool(dc, kunit_kzalloc(test, sizeof(*dc_get_res_pool(dc)), GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_res_pool(dc));
adev->dm.dc = dc;
KUNIT_EXPECT_EQ(test, dm_oem_i2c_hw_init(adev), 0);
@@ -4471,8 +4472,8 @@ static void dm_test_commit_zero_streams_empty(struct kunit *test)
{
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = dm_kunit_alloc_dc_state(test);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
KUNIT_EXPECT_EQ(test, (int)amdgpu_dm_commit_zero_streams(dc), (int)DC_OK);
}
@@ -4550,7 +4551,7 @@ static void dm_test_clear_writeback_removes_stream(struct kunit *test)
acrtc = kunit_kzalloc(test, sizeof(*acrtc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, acrtc);
stream = dm_kunit_alloc_stream(test, NULL);
- dm->dc->hwss.update_bandwidth = dm_test_update_bandwidth;
+ dc_test_hwss(dm->dc)->update_bandwidth = dm_test_update_bandwidth;
crtc_state->stream = stream;
stream->num_wb_info = 1;
stream->writeback_info[0].dwb_pipe_inst = 0;
@@ -4588,7 +4589,7 @@ static void dm_test_set_writeback_no_pipe(struct kunit *test)
acrtc = kunit_kzalloc(test, sizeof(*acrtc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, acrtc);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = dm_kunit_alloc_dc_state(test);
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
adev->dm.adev = adev;
adev->dm.dc = dc;
@@ -4735,8 +4736,8 @@ dm_test_plane_attr_ctx_alloc(struct kunit *test, u32 drm_format)
ctx->adev = dm_kunit_alloc_adev(test);
ctx->adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- ctx->adev->dm.dc->caps.planes[0].max_upscale_factor.argb8888 = 1;
- ctx->adev->dm.dc->caps.planes[0].max_downscale_factor.argb8888 = 1;
+ dc_test_caps(ctx->adev->dm.dc)->planes[0].max_upscale_factor.argb8888 = 1;
+ dc_test_caps(ctx->adev->dm.dc)->planes[0].max_downscale_factor.argb8888 = 1;
ctx->crtc_state->stream = dm_kunit_alloc_stream(test, NULL);
/* Colour management resolves the device through the commit backpointer. */
@@ -4821,7 +4822,7 @@ static void dm_test_plane_attributes_bad_color_mgmt(struct kunit *test)
/* A 3D LUT that is not a perfect cube fails validation. */
blob->data = lut;
blob->length = 16 * sizeof(*lut);
- ctx->adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(ctx->adev->dm.dc)->color.dpp.hw_3d_lut = true;
ctx->plane->dm_plane_state->lut3d = blob;
KUNIT_EXPECT_EQ(test, dm_test_fill_plane_attr(ctx), -EINVAL);
@@ -4980,8 +4981,8 @@ static struct amdgpu_device *dm_test_late_init_adev(struct kunit *test)
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->res_pool = kunit_kzalloc(test, sizeof(*dc->res_pool), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->res_pool);
+ dc_test_set_res_pool(dc, kunit_kzalloc(test, sizeof(*dc_get_res_pool(dc)), GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_res_pool(dc));
adev->dm.dc = dc;
return adev;
@@ -5044,7 +5045,7 @@ static void dm_test_late_init_boot_crc_disabled(struct kunit *test)
dm_test_fw_boot_options.bits.bootcrc_en_at_S0i3 = 0;
dmub->hw_funcs.get_fw_boot_option = dm_test_get_fw_boot_option;
dmub_srv->dmub = dmub;
- adev->dm.dc->ctx->dmub_srv = dmub_srv;
+ dc_get_ctx(adev->dm.dc)->dmub_srv = dmub_srv;
adev->ip_versions[DCE_HWIP][0] = IP_VERSION(3, 6, 0);
KUNIT_EXPECT_EQ(test, dm_test_run_late_init(adev), 0);
@@ -5074,8 +5075,8 @@ static struct amdgpu_device *dm_test_mode_config_adev(struct kunit *test)
long saved_audio = amdgpu_dm_audio_get_param();
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- adev->dm.dc->current_state = dm_kunit_alloc_dc_state(test);
- KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, dm_kunit_alloc_dc_state(test));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(adev->dm.dc));
amdgpu_dm_audio_set_param(0);
KUNIT_ASSERT_EQ(test, kunit_add_action_or_reset(test, dm_test_restore_audio_param,
@@ -5141,7 +5142,7 @@ static void dm_test_initialize_plane_primary(struct kunit *test)
adev->family = AMDGPU_FAMILY_NV;
adev->dm.adev = adev;
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- adev->dm.dc->caps.max_streams = 1;
+ dc_test_caps(adev->dm.dc)->max_streams = 1;
KUNIT_ASSERT_EQ(test, initialize_plane(&adev->dm, mode_info, 0,
DRM_PLANE_TYPE_PRIMARY, NULL), 0);
@@ -5167,7 +5168,7 @@ static void dm_test_initialize_plane_overlay(struct kunit *test)
adev->family = AMDGPU_FAMILY_NV;
adev->dm.adev = adev;
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- adev->dm.dc->caps.max_streams = 1;
+ dc_test_caps(adev->dm.dc)->max_streams = 1;
plane_cap->per_pixel_alpha = true;
plane_cap->pixel_format_support.nv12 = true;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_wb_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_wb_test.c
index 047ac88cb2a9..d43f150704d1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_wb_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_wb_test.c
@@ -18,6 +18,7 @@
#include <drm/drm_writeback.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_wb.h"
@@ -495,13 +496,12 @@ static void dm_test_wb_connector_init_success(struct kunit *test)
dm = &adev->dm;
dm->adev = adev;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
- dc->links[0] = link;
+ dc_test_set_link(dc, 0, link);
dm->dc = dc;
ret = amdgpu_dm_wb_connector_init(dm, wbcon, 0);
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 0f39a15dfc60..440f5d358188 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -92,5 +92,9 @@ FILES += bls_executor/bls_executor.o
FILES += workaround_manager/workaround_manager.o
FILES += dmub_messenger/dmub_messenger.o
+ifneq ($(CONFIG_DRM_AMD_DC_KUNIT_TEST),)
+FILES += core/dc_test.o
+endif
+
AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/, $(FILES))
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 2803471d7333..4c583d452446 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -31,6 +31,7 @@
* mapping stays obvious and auditable.
*/
#include "dc.h"
+#include "dm_helpers.h" /* EXPORT_IF_KUNIT */
uint8_t dc_get_link_count(const struct dc *dc)
{
@@ -41,6 +42,7 @@ struct dc_context *dc_get_ctx(const struct dc *dc)
{
return dc->ctx;
}
+EXPORT_IF_KUNIT(dc_get_ctx);
enum dce_version dc_get_dce_version(const struct dc *dc)
{
@@ -77,21 +79,25 @@ struct dc_state *dc_get_current_state(const struct dc *dc)
{
return dc->current_state;
}
+EXPORT_IF_KUNIT(dc_get_current_state);
bool dc_is_idle_optimizations_allowed(const struct dc *dc)
{
return dc->idle_optimizations_allowed;
}
+EXPORT_IF_KUNIT(dc_is_idle_optimizations_allowed);
struct resource_pool *dc_get_res_pool(const struct dc *dc)
{
return dc->res_pool;
}
+EXPORT_IF_KUNIT(dc_get_res_pool);
struct clk_mgr *dc_get_clk_mgr(struct dc *dc)
{
return dc->clk_mgr;
}
+EXPORT_IF_KUNIT(dc_get_clk_mgr);
bool dc_get_dcc_compression_cap(const struct dc *dc,
const struct dc_dcc_surface_param *input,
@@ -139,6 +145,7 @@ bool dc_is_fbc_compressor_available(const struct dc *dc)
{
return dc->fbc_compressor != NULL;
}
+EXPORT_IF_KUNIT(dc_is_fbc_compressor_available);
void dc_set_fbc_gpu_addr(struct dc *dc, uint64_t gpu_addr)
{
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_test.c b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
new file mode 100644
index 000000000000..60fb45f9cfaa
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/* FILE POLICY AND INTENDED USAGE:
+ * Implementation of the KUnit test double API declared in dc_test.h.
+ * struct dc is private to DC; this file is the only place outside of the
+ * accessors that maps test operations onto struct dc members. It carries
+ * no functional behavior.
+ */
+#include <linux/slab.h>
+#include <linux/export.h>
+
+#include "dc.h"
+#include "dc_test.h"
+
+struct dc *dc_test_create(void)
+{
+ return kvzalloc(sizeof(struct dc), GFP_KERNEL);
+}
+EXPORT_SYMBOL(dc_test_create);
+
+void dc_test_destroy(struct dc *dc)
+{
+ kvfree(dc);
+}
+EXPORT_SYMBOL(dc_test_destroy);
+
+void dc_test_set_ctx(struct dc *dc, struct dc_context *ctx)
+{
+ dc->ctx = ctx;
+}
+EXPORT_SYMBOL(dc_test_set_ctx);
+
+void dc_test_set_current_state(struct dc *dc, struct dc_state *state)
+{
+ dc->current_state = state;
+}
+EXPORT_SYMBOL(dc_test_set_current_state);
+
+void dc_test_install_link_service(struct dc *dc,
+ struct link_service *link_srv)
+{
+ dc->link_srv = link_srv;
+}
+EXPORT_SYMBOL(dc_test_install_link_service);
+
+void dc_test_set_res_pool(struct dc *dc, struct resource_pool *res_pool)
+{
+ dc->res_pool = res_pool;
+}
+EXPORT_SYMBOL(dc_test_set_res_pool);
+
+void dc_test_set_clk_mgr(struct dc *dc, struct clk_mgr *clk_mgr)
+{
+ dc->clk_mgr = clk_mgr;
+}
+EXPORT_SYMBOL(dc_test_set_clk_mgr);
+
+void dc_test_set_fbc_compressor(struct dc *dc, struct compressor *compressor)
+{
+ dc->fbc_compressor = compressor;
+}
+EXPORT_SYMBOL(dc_test_set_fbc_compressor);
+
+void dc_test_set_link(struct dc *dc, unsigned int index, struct dc_link *link)
+{
+ if (index >= MAX_LINKS)
+ return;
+
+ dc->links[index] = link;
+}
+EXPORT_SYMBOL(dc_test_set_link);
+
+void dc_test_set_link_count(struct dc *dc, unsigned int count)
+{
+ dc->link_count = count;
+}
+EXPORT_SYMBOL(dc_test_set_link_count);
+
+void dc_test_set_idle_optimizations_allowed(struct dc *dc, bool allowed)
+{
+ dc->idle_optimizations_allowed = allowed;
+}
+EXPORT_SYMBOL(dc_test_set_idle_optimizations_allowed);
+
+struct dc_caps *dc_test_caps(struct dc *dc)
+{
+ return &dc->caps;
+}
+EXPORT_SYMBOL(dc_test_caps);
+
+struct dc_config *dc_test_config(struct dc *dc)
+{
+ return &dc->config;
+}
+EXPORT_SYMBOL(dc_test_config);
+
+struct dc_debug_options *dc_test_debug_options(struct dc *dc)
+{
+ return &dc->debug;
+}
+EXPORT_SYMBOL(dc_test_debug_options);
+
+struct dc_cap_funcs *dc_test_cap_funcs(struct dc *dc)
+{
+ return &dc->cap_funcs;
+}
+EXPORT_SYMBOL(dc_test_cap_funcs);
+
+struct hw_sequencer_funcs *dc_test_hwss(struct dc *dc)
+{
+ return &dc->hwss;
+}
+EXPORT_SYMBOL(dc_test_hwss);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_test.h b/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
new file mode 100644
index 000000000000..61911de9da05
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __DC_TEST_H__
+#define __DC_TEST_H__
+
+/*
+ * KUnit support for building DC test doubles.
+ *
+ * struct dc is private to DC, so test code outside the dc directory cannot
+ * allocate one or poke its members directly. These helpers construct an
+ * empty fake DC instance and let tests install the pieces they need. They
+ * exist only when the amdgpu_dm KUnit tests are enabled and must never be
+ * used outside tests.
+ */
+
+struct dc;
+struct dc_context;
+struct dc_state;
+struct dc_link;
+struct dc_caps;
+struct dc_config;
+struct dc_debug_options;
+struct dc_cap_funcs;
+struct link_service;
+struct resource_pool;
+struct clk_mgr;
+struct compressor;
+struct hw_sequencer_funcs;
+
+#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
+
+/*
+ * Allocate a zeroed fake DC instance. Free it with dc_test_destroy() (or
+ * register that as a KUnit action).
+ */
+struct dc *dc_test_create(void);
+void dc_test_destroy(struct dc *dc);
+
+void dc_test_set_ctx(struct dc *dc, struct dc_context *ctx);
+void dc_test_set_current_state(struct dc *dc, struct dc_state *state);
+void dc_test_install_link_service(struct dc *dc,
+ struct link_service *link_srv);
+void dc_test_set_res_pool(struct dc *dc, struct resource_pool *res_pool);
+void dc_test_set_clk_mgr(struct dc *dc, struct clk_mgr *clk_mgr);
+void dc_test_set_fbc_compressor(struct dc *dc, struct compressor *compressor);
+void dc_test_set_link(struct dc *dc, unsigned int index, struct dc_link *link);
+void dc_test_set_link_count(struct dc *dc, unsigned int count);
+void dc_test_set_idle_optimizations_allowed(struct dc *dc, bool allowed);
+
+/* Mutable views of embedded sub-structures, for test faking only. */
+struct dc_caps *dc_test_caps(struct dc *dc);
+struct dc_config *dc_test_config(struct dc *dc);
+struct dc_debug_options *dc_test_debug_options(struct dc *dc);
+struct dc_cap_funcs *dc_test_cap_funcs(struct dc *dc);
+struct hw_sequencer_funcs *dc_test_hwss(struct dc *dc);
+
+#endif /* IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) */
+
+#endif /* __DC_TEST_H__ */
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 12/19] drm/amd/display: Migrate amdgpu_dm KUnit tests off struct dc internals
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
The amdgpu_dm KUnit tests constructed fake struct dc instances with
kunit_kzalloc(sizeof(*dc)) and populated members directly. Add a
KUnit-gated test double API in DC (dc/inc/dc_test.h implemented in
dc/core/dc_test.c) that allocates the fake and exposes setters and
mutable views for the members tests need:
- dc_test_create/destroy for the fake instance
- setters for ctx, current_state, link_srv, res_pool, clk_mgr,
fbc_compressor, links[], link_count, idle_optimizations_allowed
- mutable views for caps, config, debug, hwss and cap_funcs
Rework dm_kunit_alloc_dc* helpers on top of it and convert all test
files to the API plus the public accessors (dc_get_ctx,
dc_get_current_state, dc_get_res_pool, dc_get_clk_mgr, ...), which
are exported for the test modules with EXPORT_IF_KUNIT.
No test logic changes; only how the fakes are built.
Part of making struct dc private to DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../display/amdgpu_dm/tests/amdgpu_dm_audio_test.c | 41 ++---
.../amdgpu_dm/tests/amdgpu_dm_backlight_test.c | 71 ++++----
.../display/amdgpu_dm/tests/amdgpu_dm_color_test.c | 21 +--
.../amdgpu_dm/tests/amdgpu_dm_colorop_test.c | 8 +-
.../amdgpu_dm/tests/amdgpu_dm_connector_test.c | 62 ++++---
.../display/amdgpu_dm/tests/amdgpu_dm_crc_test.c | 5 +-
.../display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c | 59 ++++---
.../display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c | 74 ++++----
.../amdgpu_dm/tests/amdgpu_dm_freesync_test.c | 3 +-
.../display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c | 23 ++-
.../amdgpu_dm/tests/amdgpu_dm_helpers_test.c | 70 ++++----
.../display/amdgpu_dm/tests/amdgpu_dm_irq_test.c | 195 ++++++++++-----------
.../display/amdgpu_dm/tests/amdgpu_dm_ism_test.c | 31 ++--
.../amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c | 26 ++-
.../amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h | 1 +
.../amdgpu_dm/tests/amdgpu_dm_mst_types_test.c | 81 ++++-----
.../display/amdgpu_dm/tests/amdgpu_dm_plane_test.c | 73 ++++----
.../display/amdgpu_dm/tests/amdgpu_dm_psr_test.c | 21 +--
.../amd/display/amdgpu_dm/tests/amdgpu_dm_test.c | 53 +++---
.../display/amdgpu_dm/tests/amdgpu_dm_wb_test.c | 6 +-
drivers/gpu/drm/amd/display/dc/Makefile | 4 +
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 7 +
drivers/gpu/drm/amd/display/dc/core/dc_test.c | 135 ++++++++++++++
drivers/gpu/drm/amd/display/dc/inc/dc_test.h | 81 +++++++++
24 files changed, 689 insertions(+), 462 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
index 281dac959dca..6d8651047ff7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
@@ -18,6 +18,7 @@
#include <drm/drm_probe_helper.h>
#include "dc.h"
+#include "dc_test.h"
#include "dc/inc/core_types.h"
#include "dc/inc/hw/audio.h"
#include "amdgpu.h"
@@ -103,7 +104,7 @@ static void dm_test_audio_init_enabled_success(struct kunit *test)
int saved_audio = amdgpu_dm_audio_get_param();
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
res_pool = kunit_kzalloc(test, sizeof(*res_pool), GFP_KERNEL);
audio0 = kunit_kzalloc(test, sizeof(*audio0), GFP_KERNEL);
audio1 = kunit_kzalloc(test, sizeof(*audio1), GFP_KERNEL);
@@ -121,7 +122,7 @@ static void dm_test_audio_init_enabled_success(struct kunit *test)
res_pool->audio_count = 2;
res_pool->audios[0] = audio0;
res_pool->audios[1] = audio1;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
adev->dm.dc = dc;
adev->dev = dev;
@@ -810,16 +811,16 @@ static void dm_test_commit_audio_notifies_added_connector(struct kunit *test)
adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
- adev->dm.dc->current_state = kunit_kzalloc(test,
- sizeof(*adev->dm.dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
+ sizeof(*dc_get_current_state(adev->dm.dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(adev->dm.dc));
stream->ctx = kunit_kzalloc(test, sizeof(*stream->ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, stream->ctx);
stream->ctx->dc = adev->dm.dc;
- adev->dm.dc->current_state->stream_count = 1;
- adev->dm.dc->current_state->streams[0] = stream;
- adev->dm.dc->current_state->stream_status[0].audio_inst = 8;
+ dc_get_current_state(adev->dm.dc)->stream_count = 1;
+ dc_get_current_state(adev->dm.dc)->streams[0] = stream;
+ dc_get_current_state(adev->dm.dc)->stream_status[0].audio_inst = 8;
mutex_init(&adev->dm.audio_lock);
dm_test_audio_setup_notify_component(test, adev);
@@ -968,10 +969,10 @@ static void dm_test_commit_audio_skips_without_stream_status(struct kunit *test)
adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
- adev->dm.dc->current_state = kunit_kzalloc(test,
- sizeof(*adev->dm.dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
+ sizeof(*dc_get_current_state(adev->dm.dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(adev->dm.dc));
stream->ctx = kunit_kzalloc(test, sizeof(*stream->ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, stream->ctx);
stream->ctx->dc = adev->dm.dc;
@@ -1173,16 +1174,16 @@ static void dm_test_commit_audio_skips_writeback_addition(struct kunit *test)
adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
- adev->dm.dc->current_state = kunit_kzalloc(test,
- sizeof(*adev->dm.dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
+ sizeof(*dc_get_current_state(adev->dm.dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(adev->dm.dc));
stream->ctx = kunit_kzalloc(test, sizeof(*stream->ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, stream->ctx);
stream->ctx->dc = adev->dm.dc;
- adev->dm.dc->current_state->stream_count = 1;
- adev->dm.dc->current_state->streams[0] = stream;
- adev->dm.dc->current_state->stream_status[0].audio_inst = 14;
+ dc_get_current_state(adev->dm.dc)->stream_count = 1;
+ dc_get_current_state(adev->dm.dc)->streams[0] = stream;
+ dc_get_current_state(adev->dm.dc)->stream_status[0].audio_inst = 14;
mutex_init(&adev->dm.audio_lock);
dm_test_audio_setup_notify_component(test, adev);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
index a60c0fbf519d..377b92d84b98 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
@@ -14,6 +14,7 @@
#include <drm/drm_property.h>
#include "dc.h"
+#include "dc_test.h"
#include "dc_dmub_srv.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
@@ -72,8 +73,8 @@ static void dm_test_find_stream_with_link_returns_match(struct kunit *test)
struct dc_link *target_link = dm_kunit_alloc_link(test);
struct dc_stream_state *stream;
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, other_link);
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 1, target_link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, other_link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 1, target_link);
stream = dm_find_stream_with_link(dm, target_link);
KUNIT_ASSERT_NOT_NULL(test, stream);
@@ -90,7 +91,7 @@ static void dm_test_find_stream_with_link_missing(struct kunit *test)
struct dc_link *stream_link = dm_kunit_alloc_link(test);
struct dc_link *missing_link = dm_kunit_alloc_link(test);
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, stream_link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, stream_link);
KUNIT_EXPECT_NULL(test, dm_find_stream_with_link(dm, missing_link));
}
@@ -182,7 +183,7 @@ static void dm_test_backlight_set_level_aux_programs_power_module(struct kunit *
dm->backlight_caps[1].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
dm->backlight_caps[1].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
dm->backlight_link[1] = link;
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, link);
amdgpu_dm_backlight_set_level(dm, 1, 2000);
@@ -227,7 +228,7 @@ static void dm_test_backlight_set_level_pwm_programs_power_module(struct kunit *
dm->backlight_caps[1].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
memcpy(dm->backlight_caps[1].luminance_data, curve, sizeof(curve));
dm->backlight_link[1] = link;
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, link);
amdgpu_dm_set_dc_debug_mask(saved_mask & ~DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE);
for (i = 0; i < ARRAY_SIZE(cases); i++) {
@@ -266,23 +267,23 @@ static void dm_test_backlight_set_level_reallows_idle(struct kunit *test)
mutex_init(&dm->dc_lock);
dm->power_module = NULL;
- /* dm_kunit_alloc_dm() leaves dc->ctx NULL; the idle path dereferences it. */
+ /* dm_kunit_alloc_dm() leaves dc_get_ctx(dc) NULL; the idle path dereferences it. */
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dm->dc->ctx = ctx;
+ dc_test_set_ctx(dm->dc, ctx);
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- dm->dc->ctx->logger = logger;
+ dc_get_ctx(dm->dc)->logger = logger;
dmub_srv = kunit_kzalloc(test, sizeof(*dmub_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dmub_srv);
dmub_srv->idle_allowed = true;
- dm->dc->ctx->dmub_srv = dmub_srv;
- dm->dc->caps.ips_support = true;
+ dc_get_ctx(dm->dc)->dmub_srv = dmub_srv;
+ dc_test_caps(dm->dc)->ips_support = true;
/* Keep dc_allow_idle_optimizations() a safe early return. */
- dm->dc->debug.disable_idle_power_optimizations = true;
+ dc_test_debug_options(dm->dc)->disable_idle_power_optimizations = true;
dm->backlight_caps[1].caps_valid = true;
dm->backlight_caps[1].aux_support = true;
@@ -291,7 +292,7 @@ static void dm_test_backlight_set_level_reallows_idle(struct kunit *test)
dm->backlight_caps[1].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
dm->backlight_caps[1].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
dm->backlight_link[1] = link;
- dm_kunit_add_stream_to_state(test, dm->dc->current_state, 0, link);
+ dm_kunit_add_stream_to_state(test, dc_get_current_state(dm->dc), 0, link);
amdgpu_dm_backlight_set_level(dm, 1, 2000);
@@ -319,24 +320,25 @@ static void dm_test_backlight_update_status_no_stream(struct kunit *test)
KUNIT_EXPECT_EQ(test, dm->brightness[1], 3456U);
}
-static void setup_test_link_service(struct kunit *test, struct dc_link *link)
+static struct link_service *setup_test_link_service(struct kunit *test, struct dc_link *link)
{
struct link_service *link_srv;
struct dc_context *ctx;
struct dc *dc;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
KUNIT_ASSERT_NOT_NULL(test, ctx);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
+
+ return link_srv;
}
static int dm_test_get_backlight_level_mid(const struct dc_link *link)
@@ -382,9 +384,10 @@ static void dm_test_backlight_get_level_pwm_success(struct kunit *test)
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
u32 hw_level = dm_test_get_backlight_level_mid(link);
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_mid;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_mid;
dm->backlight_link[0] = link;
KUNIT_EXPECT_EQ(test, amdgpu_dm_backlight_get_level(dm, 0),
@@ -399,9 +402,10 @@ static void dm_test_backlight_get_level_pwm_error(struct kunit *test)
{
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
dm->brightness[0] = 4321;
dm->backlight_link[0] = link;
@@ -417,9 +421,10 @@ static void dm_test_backlight_get_level_aux_success(struct kunit *test)
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[0];
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level_nits = dm_test_get_backlight_level_nits;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level_nits = dm_test_get_backlight_level_nits;
dm->backlight_link[0] = link;
caps->caps_valid = true;
caps->aux_support = true;
@@ -439,9 +444,10 @@ static void dm_test_backlight_get_level_aux_error(struct kunit *test)
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[0];
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level_nits = dm_test_get_backlight_level_nits_fail;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level_nits = dm_test_get_backlight_level_nits_fail;
dm->brightness[0] = 6789;
dm->backlight_link[0] = link;
caps->caps_valid = true;
@@ -459,9 +465,10 @@ static void dm_test_backlight_get_brightness_uses_device_index(struct kunit *tes
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
struct dc_link *link = dm_kunit_alloc_link(test);
struct backlight_device *bd;
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
bd = kunit_kzalloc(test, sizeof(*bd), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, bd);
dev_set_drvdata(&bd->dev, dm);
@@ -506,9 +513,10 @@ static void dm_test_register_backlight_device_success(struct kunit *test)
struct dc_link *link = dm_kunit_alloc_link(test);
struct drm_minor *primary;
unsigned int max;
+ struct link_service *link_srv;
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_error;
primary = kunit_kzalloc(test, sizeof(*primary), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, primary);
adev->ddev.primary = primary;
@@ -555,10 +563,11 @@ static void dm_test_register_backlight_device_custom_curve_readback(struct kunit
struct backlight_device *bd;
struct drm_minor *primary;
int ret;
+ struct link_service *link_srv;
amdgpu_dm_set_dc_debug_mask(saved_mask & ~DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE);
- setup_test_link_service(test, link);
- link->dc->link_srv->edp_get_backlight_level = dm_test_get_backlight_level_mid;
+ link_srv = setup_test_link_service(test, link);
+ link_srv->edp_get_backlight_level = dm_test_get_backlight_level_mid;
primary = kunit_kzalloc(test, sizeof(*primary), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, primary);
adev->ddev.primary = primary;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
index 7ad8c56cbcf3..56a47809f302 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
@@ -13,6 +13,7 @@
#include <uapi/drm/drm_mode.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
@@ -1759,7 +1760,7 @@ dm_test_verify_lut3d_alloc_adev(struct kunit *test, bool has_3dlut)
adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
- adev->dm.dc->caps.color.dpp.hw_3d_lut = has_3dlut;
+ dc_test_caps(adev->dm.dc)->color.dpp.hw_3d_lut = has_3dlut;
return adev;
}
@@ -2201,7 +2202,7 @@ static void dm_test_update_plane_color_mgmt_bad_lut3d(struct kunit *test)
{
struct dm_test_color_update_fixture f = dm_test_color_update_setup(test);
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->lut3d = dm_test_make_lut_blob(test, 128);
KUNIT_EXPECT_EQ(test,
@@ -2385,7 +2386,7 @@ static void dm_test_update_plane_color_mgmt_legacy_luts(struct kunit *test)
struct drm_plane_state *plane_state = &f.dm_plane_state->base;
int ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->shaper_lut =
dm_test_make_lut_blob(test, MAX_COLOR_LUT_ENTRIES);
f.dm_plane_state->lut3d = dm_test_make_lut_blob(test, lut3d_entries);
@@ -2537,7 +2538,7 @@ static void dm_test_update_plane_color_mgmt_colorop_bypass_pipeline(struct kunit
};
struct dm_test_color_update_fixture f = dm_test_color_update_setup(test);
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass, ARRAY_SIZE(types));
@@ -2635,7 +2636,7 @@ static void dm_test_update_plane_color_mgmt_colorop_truncated(struct kunit *test
struct dm_crtc_state *crtc_state = f.crtc_state;
int count, ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
for (count = 3; count <= ARRAY_SIZE(types); count++) {
f.dm_plane_state->base.color_pipeline =
@@ -2681,11 +2682,11 @@ static void dm_test_update_plane_color_mgmt_colorop_no_3dlut_hw(struct kunit *te
};
struct dm_test_color_update_fixture f = dm_test_color_update_setup(test);
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass,
ARRAY_SIZE(types));
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = false;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = false;
KUNIT_EXPECT_EQ(test,
amdgpu_dm_update_plane_color_mgmt(f.crtc_state, &f.dm_plane_state->base,
@@ -2729,7 +2730,7 @@ static void dm_test_update_plane_color_mgmt_colorop_shaper(struct kunit *test)
struct drm_property_blob *blob;
int ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass,
ARRAY_SIZE(types));
@@ -2784,7 +2785,7 @@ static void dm_test_update_plane_color_mgmt_colorop_3dlut(struct kunit *test)
struct drm_property_blob *blob;
int ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass,
ARRAY_SIZE(types));
@@ -2839,7 +2840,7 @@ static void dm_test_update_plane_color_mgmt_colorop_3dlut_no_data(struct kunit *
struct drm_plane_state *plane_state = &f.dm_plane_state->base;
int ret;
- f.adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(f.adev->dm.dc)->color.dpp.hw_3d_lut = true;
f.dm_plane_state->base.color_pipeline =
dm_test_colorop_pipeline_setup(test, &f, types, curves, bypass,
ARRAY_SIZE(types));
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_colorop_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_colorop_test.c
index 27cd4b8500e8..de49c54e988e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_colorop_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_colorop_test.c
@@ -10,6 +10,7 @@
#include <drm/drm_kunit_helpers.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_dm_colorop.h"
#include "amdgpu_dm_kunit_test_helpers.h"
@@ -231,11 +232,10 @@ static void dm_test_initialize_default_pipeline_caps(struct kunit *test,
adev = dm_kunit_alloc_adev(test);
drm = &adev->ddev;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
- adev->dm.dc->caps.color.dpp.hw_3d_lut = dpp_hw_3d_lut;
- adev->dm.dc->caps.color.mpc.preblend = mpc_preblend;
+ dc_test_caps(adev->dm.dc)->color.dpp.hw_3d_lut = dpp_hw_3d_lut;
+ dc_test_caps(adev->dm.dc)->color.mpc.preblend = mpc_preblend;
plane = drm_kunit_helper_create_primary_plane(test, drm,
NULL, NULL, NULL, 0, NULL);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
index c0bbb95c4af4..204dc86266a3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
@@ -22,6 +22,7 @@
#include <linux/i2c.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_display.h"
@@ -3052,9 +3053,9 @@ static struct dm_test_fbc_ctx *dm_test_fbc_ctx_alloc(struct kunit *test)
/* Default to the fully-enabled path so each test only flips one knob */
ctx->link->connector_signal = SIGNAL_TYPE_EDP;
- ctx->dc->fbc_compressor =
- (struct compressor *)kunit_kzalloc(test, sizeof(void *), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, ctx->dc->fbc_compressor);
+ dc_test_set_fbc_compressor(ctx->dc,
+ (struct compressor *)kunit_kzalloc(test, sizeof(void *), GFP_KERNEL));
+ KUNIT_ASSERT_TRUE(test, dc_is_fbc_compressor_available(ctx->dc));
return ctx;
}
@@ -3067,7 +3068,7 @@ static void dm_test_fbc_init_no_compressor(struct kunit *test)
{
struct dm_test_fbc_ctx *ctx = dm_test_fbc_ctx_alloc(test);
- ctx->dc->fbc_compressor = NULL;
+ dc_test_set_fbc_compressor(ctx->dc, NULL);
amdgpu_dm_fbc_init(&ctx->aconnector->base);
@@ -5076,7 +5077,7 @@ static struct dm_test_poll_ctx *dm_test_poll_ctx_alloc(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link_srv = kunit_kzalloc(test, sizeof(*ctx->link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link_srv);
- ctx->dc->link_srv = ctx->link_srv;
+ dc_test_install_link_service(ctx->dc, ctx->link_srv);
ctx->dc_ctx = kunit_kzalloc(test, sizeof(*ctx->dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc_ctx);
@@ -5676,7 +5677,7 @@ static void dm_test_atomic_check_mst_scaffold(struct kunit *test,
/* Fake DC link so dm_mst_get_pbn_divider() yields a non-zero divider. */
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -5685,7 +5686,7 @@ static void dm_test_atomic_check_mst_scaffold(struct kunit *test,
dm_test_atomic_check_dp_get_verified_link_cap;
link_srv->dp_link_bandwidth_kbps =
dm_test_atomic_check_dp_link_bandwidth_kbps;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
s->mst_root->dc_link = link;
@@ -6016,7 +6017,7 @@ static enum dc_status dm_test_vs_validate_mode_timing_ok(
static void dm_test_validate_stream_dc_ok_no_pipe(struct kunit *test)
{
struct drm_device *drm = dm_test_alloc_drm(test);
- struct dc *dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ struct dc *dc = dm_kunit_alloc_dc(test);
struct dc_context *ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
struct dal_logger *logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
struct resource_pool *pool = kunit_kzalloc(test, sizeof(*pool), GFP_KERNEL);
@@ -6057,9 +6058,9 @@ static void dm_test_validate_stream_dc_ok_no_pipe(struct kunit *test)
link_srv->validate_mode_timing = dm_test_vs_validate_mode_timing_ok;
- dc->ctx = ctx;
- dc->res_pool = pool;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_set_res_pool(dc, pool);
+ dc_test_install_link_service(dc, link_srv);
link->ep_type = DISPLAY_ENDPOINT_UNKNOWN;
stream->link = link;
@@ -6472,7 +6473,7 @@ static struct dm_test_i2c_ctx *dm_test_i2c_setup(struct kunit *test)
ctx->dc_ctx->dc = ctx->dc;
ctx->link->link_index = 0;
ctx->link->ddc = link_ddc;
- ctx->dc->links[0] = ctx->link;
+ dc_test_set_link(ctx->dc, 0, ctx->link);
ctx->i2c->ddc_service = ctx->ddc;
i2c_set_adapdata(&ctx->i2c->base, ctx->i2c);
@@ -6517,7 +6518,7 @@ static void dm_test_i2c_xfer_oem_no_device(struct kunit *test)
pool = kunit_kzalloc(test, sizeof(*pool), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, pool);
- ctx->dc->res_pool = pool;
+ dc_test_set_res_pool(ctx->dc, pool);
ctx->i2c->oem = true;
KUNIT_EXPECT_EQ(test, amdgpu_dm_i2c_xfer(&ctx->i2c->base, msgs, 1), -EIO);
@@ -7383,9 +7384,9 @@ static struct dm_test_cvs_dc *dm_test_cvs_dc_alloc(struct kunit *test)
c->dc = kunit_kzalloc(test, sizeof(*c->dc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, c->dc);
- c->dc->ctx = dcc;
- c->dc->res_pool = pool;
- c->dc->link_srv = c->link_srv;
+ dc_test_set_ctx(c->dc, dcc);
+ dc_test_set_res_pool(c->dc, pool);
+ dc_test_install_link_service(c->dc, c->link_srv);
c->adev->dm.dc = c->dc;
c->dm_state = kunit_kzalloc(test, sizeof(*c->dm_state), GFP_KERNEL);
@@ -8310,12 +8311,11 @@ static void dm_test_ces_setup(struct kunit *test, struct dm_test_edid_ctx *ctx,
i2c->base.lock_ops = &dm_test_force_edid_lock_ops;
ctx->aconnector->i2c = i2c;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link_srv->add_remote_sink = dm_test_ces_add_remote_sink;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
ctx->link->dc = dc;
ctx->link->aux_mode = false;
@@ -8484,7 +8484,7 @@ dm_test_gm_ctx_alloc(struct kunit *test, int connector_type)
KUNIT_ASSERT_NOT_NULL(test, ctx->link);
ctx->link_srv->dp_get_encoding_format = dm_test_gm_enc_8b10b;
- ctx->dc->link_srv = ctx->link_srv;
+ dc_test_install_link_service(ctx->dc, ctx->link_srv);
ctx->adev->dm.dc = ctx->dc;
ctx->link->dc = ctx->dc;
ctx->aconnector->dc_link = ctx->link;
@@ -9079,7 +9079,7 @@ static struct dm_test_frl_ctx *dm_test_frl_ctx_alloc(struct kunit *test)
ctx->link_srv->hdmi_frl_poll_status_flag = dm_test_frl_poll_true;
ctx->link_srv->detect_link = dm_test_frl_detect;
- ctx->dc->link_srv = ctx->link_srv;
+ dc_test_install_link_service(ctx->dc, ctx->link_srv);
ctx->dm->dc = ctx->dc;
mutex_init(&ctx->dm->dc_lock);
INIT_DELAYED_WORK(&ctx->dm->hdmi_frl_status_polling_work, hdmi_frl_status_polling_work);
@@ -9099,7 +9099,7 @@ static struct dc_link *dm_test_frl_add_link(struct kunit *test, struct dm_test_f
KUNIT_ASSERT_NOT_NULL(test, link);
link->dc = ctx->dc;
- ctx->dc->links[0] = link;
+ dc_test_set_link(ctx->dc, 0, link);
return link;
}
@@ -9760,10 +9760,9 @@ dm_test_fs_caps_ctx_alloc(struct kunit *test, enum signal_type sink_signal)
ctx->pool = kunit_kzalloc(test, sizeof(*ctx->pool), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->pool);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
- dc->ctx = dc_ctx;
- dc->res_pool = ctx->pool;
+ dc = dm_kunit_alloc_dc(test);
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_res_pool(dc, ctx->pool);
ctx->adev->dm.dc = dc;
ctx->adev->dm.freesync_module =
@@ -10036,10 +10035,9 @@ dm_test_conn_init_ctx_alloc(struct kunit *test, enum signal_type signal)
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link_srv->dp_get_encoding_format = dm_test_gm_enc_8b10b;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
- dc->ctx = dc_ctx;
- dc->link_srv = link_srv;
+ dc = dm_kunit_alloc_dc(test);
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->link = kunit_kzalloc(test, sizeof(*ctx->link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link);
@@ -10054,8 +10052,8 @@ dm_test_conn_init_ctx_alloc(struct kunit *test, enum signal_type signal)
ddc->link = ctx->link;
ctx->link->ddc = ddc;
- dc->links[0] = ctx->link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, ctx->link);
+ dc_test_set_link_count(dc, 1);
ctx->dm->dc = dc;
/* amdgpu_dm_connector_destroy() and amdgpu_dm_encoder_destroy() kfree() these. */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
index 7f6340702502..8d3123904548 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
@@ -16,6 +16,7 @@
#include <drm/drm_vblank.h>
#include "dc.h"
+#include "dc_test.h"
#include "core_types.h"
#include "logger_types.h"
#include "opp.h"
@@ -137,8 +138,8 @@ static struct dm_test_crc_dc_fixture *dm_test_alloc_crc_dc_fixture(struct kunit
mutex_init(&adev->dm.dc_lock);
adev->dm.dc = fixture->dc;
- fixture->dc->ctx = fixture->dc_ctx;
- fixture->dc->current_state = fixture->dc_state;
+ dc_test_set_ctx(fixture->dc, fixture->dc_ctx);
+ dc_test_set_current_state(fixture->dc, fixture->dc_state);
fixture->dc_ctx->dc = fixture->dc;
fixture->dc_ctx->logger = fixture->logger;
fixture->link->dc = fixture->dc;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
index c130d809098c..96cf015a12d9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
@@ -13,6 +13,7 @@
#include <linux/debugfs.h>
#include "dc.h"
+#include "dc_test.h"
#include "inc/core_types.h"
#include "irq/irq_service.h"
#include "inc/hw/timing_generator.h"
@@ -532,7 +533,7 @@ static void dm_test_crtc_set_vupdate_irq_enable(struct kunit *test)
irqs->info = info;
res_pool->irqs = irqs;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
adev->dm.dc = dc;
acrtc->base.dev = &adev->ddev;
@@ -619,7 +620,7 @@ static void dm_test_idle_worker_enabled_breaks_when_idle_disallowed(struct kunit
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* First loop iteration breaks before any dc_allow_idle_optimizations(). */
- adev->dm.dc->idle_optimizations_allowed = false;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, false);
idle_work = kunit_kzalloc(test, sizeof(*idle_work), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, idle_work);
@@ -658,12 +659,12 @@ static void dm_test_idle_worker_enabled_breaks_when_not_headless(struct kunit *t
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* Allow idle so the first branch is skipped and dc_allow() is exercised. */
- adev->dm.dc->idle_optimizations_allowed = true;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, true);
/* is_apu path avoids DC_LOG_DC()'s NULL-logger dereference. */
- adev->dm.dc->caps.is_apu = true;
+ dc_test_caps(adev->dm.dc)->is_apu = true;
/* Empty stream list -> amdgpu_dm_psr_is_active_allowed() returns false. */
- adev->dm.dc->current_state = dm_kunit_alloc_dc_state(test);
- KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, dm_kunit_alloc_dc_state(test));
+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc_get_current_state(adev->dm.dc));
/* A connected display makes amdgpu_dm_is_headless() false. */
display = kunit_kzalloc(test, sizeof(*display), GFP_KERNEL);
@@ -684,7 +685,7 @@ static void dm_test_idle_worker_enabled_breaks_when_not_headless(struct kunit *t
/*
* Report success only when disabling idle. dc_allow_idle_optimizations() then
- * clears dc->idle_optimizations_allowed on the disable call but leaves it clear
+ * clears dc_is_idle_optimizations_allowed(dc) on the disable call but leaves it clear
* on the re-enable call inside the worker's enable-body, so the next loop
* iteration breaks at the first branch instead of looping forever.
*/
@@ -721,18 +722,18 @@ static void dm_test_idle_worker_enabled_runs_body(struct kunit *test)
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* Allow idle so the first branch is skipped and dc_allow() is exercised. */
- adev->dm.dc->idle_optimizations_allowed = true;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, true);
/* is_apu path avoids DC_LOG_DC()'s NULL-logger dereference. */
- adev->dm.dc->caps.is_apu = true;
+ dc_test_caps(adev->dm.dc)->is_apu = true;
/* dc_allow() logs via DC_LOG_DEBUG() when it flips the flag. */
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- adev->dm.dc->ctx->logger = logger;
+ dc_get_ctx(adev->dm.dc)->logger = logger;
/* dc_allow() only flips the flag when clk_mgr and apply() are present. */
- adev->dm.dc->clk_mgr = dm_kunit_alloc_clk_mgr(test);
- KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc->clk_mgr);
- adev->dm.dc->hwss.apply_idle_power_optimizations = dm_test_idle_apply_flip;
+ dc_test_set_clk_mgr(adev->dm.dc, dm_kunit_alloc_clk_mgr(test));
+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc_get_clk_mgr(adev->dm.dc));
+ dc_test_hwss(adev->dm.dc)->apply_idle_power_optimizations = dm_test_idle_apply_flip;
idle_work = kunit_kzalloc(test, sizeof(*idle_work), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, idle_work);
@@ -743,7 +744,7 @@ static void dm_test_idle_worker_enabled_runs_body(struct kunit *test)
amdgpu_dm_idle_worker(&idle_work->work);
/* Enable-body ran, then the next iteration disabled idle and stopped. */
- KUNIT_EXPECT_FALSE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_FALSE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
KUNIT_EXPECT_FALSE(test, idle_work->running);
}
@@ -963,7 +964,7 @@ dm_test_crtc_setup_enable(struct kunit *test, struct amdgpu_device **adev_out,
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
- adev->dm.dc->ctx->dce_version = dce_version;
+ dc_get_ctx(adev->dm.dc)->dce_version = dce_version;
/* crtc_id 0 maps to a valid IRQ type only when a CRTC is registered. */
adev->mode_info.num_crtc = 1;
@@ -1066,7 +1067,7 @@ static void dm_test_crtc_enable_vblank_vupdate_busy(struct kunit *test)
irqs->info = info;
res_pool->irqs = irqs;
- adev->dm.dc->res_pool = res_pool;
+ dc_test_set_res_pool(adev->dm.dc, res_pool);
KUNIT_EXPECT_EQ(test,
amdgpu_dm_crtc_enable_vblank(&acrtc->base), -EBUSY);
@@ -1193,8 +1194,8 @@ static void dm_test_crtc_enable_vblank_ips_restore(struct kunit *test)
acrtc->base.funcs = &dm_test_crtc_funcs;
/* IPS enabled and not fully disabled -> first restore condition holds. */
- adev->dm.dc->caps.ips_support = true;
- adev->dm.dc->config.disable_ips = DMUB_IPS_ENABLE;
+ dc_test_caps(adev->dm.dc)->ips_support = true;
+ dc_test_config(adev->dm.dc)->disable_ips = DMUB_IPS_ENABLE;
/* Supported PSR version makes self-refresh supported. */
link = acrtc_state->stream->link;
@@ -1240,8 +1241,8 @@ static void dm_test_crtc_enable_vblank_ips_restore_replay(struct kunit *test)
acrtc->base.funcs = &dm_test_crtc_funcs;
/* IPS enabled and not fully disabled -> first restore condition holds. */
- adev->dm.dc->caps.ips_support = true;
- adev->dm.dc->config.disable_ips = DMUB_IPS_ENABLE;
+ dc_test_caps(adev->dm.dc)->ips_support = true;
+ dc_test_config(adev->dm.dc)->disable_ips = DMUB_IPS_ENABLE;
/*
* PSR unsupported but replay supported -> sr_supported is driven by the
@@ -2002,7 +2003,7 @@ static void dm_test_crtc_disable_vblank_no_irq_installed(struct kunit *test)
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* DCE_VERSION_6_0 has no VRR, so the vupdate-irq branch is skipped. */
- adev->dm.dc->ctx->dce_version = DCE_VERSION_6_0;
+ dc_get_ctx(adev->dm.dc)->dce_version = DCE_VERSION_6_0;
adev->dm.active_vblank_irq_count = 0;
/* No CRTCs registered and IRQs not installed -> irq_put returns early. */
@@ -2039,7 +2040,7 @@ static void dm_test_crtc_disable_vblank_vrr(struct kunit *test)
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* DCE_VERSION_8_0 supports VRR -> the vupdate-irq branch is walked. */
- adev->dm.dc->ctx->dce_version = DCE_VERSION_8_0;
+ dc_get_ctx(adev->dm.dc)->dce_version = DCE_VERSION_8_0;
adev->mode_info.num_crtc = 1;
adev->irq.installed = true;
@@ -2089,7 +2090,7 @@ static void dm_test_crtc_disable_vblank_queues_work(struct kunit *test)
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev->dm.dc);
/* DCE_VERSION_6_0 has no VRR, so the vupdate-irq branch is skipped. */
- adev->dm.dc->ctx->dce_version = DCE_VERSION_6_0;
+ dc_get_ctx(adev->dm.dc)->dce_version = DCE_VERSION_6_0;
adev->dm.active_vblank_irq_count = 2;
adev->mode_info.num_crtc = 1;
@@ -2187,7 +2188,7 @@ static void dm_test_crtc_init_registers_crtc(struct kunit *test)
dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc);
- dc->caps.max_cursor_size = 256;
+ dc_test_caps(dc)->max_cursor_size = 256;
adev->dm.adev = adev;
adev->dm.ddev = &adev->ddev;
@@ -2249,8 +2250,8 @@ static void dm_test_crtc_init_enables_degamma(struct kunit *test)
dc = dm_kunit_alloc_dc_with_ctx(test);
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc);
/* DCN DPP with a non-4.01 ASIC selects the degamma-enabled path. */
- dc->caps.color.dpp.dcn_arch = 1;
- dc->ctx->dce_version = DCN_VERSION_3_0;
+ dc_test_caps(dc)->color.dpp.dcn_arch = 1;
+ dc_get_ctx(dc)->dce_version = DCN_VERSION_3_0;
adev->dm.adev = adev;
adev->dm.ddev = &adev->ddev;
@@ -2520,12 +2521,12 @@ static void dm_test_crtc_atomic_check_valid_stream_passes(struct kunit *test)
tg_funcs->validate_timing = dm_test_atomic_check_validate_timing_ok;
tg->funcs = tg_funcs;
res_pool->timing_generators[0] = tg;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link_srv->validate_mode_timing = dm_test_atomic_check_validate_mode_timing_ok;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
adev->dm.dc = dc;
link = dm_kunit_alloc_link(test);
@@ -2588,7 +2589,7 @@ static void dm_test_crtc_atomic_check_invalid_stream_fails(struct kunit *test)
tg_funcs->validate_timing = dm_test_atomic_check_validate_timing_fail;
tg->funcs = tg_funcs;
res_pool->timing_generators[0] = tg;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
adev->dm.dc = dc;
link = dm_kunit_alloc_link(test);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
index 2e273dea17ef..449fb6d94f75 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
@@ -9,6 +9,8 @@
#include <linux/firmware.h>
#include "dc.h"
+#include "dc_test.h"
+#include "amdgpu_dm_kunit_test_helpers.h"
#include "dc/inc/core_types.h"
#include "dc/inc/hw/dmcu.h"
#include "dc/inc/hw/abm.h"
@@ -524,8 +526,7 @@ static struct amdgpu_device *dm_test_alloc_adev_with_dc(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
res_pool = kunit_kzalloc(test, sizeof(*res_pool), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, res_pool);
@@ -533,8 +534,8 @@ static struct amdgpu_device *dm_test_alloc_adev_with_dc(struct kunit *test)
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc->res_pool = res_pool;
- dc->ctx = ctx;
+ dc_test_set_res_pool(dc, res_pool);
+ dc_test_set_ctx(dc, ctx);
ctx->dc = dc;
ctx->driver_context = adev;
adev->dm.dc = dc;
@@ -647,7 +648,7 @@ static void dm_test_dmub_hw_init_success_fake_dmub(struct kunit *test)
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, adev->dm.dmub_srv->hw_init);
- KUNIT_EXPECT_NOT_NULL(test, adev->dm.dc->ctx->dmub_srv);
+ KUNIT_EXPECT_NOT_NULL(test, dc_get_ctx(adev->dm.dc)->dmub_srv);
}
/**
@@ -664,7 +665,7 @@ static void dm_test_dmub_hw_init_no_hw_support(struct kunit *test)
adev->dm.dmub_srv->hw_funcs.is_supported = dm_test_dmub_unsupported;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
- KUNIT_EXPECT_NULL(test, adev->dm.dc->ctx->dmub_srv);
+ KUNIT_EXPECT_NULL(test, dc_get_ctx(adev->dm.dc)->dmub_srv);
}
/**
@@ -717,7 +718,7 @@ static void dm_test_dmub_hw_init_auto_load_timeout(struct kunit *test)
adev->dm.dmub_srv->hw_funcs.get_fw_status = dm_test_dmub_fw_not_ready;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
- KUNIT_EXPECT_NOT_NULL(test, adev->dm.dc->ctx->dmub_srv);
+ KUNIT_EXPECT_NOT_NULL(test, dc_get_ctx(adev->dm.dc)->dmub_srv);
}
/**
@@ -733,8 +734,8 @@ static void dm_test_dmub_hw_init_apu_dpia_dcn35(struct kunit *test)
struct amdgpu_device *adev = dm_test_alloc_adev_with_dmub(test);
adev->ip_versions[DCE_HWIP][0] = IP_VERSION(3, 5, 0);
- adev->dm.dc->caps.is_apu = true;
- adev->dm.dc->res_pool->usb4_dpia_count = 1;
+ dc_test_caps(adev->dm.dc)->is_apu = true;
+ dc_get_res_pool(adev->dm.dc)->usb4_dpia_count = 1;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, adev->dm.dmub_srv->hw_init);
@@ -755,7 +756,7 @@ static void dm_test_dmub_hw_init_sanity_checks_dcn31(struct kunit *test)
adev->dm.dmcub_fw_version = DMUB_FW_VERSION(4, 0, 10);
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->debug.sanity_checks);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(adev->dm.dc)->sanity_checks);
}
/**
@@ -773,7 +774,7 @@ static void dm_test_dmub_hw_init_sanity_checks_dcn314(struct kunit *test)
adev->dm.dmcub_fw_version = DMUB_FW_VERSION(4, 0, 10);
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->debug.sanity_checks);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(adev->dm.dc)->sanity_checks);
}
/**
@@ -798,8 +799,8 @@ static void dm_test_dmub_hw_init_dmcu_abm(struct kunit *test)
dmcu->funcs = &dm_test_dmcu_funcs;
dmcu->psp_version = 0x12345678;
- adev->dm.dc->res_pool->dmcu = dmcu;
- adev->dm.dc->res_pool->abm = abm;
+ dc_get_res_pool(adev->dm.dc)->dmcu = dmcu;
+ dc_get_res_pool(adev->dm.dc)->abm = abm;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, abm->dmcu_is_running);
@@ -857,7 +858,7 @@ static void dm_test_dmub_hw_resume_full_init(struct kunit *test)
dm_dmub_hw_resume(adev);
- KUNIT_EXPECT_NOT_NULL(test, adev->dm.dc->ctx->dmub_srv);
+ KUNIT_EXPECT_NOT_NULL(test, dc_get_ctx(adev->dm.dc)->dmub_srv);
}
/**
@@ -999,7 +1000,7 @@ static void dm_test_execute_dmub_cmd_null_dmub_srv(struct kunit *test)
* dm_test_process_dmub_aux_transfer_sync_engine_acquire - Test AUX transfer engine-acquire failure
* @test: The KUnit test context
*
- * With dc->link_count == 0, dc_process_dmub_aux_transfer_async() rejects the
+ * With dc_get_link_count(dc) == 0, dc_process_dmub_aux_transfer_async() rejects the
* link index and amdgpu_dm_process_dmub_aux_transfer_sync() reports an
* engine-acquire error and returns -1.
*/
@@ -1019,8 +1020,7 @@ static void dm_test_process_dmub_aux_transfer_sync_engine_acquire(struct kunit *
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
payload = kunit_kzalloc(test, sizeof(*payload), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, payload);
@@ -1028,7 +1028,7 @@ static void dm_test_process_dmub_aux_transfer_sync_engine_acquire(struct kunit *
notify = kunit_kzalloc(test, sizeof(*notify), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, notify);
- dc->link_count = 0;
+ dc_test_set_link_count(dc, 0);
ctx->dc = dc;
ctx->driver_context = adev;
adev->dm.dmub_notify = notify;
@@ -1071,8 +1071,7 @@ static void dm_test_process_dmub_aux_transfer_sync_protocol_error(struct kunit *
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -1087,9 +1086,9 @@ static void dm_test_process_dmub_aux_transfer_sync_protocol_error(struct kunit *
KUNIT_ASSERT_NOT_NULL(test, notify);
link->ddc = ddc;
- dc->ctx = dc_ctx;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
dc_ctx->dc = dc;
dc_ctx->driver_context = adev;
dc_ctx->dmub_srv = NULL;
@@ -1139,8 +1138,7 @@ static void dm_test_process_dmub_aux_transfer_sync_copies_data(struct kunit *tes
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -1155,9 +1153,9 @@ static void dm_test_process_dmub_aux_transfer_sync_copies_data(struct kunit *tes
KUNIT_ASSERT_NOT_NULL(test, notify);
link->ddc = ddc;
- dc->ctx = dc_ctx;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
dc_ctx->dc = dc;
dc_ctx->driver_context = adev;
dc_ctx->dmub_srv = NULL;
@@ -1220,8 +1218,7 @@ static void dm_test_process_dmub_aux_transfer_sync_zero_length(struct kunit *tes
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -1236,9 +1233,9 @@ static void dm_test_process_dmub_aux_transfer_sync_zero_length(struct kunit *tes
KUNIT_ASSERT_NOT_NULL(test, notify);
link->ddc = ddc;
- dc->ctx = dc_ctx;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
dc_ctx->dc = dc;
dc_ctx->driver_context = adev;
dc_ctx->dmub_srv = NULL;
@@ -1294,8 +1291,7 @@ static void dm_test_process_dmub_set_config_sync_unknown_error(struct kunit *tes
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -1306,9 +1302,9 @@ static void dm_test_process_dmub_set_config_sync_unknown_error(struct kunit *tes
notify = kunit_kzalloc(test, sizeof(*notify), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, notify);
- dc->ctx = dc_ctx;
+ dc_test_set_ctx(dc, dc_ctx);
dc_ctx->dmub_srv = NULL;
- dc->links[0] = link;
+ dc_test_set_link(dc, 0, link);
ctx->dc = dc;
ctx->driver_context = adev;
adev->dm.dmub_notify = notify;
@@ -1534,8 +1530,8 @@ static void dm_test_dmub_reg_write_then_read(struct kunit *test)
perf_trace = kunit_kzalloc(test, sizeof(*perf_trace), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, perf_trace);
- adev->dm.dc->ctx->cgs_device = &dm_test_cgs.dev;
- adev->dm.dc->ctx->perf_trace = perf_trace;
+ dc_get_ctx(adev->dm.dc)->cgs_device = &dm_test_cgs.dev;
+ dc_get_ctx(adev->dm.dc)->perf_trace = perf_trace;
amdgpu_dm_dmub_reg_write(adev, 0x1234, 0x0BADF00D);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
index 710cdc7f40bf..a3b9ee396e5c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
@@ -13,6 +13,7 @@
#include <drm/drm_vblank.h>
#include "dc.h"
+#include "dc_test.h"
#include "inc/core_types.h"
#include "amd_shared.h"
#include "amdgpu.h"
@@ -594,7 +595,7 @@ static void dm_test_update_freesync_state_pre_ai_active(struct kunit *test)
stream->timing.v_total = 1125;
adev->dm.adev = adev;
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- adev->dm.dc->current_state = dm_kunit_alloc_dc_state(test);
+ dc_test_set_current_state(adev->dm.dc, dm_kunit_alloc_dc_state(test));
amdgpu_dm_update_freesync_state_on_stream(&adev->dm, &crtc_state, stream, surface, 0);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c
index 5af6ae47bb21..b53aba4153f8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_hdcp_test.c
@@ -11,6 +11,7 @@
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/i2c.h>
+#include "dc_test.h"
#include <drm/display/drm_dp_helper.h>
@@ -1161,7 +1162,7 @@ static void dm_test_hdcp_update_display_disable_resets_status_and_cancels_valida
* dm_test_hdcp_create_workqueue_zero_max_links_returns_null - zero-link creation fails early
* @test: KUnit test context
*
- * When dc->caps.max_links is zero, hdcp_create_workqueue() should fail
+ * When dc_test_caps(dc)->max_links is zero, hdcp_create_workqueue() should fail
* the initial allocation path and return NULL.
*/
static void dm_test_hdcp_create_workqueue_zero_max_links_returns_null(struct kunit *test)
@@ -1170,10 +1171,9 @@ static void dm_test_hdcp_create_workqueue_zero_max_links_returns_null(struct kun
struct dc *dc;
struct hdcp_workqueue *work;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
- dc->caps.max_links = 0;
+ dc_test_caps(dc)->max_links = 0;
work = hdcp_create_workqueue(NULL, &cp_psp, dc);
@@ -1200,9 +1200,9 @@ static void dm_test_hdcp_create_workqueue_initializes_work(struct kunit *test)
/* sysfs_create_bin_file() needs a real device kobject. */
adev->dev = adev->ddev.dev;
- dc->caps.max_links = 1;
+ dc_test_caps(dc)->max_links = 1;
/* DCE_VERSION_UNKNOWN (0) is not in the DTM v3 list. */
- dc->ctx->dce_version = DCE_VERSION_UNKNOWN;
+ dc_get_ctx(dc)->dce_version = DCE_VERSION_UNKNOWN;
work = hdcp_create_workqueue(adev, &cp_psp, dc);
@@ -1236,8 +1236,8 @@ static void dm_test_hdcp_create_workqueue_sets_dtm_v3_for_dcn31(struct kunit *te
struct hdcp_workqueue *work;
adev->dev = adev->ddev.dev;
- dc->caps.max_links = 1;
- dc->ctx->dce_version = DCN_VERSION_3_1;
+ dc_test_caps(dc)->max_links = 1;
+ dc_get_ctx(dc)->dce_version = DCN_VERSION_3_1;
work = hdcp_create_workqueue(adev, &cp_psp, dc);
@@ -1264,8 +1264,8 @@ static void dm_test_hdcp_create_workqueue_initializes_all_links(struct kunit *te
int i;
adev->dev = adev->ddev.dev;
- dc->caps.max_links = 3;
- dc->ctx->dce_version = DCN_VERSION_3_1;
+ dc_test_caps(dc)->max_links = 3;
+ dc_get_ctx(dc)->dce_version = DCN_VERSION_3_1;
work = hdcp_create_workqueue(adev, &cp_psp, dc);
@@ -2089,8 +2089,7 @@ static struct amdgpu_dm_connector *alloc_test_connector(struct kunit *test,
KUNIT_ASSERT_NOT_NULL(test, aconnector);
dc_link = kunit_kzalloc(test, sizeof(*dc_link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_link);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
kref_init(&aconnector->base.base.refcount);
aconnector->base.index = index;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
index 6e564f60b0df..48e30f1936b5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
@@ -13,6 +13,7 @@
#include <drm/display/drm_dp_mst_helper.h>
#include "dc.h"
+#include "dc_test.h"
#include "core_types.h"
#include "clk_mgr.h"
#include "link_service.h"
@@ -193,15 +194,16 @@ static void dm_test_apply_edid_quirks_psr_phy_power_down(struct kunit *test)
struct edid *embedded = dm_test_edid_with_panel_id(test,
drm_edid_encode_panel_id('S', 'D', 'C', 0x4203));
- link->ctx = dc->ctx;
+ link->ctx = dc_get_ctx(dc);
link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
apply_edid_quirks(link, external, &edid_caps);
- KUNIT_EXPECT_FALSE(test, dc->debug.psr_phy_force_phy_power_down_up_level_2);
+ KUNIT_EXPECT_FALSE(
+ test, dc_test_debug_options(dc)->psr_phy_force_phy_power_down_up_level_2);
link->connector_signal = SIGNAL_TYPE_EDP;
apply_edid_quirks(link, embedded, &edid_caps);
- KUNIT_EXPECT_TRUE(test, dc->debug.psr_phy_force_phy_power_down_up_level_2);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(dc)->psr_phy_force_phy_power_down_up_level_2);
}
/**
@@ -430,11 +432,10 @@ static void dm_test_parse_edid_caps_hdmi_frl(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dc_edid);
edid_caps = kunit_kzalloc(test, sizeof(*edid_caps), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, edid_caps);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link->dc = dc;
- dc->config.enable_frl = true;
+ dc_test_config(dc)->enable_frl = true;
dm_test_fill_base_edid(dc_edid, true);
@@ -473,11 +474,10 @@ static void dm_test_parse_edid_caps_hdmi_frl_dsc(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dc_edid);
edid_caps = kunit_kzalloc(test, sizeof(*edid_caps), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, edid_caps);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link->dc = dc;
- dc->config.enable_frl = true;
+ dc_test_config(dc)->enable_frl = true;
dm_test_fill_base_edid(dc_edid, true);
@@ -512,7 +512,7 @@ static void dm_test_parse_edid_caps_hdmi_comp_auto(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, edid_caps);
link->dc = dc;
- link->ctx = dc->ctx;
+ link->ctx = dc_get_ctx(dc);
dm_test_fill_base_edid(dc_edid, true);
@@ -521,8 +521,8 @@ static void dm_test_parse_edid_caps_hdmi_comp_auto(struct kunit *test)
KUNIT_EXPECT_EQ(test, dm_helpers_parse_edid_caps(link, dc_edid, edid_caps), EDID_OK);
KUNIT_EXPECT_TRUE(test, edid_caps->panel_patch.hdmi_comp_auto);
- KUNIT_EXPECT_TRUE(test, dc->debug.force_frl_max);
- KUNIT_EXPECT_TRUE(test, dc->debug.force_frl_dsc);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(dc)->force_frl_max);
+ KUNIT_EXPECT_TRUE(test, dc_test_debug_options(dc)->force_frl_dsc);
}
/*
@@ -2143,13 +2143,12 @@ static void dm_test_override_panel_settings_debug_mask_disables_dsc(struct kunit
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link = dm_kunit_alloc_link(test);
ctx->dc = dc;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
link_srv->dp_should_enable_fec = dm_test_dp_should_enable_fec;
link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
@@ -2176,21 +2175,20 @@ static void dm_test_override_panel_settings_second_edp_disables_psr(struct kunit
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
first_link = dm_kunit_alloc_link(test);
second_link = dm_kunit_alloc_link(test);
ctx->dc = dc;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link_srv->dp_should_enable_fec = dm_test_dp_should_enable_fec;
first_link->dc = dc;
second_link->dc = dc;
- dc->link_count = 2;
- dc->links[0] = first_link;
- dc->links[1] = second_link;
+ dc_test_set_link_count(dc, 2);
+ dc_test_set_link(dc, 0, first_link);
+ dc_test_set_link(dc, 1, second_link);
first_link->connector_signal = SIGNAL_TYPE_EDP;
second_link->connector_signal = SIGNAL_TYPE_EDP;
@@ -2538,7 +2536,7 @@ static void dm_test_dmub_aux_transfer_sync_hpd_discon(struct kunit *test)
* @test: The KUnit test context
*
* With HPD connected the helper forwards the payload to
- * amdgpu_dm_process_dmub_aux_transfer_sync(). dc->link_count is zero, so the
+ * amdgpu_dm_process_dmub_aux_transfer_sync(). dc_get_link_count(dc) is zero, so the
* async transfer is rejected and the engine-acquire error is reported.
*/
static void dm_test_dmub_aux_transfer_sync_hpd_connected(struct kunit *test)
@@ -4117,15 +4115,14 @@ static void dm_test_dp_handle_test_pattern_no_pipe(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, state);
link = dm_kunit_alloc_link(test);
aconnector = dm_kunit_alloc_connector(test, adev, link);
ctx->dc = dc;
- dc->current_state = state;
+ dc_test_set_current_state(dc, state);
link->dc = dc;
link->priv = aconnector;
@@ -4267,14 +4264,13 @@ static void dm_test_dmub_set_config_sync_unknown_error(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, ctx);
dc_ctx = kunit_kzalloc(test, sizeof(*dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
notify = kunit_kzalloc(test, sizeof(*notify), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, notify);
link = dm_kunit_alloc_link(test);
- dc->ctx = dc_ctx;
- dc->links[0] = link;
+ dc_test_set_ctx(dc, dc_ctx);
+ dc_test_set_link(dc, 0, link);
ctx->dc = dc;
ctx->driver_context = adev;
adev->dm.dmub_notify = notify;
@@ -4309,8 +4305,7 @@ static void dm_test_is_dp_sink_present_queries_link_service(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_NOT_NULL(test, adev);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link = dm_kunit_alloc_link(test);
@@ -4321,7 +4316,7 @@ static void dm_test_is_dp_sink_present_queries_link_service(struct kunit *test)
drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
link_srv->dp_is_sink_present = dm_test_dp_sink_present_true;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
link->priv = aconnector;
@@ -4588,8 +4583,7 @@ static struct dm_test_pattern_fixture dm_test_setup_pattern(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, adev);
fixture.ctx = kunit_kzalloc(test, sizeof(*fixture.ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, fixture.ctx);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, state);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -4607,9 +4601,9 @@ static struct dm_test_pattern_fixture dm_test_setup_pattern(struct kunit *test)
clk_mgr->funcs = &dm_test_clk_mgr_funcs;
clk_mgr->bw_params = bw_params;
- dc->link_srv = link_srv;
- dc->clk_mgr = clk_mgr;
- dc->current_state = state;
+ dc_test_install_link_service(dc, link_srv);
+ dc_test_set_clk_mgr(dc, clk_mgr);
+ dc_test_set_current_state(dc, state);
fixture.ctx->dc = dc;
fixture.link->dc = dc;
fixture.link->priv = fixture.aconnector;
@@ -4794,7 +4788,7 @@ static void dm_test_read_local_edid_i2c_no_response(struct kunit *test)
fixture.link->aux_mode = false;
fixture.link->ddc_hw_inst = 1;
fixture.aconnector->i2c = (struct amdgpu_i2c_adapter *)ddc;
- fixture.dc->hwss.prepare_ddc = dm_test_prepare_ddc;
+ dc_test_hwss(fixture.dc)->prepare_ddc = dm_test_prepare_ddc;
dm_test_prepare_ddc_calls = 0;
KUNIT_EXPECT_EQ(test,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
index 8c112bda46c8..b64d63fe15fd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
@@ -15,6 +15,7 @@
#include <drm/display/drm_dp_helper.h>
#include "dc.h"
+#include "dc_test.h"
#include "inc/core_types.h"
#include "inc/hw/timing_generator.h"
#include "irq/irq_service.h"
@@ -444,7 +445,7 @@ static struct dc *dm_test_alloc_dc_with_irq_service(struct kunit *test,
irqs->funcs = funcs;
irqs->info = info;
res_pool->irqs = irqs;
- dc->res_pool = res_pool;
+ dc_test_set_res_pool(dc, res_pool);
return dc;
}
@@ -1532,9 +1533,8 @@ static void dm_test_hpd_rx_irq_create_workqueue(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
- dc->caps.max_links = 4;
+ dc = dm_kunit_alloc_dc(test);
+ dc_test_caps(dc)->max_links = 4;
adev->dm.dc = dc;
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
@@ -1542,10 +1542,10 @@ static void dm_test_hpd_rx_irq_create_workqueue(struct kunit *test)
ctx->wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev);
KUNIT_ASSERT_NOT_NULL(test, ctx->wq);
- ctx->count = dc->caps.max_links;
+ ctx->count = dc_test_caps(dc)->max_links;
KUNIT_ASSERT_EQ(test, kunit_add_action_or_reset(test, dm_test_destroy_hpd_rx_wq, ctx), 0);
- for (i = 0; i < dc->caps.max_links; i++)
+ for (i = 0; i < dc_test_caps(dc)->max_links; i++)
KUNIT_EXPECT_TRUE(test, ctx->wq[i].wq != NULL);
}
@@ -1578,9 +1578,8 @@ static void dm_test_hpd_rx_irq_work_suspend_flushes(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
- dc->caps.max_links = 2;
+ dc = dm_kunit_alloc_dc(test);
+ dc_test_caps(dc)->max_links = 2;
adev->dm.dc = dc;
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
@@ -1588,7 +1587,7 @@ static void dm_test_hpd_rx_irq_work_suspend_flushes(struct kunit *test)
ctx->wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev);
KUNIT_ASSERT_NOT_NULL(test, ctx->wq);
- ctx->count = dc->caps.max_links;
+ ctx->count = dc_test_caps(dc)->max_links;
KUNIT_ASSERT_EQ(test, kunit_add_action_or_reset(test, dm_test_destroy_hpd_rx_wq, ctx), 0);
adev->dm.hpd_rx_offload_wq = ctx->wq;
@@ -1756,12 +1755,12 @@ static void dm_test_set_crtc_irq_state_allows_idle(struct kunit *test)
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- dc->ctx->logger = logger;
+ dc_get_ctx(dc)->logger = logger;
- dc->caps.ips_support = true;
- dc->idle_optimizations_allowed = true;
+ dc_test_caps(dc)->ips_support = true;
+ dc_test_set_idle_optimizations_allowed(dc, true);
/* Keep dc_allow_idle_optimizations() a safe early return. */
- dc->debug.disable_idle_power_optimizations = true;
+ dc_test_debug_options(dc)->disable_idle_power_optimizations = true;
adev->dm.dc = dc;
acrtc->otg_inst = 0;
@@ -2052,8 +2051,8 @@ static void dm_test_hpd_init_empty_connectors(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, link);
link->irq_source_hpd = DC_IRQ_SOURCE_HPD1;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX;
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
amdgpu_dm_hpd_init(adev);
}
@@ -2118,8 +2117,8 @@ static void dm_test_hpd_init_fini_with_connectors(struct kunit *test)
link->irq_source_hpd = DC_IRQ_SOURCE_HPD1;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX;
aconn->dc_link = link;
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
/* The irq service stubs accept the HW writes without register access. */
amdgpu_dm_hpd_init(adev);
@@ -2159,8 +2158,8 @@ static void dm_test_hpd_init_fini_analog_connector(struct kunit *test)
/* An analog connector id makes the loop request polling. */
link->link_id.id = CONNECTOR_ID_VGA;
aconn->dc_link = link;
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
/* use_polling becomes true, so init must enable KMS polling. */
amdgpu_dm_hpd_init(adev);
@@ -2210,8 +2209,8 @@ static void dm_test_hpd_init_fini_irq_ref(struct kunit *test)
link->irq_source_hpd = DC_IRQ_SOURCE_HPD1;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
aconn->dc_link = link;
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
amdgpu_dm_hpd_init(adev);
amdgpu_dm_hpd_fini(adev);
@@ -2310,8 +2309,7 @@ dm_test_setup_hpd_rx_offload_work(struct kunit *test,
mutex_init(&aconn->hpd_lock);
offload_wq->aconnector = aconn;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -2320,8 +2318,8 @@ dm_test_setup_hpd_rx_offload_work(struct kunit *test,
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->detect_connection_type = dm_test_detect_connection_single;
- dc->link_srv = link_srv;
- dc->ctx = ctx;
+ dc_test_install_link_service(dc, link_srv);
+ dc_test_set_ctx(dc, ctx);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -2542,8 +2540,7 @@ static struct amdgpu_dm_connector *dm_test_setup_hdmi_debounce(struct kunit *tes
INIT_DELAYED_WORK(&aconn->hdmi_hpd_debounce_work,
amdgpu_dm_hdmi_hpd_debounce_work);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -2552,8 +2549,8 @@ static struct amdgpu_dm_connector *dm_test_setup_hdmi_debounce(struct kunit *tes
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->detect_link = dm_test_detect_link_false;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -2607,13 +2604,13 @@ static void dm_test_hdmi_hpd_debounce_reallow_idle(struct kunit *test)
/* DC_LOG_* dereferences ctx->logger->dev, so wire a real drm device. */
logger->dev = aconn->base.dev;
- dc->ctx->logger = logger;
+ dc_get_ctx(dc)->logger = logger;
/* Make reallow_idle true and keep dc_allow_idle*() a safe early return. */
dmub_srv->idle_allowed = true;
- dc->ctx->dmub_srv = dmub_srv;
- dc->caps.ips_support = true;
- dc->debug.disable_idle_power_optimizations = true;
+ dc_get_ctx(dc)->dmub_srv = dmub_srv;
+ dc_test_caps(dc)->ips_support = true;
+ dc_test_debug_options(dc)->disable_idle_power_optimizations = true;
/* A cached previous sink must be released and cleared. */
aconn->hdmi_prev_sink = dm_test_sink_create(aconn->dc_link);
@@ -2707,14 +2704,13 @@ static void dm_test_handle_hpd_irq_disabled(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, state);
aconn->base.state = &state->base;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
- dc->ctx = ctx;
+ dc_test_set_ctx(dc, ctx);
ctx->dc = dc;
link->ctx = ctx;
aconn->dc_link = link;
@@ -2756,8 +2752,7 @@ static struct amdgpu_dm_connector *dm_test_setup_hpd_irq_helper(struct kunit *te
KUNIT_ASSERT_NOT_NULL(test, state);
aconn->base.state = &state->base;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -2766,8 +2761,8 @@ static struct amdgpu_dm_connector *dm_test_setup_hpd_irq_helper(struct kunit *te
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->detect_connection_type = dm_test_detect_connection_none;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -3017,8 +3012,7 @@ static void dm_test_handle_hpd_rx_irq_disabled(struct kunit *test)
aconn = dm_kunit_alloc_connector(test, adev, NULL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -3027,8 +3021,8 @@ static void dm_test_handle_hpd_rx_irq_disabled(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->dp_handle_hpd_rx_irq = dm_test_handle_hpd_rx_no_work;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -3101,8 +3095,7 @@ static struct amdgpu_dm_connector *dm_test_setup_hpd_rx_irq(struct kunit *test,
mutex_init(&aconn->hpd_lock);
aconn->mst_mgr.mst_state = true;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -3110,8 +3103,8 @@ static struct amdgpu_dm_connector *dm_test_setup_hpd_rx_irq(struct kunit *test,
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -3332,8 +3325,7 @@ static void dm_test_dmub_hpd_callback_invalid_index(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
notify.link_index = 1;
@@ -3351,11 +3343,10 @@ static void dm_test_dmub_hpd_callback_empty_connectors(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
adev->dm.ddev = &adev->ddev;
- dc->link_count = 1;
+ dc_test_set_link_count(dc, 1);
notify.type = DMUB_NOTIFICATION_HPD_SENSE_NOTIFY;
dmub_hpd_callback(adev, ¬ify);
@@ -3376,11 +3367,10 @@ static void dm_test_dmub_hpd_callback_suspend_skip(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
adev->in_suspend = true;
- dc->link_count = 1;
+ dc_test_set_link_count(dc, 1);
notify.type = DMUB_NOTIFICATION_HPD;
/* adev->dm.ddev is left NULL: reaching the connector walk would crash. */
@@ -3408,15 +3398,14 @@ static void dm_test_dmub_hpd_callback_unknown_type_match(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
adev->dm.ddev = &adev->ddev;
- dc->link_count = 1;
+ dc_test_set_link_count(dc, 1);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
- dc->links[0] = link;
+ dc_test_set_link(dc, 0, link);
/* A writeback connector must be skipped by the loop. */
wbconn = kunit_kzalloc(test, sizeof(*wbconn), GFP_KERNEL);
@@ -3463,8 +3452,7 @@ static void dm_test_dmub_hpd_callback_hpd_type(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
mutex_init(&adev->dm.dc_lock);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -3474,16 +3462,16 @@ static void dm_test_dmub_hpd_callback_hpd_type(struct kunit *test)
link_srv->detect_connection_type = dm_test_detect_connection_none;
link_srv->detect_link = dm_test_detect_link_false;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
adev->dm.dc = dc;
adev->dm.ddev = &adev->ddev;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
aconn = kunit_kzalloc(test, sizeof(*aconn), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, aconn);
@@ -3532,8 +3520,7 @@ static void dm_test_dmub_hpd_callback_hpd_irq_type(struct kunit *test)
spin_lock_init(&offload_wq->offload_lock);
adev->dm.hpd_rx_offload_wq = offload_wq;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
@@ -3542,8 +3529,8 @@ static void dm_test_dmub_hpd_callback_hpd_irq_type(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, link);
link_srv->dp_handle_hpd_rx_irq = dm_test_handle_hpd_rx_no_work;
- dc->ctx = ctx;
- dc->link_srv = link_srv;
+ dc_test_set_ctx(dc, ctx);
+ dc_test_install_link_service(dc, link_srv);
ctx->dc = dc;
link->dc = dc;
link->ctx = ctx;
@@ -3552,8 +3539,8 @@ static void dm_test_dmub_hpd_callback_hpd_irq_type(struct kunit *test)
adev->dm.dc = dc;
adev->dm.ddev = &adev->ddev;
- dc->link_count = 1;
- dc->links[0] = link;
+ dc_test_set_link_count(dc, 1);
+ dc_test_set_link(dc, 0, link);
aconn = kunit_kzalloc(test, sizeof(*aconn), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, aconn);
@@ -3584,8 +3571,7 @@ static void dm_test_register_hpd_handlers_empty(struct kunit *test)
struct dc *dc;
adev = dm_kunit_alloc_adev(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
KUNIT_EXPECT_EQ(test, amdgpu_dm_register_hpd_handlers(adev), 0);
@@ -3609,8 +3595,7 @@ static void dm_test_register_hpd_handlers_valid(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
wbconn = kunit_kzalloc(test, sizeof(*wbconn), GFP_KERNEL);
@@ -3656,8 +3641,7 @@ static void dm_test_register_hpd_handlers_invalid_hpd(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
aconn = kunit_kzalloc(test, sizeof(*aconn), GFP_KERNEL);
@@ -3691,8 +3675,7 @@ static void dm_test_register_hpd_handlers_invalid_hpd_rx(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
adev->dm.dc = dc;
aconn = kunit_kzalloc(test, sizeof(*aconn), GFP_KERNEL);
@@ -3732,8 +3715,8 @@ static void dm_test_register_hpd_handlers_dmub_outbox(struct kunit *test)
adev->dm.dc = dc;
/* Make dc_is_dmub_outbox_supported() return true. */
- dc->caps.dmcub_support = true;
- dc->ctx->asic_id.chip_family = AMDGPU_FAMILY_GC_11_0_1;
+ dc_test_caps(dc)->dmcub_support = true;
+ dc_get_ctx(dc)->asic_id.chip_family = AMDGPU_FAMILY_GC_11_0_1;
KUNIT_EXPECT_EQ(test, amdgpu_dm_register_hpd_handlers(adev), 0);
KUNIT_EXPECT_PTR_EQ(test, adev->dm.dmub_callback[DMUB_NOTIFICATION_HPD],
@@ -3843,18 +3826,18 @@ static struct amdgpu_crtc *dm_test_setup_vrr_pflip_crtc(struct kunit *test,
KUNIT_ASSERT_EQ(test, drm_vblank_init(&adev->ddev, 1), 0);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = kunit_kzalloc(test, sizeof(*dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, kunit_kzalloc(test, sizeof(*dc_get_current_state(dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
adev->dm.dc = dc;
link = dm_kunit_alloc_link(test);
stream = dm_kunit_alloc_stream(test, link);
- stream->ctx = dc->ctx;
+ stream->ctx = dc_get_ctx(dc);
if (tg) {
- dc->current_state->res_ctx.pipe_ctx[0].stream = stream;
- dc->current_state->res_ctx.pipe_ctx[0].stream_res.tg = tg;
+ dc_get_current_state(dc)->res_ctx.pipe_ctx[0].stream = stream;
+ dc_get_current_state(dc)->res_ctx.pipe_ctx[0].stream_res.tg = tg;
}
acrtc = dm_test_add_crtc(test, adev);
@@ -4056,9 +4039,9 @@ static struct amdgpu_crtc *dm_test_setup_vmin_vmax_crtc(struct kunit *test,
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = kunit_kzalloc(test, sizeof(*dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, kunit_kzalloc(test, sizeof(*dc_get_current_state(dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
adev->dm.dc = dc;
link = dm_kunit_alloc_link(test);
@@ -4205,7 +4188,7 @@ static void dm_test_crtc_high_irq_writeback_disables(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, drm_vblank_init(&adev->ddev, 1), 0);
- /* dc_stream_fc_disable_writeback() dereferences dc->res_pool. */
+ /* dc_stream_fc_disable_writeback() dereferences dc_get_res_pool(dc). */
dc = dm_test_alloc_dc_with_irq_service(test,
&dm_test_irq_service_funcs_dcn10);
adev->dm.dc = dc;
@@ -4384,7 +4367,7 @@ static void dm_test_dmub_outbox1_low_irq_empty(struct kunit *test)
dmub->hw_funcs.get_outbox0_wptr = dm_test_dmub_get_outbox0_wptr;
dc_dmub_srv->dmub = dmub;
- dc->ctx->dmub_srv = dc_dmub_srv;
+ dc_get_ctx(dc)->dmub_srv = dc_dmub_srv;
adev->dm.dc = dc;
params.adev = adev;
params.irq_src = DC_IRQ_SOURCE_DMCUB_OUTBOX;
@@ -4422,7 +4405,7 @@ static void dm_test_dmub_outbox1_low_irq_drains_trace(struct kunit *test)
dmub->outbox0_rb.capacity = DM_TEST_OUTBOX0_RB_SIZE;
dmub->hw_funcs.get_outbox0_wptr = dm_test_dmub_get_outbox0_wptr_full;
dc_dmub_srv->dmub = dmub;
- dc->ctx->dmub_srv = dc_dmub_srv;
+ dc_get_ctx(dc)->dmub_srv = dc_dmub_srv;
adev->dm.dc = dc;
params.adev = adev;
params.irq_src = DC_IRQ_SOURCE_DMCUB_OUTBOX;
@@ -4460,11 +4443,11 @@ static struct amdgpu_device *dm_test_alloc_adev_outbox_notify(struct kunit *test
dmub->hw_funcs.get_outbox0_wptr = dm_test_dmub_get_outbox0_wptr;
dmub->hw_funcs.get_outbox1_wptr = dm_test_dmub_get_outbox1_wptr;
dc_dmub_srv->dmub = dmub;
- dc->ctx->dmub_srv = dc_dmub_srv;
+ dc_get_ctx(dc)->dmub_srv = dc_dmub_srv;
/* Make dc_enable_dmub_notifications() return true. */
- dc->caps.dmcub_support = true;
- dc->ctx->asic_id.chip_family = AMDGPU_FAMILY_GC_11_0_1;
+ dc_test_caps(dc)->dmcub_support = true;
+ dc_get_ctx(dc)->asic_id.chip_family = AMDGPU_FAMILY_GC_11_0_1;
adev->dm.dc = dc;
@@ -4578,8 +4561,8 @@ static struct amdgpu_device *dm_test_setup_irq_regs(struct kunit *test,
KUNIT_ASSERT_EQ(test, kunit_add_action_or_reset(test, dm_test_free_irq_sources,
adev), 0);
dc = dm_test_alloc_dc_with_irq_service(test, funcs);
- dc->ctx->dce_version = DCE_VERSION_11_0;
- dc->caps.max_otg_num = 1;
+ dc_get_ctx(dc)->dce_version = DCE_VERSION_11_0;
+ dc_test_caps(dc)->max_otg_num = 1;
adev->dm.dc = dc;
adev->mode_info.num_crtc = 1;
adev->mode_info.num_hpd = 1;
@@ -4663,7 +4646,7 @@ static void dm_test_dce110_register_irq_handlers_crtc_add_id_fails(struct kunit
adev = dm_kunit_alloc_adev(test);
dc = dm_test_alloc_dc_with_irq_service(test, &dm_test_irq_service_funcs_dce110);
- dc->ctx->dce_version = DCE_VERSION_11_0;
+ dc_get_ctx(dc)->dce_version = DCE_VERSION_11_0;
adev->dm.dc = dc;
adev->mode_info.num_crtc = 1;
@@ -4917,7 +4900,7 @@ static void dm_test_register_outbox_irq_handlers_add_id_fails(struct kunit *test
* dm_test_register_outbox_irq_handlers_with_dmub - Test outbox registration with DMUB
* @test: The KUnit test context
*
- * Exercises the dc->ctx->dmub_srv branch which maps the outbox source and
+ * Exercises the dc_get_ctx(dc)->dmub_srv branch which maps the outbox source and
* registers dm_dmub_outbox1_low_irq in the low IRQ context table.
*/
static void dm_test_register_outbox_irq_handlers_with_dmub(struct kunit *test)
@@ -4933,7 +4916,7 @@ static void dm_test_register_outbox_irq_handlers_with_dmub(struct kunit *test)
dc = dm_test_alloc_dc_with_irq_service(test, &dm_test_irq_service_funcs_dcn10);
dc_dmub_srv = kunit_kzalloc(test, sizeof(*dc_dmub_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc_dmub_srv);
- dc->ctx->dmub_srv = dc_dmub_srv;
+ dc_get_ctx(dc)->dmub_srv = dc_dmub_srv;
adev->dm.dc = dc;
amdgpu_dm_set_irq_funcs(adev);
KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0);
@@ -5086,9 +5069,9 @@ static void dm_test_handle_vmin_vmax_update(struct kunit *test)
mutex_init(&adev->dm.dc_lock);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = kunit_kzalloc(test, sizeof(*dc->current_state),
- GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, kunit_kzalloc(test, sizeof(*dc_get_current_state(dc)),
+ GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
adev->dm.dc = dc;
stream = kunit_kzalloc(test, sizeof(*stream), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
index a9c6485e2a9e..5864147faf1c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_ism_test.c
@@ -8,6 +8,7 @@
#include <kunit/test.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
@@ -1191,9 +1192,9 @@ static void dm_test_ism_dispatch_optimized_idle_defers_sso(struct kunit *test)
* ===== Behavioural tests for dm_ism_commit_idle_optimization_state =====
*
* The commit path runs the real DC calls. dc_allow_idle_optimizations() only
- * reaches hardware through dc->hwss.apply_idle_power_optimizations(), so the
+ * reaches hardware through dc_test_hwss(dc)->apply_idle_power_optimizations(), so the
* spy is installed there — DC's own seam — and the outcome is read back from
- * dc->idle_optimizations_allowed. The callback fires only on an actual
+ * dc_is_idle_optimizations_allowed(dc). The callback fires only on an actual
* transition, so the call count is the number of idle state changes requested.
*/
@@ -1236,12 +1237,12 @@ static struct dc_stream_state *setup_commit_test(struct kunit *test,
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- dc->ctx->logger = logger;
+ dc_get_ctx(dc)->logger = logger;
/* is_apu path avoids DC_LOG_DC()'s NULL-logger dereference. */
- dc->caps.is_apu = true;
+ dc_test_caps(dc)->is_apu = true;
/* dc_allow() only calls apply() when clk_mgr is present. */
- dc->clk_mgr = dm_kunit_alloc_clk_mgr(test);
- dc->hwss.apply_idle_power_optimizations = dm_ism_test_apply_idle;
+ dc_test_set_clk_mgr(dc, dm_kunit_alloc_clk_mgr(test));
+ dc_test_hwss(dc)->apply_idle_power_optimizations = dm_ism_test_apply_idle;
dm_ism_test_idle = (typeof(dm_ism_test_idle)){ };
amdgpu_dm_ism_init(&acrtc->ism, config);
@@ -1281,7 +1282,7 @@ static void dm_test_ism_commit_allows_idle_on_optimized_idle(struct kunit *test)
/* vblank disabled + no SSO -> a single allow-idle transition. */
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 1);
KUNIT_EXPECT_TRUE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_TRUE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
cancel_delayed_work(&acrtc->ism.sso_delayed_work);
}
@@ -1308,7 +1309,7 @@ static void dm_test_ism_commit_enables_sso_on_optimized_idle_sso(struct kunit *t
};
setup_commit_test(test, acrtc, &config);
- adev->dm.dc->idle_optimizations_allowed = true;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, true);
scoped_guard(mutex, &adev->dm.dc_lock) {
amdgpu_dm_ism_commit_event(&acrtc->ism,
@@ -1320,7 +1321,7 @@ static void dm_test_ism_commit_enables_sso_on_optimized_idle_sso(struct kunit *t
/* SSO engagement disallows idle, then re-allows it. */
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 2);
KUNIT_EXPECT_TRUE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_TRUE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
}
amdgpu_dm_ism_flush(&acrtc->ism);
@@ -1351,7 +1352,7 @@ static void dm_test_ism_commit_disallows_idle_on_timer_aborted(struct kunit *tes
stream = setup_commit_test(test, acrtc, &config);
setup_idle_delay_history(&acrtc->ism, stream);
- adev->dm.dc->idle_optimizations_allowed = true;
+ dc_test_set_idle_optimizations_allowed(adev->dm.dc, true);
scoped_guard(mutex, &adev->dm.dc_lock) {
/* Non-zero delay parks the FSM in HYSTERESIS_WAITING. */
@@ -1369,7 +1370,7 @@ static void dm_test_ism_commit_disallows_idle_on_timer_aborted(struct kunit *tes
/* TIMER_ABORTED commit runs with vblank_enabled=true. */
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 1);
KUNIT_EXPECT_FALSE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_FALSE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_FALSE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
}
amdgpu_dm_ism_flush(&acrtc->ism);
@@ -1409,7 +1410,7 @@ static void dm_test_ism_exit_from_optimized_idle_disallows_idle(struct kunit *te
/* Allow on entry, disallow on exit. */
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 2);
KUNIT_EXPECT_FALSE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_FALSE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_FALSE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
/* The idle period was recorded on the way out. */
KUNIT_EXPECT_EQ(test, acrtc->ism.next_record_idx, 1);
}
@@ -1449,7 +1450,7 @@ static void dm_test_ism_exit_from_sso_disallows_idle(struct kunit *test)
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 2);
KUNIT_EXPECT_FALSE(test, dm_ism_test_idle.last_allow);
- KUNIT_EXPECT_FALSE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_FALSE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
KUNIT_EXPECT_EQ(test, acrtc->ism.next_record_idx, 1);
}
@@ -1495,7 +1496,7 @@ static void dm_test_ism_delayed_work_runs_timer_elapsed(struct kunit *test)
KUNIT_EXPECT_EQ(test, (int)acrtc->ism.current_state,
(int)DM_ISM_STATE_OPTIMIZED_IDLE_SSO);
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 1);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_TRUE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
amdgpu_dm_ism_flush(&acrtc->ism);
}
@@ -1533,7 +1534,7 @@ static void dm_test_ism_sso_delayed_work_runs_sso_elapsed(struct kunit *test)
KUNIT_EXPECT_EQ(test, (int)acrtc->ism.current_state,
(int)DM_ISM_STATE_OPTIMIZED_IDLE_SSO);
KUNIT_EXPECT_EQ(test, dm_ism_test_idle.calls, 3);
- KUNIT_EXPECT_TRUE(test, adev->dm.dc->idle_optimizations_allowed);
+ KUNIT_EXPECT_TRUE(test, dc_is_idle_optimizations_allowed(adev->dm.dc));
amdgpu_dm_ism_flush(&acrtc->ism);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
index f844b644bb77..9954cbab6541 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
@@ -11,6 +11,7 @@
#include <drm/drm_managed.h>
#include "dc.h"
+#include "dc_test.h"
#include "core_types.h"
#include "clk_mgr.h"
#include "amdgpu.h"
@@ -47,18 +48,29 @@ struct dc_link *dm_kunit_alloc_link(struct kunit *test)
}
EXPORT_SYMBOL(dm_kunit_alloc_link);
+struct dc *dm_kunit_alloc_dc(struct kunit *test)
+{
+ struct dc *dc;
+
+ dc = dc_test_create();
+ KUNIT_ASSERT_NOT_NULL(test, dc);
+ kunit_add_action(test, (kunit_action_t *)dc_test_destroy, dc);
+
+ return dc;
+}
+EXPORT_SYMBOL(dm_kunit_alloc_dc);
+
struct dc *dm_kunit_alloc_dc_with_ctx(struct kunit *test)
{
struct dc_context *ctx;
struct dc *dc;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx);
- dc->ctx = ctx;
+ dc_test_set_ctx(dc, ctx);
ctx->dc = dc;
return dc;
@@ -72,7 +84,7 @@ struct dc_link *dm_kunit_alloc_link_with_ctx(struct kunit *test)
link = dm_kunit_alloc_link(test);
dc = dm_kunit_alloc_dc_with_ctx(test);
- link->ctx = dc->ctx;
+ link->ctx = dc_get_ctx(dc);
return link;
}
@@ -87,14 +99,12 @@ struct amdgpu_display_manager *dm_kunit_alloc_dm(struct kunit *test)
dm = kunit_kzalloc(test, sizeof(*dm), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
-
+ dc = dm_kunit_alloc_dc(test);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, state);
dm->dc = dc;
- dc->current_state = state;
+ dc_test_set_current_state(dc, state);
return dm;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
index 7d7bcd321775..b4bbf4a3750d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
@@ -21,6 +21,7 @@ struct dc_stream_state;
struct drm_device;
struct amdgpu_device *dm_kunit_alloc_adev(struct kunit *test);
+struct dc *dm_kunit_alloc_dc(struct kunit *test);
struct dc *dm_kunit_alloc_dc_with_ctx(struct kunit *test);
struct dc_link *dm_kunit_alloc_link(struct kunit *test);
struct dc_link *dm_kunit_alloc_link_with_ctx(struct kunit *test);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
index e624eb55cae1..b8ea85846872 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
@@ -23,6 +23,7 @@
#include <drm/display/drm_dp_mst_helper.h>
#include "dc.h"
+#include "dc_test.h"
#include "dpcd_defs.h"
#include "dmub_cmd.h"
#include "amdgpu.h"
@@ -83,7 +84,7 @@ static void dm_mst_test_setup_dm_aux(struct amdgpu_dm_dp_aux *dm_aux,
dm_mst_test_aux_transfer_raw_reply = 0;
dm_mst_test_aux_transfer_raw_operation_result = AUX_RET_SUCCESS;
link_srv->aux_transfer_raw = dm_mst_test_aux_transfer_raw;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
ctx->driver_context = adev;
ddc->link = link;
@@ -137,7 +138,7 @@ static struct amdgpu_dm_connector *dm_mst_test_alloc_sideband_connector(struct k
aconnector = kunit_kzalloc(test, sizeof(*aconnector), GFP_KERNEL);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, aconnector);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
KUNIT_ASSERT_NOT_NULL(test, link);
@@ -145,7 +146,7 @@ static struct amdgpu_dm_connector *dm_mst_test_alloc_sideband_connector(struct k
mutex_init(&aconnector->handle_mst_msg_ready);
link_srv->get_status = dm_mst_test_get_status;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
link->dpcd_caps.dpcd_rev.raw = DPCD_REV_14;
link->link_status.dpcd_caps = &link->dpcd_caps;
@@ -341,14 +342,14 @@ static void dm_mst_test_pbn_divider_uses_link_bandwidth(struct kunit *test)
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
KUNIT_ASSERT_NOT_NULL(test, link);
KUNIT_ASSERT_NOT_NULL(test, dc);
link_srv->dp_get_verified_link_cap = dm_mst_test_dp_get_verified_link_cap;
link_srv->dp_link_bandwidth_kbps = dm_mst_test_dp_link_bandwidth_kbps;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
KUNIT_EXPECT_EQ(test, dm_mst_get_pbn_divider(link),
@@ -624,7 +625,7 @@ static void dm_mst_test_aux_transfer_native_read(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -675,7 +676,7 @@ static void dm_mst_test_aux_transfer_native_write(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -727,7 +728,7 @@ static void dm_mst_test_aux_transfer_partial_write(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -771,7 +772,7 @@ static void dm_mst_test_aux_transfer_error_result(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -816,7 +817,7 @@ static void dm_mst_test_aux_transfer_hpd_discon_quirk(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -870,7 +871,7 @@ static void dm_mst_test_aux_transfer_non_ack_reply(struct kunit *test)
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dm_aux);
@@ -1196,14 +1197,14 @@ static void dm_mst_test_initialize_dp_connector_mst(struct kunit *test)
ddc = kunit_kzalloc(test, sizeof(*ddc), GFP_KERNEL);
link = dm_kunit_alloc_link(test);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ddc);
KUNIT_ASSERT_NOT_NULL(test, dc);
KUNIT_ASSERT_NOT_NULL(test, link_srv);
link_srv->dp_get_max_link_enc_cap = dm_mst_test_dp_get_max_link_enc_cap;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
link->dc = dc;
link->ddc = ddc;
@@ -1656,7 +1657,7 @@ static void dm_mst_test_init_child(struct kunit *test, struct dm_mst_test_child
ret = drmm_mode_config_init(&adev->ddev);
KUNIT_ASSERT_EQ(test, ret, 0);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL);
child->port = kunit_kzalloc(test, sizeof(*child->port), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1665,7 +1666,7 @@ static void dm_mst_test_init_child(struct kunit *test, struct dm_mst_test_child
link_srv->add_remote_sink = dm_mst_test_add_remote_sink;
link_srv->remove_remote_sink = dm_mst_test_remove_remote_sink;
- dc->link_srv = link_srv;
+ dc_test_install_link_service(dc, link_srv);
child->adev = adev;
child->link = dm_kunit_alloc_link(test);
@@ -2519,7 +2520,7 @@ static void dm_mst_test_init_dsc_ctx(struct kunit *test, struct dm_mst_test_dsc_
dc = dm_kunit_alloc_dc_with_ctx(test);
ctx->link = dm_kunit_alloc_link(test);
- ctx->link->ctx = dc->ctx;
+ ctx->link->ctx = dc_get_ctx(dc);
ctx->port = dm_mst_test_alloc_mgr_port(test);
ctx->port->parent = branch;
@@ -2680,14 +2681,14 @@ static void dm_mst_test_init_port_mode_ctx(struct kunit *test,
link_srv->dp_link_bandwidth_kbps = dm_mst_test_root_bandwidth_kbps;
ctx->dc = dm_kunit_alloc_dc_with_ctx(test);
- ctx->dc->link_srv = link_srv;
- ctx->dc->res_pool = res_pool;
+ dc_test_install_link_service(ctx->dc, link_srv);
+ dc_test_set_res_pool(ctx->dc, res_pool);
ctx->link = dm_kunit_alloc_link(test);
ctx->link->dc = ctx->dc;
- ctx->link->ctx = ctx->dc->ctx;
+ ctx->link->ctx = dc_get_ctx(ctx->dc);
- ctx->sink->ctx = ctx->dc->ctx;
+ ctx->sink->ctx = dc_get_ctx(ctx->dc);
ctx->port = dm_mst_test_alloc_mgr_port(test);
ctx->port->full_pbn = full_pbn;
@@ -2789,8 +2790,8 @@ static void dm_mst_test_setup_dsc_caps(struct kunit *test, struct dc *dc, struct
KUNIT_ASSERT_NOT_NULL(test, dsc);
dsc->funcs = &dm_mst_test_dsc_funcs;
- dsc->ctx = dc->ctx;
- dc->res_pool->dscs[0] = dsc;
+ dsc->ctx = dc_get_ctx(dc);
+ dc_get_res_pool(dc)->dscs[0] = dsc;
dec->is_dsc_supported = true;
dec->dsc_version = 0x21;
@@ -3026,8 +3027,8 @@ static struct amdgpu_dm_connector *dm_mst_test_alloc_frl_connector(struct kunit
link_srv->bw_kbps_from_raw_frl_link_rate_data = dm_mst_test_bw_kbps_from_raw_frl;
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->link_srv = link_srv;
- dc->caps.dp_hdmi21_pcon_support = pcon_support;
+ dc_test_install_link_service(dc, link_srv);
+ dc_test_caps(dc)->dp_hdmi21_pcon_support = pcon_support;
link = dm_kunit_alloc_link(test);
link->dc = dc;
@@ -3314,7 +3315,7 @@ static void dm_mst_test_init_recompute_ctx(struct kunit *test,
ctx->adev->ddev.mode_config.num_crtc = 1;
ctx->dc = dm_kunit_alloc_dc_with_ctx(test);
- ctx->dc->current_state = dm_kunit_alloc_dc_state(test);
+ dc_test_set_current_state(ctx->dc, dm_kunit_alloc_dc_state(test));
ctx->dc_state = dm_kunit_alloc_dc_state(test);
ctx->link = dm_kunit_alloc_link(test);
@@ -3444,7 +3445,7 @@ static void dm_mst_test_recompute_unchanged_stream(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- dm_mst_test_add_link_stream(test, ctx.dc->current_state, ctx.link, ctx.aconnector);
+ dm_mst_test_add_link_stream(test, dc_get_current_state(ctx.dc), ctx.link, ctx.aconnector);
ctx.crtc_state->enable = true;
ctx.crtc_state->active = true;
@@ -3466,7 +3467,7 @@ static void dm_mst_test_recompute_stream_removed(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
gone = dm_kunit_alloc_connector(test, ctx.adev, ctx.link);
dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- dm_mst_test_add_link_stream(test, ctx.dc->current_state, ctx.link, gone);
+ dm_mst_test_add_link_stream(test, dc_get_current_state(ctx.dc), ctx.link, gone);
ctx.crtc_state->enable = true;
ctx.crtc_state->active = true;
@@ -3500,7 +3501,7 @@ static void dm_mst_test_recompute_connector_without_crtc(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- dm_mst_test_add_link_stream(test, ctx.dc->current_state, ctx.link, ctx.aconnector);
+ dm_mst_test_add_link_stream(test, dc_get_current_state(ctx.dc), ctx.link, ctx.aconnector);
ctx.conn_state->crtc = NULL;
KUNIT_EXPECT_FALSE(test, is_dsc_need_re_compute(ctx.state, ctx.dc_state, ctx.link));
@@ -3544,13 +3545,13 @@ dm_mst_test_add_mst_dsc_stream(struct kunit *test, struct dm_mst_test_recompute_
funcs->remove_stream_from_ctx = remove_stream;
res_pool->funcs = funcs;
- ctx->dc->res_pool = res_pool;
+ dc_test_set_res_pool(ctx->dc, res_pool);
sink->dsc_caps.dsc_dec_caps.is_dsc_supported = true;
ctx->aconnector->dc_sink = sink;
ctx->aconnector->mst_output_port = port;
stream = dm_mst_test_add_link_stream(test, ctx->dc_state, ctx->link, ctx->aconnector);
- stream->ctx = ctx->dc->ctx;
+ stream->ctx = dc_get_ctx(ctx->dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
return stream;
@@ -3568,7 +3569,7 @@ static void dm_mst_test_compute_configs_skips_sst(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
stream = dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- stream->ctx = ctx.dc->ctx;
+ stream->ctx = dc_get_ctx(ctx.dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT;
KUNIT_EXPECT_EQ(test, compute_mst_dsc_configs_for_state(ctx.state, ctx.dc_state, vars), 0);
@@ -3589,7 +3590,7 @@ static void dm_mst_test_compute_configs_skips_incomplete(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
stream = dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- stream->ctx = ctx.dc->ctx;
+ stream->ctx = dc_get_ctx(ctx.dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
KUNIT_EXPECT_EQ(test, compute_mst_dsc_configs_for_state(ctx.state, ctx.dc_state, vars), 0);
@@ -3663,7 +3664,7 @@ static void dm_mst_test_pre_compute_configs_skips_sst(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
stream = dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- stream->ctx = ctx.dc->ctx;
+ stream->ctx = dc_get_ctx(ctx.dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT;
KUNIT_EXPECT_EQ(test, pre_compute_mst_dsc_configs_for_state(ctx.state, ctx.dc_state, vars), 0);
@@ -3681,7 +3682,7 @@ static void dm_mst_test_pre_compute_configs_skips_incomplete(struct kunit *test)
dm_mst_test_init_recompute_ctx(test, &ctx);
stream = dm_mst_test_add_link_stream(test, ctx.dc_state, ctx.link, ctx.aconnector);
- stream->ctx = ctx.dc->ctx;
+ stream->ctx = dc_get_ctx(ctx.dc);
stream->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
KUNIT_EXPECT_EQ(test, pre_compute_mst_dsc_configs_for_state(ctx.state, ctx.dc_state, vars), 0);
@@ -3846,16 +3847,16 @@ dm_mst_test_alloc_dsc_link_ctx(struct kunit *test, int total_avail_slots)
link_srv->mst_decide_link_encoding_format = dm_mst_test_mst_encoding_format;
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->link_srv = link_srv;
- dc->res_pool = res_pool;
- dc->current_state = dm_kunit_alloc_dc_state(test);
+ dc_test_install_link_service(dc, link_srv);
+ dc_test_set_res_pool(dc, res_pool);
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
link = dm_kunit_alloc_link(test);
link->dc = dc;
- link->ctx = dc->ctx;
+ link->ctx = dc_get_ctx(dc);
link->type = dc_connection_mst_branch;
- sink->ctx = dc->ctx;
+ sink->ctx = dc_get_ctx(dc);
dm_mst_test_setup_dsc_caps(test, dc, sink);
/* The payload allocation takes a reference, so start above zero. */
@@ -3870,7 +3871,7 @@ dm_mst_test_alloc_dsc_link_ctx(struct kunit *test, int total_avail_slots)
ctx->dc_state = dm_kunit_alloc_dc_state(test);
ctx->stream = dm_kunit_alloc_stream(test, link);
- ctx->stream->ctx = dc->ctx;
+ ctx->stream->ctx = dc_get_ctx(dc);
ctx->stream->sink = sink;
ctx->stream->dm_stream_context = ctx->aconnector;
ctx->stream->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
index 7422e8ba9564..0d8fd26bb0ac 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
@@ -18,6 +18,7 @@
#include <drm/drm_mode_config.h>
#include <drm/drm_plane.h>
#include <drm/drm_property.h>
+#include "dc_test.h"
struct dm_test_dcc_cap_ctx {
bool callback_ret;
@@ -364,19 +365,19 @@ static void dm_test_get_min_max_dc_plane_scaling(struct kunit *test)
int max_upscale = 0;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
KUNIT_ASSERT_NOT_NULL(test, fb);
adev->dm.dc = dc;
- dc->caps.planes[0].max_upscale_factor.nv12 = 1;
- dc->caps.planes[0].max_downscale_factor.nv12 = 1;
- dc->caps.planes[0].max_upscale_factor.argb8888 = 1600;
- dc->caps.planes[0].max_downscale_factor.argb8888 = 250;
- dc->caps.planes[0].max_upscale_factor.fp16 = 2000;
- dc->caps.planes[0].max_downscale_factor.fp16 = 500;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.nv12 = 1;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.nv12 = 1;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.argb8888 = 1600;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.argb8888 = 250;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.fp16 = 2000;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.fp16 = 500;
fb->format = drm_format_info(DRM_FORMAT_NV12);
KUNIT_ASSERT_NOT_NULL(test, fb->format);
@@ -688,7 +689,7 @@ static void dm_test_validate_dcc_rejects_from_cap(struct kunit *test)
dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
&plane_size, test);
dcc.independent_64b_blks = cases[i].independent_64b_blks;
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
dm_test_dcc_ctx = &ctx;
ret = amdgpu_dm_plane_validate_dcc(adev, SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
@@ -723,7 +724,7 @@ static void dm_test_validate_dcc_success_and_scan_mapping(struct kunit *test)
dm_test_init_validate_dcc_inputs(&adev, &dc, &tiling_info, &dcc, &address,
&plane_size, test);
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
dm_test_dcc_ctx = &ctx;
KUNIT_EXPECT_EQ(test,
@@ -1103,7 +1104,7 @@ static void dm_test_setup_gfx9_dcc_device(struct amdgpu_device *adev,
adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
adev->gfx.config.gb_addr_config_fields.num_pkrs = 2;
adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
ctx->callback_ret = true;
ctx->capable = true;
ctx->output_independent_64b_blks = output_independent_64b_blks;
@@ -1406,7 +1407,7 @@ static void dm_test_fill_gfx9_plane_attributes_dcc(struct kunit *test)
int ret;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1417,7 +1418,7 @@ static void dm_test_fill_gfx9_plane_attributes_dcc(struct kunit *test)
adev->gfx.config.gb_addr_config_fields.num_pipes = 2;
adev->gfx.config.gb_addr_config_fields.num_pkrs = 2;
adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 3, 0);
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
dm_test_dcc_ctx = &ctx;
afb->base.pitches[1] = 256;
@@ -1460,7 +1461,7 @@ static void dm_test_fill_gfx9_plane_attributes_validate_fails(struct kunit *test
int ret;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1511,7 +1512,7 @@ static void dm_test_fill_gfx9_plane_attributes_dcc_ind_blk(struct kunit *test)
unsigned int i;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1575,7 +1576,7 @@ static void dm_test_fill_gfx12_plane_attributes_dcc_blocks(struct kunit *test)
unsigned int i;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1583,7 +1584,7 @@ static void dm_test_fill_gfx12_plane_attributes_dcc_blocks(struct kunit *test)
adev->family = AMDGPU_FAMILY_GC_12_0_0;
adev->dm.dc = dc;
- dc->cap_funcs.get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
+ dc_test_cap_funcs(dc)->get_dcc_compression_cap = dm_test_get_dcc_compression_cap;
plane_size.surface_size.width = 1920;
plane_size.surface_size.height = 1080;
@@ -1635,7 +1636,7 @@ static void dm_test_fill_gfx12_plane_attributes_validate_fails(struct kunit *tes
int ret;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, adev);
KUNIT_ASSERT_NOT_NULL(test, dc);
@@ -1726,7 +1727,7 @@ static void dm_test_fill_plane_buffer_attributes_gfx12(struct kunit *test)
int ret;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
afb = kunit_kzalloc(test, sizeof(*afb), GFP_KERNEL);
tiling_info = (struct dc_tiling_info){0};
plane_size = (struct plane_size){0};
@@ -1772,7 +1773,7 @@ static void dm_test_helper_check_state_scaling_caps(struct kunit *test)
struct drm_framebuffer *fb;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
crtc = kunit_kzalloc(test, sizeof(*crtc), GFP_KERNEL);
@@ -1787,8 +1788,8 @@ static void dm_test_helper_check_state_scaling_caps(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, fb);
adev->dm.dc = dc;
- dc->caps.planes[0].max_upscale_factor.argb8888 = 1;
- dc->caps.planes[0].max_downscale_factor.argb8888 = 1;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.argb8888 = 1;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.argb8888 = 1;
plane->type = DRM_PLANE_TYPE_OVERLAY;
plane->dev = &adev->ddev;
@@ -1873,7 +1874,7 @@ static void dm_test_fill_dc_scaling_info_plane_caps(struct kunit *test)
struct dc_scaling_info info = {0};
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
plane = kunit_kzalloc(test, sizeof(*plane), GFP_KERNEL);
state = kunit_kzalloc(test, sizeof(*state), GFP_KERNEL);
fb = kunit_kzalloc(test, sizeof(*fb), GFP_KERNEL);
@@ -1884,8 +1885,8 @@ static void dm_test_fill_dc_scaling_info_plane_caps(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, fb);
adev->dm.dc = dc;
- dc->caps.planes[0].max_upscale_factor.argb8888 = 16000;
- dc->caps.planes[0].max_downscale_factor.argb8888 = 250;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.argb8888 = 16000;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.argb8888 = 250;
plane->dev = &adev->ddev;
fb->format = drm_format_info(DRM_FORMAT_XRGB8888);
@@ -2025,7 +2026,7 @@ static struct amdgpu_device *dm_test_init_atomic_check_state(struct kunit *test,
struct drm_crtc *crtc;
adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL);
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
+ dc = dm_kunit_alloc_dc(test);
*state = kunit_kzalloc(test, sizeof(**state), GFP_KERNEL);
planes = kunit_kzalloc(test, sizeof(*planes), GFP_KERNEL);
crtcs = kunit_kzalloc(test, sizeof(*crtcs), GFP_KERNEL);
@@ -2048,10 +2049,10 @@ static struct amdgpu_device *dm_test_init_atomic_check_state(struct kunit *test,
KUNIT_ASSERT_NOT_NULL(test, *fb);
adev->dm.dc = dc;
- dc->caps.planes[0].max_upscale_factor.argb8888 = 1000;
- dc->caps.planes[0].max_downscale_factor.argb8888 = 1000;
- dc->caps.planes[0].max_upscale_factor.nv12 = 1000;
- dc->caps.planes[0].max_downscale_factor.nv12 = 1000;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.argb8888 = 1000;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.argb8888 = 1000;
+ dc_test_caps(dc)->planes[0].max_upscale_factor.nv12 = 1000;
+ dc_test_caps(dc)->planes[0].max_downscale_factor.nv12 = 1000;
(*plane)->dev = &adev->ddev;
(*plane)->index = 0;
@@ -3009,7 +3010,7 @@ static void dm_test_atomic_check_success(struct kunit *test)
res_pool->funcs = kunit_kzalloc(test, sizeof(*res_pool->funcs), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, res_pool->funcs);
- adev->dm.dc->res_pool = res_pool;
+ dc_test_set_res_pool(adev->dm.dc, res_pool);
dm_plane_state->dc_state->src_rect.width = 100;
dm_plane_state->dc_state->src_rect.height = 100;
@@ -3107,7 +3108,7 @@ static void dm_test_handle_cursor_update_no_stream(struct kunit *test)
struct dm_test_cursor_ctx *ctx = dm_test_alloc_cursor_ctx(test);
ctx->crtc_state->cm_is_degamma_srgb = true;
- ctx->adev->dm.dc->caps.color.dpp.gamma_corr = true;
+ dc_test_caps(ctx->adev->dm.dc)->color.dpp.gamma_corr = true;
amdgpu_dm_plane_handle_cursor_update(ctx->plane, &ctx->old_state);
@@ -3153,11 +3154,11 @@ static void dm_test_panic_flush_disables_dcc(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, res_pool);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = dm_kunit_alloc_dc_state(test);
- dc->hwss.clear_surface_dcc_and_tiling = dm_test_clear_surface_dcc_and_tiling;
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
+ dc_test_hwss(dc)->clear_surface_dcc_and_tiling = dm_test_clear_surface_dcc_and_tiling;
res_pool->pipe_count = 1;
- dc->res_pool = res_pool;
- dc_plane_state->ctx = dc->ctx;
+ dc_test_set_res_pool(dc, res_pool);
+ dc_plane_state->ctx = dc_get_ctx(dc);
fb->modifier = AMD_FMT_MOD;
dm_plane_state->base.fb = fb;
@@ -3231,7 +3232,7 @@ static void dm_test_plane_init_creates_color_pipeline(struct kunit *test)
struct drm_plane *plane;
plane = dm_test_alloc_init_plane(test, &adev);
- adev->dm.dc->ctx->dce_version = DCN_VERSION_3_0;
+ dc_get_ctx(adev->dm.dc)->dce_version = DCN_VERSION_3_0;
KUNIT_ASSERT_EQ(test, amdgpu_dm_plane_init(&adev->dm, plane, 1, NULL), 0);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c
index 0a484ea7c0e8..8b9e34b3c4be 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c
@@ -8,6 +8,7 @@
#include <kunit/test.h>
#include "dc.h"
+#include "dc_test.h"
#include "core_types.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
@@ -50,7 +51,7 @@ static struct dc_link *alloc_test_psrsu_link(struct kunit *test)
struct dc_context *ctx = link->ctx;
struct dc *dc = ctx->dc;
- dc->caps.dmcub_support = true;
+ dc_test_caps(dc)->dmcub_support = true;
ctx->dce_version = DCN_VERSION_3_1;
link->dpcd_caps.edp_rev = DP_EDP_14;
link->dpcd_caps.psr_info.psr_version = DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
@@ -64,7 +65,7 @@ static struct dc_link *alloc_test_psr_caps_link(struct kunit *test)
{
struct dc_link *link = alloc_test_psrsu_link(test);
- link->ctx->dc->caps.dmub_caps.psr = true;
+ dc_test_caps(link->ctx->dc)->dmub_caps.psr = true;
link->connector_signal = SIGNAL_TYPE_EDP;
link->type = dc_connection_single;
@@ -91,7 +92,7 @@ static void dm_test_link_supports_psrsu_no_dmcub(struct kunit *test)
{
struct dc_link *link = alloc_test_psrsu_link(test);
- link->ctx->dc->caps.dmcub_support = false;
+ dc_test_caps(link->ctx->dc)->dmcub_support = false;
KUNIT_EXPECT_FALSE(test, link_supports_psrsu(link));
}
@@ -232,7 +233,7 @@ static void dm_test_set_psr_caps_no_dmub_psr(struct kunit *test)
struct amdgpu_dm_connector *aconnector = alloc_test_aconnector(test);
link->psr_settings.psr_version = DC_PSR_VERSION_1;
- link->ctx->dc->caps.dmub_caps.psr = false;
+ dc_test_caps(link->ctx->dc)->dmub_caps.psr = false;
KUNIT_EXPECT_FALSE(test, amdgpu_dm_set_psr_caps(link, aconnector));
KUNIT_EXPECT_EQ(test, link->psr_settings.psr_version,
@@ -293,9 +294,9 @@ static void dm_test_set_psr_caps_edp1_disabled(struct kunit *test)
struct dc *dc = link->ctx->dc;
edp0->connector_signal = SIGNAL_TYPE_EDP;
- dc->links[0] = edp0;
- dc->links[1] = link;
- dc->link_count = 2;
+ dc_test_set_link(dc, 0, edp0);
+ dc_test_set_link(dc, 1, link);
+ dc_test_set_link_count(dc, 2);
KUNIT_EXPECT_FALSE(test, amdgpu_dm_set_psr_caps(link, aconnector));
}
@@ -647,7 +648,7 @@ static void dm_test_psr_is_active_allowed_no_streams(struct kunit *test)
static void dm_test_psr_is_active_allowed_null_link(struct kunit *test)
{
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
- struct dc_state *state = dm->dc->current_state;
+ struct dc_state *state = dc_get_current_state(dm->dc);
dm_kunit_add_stream_to_state(test, state, 0, NULL);
@@ -662,7 +663,7 @@ static void dm_test_psr_is_active_allowed_null_link(struct kunit *test)
static void dm_test_psr_is_active_allowed_requires_enabled_and_allowed(struct kunit *test)
{
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
- struct dc_state *state = dm->dc->current_state;
+ struct dc_state *state = dc_get_current_state(dm->dc);
struct dc_link *link = dm_kunit_alloc_link(test);
dm_kunit_add_stream_to_state(test, state, 0, link);
@@ -682,7 +683,7 @@ static void dm_test_psr_is_active_allowed_requires_enabled_and_allowed(struct ku
static void dm_test_psr_is_active_allowed_any_stream(struct kunit *test)
{
struct amdgpu_display_manager *dm = dm_kunit_alloc_dm(test);
- struct dc_state *state = dm->dc->current_state;
+ struct dc_state *state = dc_get_current_state(dm->dc);
struct dc_link *disabled_link = dm_kunit_alloc_link(test);
struct dc_link *allowed_link = dm_kunit_alloc_link(test);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
index c375ee68778b..c0dbab0b7c46 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
@@ -22,6 +22,7 @@
#include <drm/drm_writeback.h>
#include "dc.h"
+#include "dc_test.h"
#include "dc/dc_dmub_srv.h"
#include "dal_asic_id.h"
#include "dm_services_types.h"
@@ -1279,13 +1280,13 @@ static void dm_test_crtc_with_stream(struct kunit *test,
logger = kunit_kzalloc(test, sizeof(*logger), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, logger);
logger->dev = &adev->ddev;
- dc->ctx->logger = logger;
+ dc_get_ctx(dc)->logger = logger;
- dc->current_state = dm_kunit_alloc_dc_state(test);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
stream = dm_kunit_alloc_stream(test, NULL);
- stream->ctx = dc->ctx;
+ stream->ctx = dc_get_ctx(dc);
adev->dm.dc = dc;
adev->mode_info.num_crtc = 1;
@@ -1337,8 +1338,8 @@ static void dm_test_crtc_get_scanoutpos_exits_idle(struct kunit *test)
u32 position = 0;
dm_test_crtc_with_stream(test, adev, dc);
- dc->caps.ips_support = true;
- dc->idle_optimizations_allowed = true;
+ dc_test_caps(dc)->ips_support = true;
+ dc_test_set_idle_optimizations_allowed(dc, true);
KUNIT_EXPECT_EQ(test, dm_crtc_get_scanoutpos(adev, 0, &vbl, &position), 0);
}
@@ -2940,8 +2941,8 @@ static struct dc_link *dm_test_dc_with_link(struct kunit *test,
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
struct dc_link *link = dm_kunit_alloc_link(test);
- dc->links[0] = link;
- dc->link_count = 1;
+ dc_test_set_link(dc, 0, link);
+ dc_test_set_link_count(dc, 1);
adev->dm.dc = dc;
return link;
@@ -2967,7 +2968,7 @@ static void dm_test_dump_links_with_sinks(struct kunit *test)
link->local_sink = local_sink;
link->sink_count = 1;
link->remote_sinks[0] = remote_sink;
- adev->dm.dc->link_count = 2;
+ dc_test_set_link_count(adev->dm.dc, 2);
amdgpu_dm_dump_links_and_sinks(adev);
}
@@ -3328,7 +3329,7 @@ static void dm_test_trigger_timing_sync_streams(struct kunit *test)
context->streams[0] = stream;
context->stream_count = 1;
- dc->current_state = context;
+ dc_test_set_current_state(dc, context);
adev->dm.dc = dc;
adev->dm.force_timing_sync = true;
mutex_init(&adev->dm.dc_lock);
@@ -3387,8 +3388,8 @@ static void dm_test_oem_i2c_hw_init_no_device(struct kunit *test)
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->res_pool = kunit_kzalloc(test, sizeof(*dc->res_pool), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->res_pool);
+ dc_test_set_res_pool(dc, kunit_kzalloc(test, sizeof(*dc_get_res_pool(dc)), GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_res_pool(dc));
adev->dm.dc = dc;
KUNIT_EXPECT_EQ(test, dm_oem_i2c_hw_init(adev), 0);
@@ -4471,8 +4472,8 @@ static void dm_test_commit_zero_streams_empty(struct kunit *test)
{
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = dm_kunit_alloc_dc_state(test);
- KUNIT_ASSERT_NOT_NULL(test, dc->current_state);
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(dc));
KUNIT_EXPECT_EQ(test, (int)amdgpu_dm_commit_zero_streams(dc), (int)DC_OK);
}
@@ -4550,7 +4551,7 @@ static void dm_test_clear_writeback_removes_stream(struct kunit *test)
acrtc = kunit_kzalloc(test, sizeof(*acrtc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, acrtc);
stream = dm_kunit_alloc_stream(test, NULL);
- dm->dc->hwss.update_bandwidth = dm_test_update_bandwidth;
+ dc_test_hwss(dm->dc)->update_bandwidth = dm_test_update_bandwidth;
crtc_state->stream = stream;
stream->num_wb_info = 1;
stream->writeback_info[0].dwb_pipe_inst = 0;
@@ -4588,7 +4589,7 @@ static void dm_test_set_writeback_no_pipe(struct kunit *test)
acrtc = kunit_kzalloc(test, sizeof(*acrtc), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, acrtc);
dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->current_state = dm_kunit_alloc_dc_state(test);
+ dc_test_set_current_state(dc, dm_kunit_alloc_dc_state(test));
adev->dm.adev = adev;
adev->dm.dc = dc;
@@ -4735,8 +4736,8 @@ dm_test_plane_attr_ctx_alloc(struct kunit *test, u32 drm_format)
ctx->adev = dm_kunit_alloc_adev(test);
ctx->adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- ctx->adev->dm.dc->caps.planes[0].max_upscale_factor.argb8888 = 1;
- ctx->adev->dm.dc->caps.planes[0].max_downscale_factor.argb8888 = 1;
+ dc_test_caps(ctx->adev->dm.dc)->planes[0].max_upscale_factor.argb8888 = 1;
+ dc_test_caps(ctx->adev->dm.dc)->planes[0].max_downscale_factor.argb8888 = 1;
ctx->crtc_state->stream = dm_kunit_alloc_stream(test, NULL);
/* Colour management resolves the device through the commit backpointer. */
@@ -4821,7 +4822,7 @@ static void dm_test_plane_attributes_bad_color_mgmt(struct kunit *test)
/* A 3D LUT that is not a perfect cube fails validation. */
blob->data = lut;
blob->length = 16 * sizeof(*lut);
- ctx->adev->dm.dc->caps.color.dpp.hw_3d_lut = true;
+ dc_test_caps(ctx->adev->dm.dc)->color.dpp.hw_3d_lut = true;
ctx->plane->dm_plane_state->lut3d = blob;
KUNIT_EXPECT_EQ(test, dm_test_fill_plane_attr(ctx), -EINVAL);
@@ -4980,8 +4981,8 @@ static struct amdgpu_device *dm_test_late_init_adev(struct kunit *test)
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc->res_pool = kunit_kzalloc(test, sizeof(*dc->res_pool), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc->res_pool);
+ dc_test_set_res_pool(dc, kunit_kzalloc(test, sizeof(*dc_get_res_pool(dc)), GFP_KERNEL));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_res_pool(dc));
adev->dm.dc = dc;
return adev;
@@ -5044,7 +5045,7 @@ static void dm_test_late_init_boot_crc_disabled(struct kunit *test)
dm_test_fw_boot_options.bits.bootcrc_en_at_S0i3 = 0;
dmub->hw_funcs.get_fw_boot_option = dm_test_get_fw_boot_option;
dmub_srv->dmub = dmub;
- adev->dm.dc->ctx->dmub_srv = dmub_srv;
+ dc_get_ctx(adev->dm.dc)->dmub_srv = dmub_srv;
adev->ip_versions[DCE_HWIP][0] = IP_VERSION(3, 6, 0);
KUNIT_EXPECT_EQ(test, dm_test_run_late_init(adev), 0);
@@ -5074,8 +5075,8 @@ static struct amdgpu_device *dm_test_mode_config_adev(struct kunit *test)
long saved_audio = amdgpu_dm_audio_get_param();
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- adev->dm.dc->current_state = dm_kunit_alloc_dc_state(test);
- KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc->current_state);
+ dc_test_set_current_state(adev->dm.dc, dm_kunit_alloc_dc_state(test));
+ KUNIT_ASSERT_NOT_NULL(test, dc_get_current_state(adev->dm.dc));
amdgpu_dm_audio_set_param(0);
KUNIT_ASSERT_EQ(test, kunit_add_action_or_reset(test, dm_test_restore_audio_param,
@@ -5141,7 +5142,7 @@ static void dm_test_initialize_plane_primary(struct kunit *test)
adev->family = AMDGPU_FAMILY_NV;
adev->dm.adev = adev;
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- adev->dm.dc->caps.max_streams = 1;
+ dc_test_caps(adev->dm.dc)->max_streams = 1;
KUNIT_ASSERT_EQ(test, initialize_plane(&adev->dm, mode_info, 0,
DRM_PLANE_TYPE_PRIMARY, NULL), 0);
@@ -5167,7 +5168,7 @@ static void dm_test_initialize_plane_overlay(struct kunit *test)
adev->family = AMDGPU_FAMILY_NV;
adev->dm.adev = adev;
adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test);
- adev->dm.dc->caps.max_streams = 1;
+ dc_test_caps(adev->dm.dc)->max_streams = 1;
plane_cap->per_pixel_alpha = true;
plane_cap->pixel_format_support.nv12 = true;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_wb_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_wb_test.c
index 047ac88cb2a9..d43f150704d1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_wb_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_wb_test.c
@@ -18,6 +18,7 @@
#include <drm/drm_writeback.h>
#include "dc.h"
+#include "dc_test.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_wb.h"
@@ -495,13 +496,12 @@ static void dm_test_wb_connector_init_success(struct kunit *test)
dm = &adev->dm;
dm->adev = adev;
- dc = kunit_kzalloc(test, sizeof(*dc), GFP_KERNEL);
- KUNIT_ASSERT_NOT_NULL(test, dc);
+ dc = dm_kunit_alloc_dc(test);
link = kunit_kzalloc(test, sizeof(*link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, link);
- dc->links[0] = link;
+ dc_test_set_link(dc, 0, link);
dm->dc = dc;
ret = amdgpu_dm_wb_connector_init(dm, wbcon, 0);
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 0f39a15dfc60..440f5d358188 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -92,5 +92,9 @@ FILES += bls_executor/bls_executor.o
FILES += workaround_manager/workaround_manager.o
FILES += dmub_messenger/dmub_messenger.o
+ifneq ($(CONFIG_DRM_AMD_DC_KUNIT_TEST),)
+FILES += core/dc_test.o
+endif
+
AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/, $(FILES))
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 2803471d7333..4c583d452446 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -31,6 +31,7 @@
* mapping stays obvious and auditable.
*/
#include "dc.h"
+#include "dm_helpers.h" /* EXPORT_IF_KUNIT */
uint8_t dc_get_link_count(const struct dc *dc)
{
@@ -41,6 +42,7 @@ struct dc_context *dc_get_ctx(const struct dc *dc)
{
return dc->ctx;
}
+EXPORT_IF_KUNIT(dc_get_ctx);
enum dce_version dc_get_dce_version(const struct dc *dc)
{
@@ -77,21 +79,25 @@ struct dc_state *dc_get_current_state(const struct dc *dc)
{
return dc->current_state;
}
+EXPORT_IF_KUNIT(dc_get_current_state);
bool dc_is_idle_optimizations_allowed(const struct dc *dc)
{
return dc->idle_optimizations_allowed;
}
+EXPORT_IF_KUNIT(dc_is_idle_optimizations_allowed);
struct resource_pool *dc_get_res_pool(const struct dc *dc)
{
return dc->res_pool;
}
+EXPORT_IF_KUNIT(dc_get_res_pool);
struct clk_mgr *dc_get_clk_mgr(struct dc *dc)
{
return dc->clk_mgr;
}
+EXPORT_IF_KUNIT(dc_get_clk_mgr);
bool dc_get_dcc_compression_cap(const struct dc *dc,
const struct dc_dcc_surface_param *input,
@@ -139,6 +145,7 @@ bool dc_is_fbc_compressor_available(const struct dc *dc)
{
return dc->fbc_compressor != NULL;
}
+EXPORT_IF_KUNIT(dc_is_fbc_compressor_available);
void dc_set_fbc_gpu_addr(struct dc *dc, uint64_t gpu_addr)
{
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_test.c b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
new file mode 100644
index 000000000000..60fb45f9cfaa
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/* FILE POLICY AND INTENDED USAGE:
+ * Implementation of the KUnit test double API declared in dc_test.h.
+ * struct dc is private to DC; this file is the only place outside of the
+ * accessors that maps test operations onto struct dc members. It carries
+ * no functional behavior.
+ */
+#include <linux/slab.h>
+#include <linux/export.h>
+
+#include "dc.h"
+#include "dc_test.h"
+
+struct dc *dc_test_create(void)
+{
+ return kvzalloc(sizeof(struct dc), GFP_KERNEL);
+}
+EXPORT_SYMBOL(dc_test_create);
+
+void dc_test_destroy(struct dc *dc)
+{
+ kvfree(dc);
+}
+EXPORT_SYMBOL(dc_test_destroy);
+
+void dc_test_set_ctx(struct dc *dc, struct dc_context *ctx)
+{
+ dc->ctx = ctx;
+}
+EXPORT_SYMBOL(dc_test_set_ctx);
+
+void dc_test_set_current_state(struct dc *dc, struct dc_state *state)
+{
+ dc->current_state = state;
+}
+EXPORT_SYMBOL(dc_test_set_current_state);
+
+void dc_test_install_link_service(struct dc *dc,
+ struct link_service *link_srv)
+{
+ dc->link_srv = link_srv;
+}
+EXPORT_SYMBOL(dc_test_install_link_service);
+
+void dc_test_set_res_pool(struct dc *dc, struct resource_pool *res_pool)
+{
+ dc->res_pool = res_pool;
+}
+EXPORT_SYMBOL(dc_test_set_res_pool);
+
+void dc_test_set_clk_mgr(struct dc *dc, struct clk_mgr *clk_mgr)
+{
+ dc->clk_mgr = clk_mgr;
+}
+EXPORT_SYMBOL(dc_test_set_clk_mgr);
+
+void dc_test_set_fbc_compressor(struct dc *dc, struct compressor *compressor)
+{
+ dc->fbc_compressor = compressor;
+}
+EXPORT_SYMBOL(dc_test_set_fbc_compressor);
+
+void dc_test_set_link(struct dc *dc, unsigned int index, struct dc_link *link)
+{
+ if (index >= MAX_LINKS)
+ return;
+
+ dc->links[index] = link;
+}
+EXPORT_SYMBOL(dc_test_set_link);
+
+void dc_test_set_link_count(struct dc *dc, unsigned int count)
+{
+ dc->link_count = count;
+}
+EXPORT_SYMBOL(dc_test_set_link_count);
+
+void dc_test_set_idle_optimizations_allowed(struct dc *dc, bool allowed)
+{
+ dc->idle_optimizations_allowed = allowed;
+}
+EXPORT_SYMBOL(dc_test_set_idle_optimizations_allowed);
+
+struct dc_caps *dc_test_caps(struct dc *dc)
+{
+ return &dc->caps;
+}
+EXPORT_SYMBOL(dc_test_caps);
+
+struct dc_config *dc_test_config(struct dc *dc)
+{
+ return &dc->config;
+}
+EXPORT_SYMBOL(dc_test_config);
+
+struct dc_debug_options *dc_test_debug_options(struct dc *dc)
+{
+ return &dc->debug;
+}
+EXPORT_SYMBOL(dc_test_debug_options);
+
+struct dc_cap_funcs *dc_test_cap_funcs(struct dc *dc)
+{
+ return &dc->cap_funcs;
+}
+EXPORT_SYMBOL(dc_test_cap_funcs);
+
+struct hw_sequencer_funcs *dc_test_hwss(struct dc *dc)
+{
+ return &dc->hwss;
+}
+EXPORT_SYMBOL(dc_test_hwss);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_test.h b/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
new file mode 100644
index 000000000000..61911de9da05
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __DC_TEST_H__
+#define __DC_TEST_H__
+
+/*
+ * KUnit support for building DC test doubles.
+ *
+ * struct dc is private to DC, so test code outside the dc directory cannot
+ * allocate one or poke its members directly. These helpers construct an
+ * empty fake DC instance and let tests install the pieces they need. They
+ * exist only when the amdgpu_dm KUnit tests are enabled and must never be
+ * used outside tests.
+ */
+
+struct dc;
+struct dc_context;
+struct dc_state;
+struct dc_link;
+struct dc_caps;
+struct dc_config;
+struct dc_debug_options;
+struct dc_cap_funcs;
+struct link_service;
+struct resource_pool;
+struct clk_mgr;
+struct compressor;
+struct hw_sequencer_funcs;
+
+#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
+
+/*
+ * Allocate a zeroed fake DC instance. Free it with dc_test_destroy() (or
+ * register that as a KUnit action).
+ */
+struct dc *dc_test_create(void);
+void dc_test_destroy(struct dc *dc);
+
+void dc_test_set_ctx(struct dc *dc, struct dc_context *ctx);
+void dc_test_set_current_state(struct dc *dc, struct dc_state *state);
+void dc_test_install_link_service(struct dc *dc,
+ struct link_service *link_srv);
+void dc_test_set_res_pool(struct dc *dc, struct resource_pool *res_pool);
+void dc_test_set_clk_mgr(struct dc *dc, struct clk_mgr *clk_mgr);
+void dc_test_set_fbc_compressor(struct dc *dc, struct compressor *compressor);
+void dc_test_set_link(struct dc *dc, unsigned int index, struct dc_link *link);
+void dc_test_set_link_count(struct dc *dc, unsigned int count);
+void dc_test_set_idle_optimizations_allowed(struct dc *dc, bool allowed);
+
+/* Mutable views of embedded sub-structures, for test faking only. */
+struct dc_caps *dc_test_caps(struct dc *dc);
+struct dc_config *dc_test_config(struct dc *dc);
+struct dc_debug_options *dc_test_debug_options(struct dc *dc);
+struct dc_cap_funcs *dc_test_cap_funcs(struct dc *dc);
+struct hw_sequencer_funcs *dc_test_hwss(struct dc *dc);
+
+#endif /* IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) */
+
+#endif /* __DC_TEST_H__ */
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 12/19] drm/amd/display: Migrate amdgpu_dm KUnit tests off struct dc internals
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 1:59 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 1:59 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] drm/amd/display: CFI violation and unchecked kunit_add_action()
in dm_kunit_alloc_dc()
--
commit 3e7024f14775977bb5d35f97fcb673f3cd943908
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display: Migrate amdgpu_dm KUnit tests off struct dc internals
This commit adds a KUnit test double API for struct dc and converts the
amdgpu_dm KUnit tests to use it instead of accessing struct dc fields
directly.
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
> index f844b644bb776..9954cbab65416 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
> @@ -47,18 +48,29 @@ struct dc_link *dm_kunit_alloc_link(struct kunit *test)
> }
> EXPORT_SYMBOL(dm_kunit_alloc_link);
>
> +struct dc *dm_kunit_alloc_dc(struct kunit *test)
> +{
> + struct dc *dc;
> +
> + dc = dc_test_create();
> + KUNIT_ASSERT_NOT_NULL(test, dc);
> + kunit_add_action(test, (kunit_action_t *)dc_test_destroy, dc);
[Severity: Low]
Does casting dc_test_destroy() (which takes struct dc *) to kunit_action_t *
(void (*)(void *)) trigger a KCFI failure on test teardown when built with
CONFIG_CFI_CLANG? Also, kunit_add_action() can fail and leak dc if its
return value is not checked, whereas KUNIT_DEFINE_ACTION_WRAPPER() with
kunit_add_action_or_reset() avoids both issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=12
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 13/19] drm/amd/display: Move struct dc out of the public dc.h
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
struct dc is now defined in the new dc/dc_priv.h, which must only be
included from inside the dc directory. dc.h keeps the public API and
public types and forward-declares struct dc; consumers outside DC hold
opaque pointers and go through the accessor layer.
Also move the BW_VAL_TRACE_* macros, which dereference a dc-local
variable, from dc.h into dc_priv.h.
Update DC-internal includes accordingly (~300 files gain an include of
dc_priv.h next to their existing dc.h include or at the end of their
include block). With this, code outside the dc directory can no
longer compile against struct dc members: the compiler enforces the
boundary.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../display/amdgpu_dm/tests/amdgpu_dm_audio_test.c | 6 +-
.../display/amdgpu_dm/tests/amdgpu_dm_color_test.c | 4 +-
.../amdgpu_dm/tests/amdgpu_dm_connector_test.c | 12 +-
.../display/amdgpu_dm/tests/amdgpu_dm_crc_test.c | 2 +-
.../amdgpu_dm/tests/amdgpu_dm_freesync_test.c | 2 +-
.../amdgpu_dm/tests/amdgpu_dm_helpers_test.c | 4 +-
.../display/amdgpu_dm/tests/amdgpu_dm_plane_test.c | 2 +-
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c | 1 +
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 +
.../gpu/drm/amd/display/dc/bios/command_table2.c | 1 +
.../drm/amd/display/dc/bls_builder/bls_builder.c | 1 +
.../display/dc/bls_builder/dcn401_init_builder.c | 1 +
.../dc/bls_builder/dcn401_init_builder_legacy.c | 1 +
.../drm/amd/display/dc/bls_executor/bls_executor.c | 1 +
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 1 +
.../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 1 +
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_link_exports.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_test.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 1 +
drivers/gpu/drm/amd/display/dc/dc.h | 131 ---------------
.../drm/amd/display/dc/dc_api_dispatch/api_shim.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 1 +
drivers/gpu/drm/amd/display/dc/dc_priv.h | 186 +++++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 1 +
.../gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c | 1 +
.../drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c | 1 +
.../gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 1 +
.../drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c | 1 +
.../gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 1 +
.../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 1 +
.../gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 1 +
.../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 1 +
.../drm/amd/display/dc/dce110/dce110_transform_v.c | 1 +
.../display/dc/dcn10/dcn10_hw_sequencer_debug.c | 1 +
.../amd/display/dc/dcn201/dcn201_link_encoder.c | 1 +
.../drm/amd/display/dc/dcn21/dcn21_link_encoder.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c | 1 +
.../drm/amd/display/dc/dcn31/dcn31_panel_cntl.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c | 1 +
.../amd/display/dc/dio/dcn10/dcn10_link_encoder.c | 1 +
.../display/dc/dio/dcn10/dcn10_stream_encoder.c | 1 +
.../amd/display/dc/dio/dcn20/dcn20_link_encoder.c | 1 +
.../display/dc/dio/dcn20/dcn20_stream_encoder.c | 1 +
.../display/dc/dio/dcn30/dcn30_dio_link_encoder.c | 1 +
.../dc/dio/dcn30/dcn30_dio_stream_encoder.c | 1 +
.../dc/dio/dcn301/dcn301_dio_link_encoder.c | 1 +
.../display/dc/dio/dcn31/dcn31_dio_link_encoder.c | 1 +
.../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 1 +
.../display/dc/dio/dcn32/dcn32_dio_link_encoder.c | 1 +
.../dc/dio/dcn32/dcn32_dio_stream_encoder.c | 1 +
.../dc/dio/dcn321/dcn321_dio_link_encoder.c | 1 +
.../display/dc/dio/dcn35/dcn35_dio_link_encoder.c | 1 +
.../dc/dio/dcn35/dcn35_dio_stream_encoder.c | 1 +
.../dc/dio/dcn401/dcn401_dio_link_encoder.c | 1 +
.../dc/dio/dcn401/dcn401_dio_stream_encoder.c | 1 +
.../display/dc/dio/dcn42/dcn42_dio_link_encoder.c | 1 +
.../dc/dio/dcn42/dcn42_dio_stream_encoder.c | 1 +
.../display/dc/dio/dcn60/dcn60_dio_link_encoder.c | 1 +
.../dc/dio/dcn60/dcn60_dio_stream_encoder.c | 1 +
.../gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c | 1 +
.../dml21_wrapper/dml21_translation_helper.c | 1 +
.../dc/dml2_wrapper/dml21_wrapper/dml21_utils.c | 1 +
.../dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c | 1 +
.../dc/dml2_wrapper/dml2_dc_resource_mgmt.c | 1 +
.../display/dc/dml2_wrapper/dml2_mall_phantom.c | 1 +
.../dc/dml2_wrapper/dml2_translation_helper.c | 1 +
.../drm/amd/display/dc/dml2_wrapper/dml2_utils.c | 1 +
.../drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c | 1 +
.../amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c | 1 +
.../drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c | 1 +
.../drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c | 1 +
.../gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c | 1 +
.../gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 1 +
.../drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c | 1 +
.../amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 1 +
.../drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c | 1 +
.../drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 1 +
drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 1 +
.../dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c | 1 +
.../drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c | 1 +
.../amd/display/dc/hubbub/dcn201/dcn201_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c | 1 +
.../amd/display/dc/hubbub/dcn401/dcn401_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c | 1 +
.../gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c | 1 +
.../gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c | 1 +
.../gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce100/dce100_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce112/dce112_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce120/dce120_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce60/dce60_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce80/dce80_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn201/dcn201_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn301/dcn301_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn302/dcn302_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn303/dcn303_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn314/dcn314_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn401/dcn401_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c | 1 +
.../amd/display/dc/irq/dce110/irq_service_dce110.c | 1 +
.../amd/display/dc/link/accessories/link_dp_cts.c | 1 +
.../display/dc/link/accessories/link_dp_trace.c | 1 +
.../drm/amd/display/dc/link/hwss/link_hwss_dio.c | 1 +
.../link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c | 1 +
.../drm/amd/display/dc/link/hwss/link_hwss_dpia.c | 1 +
.../amd/display/dc/link/hwss/link_hwss_hpo_dp.c | 1 +
.../hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 1 +
.../amd/display/dc/link/hwss/link_hwss_hpo_frl.c | 1 +
.../gpu/drm/amd/display/dc/link/link_detection.c | 1 +
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 1 +
drivers/gpu/drm/amd/display/dc/link/link_factory.c | 1 +
.../gpu/drm/amd/display/dc/link/link_resource.c | 1 +
.../gpu/drm/amd/display/dc/link/link_validation.c | 1 +
.../drm/amd/display/dc/link/protocols/link_ddc.c | 1 +
.../display/dc/link/protocols/link_dp_capability.c | 1 +
.../display/dc/link/protocols/link_dp_dpia_bw.c | 1 +
.../dc/link/protocols/link_dp_irq_handler.c | 1 +
.../dc/link/protocols/link_dp_panel_replay.c | 1 +
.../amd/display/dc/link/protocols/link_dp_phy.c | 1 +
.../display/dc/link/protocols/link_dp_training.c | 1 +
.../dc/link/protocols/link_dp_training_128b_132b.c | 1 +
.../dc/link/protocols/link_dp_training_8b_10b.c | 1 +
.../dc/link/protocols/link_dp_training_dpia.c | 1 +
.../link_dp_training_fixed_vs_pe_retimer.c | 1 +
.../dc/link/protocols/link_edp_panel_control.c | 1 +
.../amd/display/dc/link/protocols/link_hdmi_frl.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c | 1 +
.../gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c | 1 +
.../gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 1 +
.../drm/amd/display/dc/optc/dcn401/dcn401_optc.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c | 1 +
.../drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c | 1 +
.../drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c | 1 +
.../display/dc/resource/dce100/dce100_resource.c | 1 +
.../display/dc/resource/dce110/dce110_resource.c | 1 +
.../display/dc/resource/dce112/dce112_resource.c | 1 +
.../display/dc/resource/dce120/dce120_resource.c | 1 +
.../amd/display/dc/resource/dce60/dce60_resource.c | 1 +
.../amd/display/dc/resource/dce80/dce80_resource.c | 1 +
.../amd/display/dc/resource/dcn10/dcn10_resource.c | 1 +
.../amd/display/dc/resource/dcn20/dcn20_resource.c | 1 +
.../display/dc/resource/dcn201/dcn201_resource.c | 1 +
.../amd/display/dc/resource/dcn21/dcn21_resource.c | 1 +
.../amd/display/dc/resource/dcn30/dcn30_resource.c | 1 +
.../display/dc/resource/dcn301/dcn301_resource.c | 1 +
.../display/dc/resource/dcn302/dcn302_resource.c | 1 +
.../display/dc/resource/dcn303/dcn303_resource.c | 1 +
.../amd/display/dc/resource/dcn31/dcn31_resource.c | 1 +
.../display/dc/resource/dcn314/dcn314_resource.c | 1 +
.../display/dc/resource/dcn315/dcn315_resource.c | 1 +
.../display/dc/resource/dcn316/dcn316_resource.c | 1 +
.../amd/display/dc/resource/dcn32/dcn32_resource.c | 1 +
.../dc/resource/dcn32/dcn32_resource_helpers.c | 1 +
.../display/dc/resource/dcn321/dcn321_resource.c | 1 +
.../amd/display/dc/resource/dcn35/dcn35_resource.c | 1 +
.../display/dc/resource/dcn351/dcn351_resource.c | 1 +
.../amd/display/dc/resource/dcn36/dcn36_resource.c | 1 +
.../display/dc/resource/dcn401/dcn401_resource.c | 1 +
.../amd/display/dc/resource/dcn42/dcn42_resource.c | 1 +
.../display/dc/resource/dcn42/dcn42_resource_fpu.c | 1 +
.../display/dc/resource/dcn42b/dcn42b_resource.c | 1 +
.../amd/display/dc/resource/dcn60/dcn60_resource.c | 1 +
.../gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c | 1 +
.../gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c | 1 +
.../dcn401/dcn401_soc_and_ip_translator.c | 1 +
.../dcn42/dcn42_soc_and_ip_translator.c | 1 +
.../dcn60/dcn60_soc_and_ip_translator.c | 1 +
271 files changed, 464 insertions(+), 147 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
index 6d8651047ff7..c2ed369f3ca2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
@@ -809,7 +809,7 @@ static void dm_test_commit_audio_notifies_added_connector(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dm_crtc_state);
KUNIT_ASSERT_NOT_NULL(test, stream);
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
sizeof(*dc_get_current_state(adev->dm.dc)),
@@ -967,7 +967,7 @@ static void dm_test_commit_audio_skips_without_stream_status(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dm_crtc_state);
KUNIT_ASSERT_NOT_NULL(test, stream);
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
sizeof(*dc_get_current_state(adev->dm.dc)),
@@ -1172,7 +1172,7 @@ static void dm_test_commit_audio_skips_writeback_addition(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dm_crtc_state);
KUNIT_ASSERT_NOT_NULL(test, stream);
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
sizeof(*dc_get_current_state(adev->dm.dc)),
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
index 56a47809f302..28570f8a82ca 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
@@ -1758,7 +1758,7 @@ dm_test_verify_lut3d_alloc_adev(struct kunit *test, bool has_3dlut)
{
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
dc_test_caps(adev->dm.dc)->color.dpp.hw_3d_lut = has_3dlut;
@@ -2060,7 +2060,7 @@ dm_test_color_update_setup(struct kunit *test)
struct dm_test_color_update_fixture f = {0};
f.adev = dm_kunit_alloc_adev(test);
- f.adev->dm.dc = kunit_kzalloc(test, sizeof(*f.adev->dm.dc), GFP_KERNEL);
+ f.adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, f.adev->dm.dc);
f.state = kunit_kzalloc(test, sizeof(*f.state), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
index 204dc86266a3..94bb2181d141 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
@@ -3041,7 +3041,7 @@ static struct dm_test_fbc_ctx *dm_test_fbc_ctx_alloc(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, ctx->adev);
ctx->aconnector = kunit_kzalloc(test, sizeof(*ctx->aconnector), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->aconnector);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link = kunit_kzalloc(test, sizeof(*ctx->link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link);
@@ -5073,7 +5073,7 @@ static struct dm_test_poll_ctx *dm_test_poll_ctx_alloc(struct kunit *test)
DRM_MODE_CONNECTOR_VGA, NULL), 0);
mutex_init(&ctx->aconnector->hpd_lock);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link_srv = kunit_kzalloc(test, sizeof(*ctx->link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link_srv);
@@ -6458,7 +6458,7 @@ static struct dm_test_i2c_ctx *dm_test_i2c_setup(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, ctx->ddc);
ctx->dc_ctx = kunit_kzalloc(test, sizeof(*ctx->dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc_ctx);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link = kunit_kzalloc(test, sizeof(*ctx->link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link);
@@ -7382,7 +7382,7 @@ static struct dm_test_cvs_dc *dm_test_cvs_dc_alloc(struct kunit *test)
pool->timing_generators[0] = tg;
pool->timing_generator_count = 0;
- c->dc = kunit_kzalloc(test, sizeof(*c->dc), GFP_KERNEL);
+ c->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, c->dc);
dc_test_set_ctx(c->dc, dcc);
dc_test_set_res_pool(c->dc, pool);
@@ -8476,7 +8476,7 @@ dm_test_gm_ctx_alloc(struct kunit *test, int connector_type)
&ctx->aenc->base);
KUNIT_ASSERT_EQ(test, ret, 0);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link_srv = kunit_kzalloc(test, sizeof(*ctx->link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link_srv);
@@ -9072,7 +9072,7 @@ static struct dm_test_frl_ctx *dm_test_frl_ctx_alloc(struct kunit *test)
ctx->dm = kunit_kzalloc(test, sizeof(*ctx->dm), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->dm);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link_srv = kunit_kzalloc(test, sizeof(*ctx->link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link_srv);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
index 8d3123904548..d14912e1e095 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
@@ -121,7 +121,7 @@ static struct dm_test_crc_dc_fixture *dm_test_alloc_crc_dc_fixture(struct kunit
fixture->dm_state = kunit_kzalloc(test, sizeof(*fixture->dm_state), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, fixture->dm_state);
- fixture->dc = kunit_kzalloc(test, sizeof(*fixture->dc), GFP_KERNEL);
+ fixture->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, fixture->dc);
fixture->dc_ctx = kunit_kzalloc(test, sizeof(*fixture->dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, fixture->dc_ctx);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
index a3b9ee396e5c..b751c64d88aa 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
@@ -851,7 +851,7 @@ static void dm_test_handle_vrr_transition_round_trip(struct kunit *test)
vblank = drm_crtc_vblank_crtc(&acrtc->base);
adev->ddev.vblank[0].enabled = true;
adev->dm.adev = adev;
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
mutex_init(&adev->dm.dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
index 48e30f1936b5..65bffc57ea40 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
@@ -2550,7 +2550,7 @@ static void dm_test_dmub_aux_transfer_sync_hpd_connected(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_NOT_NULL(test, adev);
- ctx = dm_kunit_alloc_dc_with_ctx(test)->ctx;
+ ctx = dc_get_ctx(dm_kunit_alloc_dc_with_ctx(test));
link = dm_kunit_alloc_link(test);
ctx->driver_context = adev;
@@ -4454,7 +4454,7 @@ static struct dm_test_local_edid dm_test_setup_local_edid(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, fixture.ctx);
fixture.sink = kunit_kzalloc(test, sizeof(*fixture.sink), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, fixture.sink);
- fixture.dc = kunit_kzalloc(test, sizeof(*fixture.dc), GFP_KERNEL);
+ fixture.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, fixture.dc);
fixture.link = dm_kunit_alloc_link(test);
dc_edid = kunit_kzalloc(test, sizeof(*dc_edid), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
index 0d8fd26bb0ac..4be4d1487f11 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
@@ -87,7 +87,7 @@ static void dm_test_init_validate_dcc_inputs(struct amdgpu_device **adev,
struct kunit *test)
{
*adev = kunit_kzalloc(test, sizeof(**adev), GFP_KERNEL);
- *dc = kunit_kzalloc(test, sizeof(**dc), GFP_KERNEL);
+ *dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, *adev);
KUNIT_ASSERT_NOT_NULL(test, *dc);
diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
index 1b8e843020d6..f2acc582e130 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "dce_calcs.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dal_asic_id.h"
#include "calcs_logger.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 7a53b49dc4cd..91eb20833d81 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -43,6 +43,7 @@
#include "bios_parser_interface.h"
#include "bios_parser_common.h"
+#include "dc_priv.h"
#define DC_LOGGER \
bp->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index 5bca5e534277..00a4a62e8d3f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -39,6 +39,7 @@
#include "dc_dmub_srv.h"
#include "dc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
bp->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.c b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.c
index 8ac202487189..28eeef2f3a73 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.c
+++ b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.c
@@ -5,6 +5,7 @@
#include "dm_services.h"
#include "bls_builder/bls_builder_internal.h"
+#include "dc_priv.h"
const struct bls_builder *bls_builder_create(struct dc *dc,
enum bls_builder_name name)
diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c
index 589a950e078b..4622d3d76f25 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c
+++ b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c
@@ -13,6 +13,7 @@
#include "bls_builder/bls_builder_internal.h"
#include "bls_builder/dcn401_init_builder.h"
#include "bls_builder/dcn401_init_builder_legacy.h"
+#include "dc_priv.h"
static const enum block_sequence_func dcn401_dc2_init_sequence[] = {
LEGACY_CLK_MGR_INIT_CLOCKS,
diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder_legacy.c b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder_legacy.c
index e13c16920a0c..66f708ec709b 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder_legacy.c
+++ b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder_legacy.c
@@ -23,6 +23,7 @@
#include "dcn32/dcn32_resource.h"
#include "bls_builder/dcn401_init_builder.h"
#include "bls_builder/dcn401_init_builder_legacy.h"
+#include "dc_priv.h"
/*
* DC2_DC1_Wrapped: dcn401_init_hw as BLS entries, built one stage per
diff --git a/drivers/gpu/drm/amd/display/dc/bls_executor/bls_executor.c b/drivers/gpu/drm/amd/display/dc/bls_executor/bls_executor.c
index 7600954c3478..81ea2e294f10 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_executor/bls_executor.c
+++ b/drivers/gpu/drm/amd/display/dc/bls_executor/bls_executor.c
@@ -22,6 +22,7 @@
#include "hwss/hw_sequencer_private.h"
#include "bls_executor/bls_executor.h"
#include "dmub_messenger/dmub_messenger.h"
+#include "dc_priv.h"
static noinline_for_stack bool dc2_bls_step_supported(const struct dc2 *dc2,
const struct block_sequence *step)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 7f24433a42c1..4d187bd8d0ad 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -53,6 +53,7 @@
#include "dcn42/dcn42_clk_mgr.h"
#include "dcn42b/dcn42b_clk_mgr.h"
#include "dcn60/dcn60_clk_mgr.h"
+#include "dc_priv.h"
int clk_mgr_helper_get_active_display_cnt(
struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index d891b3bfe2a1..89858aafb6c7 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -42,6 +42,7 @@
*/
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
+#include "dc_priv.h"
#define REG(reg) \
(clk_mgr->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index d52789ba2613..4b3dc1a3b102 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -30,6 +30,7 @@
#include "dce/dce_11_0_sh_mask.h"
#include "dce110_clk_mgr.h"
#include "../clk_mgr/dce100/dce_clk_mgr.h"
+#include "dc_priv.h"
/* set register offset */
#define SR(reg_name)\
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 3da0c220d17f..14577c95d376 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -32,6 +32,7 @@
#include "dce110/dce110_clk_mgr.h"
#include "dce112_clk_mgr.h"
#include "dal_asic_id.h"
+#include "dc_priv.h"
/* set register offset */
#define SR(reg_name)\
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
index f8ef3a4710fc..4038dcbf7bfd 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
@@ -31,6 +31,7 @@
#include "dce120_clk_mgr.h"
#include "dce100/dce_clk_mgr.h"
#include "dce120/dce120_hwseq.h"
+#include "dc_priv.h"
/**
* dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c
index 172bba20a156..0a573753bf9f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c
@@ -6,6 +6,7 @@
#include "core_types.h"
#include "dal_asic_id.h"
#include "dcn10_clk_mgr.h"
+#include "dc_priv.h"
unsigned int dcn10_dentist_get_divider_from_did(unsigned int did)
{
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 9450b1733f60..a8100d895d61 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -29,6 +29,7 @@
#include "dcn10/dcn10_clk_mgr.h"
#include "rv1_clk_mgr_vbios_smu.h"
#include "rv1_clk_mgr_clk.h"
+#include "dc_priv.h"
static void rv1_init_clocks(struct clk_mgr *clk_mgr)
{
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
index d82a52319088..823748ee0fc0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
@@ -28,6 +28,7 @@
#include "reg_helper.h"
#include "rv1_clk_mgr_vbios_smu.h"
+#include "dc_priv.h"
#define MAX_INSTANCE 5
#define MAX_SEGMENT 5
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 86f3f32768e3..56e90db06a3d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -37,6 +37,7 @@
#include "dcn/dcn_2_0_0_sh_mask.h"
#include "clk/clk_11_0_0_offset.h"
#include "clk/clk_11_0_0_sh_mask.h"
+#include "dc_priv.h"
#undef FN
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
index 7ab548e41b40..a04e26720117 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
@@ -38,6 +38,7 @@
#include "dcn/dcn_2_0_1_sh_mask.h"
#include "clk/clk_11_0_1_offset.h"
#include "clk/clk_11_0_1_sh_mask.h"
+#include "dc_priv.h"
#define REG(reg) \
(clk_mgr->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 488ae92d24fa..b31fadd8a86f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -40,6 +40,7 @@
#include "clk/clk_10_0_2_offset.h"
#include "clk/clk_10_0_2_sh_mask.h"
#include "renoir_ip_offset.h"
+#include "dc_priv.h"
/* Constants */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 5a633333dbb5..722f149babe9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -44,6 +44,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 80bdaf762a23..f562c5c10ceb 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -44,6 +44,7 @@
#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"
#include "dcn30_smu11_driver_if.h"
+#include "dc_priv.h"
#undef FN
#define FN(reg_name, field_name) \
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index ace3ceb228c6..07d2d542b476 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -45,6 +45,7 @@
#include "vangogh_ip_offset.h"
#include "clk/clk_11_5_0_offset.h"
#include "clk/clk_11_5_0_sh_mask.h"
+#include "dc_priv.h"
/* Constants */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 938bc2bbe6d7..6a74fdd71b4c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -53,6 +53,7 @@
#include "yellow_carp_offset.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
clk_mgr->base.base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index f201628e4e98..e7af83af1a5c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -40,6 +40,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index 2aa3e8e66cb7..a62076820bb4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -53,6 +53,7 @@
#include "logger_types.h"
+#include "dc_priv.h"
#define MAX_INSTANCE 7
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
index c4af406146b7..c986abfe0531 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
@@ -56,6 +56,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 8ca367b72325..a78082876327 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -47,6 +47,7 @@
clk_mgr->base.base.ctx->logger
#include "link_service.h"
+#include "dc_priv.h"
#define TO_CLK_MGR_DCN315(clk_mgr)\
container_of(clk_mgr, struct clk_mgr_dcn315, base)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
index 478b4d6a3544..4997a45064fa 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
@@ -30,6 +30,7 @@
#include "dcn315_smu.h"
#include "mp/mp_13_0_5_offset.h"
#include "logger_types.h"
+#include "dc_priv.h"
#define MAX_INSTANCE 6
#define MAX_SEGMENT 6
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index 96bd653a9b71..efd83e7a52fb 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -40,6 +40,7 @@
#include "dm_helpers.h"
#include "dc_dmub_srv.h"
#include "link_service.h"
+#include "dc_priv.h"
// DCN316 this is CLK1 instance
#define MAX_INSTANCE 7
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
index 8b82092b91cd..fd748f347079 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
@@ -57,6 +57,7 @@ static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E0000
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 7abb13ffd9f4..0da332914e3b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -42,6 +42,7 @@
#include "dcn/dcn_3_2_0_sh_mask.h"
#include "dml/dcn32/dcn32_fpu.h"
+#include "dc_priv.h"
#define DCN_BASE__INST0_SEG1 0x000000C0
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 990c362623d8..a7d2076a827c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -46,6 +46,7 @@
#include "dc_dmub_srv.h"
#include "link_service.h"
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index 9d8f81c3d3f0..faae83f44551 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -56,6 +56,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 03aec7f4df7b..14af6a336329 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -22,6 +22,7 @@
#include "dcn/dcn_4_1_0_offset.h"
#include "dcn/dcn_4_1_0_sh_mask.h"
+#include "dc_priv.h"
#define DCN_BASE__INST0_SEG1 0x000000C0
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index 405145889ba2..2050c6a1ac1e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -35,6 +35,7 @@
#include "clk/clk_15_0_0_sh_mask.h"
#include "dcn/dcn_4_2_0_offset.h"
#include "dcn/dcn_4_2_0_sh_mask.h"
+#include "dc_priv.h"
#undef DC_LOGGER
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
index 5e8d979f25f0..c225d4000d6a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
@@ -38,6 +38,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
index 33f0099075c0..d577abdc6ea5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
@@ -36,6 +36,7 @@
#include "dcn/dcn_4_2_1_sh_mask.h"
#include <linux/power_supply.h>
+#include "dc_priv.h"
#define DCN_BASE__INST0_SEG0 0x00000012
#define DCN_BASE__INST0_SEG1 0x000000C0
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index efc02ba740f5..53b6c363f747 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
@@ -25,6 +25,7 @@
#include "dcn/dcn_6_0_0_offset.h"
#include "dcn/dcn_6_0_0_sh_mask.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 4c583d452446..23aced5d5eef 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -31,6 +31,7 @@
* mapping stays obvious and auditable.
*/
#include "dc.h"
+#include "dc_priv.h"
#include "dm_helpers.h" /* EXPORT_IF_KUNIT */
uint8_t dc_get_link_count(const struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index f3348e0cb1d6..bdc2792d5f88 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -30,6 +30,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_status.h"
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 694c425e22b4..9fa2b5a34d2b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -42,6 +42,7 @@
#include "dce/dmub_hw_lock_mgr.h"
#include "link_service.h"
#include "custom_float.h"
+#include "dc_priv.h"
static union dmub_inbox0_cmd_lock_hw hwss_build_dmub_lock_command(bool lock)
{
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index d2a5e0648fc2..47dc12952f10 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -25,6 +25,7 @@
#include "link_enc_cfg.h"
#include "resource.h"
#include "link_service.h"
+#include "dc_priv.h"
#define DC_LOGGER dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index d2f52e4839fe..50dc317eed71 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -35,6 +35,7 @@
*/
#include "link_service.h"
#include "dce/dce_i2c.h"
+#include "dc_priv.h"
struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
{
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 832286f0c0b1..d5d53491e91c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -78,6 +78,7 @@
#include "dcn321/dcn321_resource.h"
#include "dcn35/dcn35_resource.h"
#include "dcn351/dcn351_resource.h"
+#include "dc_priv.h"
#include "dcn36/dcn36_resource.h"
#include "dcn401/dcn401_resource.h"
#include "dcn42/dcn42_resource.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
index f976ffd6d466..1758c0b9390b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
@@ -25,6 +25,7 @@
#include "dc/dc_stat.h"
#include "dmub/dmub_srv_stat.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
/**
* DOC: DC STAT Interface
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index edb50c23ce24..88ee99bd4494 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -26,6 +26,7 @@
#include "core_types.h"
#include "core_status.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_state.h"
#include "dc_state_priv.h"
#include "dc_stream_priv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 56c7d97733a6..65f305b3c15d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -27,6 +27,7 @@
#include "dm_helpers.h"
#include "basics/dc_common.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "resource.h"
#include "ipp.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index 0b135a9e6c4f..139a934cbf3d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -26,6 +26,7 @@
/* DC interface (public) */
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
/* DC core (private) */
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_test.c b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
index 60fb45f9cfaa..04c799ae33d3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_test.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
@@ -32,6 +32,7 @@
#include <linux/export.h>
#include "dc.h"
+#include "dc_priv.h"
#include "dc_test.h"
struct dc *dc_test_create(void)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
index 3743555133f6..cc0d5ceace5f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
@@ -25,6 +25,7 @@
#include "vm_helper.h"
#include "dc.h"
+#include "dc_priv.h"
void vm_helper_mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uint8_t hubp_idx)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 082435846ee9..d976425c190b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -857,43 +857,6 @@ struct dc_bw_validation_profile {
unsigned long long skip_fail_count;
};
-#define BW_VAL_TRACE_SETUP() \
- unsigned long long end_tick = 0; \
- unsigned long long voltage_level_tick = 0; \
- unsigned long long watermark_tick = 0; \
- unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
- dm_get_timestamp(dc->ctx) : 0
-
-#define BW_VAL_TRACE_COUNT() \
- if (dc->debug.bw_val_profile.enable) \
- dc->debug.bw_val_profile.total_count++
-
-#define BW_VAL_TRACE_SKIP(status) \
- if (dc->debug.bw_val_profile.enable) { \
- if (!voltage_level_tick) \
- voltage_level_tick = dm_get_timestamp(dc->ctx); \
- dc->debug.bw_val_profile.skip_ ## status ## _count++; \
- }
-
-#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
- if (dc->debug.bw_val_profile.enable) \
- voltage_level_tick = dm_get_timestamp(dc->ctx)
-
-#define BW_VAL_TRACE_END_WATERMARKS() \
- if (dc->debug.bw_val_profile.enable) \
- watermark_tick = dm_get_timestamp(dc->ctx)
-
-#define BW_VAL_TRACE_FINISH() \
- if (dc->debug.bw_val_profile.enable) { \
- end_tick = dm_get_timestamp(dc->ctx); \
- dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
- dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
- if (watermark_tick) { \
- dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
- dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
- } \
- }
-
union mem_low_power_enable_options {
struct {
bool vga: 1;
@@ -2020,100 +1983,6 @@ struct dc_scratch_space {
enum backlight_control_type backlight_control_type;
};
-struct dc {
- struct dc_debug_options debug;
- struct dc_versions versions;
- struct dc_caps caps;
- struct dc_check_config check_config;
- struct dc_cap_funcs cap_funcs;
- struct dc_config config;
- struct dc_bounding_box_overrides bb_overrides;
- struct dc_bug_wa work_arounds;
- struct dc_context *ctx;
- struct dc_phy_addr_space_config vm_pa_config;
-
- uint8_t link_count;
- struct dc_link *links[MAX_LINKS];
- uint8_t lowest_dpia_link_index;
- struct link_service *link_srv;
-
- struct dc_state *current_state;
- /**
- * @scratch_dc_context: Pre-allocated states for the no-allocation update
- * path, created only when dc_config.preallocate_scratch_state is set.
- * Two are kept because the commit path installs the new context as
- * @current_state, so a single buffer would alias it and self-copy.
- */
- struct dc_state *scratch_dc_context[2];
- struct resource_pool *res_pool;
-
- /**
- * @update_scratch_pool: Per-commit scratch buffers for dc_update_state.
- */
- struct dc_memory_pool *update_scratch_pool; // MAX_STREAMS + 1
-
- struct clk_mgr *clk_mgr;
-
- /* Display Engine Clock levels */
- struct dm_pp_clock_levels sclk_lvls;
-
- /* Inputs into BW and WM calculations. */
- struct bw_calcs_dceip *bw_dceip;
- struct bw_calcs_vbios *bw_vbios;
- struct dcn_soc_bounding_box *dcn_soc;
- struct dcn_ip_params *dcn_ip;
- struct display_mode_lib dml;
-
- /* HW functions */
- struct hw_sequencer_funcs hwss;
- struct dce_hwseq *hwseq;
-
- /* Require to optimize clocks and bandwidth for added/removed planes */
- bool optimized_required;
- bool idle_optimizations_allowed;
- bool enable_c20_dtm_b0;
-
- /* Require to maintain clocks and bandwidth for UEFI enabled HW */
-
- /* For eDP to know the switching state of SmartMux */
- bool is_switch_in_progress_orig;
- bool is_switch_in_progress_dest;
-
- /* FBC compressor */
- struct compressor *fbc_compressor;
-
- struct dc_debug_data debug_data;
- struct dpcd_vendor_signature vendor_signature;
-
- const char *build_id;
- struct vm_helper *vm_helper;
-
- uint32_t *dcn_reg_offsets;
- uint32_t *nbio_reg_offsets;
- uint32_t *clk_reg_offsets;
-
- /* Scratch memory */
- struct {
- struct {
- /*
- * For matching clock_limits table in driver with table
- * from PMFW.
- */
- struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
- } update_bw_bounding_box;
- struct dc_scratch_space current_state;
- struct dc_scratch_space new_state;
- struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack
- struct dc_link temp_link;
- bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */
- } scratch;
-
- struct dml2_configuration_options dml2_options;
- struct dml2_configuration_options dml2_dc_power_options;
- enum dc_acpi_cm_power_state power_state;
- struct soc_and_ip_translator *soc_and_ip_translator;
-};
-
struct dc_scaling_info {
struct rect src_rect;
struct rect dst_rect;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
index b972ae06663d..7802a18b8caa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
@@ -6,6 +6,7 @@
#pragma once
#include "dc.h"
+#include "dc_priv.h"
#include "inc/dc_core_interface.h"
#include "bls_builder/dmub_abi.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 323e8bec23dc..cde3a6a21de3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_dmub_srv.h"
#include "../dmub/dmub_srv.h"
#include "dm_helpers.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dc_priv.h b/drivers/gpu/drm/amd/display/dc/dc_priv.h
new file mode 100644
index 000000000000..70e4eee9bf0f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dc_priv.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __DC_PRIV_H__
+#define __DC_PRIV_H__
+
+/* FILE POLICY AND INTENDED USAGE:
+ * This header defines struct dc, the DC core state. It is private to the dc
+ * directory and must never be included from DM, DAL modules or any other
+ * code outside DC. Public DC interfaces are declared in dc.h; use the
+ * accessors implemented in dc/core/dc_accessors.c instead of reaching into
+ * struct dc.
+ */
+
+#include "dc.h"
+
+/* Bandwidth validation trace macros. Usable only from DC-internal code
+ * because they dereference the dc-local variable of the including function.
+ */
+#define BW_VAL_TRACE_SETUP() \
+ unsigned long long end_tick = 0; \
+ unsigned long long voltage_level_tick = 0; \
+ unsigned long long watermark_tick = 0; \
+ unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
+ dm_get_timestamp(dc->ctx) : 0
+
+#define BW_VAL_TRACE_COUNT() \
+ do { \
+ if (dc->debug.bw_val_profile.enable) \
+ dc->debug.bw_val_profile.total_count++; \
+ } while (0)
+
+#define BW_VAL_TRACE_SKIP(status) \
+ do { \
+ if (dc->debug.bw_val_profile.enable) { \
+ if (!voltage_level_tick) \
+ voltage_level_tick = dm_get_timestamp(dc->ctx); \
+ dc->debug.bw_val_profile.skip_ ## status ## _count++; \
+ } \
+ } while (0)
+
+#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
+ do { \
+ if (dc->debug.bw_val_profile.enable) \
+ voltage_level_tick = dm_get_timestamp(dc->ctx); \
+ } while (0)
+
+#define BW_VAL_TRACE_END_WATERMARKS() \
+ do { \
+ if (dc->debug.bw_val_profile.enable) \
+ watermark_tick = dm_get_timestamp(dc->ctx); \
+ } while (0)
+
+#define BW_VAL_TRACE_FINISH() \
+ do { \
+ if (dc->debug.bw_val_profile.enable) { \
+ end_tick = dm_get_timestamp(dc->ctx); \
+ dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
+ dc->debug.bw_val_profile.voltage_level_ticks += \
+ voltage_level_tick - start_tick; \
+ if (watermark_tick) { \
+ dc->debug.bw_val_profile.watermark_ticks += \
+ watermark_tick - voltage_level_tick; \
+ dc->debug.bw_val_profile.rq_dlg_ticks += \
+ end_tick - watermark_tick; \
+ } \
+ } \
+ } while (0)
+
+struct dc {
+ struct dc_debug_options debug;
+ struct dc_versions versions;
+ struct dc_caps caps;
+ struct dc_check_config check_config;
+ struct dc_cap_funcs cap_funcs;
+ struct dc_config config;
+ struct dc_bounding_box_overrides bb_overrides;
+ struct dc_bug_wa work_arounds;
+ struct dc_context *ctx;
+ struct dc_phy_addr_space_config vm_pa_config;
+
+ uint8_t link_count;
+ struct dc_link *links[MAX_LINKS];
+ uint8_t lowest_dpia_link_index;
+ struct link_service *link_srv;
+
+ struct dc_state *current_state;
+ /**
+ * @scratch_dc_context: Pre-allocated states for the no-allocation update
+ * path, created only when dc_config.preallocate_scratch_state is set.
+ * Two are kept because the commit path installs the new context as
+ * @current_state, so a single buffer would alias it and self-copy.
+ */
+ struct dc_state *scratch_dc_context[2];
+ struct resource_pool *res_pool;
+
+ /**
+ * @update_scratch_pool: Per-commit scratch buffers for dc_update_state.
+ */
+ struct dc_memory_pool *update_scratch_pool; // MAX_STREAMS + 1
+
+ struct clk_mgr *clk_mgr;
+
+ /* Display Engine Clock levels */
+ struct dm_pp_clock_levels sclk_lvls;
+
+ /* Inputs into BW and WM calculations. */
+ struct bw_calcs_dceip *bw_dceip;
+ struct bw_calcs_vbios *bw_vbios;
+ struct dcn_soc_bounding_box *dcn_soc;
+ struct dcn_ip_params *dcn_ip;
+ struct display_mode_lib dml;
+
+ /* HW functions */
+ struct hw_sequencer_funcs hwss;
+ struct dce_hwseq *hwseq;
+
+ /* Require to optimize clocks and bandwidth for added/removed planes */
+ bool optimized_required;
+ bool idle_optimizations_allowed;
+ bool enable_c20_dtm_b0;
+
+ /* Require to maintain clocks and bandwidth for UEFI enabled HW */
+
+ /* For eDP to know the switching state of SmartMux */
+ bool is_switch_in_progress_orig;
+ bool is_switch_in_progress_dest;
+
+ /* FBC compressor */
+ struct compressor *fbc_compressor;
+
+ struct dc_debug_data debug_data;
+ struct dpcd_vendor_signature vendor_signature;
+
+ const char *build_id;
+ struct vm_helper *vm_helper;
+
+ uint32_t *dcn_reg_offsets;
+ uint32_t *nbio_reg_offsets;
+ uint32_t *clk_reg_offsets;
+
+ /* Scratch memory */
+ struct {
+ struct {
+ /*
+ * For matching clock_limits table in driver with table
+ * from PMFW.
+ */
+ struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
+ } update_bw_bounding_box;
+ struct dc_scratch_space current_state;
+ struct dc_scratch_space new_state;
+ /* Used so we don't need to allocate stream on the stack */
+ struct dc_stream_state temp_stream;
+ struct dc_link temp_link;
+ /* Any of the pipes indicated here should be unlocked first */
+ bool pipes_to_unlock_first[MAX_PIPES];
+ } scratch;
+
+ struct dml2_configuration_options dml2_options;
+ struct dml2_configuration_options dml2_dc_power_options;
+ enum dc_acpi_cm_power_state power_state;
+ struct soc_and_ip_translator *soc_and_ip_translator;
+};
+#endif /* __DC_PRIV_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
index 00e121bb8ef7..124deb723064 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
@@ -6,6 +6,7 @@
#include "dcn20/dcn20_dpp.h"
#include "dcn32/dcn32_dpp.h"
#include "dcn401/dcn401_dpp.h"
+#include "dc_priv.h"
static struct spl_callbacks dcn2_spl_callbacks = {
.spl_calc_lb_num_partitions = dscl2_spl_calc_lb_num_partitions,
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
index 341509ad6f35..e6ac961c11fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
@@ -28,6 +28,7 @@
#include "dcn31_dccg.h"
#include "dcn20/dcn20_dccg.h"
#include "dal_asic_id.h"
+#include "dc_priv.h"
#define TO_DCN_DCCG(dccg)\
container_of(dccg, struct dcn_dccg, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
index 7bfe7be2bc1f..4fc1f27e9300 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
@@ -30,6 +30,7 @@
#include "dcn31/dcn31_dccg.h"
#include "dcn314_dccg.h"
#include "dcn20/dcn20_dccg.h"
+#include "dc_priv.h"
#define TO_DCN_DCCG(dccg)\
container_of(dccg, struct dcn_dccg, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 6dce2a4beca2..a4d05b5a8487 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -41,6 +41,7 @@
#define CTX \
dccg_dcn->base.ctx
#include "logger_types.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dccg->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
index a4ece209d600..c827708e8613 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
@@ -28,6 +28,7 @@
#include "dcn401_dccg.h"
#include "dcn31/dcn31_dccg.h"
#include "dcn20/dcn20_dccg.h"
+#include "dc_priv.h"
/*
#include "dmub_common.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
index b7b84152d623..e4758d48ae12 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
@@ -7,6 +7,7 @@
#include "dcn35/dcn35_dccg.h"
#include "dcn42_dccg.h"
#include "dcn20/dcn20_dccg.h"
+#include "dc_priv.h"
#define TO_DCN_DCCG(dccg)\
container_of(dccg, struct dcn_dccg, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 4abf51c8ab52..0e367433b3d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -46,6 +46,7 @@
#define LOG_FLAG_I2cAux_DceAux LOG_I2C_AUX
#include "reg_helper.h"
+#include "dc_priv.h"
#undef FN
#define FN(reg_name, field_name) \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 145c993342bd..01a78cc38139 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -38,6 +38,7 @@
#include "dccg.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg)\
(clk_src->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 23de1c793ec3..8de051b1c4f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "fixed31_32.h"
#include "dc.h"
+#include "dc_priv.h"
#define TO_DCE_DMCU(dmcu)\
container_of(dmcu, struct dce_dmcu, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
index f5261e8d7678..79c355db22ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
@@ -24,6 +24,7 @@
*/
#include "dce_i2c.h"
#include "reg_helper.h"
+#include "dc_priv.h"
bool dce_i2c_oem_device_present(
struct resource_pool *pool,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 05892ab4529f..3b4aefc0007e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -27,6 +27,7 @@
#include "dce_i2c_hw.h"
#include "reg_helper.h"
#include "include/gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
dce_i2c_hw->ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index c6a20378121b..5819c508d872 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -36,6 +36,7 @@
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#include "dce/dce_11_0_enum.h"
+#include "dc_priv.h"
#ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 168c2d0a5eaa..fe17832f98b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -26,6 +26,7 @@
#include "dce_mem_input.h"
#include "reg_helper.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define CTX \
dce_mi->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 83f819890020..1c5fcd3c99fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -28,6 +28,7 @@
#include "opp.h"
#include "basics/conversion.h"
#include "dc.h"
+#include "dc_priv.h"
#define REG(reg) \
(xfm_dce->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 8cca8599b917..da4de4141e96 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -27,6 +27,7 @@
#include "dmub_abm_lcd.h"
#include "dmub_abm_cacp.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dmub_cmd.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c
index 9f58fa2e25fd..9b8077726b17 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c
@@ -4,6 +4,7 @@
#include "dmub_abm_cacp.h"
#include "dce_abm.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
index f60e43ba6060..d0107e87b421 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
@@ -27,6 +27,7 @@
#include "dmub_abm_lcd.h"
#include "dce_abm.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index f5ff61a2e89e..f9a265ff8317 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
@@ -27,6 +27,7 @@
#include "dc_dmub_srv.h"
#include "dc_types.h"
#include "core_types.h"
+#include "dc_priv.h"
static bool dmub_hw_lock_has_inbox0_lock(const struct dc *dc)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 66d8ba73d38b..64b862a0e358 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -25,6 +25,7 @@
#include "dmub_psr.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index 365c428eae72..e7a7c4d50e01 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -3,6 +3,7 @@
// Copyright 2024 Advanced Micro Devices, Inc.
#include "dc.h"
+#include "dc_priv.h"
#include "link_service.h"
#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 095869912c09..277c9e169a1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -33,6 +33,7 @@
#include "dce/dce_mem_input.h"
#include "dce110_mem_input_v.h"
+#include "dc_priv.h"
static void set_flip_control(
struct dce_mem_input *mem_input110,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
index 6be18665b1f7..97562423b43b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -26,6 +26,7 @@
#include "dce110_transform_v.h"
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index 395bccdd0f1d..ca5803fd2d29 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -45,6 +45,7 @@
#include "dcn10_cm_common.h"
#include "clk_mgr.h"
#include "dsc.h"
+#include "dc_priv.h"
__printf(3, 4)
unsigned int snprintf_count(char *pbuf, unsigned int bufsize, const char *fmt, ...)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
index 9459e8f28338..2e6f398a68c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
@@ -32,6 +32,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
index fcaa3884d705..dda8af8aecfa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
@@ -34,6 +34,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
index d380a8ec2184..37b608ee7ca9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
@@ -29,6 +29,7 @@
#include "dcn31_afmt.h"
#include "reg_helper.h"
#include "dc/dc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
afmt31->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
index d7c3f26777e3..6943e6df9173 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
@@ -29,6 +29,7 @@
#include "dc_dmub_srv.h"
#include "dcn31_panel_cntl.h"
#include "atom.h"
+#include "dc_priv.h"
#define TO_DCN31_PANEL_CNTL(panel_cntl)\
container_of(panel_cntl, struct dcn31_panel_cntl, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
index cfb923d85630..a453cc24d82a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
@@ -28,6 +28,7 @@
#include "dcn31_vpg.h"
#include "reg_helper.h"
#include "dc/dc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
vpg31->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
index 32e12d894e31..85d6b7f15e15 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
@@ -32,6 +32,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
index c937788d0763..de3df77c36a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
@@ -31,6 +31,7 @@
#include "link_service.h"
#include "dpcd_defs.h"
#include "dcn30/dcn30_afmt.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
index dbd4c534c5c3..1596b53d62a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
@@ -32,6 +32,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
index ac6ca7771d2f..052a5d3a65a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
@@ -31,6 +31,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
index 5fd5158482ea..adbde44e18a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
@@ -31,6 +31,7 @@
#include "stream_encoder.h"
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
index 9757d3bcdf32..b516f2d9d09b 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
@@ -29,6 +29,7 @@
#include "reg_helper.h"
#include "hw_shared.h"
#include "dc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
index 7106669eab5b..79afaae47791 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
@@ -31,6 +31,7 @@
#include "stream_encoder.h"
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
index 1b9ba0e9f068..39b97f960da1 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
@@ -38,6 +38,7 @@
#include "dc_dmub_srv.h"
#include "dal_asic_id.h"
#include "link_service.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
index 482c52c1d7d6..036704e21dac 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
@@ -32,6 +32,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
index 63990c47ac14..24af37eded70 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
@@ -36,6 +36,7 @@
#include "dc_dmub_srv.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
index 3dd8fe423232..ca7615dfb11b 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
@@ -31,6 +31,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
index 67d6050d5163..c09932c3fd2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
@@ -33,6 +33,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
index 9375c9b939be..25b1e02f1874 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
@@ -29,6 +29,7 @@
#include "dcn31/dcn31_dio_link_encoder.h"
#include "dcn35_dio_link_encoder.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
index dabcb45840a7..38eac36b8304 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
@@ -31,6 +31,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
index 6594fbb3fa43..fb9a0c43f599 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
@@ -35,6 +35,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
index 4616b6f76aeb..e962c544610e 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
@@ -34,6 +34,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c
index 3b11be9991c3..6c64df545aa0 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c
@@ -8,6 +8,7 @@
#include "link_encoder.h"
#include "dcn35/dcn35_dio_link_encoder.h"
#include "dcn42_dio_link_encoder.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
index b7671d41ea24..fe8774845186 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
@@ -14,6 +14,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_link_encoder.c
index f65326a0f6d2..78af49f0e316 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_link_encoder.c
@@ -15,6 +15,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_stream_encoder.c
index b645914c1c71..5df2b7202917 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_stream_encoder.c
@@ -13,6 +13,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
index 2ad4a2635683..59c93dc3fe63 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calcs.h"
#include "dcn_calc_auto.h"
#include "dal_asic_id.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
index ae6b2d47f379..a7fdc0b0a7e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
@@ -28,6 +28,7 @@
#include "dcn10_fpu.h"
#include "resource.h"
+#include "dc_priv.h"
/**
* DOC: DCN10 FPU manipulation Overview
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 38c79239004c..458832a2d2df 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -33,6 +33,7 @@
#include "link_service.h"
#include "dcn20_fpu.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index b8e5985f9307..ac5fcaf96c10 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -34,6 +34,7 @@
#include "dcn30_fpu.h"
#include "../dml1_frl_cap_chk.h"
+#include "dc_priv.h"
#define REG(reg)\
optc1->tg_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index c4b73acd7140..2849ddd42e39 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -30,6 +30,7 @@
#include "dml/dcn20/dcn20_fpu.h"
#include "dcn301_fpu.h"
+#include "dc_priv.h"
#define TO_DCN301_RES_POOL(pool)\
container_of(pool, struct dcn301_resource_pool, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
index 781bc429807f..6b5ab8940a73 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
@@ -30,6 +30,7 @@
#include "dml/dcn20/dcn20_fpu.h"
#include "dcn302_fpu.h"
+#include "dc_priv.h"
struct _vcs_dpi_ip_params_st dcn3_02_ip = {
.use_min_dcfclk = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
index e6d7d67f06a4..61b2d8e3b7c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
@@ -29,6 +29,7 @@
#include "dml/dcn20/dcn20_fpu.h"
#include "dcn303_fpu.h"
+#include "dc_priv.h"
struct _vcs_dpi_ip_params_st dcn3_03_ip = {
.use_min_dcfclk = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index f9b2da6b2bb8..9289d5ccf5f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -31,6 +31,7 @@
#include "dml/dcn20/dcn20_fpu.h"
#include "dcn31_fpu.h"
+#include "dc_priv.h"
/**
* DOC: DCN31x FPU manipulation Overview
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
index 1854137d5b9e..bc320383ad56 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
@@ -32,6 +32,7 @@
#include "dml/dcn31/dcn31_fpu.h"
#include "dml/display_mode_vba.h"
#include "dml/dml_inline_defs.h"
+#include "dc_priv.h"
struct _vcs_dpi_ip_params_st dcn3_14_ip = {
.VBlankNomDefaultUS = 668,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index b5bd1358fdfd..f15fe3a76ddb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -33,6 +33,7 @@
#include "dcn30/dcn30_resource.h"
#include "link_service.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index f4d826e0d13a..e96d05f9e8c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -30,6 +30,7 @@
#include "dcn32/dcn32_resource.h"
#include "dcn321/dcn321_resource.h"
#include "dml/dcn32/display_mode_vba_util_32.h"
+#include "dc_priv.h"
#define DCN3_2_DEFAULT_DET_SIZE 256
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index c15fbc18bfdf..d03f82ad2108 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -32,6 +32,7 @@
#include "dml/dml_inline_defs.h"
#include "link_service.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
index 0c5a2667d526..762d37c500e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
@@ -11,6 +11,7 @@
#include "dml/dml_inline_defs.h"
#include "link_service.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
index 6a9f822b2b33..d96373c33b31 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
@@ -9,6 +9,7 @@
#include "dml21_utils.h"
#include "dml21_translation_helper.h"
#include "soc_and_ip_translator.h"
+#include "dc_priv.h"
static void dml21_populate_pmo_options(struct dml2_pmo_options *pmo_options,
const struct dc *in_dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_utils.c
index 0aecfa8b909f..62283f36d275 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_utils.c
@@ -10,6 +10,7 @@
#include "dml2_dc_resource_mgmt.h"
#include "dml2_core_dcn4_calcs.h"
+#include "dc_priv.h"
int dml21_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c
index a1525f7e0e61..6e34bfd9b239 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c
@@ -13,6 +13,7 @@
#include "dml2_wrapper_fpu.h"
#include "dml21_wrapper.h"
#include "dml21_wrapper_fpu.h"
+#include "dc_priv.h"
#define INVALID -1
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_dc_resource_mgmt.c
index 4050b0a47caf..ac23b494e9a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_dc_resource_mgmt.c
@@ -30,6 +30,7 @@
#include "dml2_internal_types.h"
#include "dml2_utils.h"
#include "dml2_dc_resource_mgmt.h"
+#include "dc_priv.h"
#define MAX_ODM_FACTOR 4
#define MAX_MPCC_FACTOR 4
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c
index edc4dcdde952..ec443cef57fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c
@@ -29,6 +29,7 @@
#include "dml2_internal_types.h"
#include "dml2_utils.h"
#include "dml2_mall_phantom.h"
+#include "dc_priv.h"
unsigned int dml2_helper_calculate_num_ways_for_subvp(struct dml2_context *ctx, struct dc_state *context)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_translation_helper.c
index a0130bbfc12a..e6960f1df77b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_translation_helper.c
@@ -27,6 +27,7 @@
#include "display_mode_core.h"
#include "dml2_internal_types.h"
#include "dml2_translation_helper.h"
+#include "dc_priv.h"
#define NUM_DCFCLK_STAS 5
#define NUM_DCFCLK_STAS_NEW 8
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_utils.c
index 8688792aa956..a74d6777bbe2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_utils.c
@@ -30,6 +30,7 @@
#include "dml2_internal_types.h"
#include "dml2_translation_helper.h"
#include "dml2_utils.h"
+#include "dc_priv.h"
void dml2_util_copy_dml_timing(struct dml_timing_cfg_st *dml_timing_array, unsigned int dst_index, unsigned int src_index)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c
index 2fe3c4643f58..133bc9e3bfb0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c
@@ -12,6 +12,7 @@
#include "dml21_wrapper/dml21_wrapper_fpu.h"
#include "dc_fpu.h"
+#include "dc_priv.h"
#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED)
#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c
index 8a31986bc299..1055764381c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c
@@ -35,6 +35,7 @@
#include "dml2_wrapper_fpu.h"
#include "dml21_wrapper/dml21_wrapper.h"
#include "dml21_wrapper/dml21_wrapper_fpu.h"
+#include "dc_priv.h"
void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
index de420cdf1514..cc893bbafc27 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dcn10/dcn10_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define NUM_PHASES 64
#define HORZ_MAX_TAPS 8
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
index b9adf8433b36..75c8842a4946 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dcn10/dcn10_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define NUM_PHASES 64
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
index 74cc176d9437..e3e31e561b18 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
@@ -32,6 +32,7 @@
#include "basics/conversion.h"
#include "dcn10/dcn10_cm_common.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
index a2079db62f63..1d2fab6f2081 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dcn201/dcn201_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
index 3db10019fa84..1ca5518255de 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
@@ -29,6 +29,7 @@
#include "dcn30/dcn30_dpp.h"
#include "basics/conversion.h"
#include "dcn30/dcn30_cm_common.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
index 86f47d33ec64..1756f0b504f0 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
@@ -31,6 +31,7 @@
#include "dcn30/dcn30_dpp.h"
#include "basics/conversion.h"
#include "dcn30/dcn30_cm_common.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
index adb3f155d051..9c2f50331056 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dcn401/dcn401_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define NUM_PHASES 64
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c
index de0d89ac3f8b..62126d5cc86b 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c
@@ -4,6 +4,7 @@
#include "dcn60/dcn60_dpp.h"
#include "dcn30/dcn30_cm_common.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define REG(reg) \
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c
index d1a81e5616b3..b37a538df6ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c
@@ -9,6 +9,7 @@
#include "reg_helper.h"
#include "dcn60/dcn60_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 56db43d1b072..63f069cb0300 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -27,6 +27,7 @@
#include "dc_hw_types.h"
#include "dsc.h"
#include "dc.h"
+#include "dc_priv.h"
#include "rc_calc.h"
#include "fixed31_32.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
index f3413d743107..b2cc2ab39838 100644
--- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
@@ -31,6 +31,7 @@
#include "link_service.h"
#include "link_hwss.h"
#include "link/protocols/link_dpcd.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
index 56e753d2f43d..7ac238c97d69 100644
--- a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
@@ -29,6 +29,7 @@
#include "dcn30_hpo_frl_link_encoder.h"
#include "reg_helper.h"
#include "dcn10/dcn10_link_encoder.h"
+#include "dc_priv.h"
#define DC_LOGGER enc3->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
index 4e33648f74bb..f7acc0d75167 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
@@ -27,6 +27,7 @@
#include "dcn10/dcn10_hubp.h"
#include "dcn10_hubbub.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define CTX \
hubbub1->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
index e5b55fe502ca..3cbde1b9e7f0 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
@@ -27,6 +27,7 @@
#include "dcn20_hubbub.h"
#include "reg_helper.h"
#include "clk_mgr.h"
+#include "dc_priv.h"
#define REG(reg)\
hubbub1->regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
index e6b527cd2047..a76a1dc9b797 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
@@ -26,6 +26,7 @@
#include "dcn20/dcn20_hubbub.h"
#include "dcn201_hubbub.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg)\
hubbub1->regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
index 881e91e9385d..afbee30245be 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
@@ -27,6 +27,7 @@
#include "dcn20/dcn20_hubbub.h"
#include "dcn21_hubbub.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg)\
hubbub1->regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
index 582d647da812..67325f1efeb3 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "reg_helper.h"
#include "dcn30_hubbub.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
index 786843362061..7965d3dc5df6 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
@@ -28,6 +28,7 @@
#include "dcn31_hubbub.h"
#include "dm_services.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
index dd9bc1f08b56..1353650cc650 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
@@ -29,6 +29,7 @@
#include "dm_services.h"
#include "reg_helper.h"
#include "dal_asic_id.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
index ad333cd3241b..b36640a6c1a5 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
@@ -32,6 +32,7 @@
#include "dm_services.h"
#include "reg_helper.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
index 957e8f5a6475..3adf0b16633d 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
@@ -28,6 +28,7 @@
#include "dcn401_hubbub.h"
#include "dm_services.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c
index 244f3f2824ed..fc417e33f467 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c
@@ -10,6 +10,7 @@
#include "dcn42/dcn42_hubbub.h"
#include "dm_services.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define DCN42_CRB_SEGMENT_SIZE_KB 64
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c
index 07282b78972a..3598b20ba1a4 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c
@@ -6,6 +6,7 @@
#include "dm_services.h"
#include "reg_helper.h"
#include "fixed31_32.h"
+#include "dc_priv.h"
#define CTX \
hubbub2->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
index c667db319baf..ef88d15c9db3 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
index c879f4901c7d..45ee7421cd38 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
@@ -26,6 +26,7 @@
#include "dcn35_hubp.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg)\
hubp2->hubp_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
index 0c8a23cef1e0..5dfc261bf0cb 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
@@ -5,6 +5,7 @@
#include "dcn401/dcn401_hubp.h"
#include "dcn42_hubp.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg) \
hubp2->hubp_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
index 0f44577572fb..9842778f2758 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
@@ -27,6 +27,7 @@
#include "reg_helper.h"
#include "hw_sequencer_private.h"
#include "core_types.h"
+#include "dc_priv.h"
#define CTX \
hws->ctx
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
index 0d7e28260db1..afcc74da11a5 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
@@ -24,6 +24,7 @@
*/
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "clk_mgr.h"
#include "dce100_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index a08ceaeda91c..6bbf5e89d4c5 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_bios_types.h"
#include "core_types.h"
#include "core_status.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
index ed9b0113a7a0..87f9bfb321cd 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dce112_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
index fbe34d1bb39a..3b728a590237 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dce120_hwseq.h"
#include "dce/dce_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
index b73a10b0acbd..58c539a908f1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dce60_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
index f44f41b13007..c56ff93be7e2 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dce80_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index f1d14b97977f..939f5e4948da 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -59,6 +59,7 @@
#include "dce/dmub_outbox.h"
#include "link_service.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
index bc3ac96de688..442830726b38 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
@@ -28,6 +28,7 @@
#include "dcn10/dcn10_hwseq.h"
#include "dcn20/dcn20_hwseq.h"
#include "dc/hwss/dce/dce_hwseq.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 636cbd947918..90a05af35782 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -57,6 +57,7 @@
#include "link_hwss.h"
#include "link_service.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
index 789bde439192..5b07f4fea9e0 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
@@ -28,6 +28,7 @@
#include "dcn20/dcn20_hwseq.h"
#include "dcn20_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn20_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
index d34f63432c6b..0aa8259297c8 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
@@ -41,6 +41,7 @@
#include "reg_helper.h"
#include "dcn10/dcn10_hubbub.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
index 33c22d9bbd2e..5323c2baf811 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
@@ -29,6 +29,7 @@
#include "dcn20/dcn20_hwseq.h"
#include "dcn201/dcn201_hwseq.h"
#include "dcn201_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn201_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
index 2be68f8dd0fc..19c6b31d7425 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
@@ -37,6 +37,7 @@
#include "dc_dmub_srv.h"
#include "abm.h"
#include "link_service.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
index 39bf0e51ec7c..f5378a40f936 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
@@ -29,6 +29,7 @@
#include "dcn21/dcn21_hwseq.h"
#include "dcn21_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn21_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 35d5cce0a791..2119710c37cf 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -54,6 +54,7 @@
#include "link_service.h"
#include "dc_state_priv.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define TO_DCN_DCCG(dccg)\
container_of(dccg, struct dcn_dccg, base)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
index ce42b8216f3b..4ec42a030dde 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
@@ -30,6 +30,7 @@
#include "dcn30/dcn30_hwseq.h"
#include "dcn30_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn30_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
index 5ed4305e4663..f36136a36bbb 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
@@ -31,6 +31,7 @@
#include "dcn301/dcn301_hwseq.h"
#include "dcn301_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn301_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
index 0a6d58dd8f6d..c2e0ab1e6831 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
@@ -29,6 +29,7 @@
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c
index 637f9514d37b..9b6f273ced8a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c
@@ -28,6 +28,7 @@
#include "dcn30/dcn30_init.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn302_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c
index edb4d68b8187..77e77a990d12 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c
@@ -26,6 +26,7 @@
#include "dcn303/dcn303_hwseq.h"
#include "dcn30/dcn30_init.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn303_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index b6f3c0480ab6..f5b96c86ca59 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -55,6 +55,7 @@
#include "dce/dmub_abm_lcd.h"
#include "dio/dcn10/dcn10_dio.h"
#include "dce/dmub_abm_cacp.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
index c7055312cc3d..8a0912d7caa8 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
@@ -32,6 +32,7 @@
#include "dcn31/dcn31_hwseq.h"
#include "dcn31_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn31_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index de7dde2b036b..d57f5be5c57f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -54,6 +54,7 @@
#include "dsc.h"
#include "dcn20/dcn20_optc.h"
#include "dcn30/dcn30_cm_common.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
index 69b020e2c4b2..0eefe089b281 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
@@ -34,6 +34,7 @@
#include "dcn314/dcn314_hwseq.h"
#include "dcn314_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn314_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 9135b01fe388..369d77f6d8f6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -53,6 +53,7 @@
#include "../dcn20/dcn20_hwseq.h"
#include "dc_state_priv.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index b755df909871..7c95e1f928c1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -33,6 +33,7 @@
#include "dcn401/dcn401_hwseq.h"
#include "dml/dcn32/dcn32_fpu.h"
#include "dcn32_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn32_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index aa047b5b4939..cd904a28fa12 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -60,6 +60,7 @@
#include "dcn31/dcn31_hwseq.h"
#include "dcn20/dcn20_hwseq.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index 2119a8e000e9..d16e58427132 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -36,6 +36,7 @@
#include "dcn35/dcn35_hwseq.h"
#include "dcn35_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn35_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
index 8720e47fb33a..5ffae3764894 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
@@ -28,6 +28,7 @@
#include "resource.h"
#include "dcn351_hwseq.h"
#include "dcn35/dcn35_hwseq.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger) \
struct dal_logger *dc_logger = logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index 0e148c6e5c50..a3c6219ff942 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -35,6 +35,7 @@
#include "dcn351/dcn351_hwseq.h"
#include "dcn351_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn351_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 508749496826..bd31d6c2af48 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -41,6 +41,7 @@
#include "../hw_sequencer.h"
#include "dio/dcn10/dcn10_dio.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index 1e79b4945801..8bffcfe2b7b7 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -12,6 +12,7 @@
#include "dcn35/dcn35_hwseq.h"
#include "dcn401/dcn401_hwseq.h"
#include "dcn401_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn401_funcs = {
.program_gamut_remap = dcn401_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
index b1cc09df5e63..9e01cb85c010 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
@@ -36,6 +36,7 @@
#include "dcn35/dcn35_hwseq.h"
#include "dcn42/dcn42_hwseq.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define DC_LOGGER \
ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
index 00fcb2559247..80ba74138cab 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
@@ -14,6 +14,7 @@
#include "dcn401/dcn401_hwseq.h"
#include "dcn42/dcn42_hwseq.h"
#include "dcn42_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn42_funcs = {
.program_gamut_remap = dcn401_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
index 167f2e53e1f4..027cdd63913f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
@@ -16,6 +16,7 @@
#include "opp.h"
#include "mpc.h"
#include "dcn42b_hwseq.h"
+#include "dc_priv.h"
#define CTX \
hws->ctx
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c
index 4210dc7a8eb4..209ae0dbc445 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c
@@ -8,6 +8,7 @@
#include "dcn42/dcn42_init.h"
#include "dcn42b_hwseq.h"
#include "dcn42b_init.h"
+#include "dc_priv.h"
void dcn42b_hw_sequencer_init_functions(struct dc *dc)
{
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c
index 151ec838f613..7d9597ebf4f6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c
@@ -36,6 +36,7 @@
#include "dc_state_priv.h"
#include "link_enc_cfg.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
index f8254dfe1ce7..b3b4135c8af7 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
@@ -39,6 +39,7 @@
#include "dc_state_priv.h"
#include "link_enc_cfg.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c
index 9fde7d1be3e5..cf205f2c574c 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c
@@ -15,6 +15,7 @@
#include "dcn50/dcn50_hwseq.h"
#include "dcn60_init.h"
#include "dcn60_hwseq.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn60_funcs = {
.program_gamut_remap = dcn401_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index 7f3084c6dd49..129a59dc171b 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -35,6 +35,7 @@
#include "ivsrcid/ivsrcid_vislands30.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#define DC_LOGGER \
irq_service->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index 83f676a49fd1..b2637ec27cd4 100644
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -35,6 +35,7 @@
#include "dc_dmub_srv.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "clk_mgr.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
index c8c55f196f8d..3a517e174b08 100644
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
@@ -24,6 +24,7 @@
*/
#include "link_dp_trace.h"
#include "link/protocols/link_dpcd.h"
+#include "dc_priv.h"
void dp_trace_init(struct dc_link *link)
{
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
index befa67b2b2ae..bbbce6cb80b9 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
@@ -25,6 +25,7 @@
#include "link_hwss_dio.h"
#include "core_types.h"
#include "link_enc_cfg.h"
+#include "dc_priv.h"
/**
* DOC: overview
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
index e1dff4e3f446..846890a87826 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
@@ -25,6 +25,7 @@
#include "link_hwss_dio.h"
#include "link_hwss_dio_fixed_vs_pe_retimer.h"
#include "link_enc_cfg.h"
+#include "dc_priv.h"
uint8_t dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg(struct dc_link *link)
{
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
index 2a87b23582f3..8cede496ab4d 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
@@ -26,6 +26,7 @@
#include "core_types.h"
#include "link_hwss_dio.h"
#include "link_enc_cfg.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
index 811048123401..cfff0029472c 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
@@ -27,6 +27,7 @@
#include "core_types.h"
#include "dccg.h"
#include "clk_mgr.h"
+#include "dc_priv.h"
#define DC_LOGGER link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
index 6d5b7450b205..4b706db98253 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
@@ -25,6 +25,7 @@
#include "link_hwss_hpo_dp.h"
#include "link_hwss_hpo_fixed_vs_pe_retimer_dp.h"
#include "link_hwss_dio_fixed_vs_pe_retimer.h"
+#include "dc_priv.h"
static void dp_hpo_fixed_vs_pe_retimer_set_tx_ffe(struct dc_link *link,
const struct dc_lane_settings *hw_lane_settings)
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c
index 62288133cd55..2ba3958d31b0 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c
@@ -25,6 +25,7 @@
#include "link_hwss_hpo_frl.h"
#include "core_types.h"
#include "link/hwss/link_hwss_virtual.h"
+#include "dc_priv.h"
static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx)
{
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index b4546f93af0c..5f7b82b39239 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -48,6 +48,7 @@
#include "link_enc_cfg.h"
#include "dm_helpers.h"
#include "clk_mgr.h"
+#include "dc_priv.h"
// Offset DPCD 050Eh == 0x5A
#define MST_HUB_ID_0x5A 0x5A
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 75e232ebffe8..2aff967e73b9 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -58,6 +58,7 @@
#include "clk_mgr.h"
#include "atomfirmware.h"
#include "vpg.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 3b192c539f8b..93eec8a35dda 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -46,6 +46,7 @@
#include "protocols/link_hpd.h"
#include "gpio_service_interface.h"
#include "atomfirmware.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_resource.c b/drivers/gpu/drm/amd/display/dc/link/link_resource.c
index bd42bb273c0c..47659537bc68 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_resource.c
@@ -28,6 +28,7 @@
#include "link_resource.h"
#include "protocols/link_dp_capability.h"
+#include "dc_priv.h"
void link_get_cur_link_res(const struct dc_link *link,
struct link_resource *link_res)
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index d7bd352880b3..ab8a8c6807fe 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -33,6 +33,7 @@
#include "protocols/link_dp_dpia_bw.h"
#include "protocols/link_hdmi_frl.h"
#include "resource.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
index db798656c8a8..15ff2c7d34de 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
@@ -38,6 +38,7 @@
#include "link_dpcd.h"
#include "dm_helpers.h"
#include "atomfirmware.h"
+#include "dc_priv.h"
#define DC_LOGGER \
ddc_service->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index c487c5b87dfd..c3f840b1a0ce 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -50,6 +50,7 @@
#include "link_enc_cfg.h"
#include "dc_dmub_srv.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
index f43fc4b78a8d..f5c4e815c404 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
@@ -29,6 +29,7 @@
#include "link_dp_dpia_bw.h"
#include "link_dpcd.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
index da679fb7d89c..a4c533ec638b 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
@@ -39,6 +39,7 @@
#include "link/link_dpms.h"
#include "dm_helpers.h"
#include "link_dp_dpia_bw.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
index 65a791ccf6b2..4b7b104bd3a8 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
@@ -30,6 +30,7 @@
#include "dm_helpers.h"
#include "dc/dc_dmub_srv.h"
#include "dce/dmub_replay.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
index 49521ac4b0e8..a3d923aff89c 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
@@ -38,6 +38,7 @@
#include "resource.h"
#include "link_enc_cfg.h"
#include "atomfirmware.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index 3be36d1063de..2a0137759ef5 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -47,6 +47,7 @@
#include "link_enc_cfg.h"
#include "resource.h"
#include "dm_helpers.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
index 1a6bfc45927d..13b1ff756949 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
@@ -32,6 +32,7 @@
#include "link_dpcd.h"
#include "link_dp_phy.h"
#include "link_dp_capability.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
index 4331e032416f..e4c258434775 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
@@ -31,6 +31,7 @@
#include "link_dpcd.h"
#include "link_dp_phy.h"
#include "link_dp_capability.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
index 34fa76d97b83..f1817c7f0948 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
@@ -28,6 +28,7 @@
*/
#include "link_dp_training_dpia.h"
#include "dc.h"
+#include "dc_priv.h"
#include "inc/core_status.h"
#include "dpcd_defs.h"
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
index 6a7c4a59ff4c..08904bc2b500 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
@@ -37,6 +37,7 @@
#include "link_dp_phy.h"
#include "link_dp_capability.h"
#include "link_ddc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 0e9b2b675eac..f88fccf007c0 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -41,6 +41,7 @@
#include "abm.h"
#include "resource.h"
#include "link_dp_panel_replay.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
index 960f18fe275b..7887d134eb28 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
@@ -42,6 +42,7 @@
#include "dccg.h"
#include "dml/dml1_frl_cap_chk.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_logger
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
index 905d4f23f92a..b637cdd3e6af 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
@@ -27,6 +27,7 @@
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "mem_input.h"
#include "dcn10/dcn10_cm_common.h"
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
index f3213ecb1745..b0af7f219bd2 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
@@ -29,6 +29,7 @@
#include "basics/conversion.h"
#include "dcn10/dcn10_cm_common.h"
#include "dc.h"
+#include "dc_priv.h"
#define REG(reg)\
mpc30->mpc_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
index 61a1e3f06575..d8b8b8cd1bfc 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
@@ -30,6 +30,7 @@
#include "basics/conversion.h"
#include "dcn10/dcn10_cm_common.h"
#include "dc.h"
+#include "dc_priv.h"
#define REG(reg)\
mpc30->mpc_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
index a485db71c166..2e2412d05a06 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
@@ -25,6 +25,7 @@
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn401_mpc.h"
#include "dcn10/dcn10_cm_common.h"
#include "basics/conversion.h"
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c
index 89c4d431a82c..de380c9caecf 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c
@@ -3,6 +3,7 @@
// Copyright 2025 Advanced Micro Devices, Inc.
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn60_mpc.h"
#include "dcn10/dcn10_cm_common.h"
#include "basics/conversion.h"
diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
index 98335a53ca52..7f0bd2cb6272 100644
--- a/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "dcn10_opp.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg) \
(oppn10->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
index 544ff2bf7100..89ad9096d356 100644
--- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "dcn20_opp.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg) \
(oppn20->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
index 90ec4cb8a9dd..8f345733105a 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
@@ -26,6 +26,7 @@
#include "reg_helper.h"
#include "dcn30_optc.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
index f9e05efcad98..447f37918527 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
@@ -29,6 +29,7 @@
#include "dcn31/dcn31_optc.h"
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
index 406446e5eae5..4e4f6f8b641f 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
@@ -31,6 +31,7 @@
#include "dcn32/dcn32_optc.h"
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
index 5fcdd74eb4a0..7ffb3a82cec5 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
@@ -8,6 +8,7 @@
#include "dcn32/dcn32_optc.h"
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
index 1e4f2051d732..7422c8602b0e 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
@@ -10,6 +10,7 @@
#include "dcn401/dcn401_optc.h"
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
#include "dc_trace.h"
diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
index 6e5ea1bbca02..15d09b11a573 100644
--- a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
@@ -28,6 +28,7 @@
#include "core_types.h"
#include "dcn35_pg_cntl.h"
#include "dccg.h"
+#include "dc_priv.h"
#define TO_DCN_PG_CNTL(pg_cntl)\
container_of(pg_cntl, struct dcn_pg_cntl, base)
diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
index e9125d2467fc..21a12a704611 100644
--- a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
@@ -7,6 +7,7 @@
#include "dcn42_pg_cntl.h"
#include "dccg.h"
#include "resource.h"
+#include "dc_priv.h"
#define TO_DCN_PG_CNTL(pg_cntl)\
container_of(pg_cntl, struct dcn_pg_cntl, base)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
index 97ea22af5d2b..1cd90a68d774 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
@@ -62,6 +62,7 @@
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_8_2_d.h"
#include "gmc/gmc_8_2_sh_mask.h"
+#include "dc_priv.h"
#endif
#ifndef mmDP_DPHY_INTERNAL_CTRL
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
index 19252b25bce0..5f8365ffdf9c 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
@@ -66,6 +66,7 @@
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_8_2_d.h"
#include "gmc/gmc_8_2_sh_mask.h"
+#include "dc_priv.h"
#endif
#ifndef mmDP_DPHY_INTERNAL_CTRL
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
index 2da5d44e5203..dc73bd5528a2 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
@@ -58,6 +58,7 @@
#include "dce100/dce100_resource.h"
#include "dce112_resource.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
index 38d3b87529b0..21a7e176b92e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
@@ -68,6 +68,7 @@
#include "dce100/dce100_resource.h"
#include "link_service.h"
+#include "dc_priv.h"
#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
index 65c7dae3ff66..b8b1eda7ef46 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
@@ -66,6 +66,7 @@
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_6_0_d.h"
#include "gmc/gmc_6_0_sh_mask.h"
+#include "dc_priv.h"
#endif
#ifndef mmDP_DPHY_INTERNAL_CTRL
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
index 2f4de697ec4b..3d7162f82986 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
@@ -64,6 +64,7 @@
#endif
#include "dce80/dce80_resource.h"
+#include "dc_priv.h"
#ifndef mmDP_DPHY_INTERNAL_CTRL
#define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
index 37974c45b44a..47f6eeebb6f9 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
@@ -26,6 +26,7 @@
#include "core_status.h"
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn10/dcn10_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index 996fce26941f..979523c92074 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn20/dcn20_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
index 765c63513a31..f53467f1fe96 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn201/dcn201_init.h"
#include "dml/dcn20/dcn20_fpu.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
index 4095a850ebc6..5f82d6823857 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
@@ -28,6 +28,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn21/dcn21_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
index aecbcd28c2d9..88dc17b1e4d1 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn30/dcn30_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
index 29113f518c53..0008c8a2867b 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn301/dcn301_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
index f67b3e00bd86..ca47e743f5bb 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
@@ -78,6 +78,7 @@
#include "dpcs/dpcs_3_0_0_sh_mask.h"
#include "nbio/nbio_7_4_offset.h"
#include "amdgpu_socbb.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
index 9e1bf34cca2a..df7fbd6180f0 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
@@ -77,6 +77,7 @@
#include "nbio/nbio_2_3_offset.h"
#include "dml/dcn303/dcn303_fpu.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index 6359fbb574df..8fa3935df077 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
index 0ddfceca69dd..f6ef9e50110e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
#include "dcn314/dcn314_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
index a1894be8cbb2..c34017e92242 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
index 4a2d56a196b4..66b02193551d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 619b9b3362fc..49c77d2c0fa1 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -27,6 +27,7 @@
#include "dc_types.h"
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
index 602a0e4e5dc0..9401709009e4 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
@@ -30,6 +30,7 @@
#include "dml/dcn32/dcn32_fpu.h"
#include "dc_state_priv.h"
#include "dc_stream_priv.h"
+#include "dc_priv.h"
static bool is_dual_plane(enum surface_pixel_format format)
{
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index 4097093d9012..5f5203324e5f 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 940dd00e97fa..a0bcba089b49 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
#include "dcn35/dcn35_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index df2aaa46e70c..e8332badd11e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -4,6 +4,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
#include "dcn351/dcn351_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
index e8580f844af9..d517dbbd9558 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
@@ -3,6 +3,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
#include "dcn35/dcn35_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index b78b0541d113..ea7010f18ca0 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -4,6 +4,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
#include "dcn401/dcn401_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index 2ad191ec5c38..0214b6cc09a4 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -4,6 +4,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
#include "dcn42/dcn42_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
index 33b9775420d3..49fdd35454b8 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
@@ -5,6 +5,7 @@
#include "dc.h"
+#include "dc_priv.h"
#include "dcn42_resource_fpu.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
index e111e7532383..177d575f7fc1 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
@@ -6,6 +6,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
#include "dcn42/dcn42_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn60/dcn60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn60/dcn60_resource.c
index fbaf4e2d31d1..2f09dfb6418c 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn60/dcn60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn60/dcn60_resource.c
@@ -5,6 +5,7 @@
#include "dm_services.h"
#include "dm_helpers.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
#include "dcn401/dcn401_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c b/drivers/gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c
index 952f0ade24a5..74fd0008ba62 100644
--- a/drivers/gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c
+++ b/drivers/gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c
@@ -25,6 +25,7 @@
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn42_rmcm.h"
#include "dcn10/dcn10_cm_common.h"
#include "basics/conversion.h"
diff --git a/drivers/gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c b/drivers/gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c
index df4d6476d70a..5d7eb93a92d9 100644
--- a/drivers/gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c
+++ b/drivers/gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "reg_helper.h"
#include "dcn/dcn_6_0_0_offset.h"
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
index c3dfcf2a73e3..17516048a616 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
@@ -4,6 +4,7 @@
#include "dcn401_soc_and_ip_translator.h"
#include "bounding_boxes/dcn4_soc_bb.h"
+#include "dc_priv.h"
/* soc_and_ip_translator component used to get up-to-date values for bounding box.
* Bounding box values are stored in several locations and locations can vary with DCN revision.
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
index c6c1b19b7370..ba9a686ffda7 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
@@ -5,6 +5,7 @@
#include "dcn42_soc_and_ip_translator.h"
#include "../dcn401/dcn401_soc_and_ip_translator.h"
#include "bounding_boxes/dcn42_soc_bb.h"
+#include "dc_priv.h"
/* soc_and_ip_translator component used to get up-to-date values for bounding box.
* Bounding box values are stored in several locations and locations can vary with DCN revision.
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c
index aef527c7584b..6af8a70188fe 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c
@@ -6,6 +6,7 @@
#include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h"
#include "bounding_boxes/dcn6_soc_bb.h"
#include "dal_asic_id.h"
+#include "dc_priv.h"
/* soc_and_ip_translator component used to get up-to-date values for bounding box.
* Bounding box values are stored in several locations and locations can vary with DCN revision.
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 13/19] drm/amd/display: Move struct dc out of the public dc.h
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
struct dc is now defined in the new dc/dc_priv.h, which must only be
included from inside the dc directory. dc.h keeps the public API and
public types and forward-declares struct dc; consumers outside DC hold
opaque pointers and go through the accessor layer.
Also move the BW_VAL_TRACE_* macros, which dereference a dc-local
variable, from dc.h into dc_priv.h.
Update DC-internal includes accordingly (~300 files gain an include of
dc_priv.h next to their existing dc.h include or at the end of their
include block). With this, code outside the dc directory can no
longer compile against struct dc members: the compiler enforces the
boundary.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../display/amdgpu_dm/tests/amdgpu_dm_audio_test.c | 6 +-
.../display/amdgpu_dm/tests/amdgpu_dm_color_test.c | 4 +-
.../amdgpu_dm/tests/amdgpu_dm_connector_test.c | 12 +-
.../display/amdgpu_dm/tests/amdgpu_dm_crc_test.c | 2 +-
.../amdgpu_dm/tests/amdgpu_dm_freesync_test.c | 2 +-
.../amdgpu_dm/tests/amdgpu_dm_helpers_test.c | 4 +-
.../display/amdgpu_dm/tests/amdgpu_dm_plane_test.c | 2 +-
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c | 1 +
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 +
.../gpu/drm/amd/display/dc/bios/command_table2.c | 1 +
.../drm/amd/display/dc/bls_builder/bls_builder.c | 1 +
.../display/dc/bls_builder/dcn401_init_builder.c | 1 +
.../dc/bls_builder/dcn401_init_builder_legacy.c | 1 +
.../drm/amd/display/dc/bls_executor/bls_executor.c | 1 +
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 1 +
.../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 1 +
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 1 +
.../drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c | 1 +
.../amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c | 1 +
.../amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 1 +
.../gpu/drm/amd/display/dc/core/dc_link_exports.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_state.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_test.c | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 1 +
drivers/gpu/drm/amd/display/dc/dc.h | 131 ---------------
.../drm/amd/display/dc/dc_api_dispatch/api_shim.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 1 +
drivers/gpu/drm/amd/display/dc/dc_priv.h | 186 +++++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 1 +
.../gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c | 1 +
.../drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c | 1 +
.../gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 1 +
.../drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c | 1 +
.../gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 1 +
.../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 1 +
.../gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 1 +
.../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 1 +
.../drm/amd/display/dc/dce110/dce110_transform_v.c | 1 +
.../display/dc/dcn10/dcn10_hw_sequencer_debug.c | 1 +
.../amd/display/dc/dcn201/dcn201_link_encoder.c | 1 +
.../drm/amd/display/dc/dcn21/dcn21_link_encoder.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c | 1 +
.../drm/amd/display/dc/dcn31/dcn31_panel_cntl.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c | 1 +
.../amd/display/dc/dio/dcn10/dcn10_link_encoder.c | 1 +
.../display/dc/dio/dcn10/dcn10_stream_encoder.c | 1 +
.../amd/display/dc/dio/dcn20/dcn20_link_encoder.c | 1 +
.../display/dc/dio/dcn20/dcn20_stream_encoder.c | 1 +
.../display/dc/dio/dcn30/dcn30_dio_link_encoder.c | 1 +
.../dc/dio/dcn30/dcn30_dio_stream_encoder.c | 1 +
.../dc/dio/dcn301/dcn301_dio_link_encoder.c | 1 +
.../display/dc/dio/dcn31/dcn31_dio_link_encoder.c | 1 +
.../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 1 +
.../display/dc/dio/dcn32/dcn32_dio_link_encoder.c | 1 +
.../dc/dio/dcn32/dcn32_dio_stream_encoder.c | 1 +
.../dc/dio/dcn321/dcn321_dio_link_encoder.c | 1 +
.../display/dc/dio/dcn35/dcn35_dio_link_encoder.c | 1 +
.../dc/dio/dcn35/dcn35_dio_stream_encoder.c | 1 +
.../dc/dio/dcn401/dcn401_dio_link_encoder.c | 1 +
.../dc/dio/dcn401/dcn401_dio_stream_encoder.c | 1 +
.../display/dc/dio/dcn42/dcn42_dio_link_encoder.c | 1 +
.../dc/dio/dcn42/dcn42_dio_stream_encoder.c | 1 +
.../display/dc/dio/dcn60/dcn60_dio_link_encoder.c | 1 +
.../dc/dio/dcn60/dcn60_dio_stream_encoder.c | 1 +
.../gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c | 1 +
.../dml21_wrapper/dml21_translation_helper.c | 1 +
.../dc/dml2_wrapper/dml21_wrapper/dml21_utils.c | 1 +
.../dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c | 1 +
.../dc/dml2_wrapper/dml2_dc_resource_mgmt.c | 1 +
.../display/dc/dml2_wrapper/dml2_mall_phantom.c | 1 +
.../dc/dml2_wrapper/dml2_translation_helper.c | 1 +
.../drm/amd/display/dc/dml2_wrapper/dml2_utils.c | 1 +
.../drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c | 1 +
.../amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c | 1 +
.../gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c | 1 +
.../drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c | 1 +
.../drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c | 1 +
.../gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c | 1 +
.../gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 1 +
.../drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c | 1 +
.../amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 1 +
.../drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c | 1 +
.../drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c | 1 +
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 1 +
drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 1 +
.../dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c | 1 +
.../drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c | 1 +
.../amd/display/dc/hubbub/dcn201/dcn201_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c | 1 +
.../amd/display/dc/hubbub/dcn401/dcn401_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c | 1 +
.../drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c | 1 +
.../gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c | 1 +
.../gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c | 1 +
.../gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce100/dce100_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce112/dce112_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce120/dce120_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce60/dce60_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dce80/dce80_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn201/dcn201_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn301/dcn301_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn302/dcn302_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn303/dcn303_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn314/dcn314_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn401/dcn401_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c | 1 +
.../drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c | 1 +
.../drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c | 1 +
.../gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c | 1 +
.../amd/display/dc/irq/dce110/irq_service_dce110.c | 1 +
.../amd/display/dc/link/accessories/link_dp_cts.c | 1 +
.../display/dc/link/accessories/link_dp_trace.c | 1 +
.../drm/amd/display/dc/link/hwss/link_hwss_dio.c | 1 +
.../link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c | 1 +
.../drm/amd/display/dc/link/hwss/link_hwss_dpia.c | 1 +
.../amd/display/dc/link/hwss/link_hwss_hpo_dp.c | 1 +
.../hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 1 +
.../amd/display/dc/link/hwss/link_hwss_hpo_frl.c | 1 +
.../gpu/drm/amd/display/dc/link/link_detection.c | 1 +
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 1 +
drivers/gpu/drm/amd/display/dc/link/link_factory.c | 1 +
.../gpu/drm/amd/display/dc/link/link_resource.c | 1 +
.../gpu/drm/amd/display/dc/link/link_validation.c | 1 +
.../drm/amd/display/dc/link/protocols/link_ddc.c | 1 +
.../display/dc/link/protocols/link_dp_capability.c | 1 +
.../display/dc/link/protocols/link_dp_dpia_bw.c | 1 +
.../dc/link/protocols/link_dp_irq_handler.c | 1 +
.../dc/link/protocols/link_dp_panel_replay.c | 1 +
.../amd/display/dc/link/protocols/link_dp_phy.c | 1 +
.../display/dc/link/protocols/link_dp_training.c | 1 +
.../dc/link/protocols/link_dp_training_128b_132b.c | 1 +
.../dc/link/protocols/link_dp_training_8b_10b.c | 1 +
.../dc/link/protocols/link_dp_training_dpia.c | 1 +
.../link_dp_training_fixed_vs_pe_retimer.c | 1 +
.../dc/link/protocols/link_edp_panel_control.c | 1 +
.../amd/display/dc/link/protocols/link_hdmi_frl.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c | 1 +
.../gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c | 1 +
.../gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c | 1 +
.../gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 1 +
.../drm/amd/display/dc/optc/dcn401/dcn401_optc.c | 1 +
.../gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c | 1 +
.../drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c | 1 +
.../drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c | 1 +
.../display/dc/resource/dce100/dce100_resource.c | 1 +
.../display/dc/resource/dce110/dce110_resource.c | 1 +
.../display/dc/resource/dce112/dce112_resource.c | 1 +
.../display/dc/resource/dce120/dce120_resource.c | 1 +
.../amd/display/dc/resource/dce60/dce60_resource.c | 1 +
.../amd/display/dc/resource/dce80/dce80_resource.c | 1 +
.../amd/display/dc/resource/dcn10/dcn10_resource.c | 1 +
.../amd/display/dc/resource/dcn20/dcn20_resource.c | 1 +
.../display/dc/resource/dcn201/dcn201_resource.c | 1 +
.../amd/display/dc/resource/dcn21/dcn21_resource.c | 1 +
.../amd/display/dc/resource/dcn30/dcn30_resource.c | 1 +
.../display/dc/resource/dcn301/dcn301_resource.c | 1 +
.../display/dc/resource/dcn302/dcn302_resource.c | 1 +
.../display/dc/resource/dcn303/dcn303_resource.c | 1 +
.../amd/display/dc/resource/dcn31/dcn31_resource.c | 1 +
.../display/dc/resource/dcn314/dcn314_resource.c | 1 +
.../display/dc/resource/dcn315/dcn315_resource.c | 1 +
.../display/dc/resource/dcn316/dcn316_resource.c | 1 +
.../amd/display/dc/resource/dcn32/dcn32_resource.c | 1 +
.../dc/resource/dcn32/dcn32_resource_helpers.c | 1 +
.../display/dc/resource/dcn321/dcn321_resource.c | 1 +
.../amd/display/dc/resource/dcn35/dcn35_resource.c | 1 +
.../display/dc/resource/dcn351/dcn351_resource.c | 1 +
.../amd/display/dc/resource/dcn36/dcn36_resource.c | 1 +
.../display/dc/resource/dcn401/dcn401_resource.c | 1 +
.../amd/display/dc/resource/dcn42/dcn42_resource.c | 1 +
.../display/dc/resource/dcn42/dcn42_resource_fpu.c | 1 +
.../display/dc/resource/dcn42b/dcn42b_resource.c | 1 +
.../amd/display/dc/resource/dcn60/dcn60_resource.c | 1 +
.../gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c | 1 +
.../gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c | 1 +
.../dcn401/dcn401_soc_and_ip_translator.c | 1 +
.../dcn42/dcn42_soc_and_ip_translator.c | 1 +
.../dcn60/dcn60_soc_and_ip_translator.c | 1 +
271 files changed, 464 insertions(+), 147 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
index 6d8651047ff7..c2ed369f3ca2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
@@ -809,7 +809,7 @@ static void dm_test_commit_audio_notifies_added_connector(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dm_crtc_state);
KUNIT_ASSERT_NOT_NULL(test, stream);
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
sizeof(*dc_get_current_state(adev->dm.dc)),
@@ -967,7 +967,7 @@ static void dm_test_commit_audio_skips_without_stream_status(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dm_crtc_state);
KUNIT_ASSERT_NOT_NULL(test, stream);
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
sizeof(*dc_get_current_state(adev->dm.dc)),
@@ -1172,7 +1172,7 @@ static void dm_test_commit_audio_skips_writeback_addition(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, dm_crtc_state);
KUNIT_ASSERT_NOT_NULL(test, stream);
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
dc_test_set_current_state(adev->dm.dc, kunit_kzalloc(test,
sizeof(*dc_get_current_state(adev->dm.dc)),
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
index 56a47809f302..28570f8a82ca 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_color_test.c
@@ -1758,7 +1758,7 @@ dm_test_verify_lut3d_alloc_adev(struct kunit *test, bool has_3dlut)
{
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
dc_test_caps(adev->dm.dc)->color.dpp.hw_3d_lut = has_3dlut;
@@ -2060,7 +2060,7 @@ dm_test_color_update_setup(struct kunit *test)
struct dm_test_color_update_fixture f = {0};
f.adev = dm_kunit_alloc_adev(test);
- f.adev->dm.dc = kunit_kzalloc(test, sizeof(*f.adev->dm.dc), GFP_KERNEL);
+ f.adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, f.adev->dm.dc);
f.state = kunit_kzalloc(test, sizeof(*f.state), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
index 204dc86266a3..94bb2181d141 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
@@ -3041,7 +3041,7 @@ static struct dm_test_fbc_ctx *dm_test_fbc_ctx_alloc(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, ctx->adev);
ctx->aconnector = kunit_kzalloc(test, sizeof(*ctx->aconnector), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->aconnector);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link = kunit_kzalloc(test, sizeof(*ctx->link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link);
@@ -5073,7 +5073,7 @@ static struct dm_test_poll_ctx *dm_test_poll_ctx_alloc(struct kunit *test)
DRM_MODE_CONNECTOR_VGA, NULL), 0);
mutex_init(&ctx->aconnector->hpd_lock);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link_srv = kunit_kzalloc(test, sizeof(*ctx->link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link_srv);
@@ -6458,7 +6458,7 @@ static struct dm_test_i2c_ctx *dm_test_i2c_setup(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, ctx->ddc);
ctx->dc_ctx = kunit_kzalloc(test, sizeof(*ctx->dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc_ctx);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link = kunit_kzalloc(test, sizeof(*ctx->link), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link);
@@ -7382,7 +7382,7 @@ static struct dm_test_cvs_dc *dm_test_cvs_dc_alloc(struct kunit *test)
pool->timing_generators[0] = tg;
pool->timing_generator_count = 0;
- c->dc = kunit_kzalloc(test, sizeof(*c->dc), GFP_KERNEL);
+ c->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, c->dc);
dc_test_set_ctx(c->dc, dcc);
dc_test_set_res_pool(c->dc, pool);
@@ -8476,7 +8476,7 @@ dm_test_gm_ctx_alloc(struct kunit *test, int connector_type)
&ctx->aenc->base);
KUNIT_ASSERT_EQ(test, ret, 0);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link_srv = kunit_kzalloc(test, sizeof(*ctx->link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link_srv);
@@ -9072,7 +9072,7 @@ static struct dm_test_frl_ctx *dm_test_frl_ctx_alloc(struct kunit *test)
ctx->dm = kunit_kzalloc(test, sizeof(*ctx->dm), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->dm);
- ctx->dc = kunit_kzalloc(test, sizeof(*ctx->dc), GFP_KERNEL);
+ ctx->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, ctx->dc);
ctx->link_srv = kunit_kzalloc(test, sizeof(*ctx->link_srv), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, ctx->link_srv);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
index 8d3123904548..d14912e1e095 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crc_test.c
@@ -121,7 +121,7 @@ static struct dm_test_crc_dc_fixture *dm_test_alloc_crc_dc_fixture(struct kunit
fixture->dm_state = kunit_kzalloc(test, sizeof(*fixture->dm_state), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, fixture->dm_state);
- fixture->dc = kunit_kzalloc(test, sizeof(*fixture->dc), GFP_KERNEL);
+ fixture->dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, fixture->dc);
fixture->dc_ctx = kunit_kzalloc(test, sizeof(*fixture->dc_ctx), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, fixture->dc_ctx);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
index a3b9ee396e5c..b751c64d88aa 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
@@ -851,7 +851,7 @@ static void dm_test_handle_vrr_transition_round_trip(struct kunit *test)
vblank = drm_crtc_vblank_crtc(&acrtc->base);
adev->ddev.vblank[0].enabled = true;
adev->dm.adev = adev;
- adev->dm.dc = kunit_kzalloc(test, sizeof(*adev->dm.dc), GFP_KERNEL);
+ adev->dm.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, adev->dm.dc);
mutex_init(&adev->dm.dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
index 48e30f1936b5..65bffc57ea40 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
@@ -2550,7 +2550,7 @@ static void dm_test_dmub_aux_transfer_sync_hpd_connected(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_NOT_NULL(test, adev);
- ctx = dm_kunit_alloc_dc_with_ctx(test)->ctx;
+ ctx = dc_get_ctx(dm_kunit_alloc_dc_with_ctx(test));
link = dm_kunit_alloc_link(test);
ctx->driver_context = adev;
@@ -4454,7 +4454,7 @@ static struct dm_test_local_edid dm_test_setup_local_edid(struct kunit *test)
KUNIT_ASSERT_NOT_NULL(test, fixture.ctx);
fixture.sink = kunit_kzalloc(test, sizeof(*fixture.sink), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, fixture.sink);
- fixture.dc = kunit_kzalloc(test, sizeof(*fixture.dc), GFP_KERNEL);
+ fixture.dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, fixture.dc);
fixture.link = dm_kunit_alloc_link(test);
dc_edid = kunit_kzalloc(test, sizeof(*dc_edid), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
index 0d8fd26bb0ac..4be4d1487f11 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c
@@ -87,7 +87,7 @@ static void dm_test_init_validate_dcc_inputs(struct amdgpu_device **adev,
struct kunit *test)
{
*adev = kunit_kzalloc(test, sizeof(**adev), GFP_KERNEL);
- *dc = kunit_kzalloc(test, sizeof(**dc), GFP_KERNEL);
+ *dc = dm_kunit_alloc_dc(test);
KUNIT_ASSERT_NOT_NULL(test, *adev);
KUNIT_ASSERT_NOT_NULL(test, *dc);
diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
index 1b8e843020d6..f2acc582e130 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "dce_calcs.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dal_asic_id.h"
#include "calcs_logger.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 7a53b49dc4cd..91eb20833d81 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -43,6 +43,7 @@
#include "bios_parser_interface.h"
#include "bios_parser_common.h"
+#include "dc_priv.h"
#define DC_LOGGER \
bp->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index 5bca5e534277..00a4a62e8d3f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -39,6 +39,7 @@
#include "dc_dmub_srv.h"
#include "dc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
bp->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.c b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.c
index 8ac202487189..28eeef2f3a73 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.c
+++ b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.c
@@ -5,6 +5,7 @@
#include "dm_services.h"
#include "bls_builder/bls_builder_internal.h"
+#include "dc_priv.h"
const struct bls_builder *bls_builder_create(struct dc *dc,
enum bls_builder_name name)
diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c
index 589a950e078b..4622d3d76f25 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c
+++ b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c
@@ -13,6 +13,7 @@
#include "bls_builder/bls_builder_internal.h"
#include "bls_builder/dcn401_init_builder.h"
#include "bls_builder/dcn401_init_builder_legacy.h"
+#include "dc_priv.h"
static const enum block_sequence_func dcn401_dc2_init_sequence[] = {
LEGACY_CLK_MGR_INIT_CLOCKS,
diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder_legacy.c b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder_legacy.c
index e13c16920a0c..66f708ec709b 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder_legacy.c
+++ b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder_legacy.c
@@ -23,6 +23,7 @@
#include "dcn32/dcn32_resource.h"
#include "bls_builder/dcn401_init_builder.h"
#include "bls_builder/dcn401_init_builder_legacy.h"
+#include "dc_priv.h"
/*
* DC2_DC1_Wrapped: dcn401_init_hw as BLS entries, built one stage per
diff --git a/drivers/gpu/drm/amd/display/dc/bls_executor/bls_executor.c b/drivers/gpu/drm/amd/display/dc/bls_executor/bls_executor.c
index 7600954c3478..81ea2e294f10 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_executor/bls_executor.c
+++ b/drivers/gpu/drm/amd/display/dc/bls_executor/bls_executor.c
@@ -22,6 +22,7 @@
#include "hwss/hw_sequencer_private.h"
#include "bls_executor/bls_executor.h"
#include "dmub_messenger/dmub_messenger.h"
+#include "dc_priv.h"
static noinline_for_stack bool dc2_bls_step_supported(const struct dc2 *dc2,
const struct block_sequence *step)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 7f24433a42c1..4d187bd8d0ad 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -53,6 +53,7 @@
#include "dcn42/dcn42_clk_mgr.h"
#include "dcn42b/dcn42b_clk_mgr.h"
#include "dcn60/dcn60_clk_mgr.h"
+#include "dc_priv.h"
int clk_mgr_helper_get_active_display_cnt(
struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index d891b3bfe2a1..89858aafb6c7 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -42,6 +42,7 @@
*/
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
+#include "dc_priv.h"
#define REG(reg) \
(clk_mgr->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index d52789ba2613..4b3dc1a3b102 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -30,6 +30,7 @@
#include "dce/dce_11_0_sh_mask.h"
#include "dce110_clk_mgr.h"
#include "../clk_mgr/dce100/dce_clk_mgr.h"
+#include "dc_priv.h"
/* set register offset */
#define SR(reg_name)\
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 3da0c220d17f..14577c95d376 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -32,6 +32,7 @@
#include "dce110/dce110_clk_mgr.h"
#include "dce112_clk_mgr.h"
#include "dal_asic_id.h"
+#include "dc_priv.h"
/* set register offset */
#define SR(reg_name)\
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
index f8ef3a4710fc..4038dcbf7bfd 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
@@ -31,6 +31,7 @@
#include "dce120_clk_mgr.h"
#include "dce100/dce_clk_mgr.h"
#include "dce120/dce120_hwseq.h"
+#include "dc_priv.h"
/**
* dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c
index 172bba20a156..0a573753bf9f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/dcn10_clk_mgr.c
@@ -6,6 +6,7 @@
#include "core_types.h"
#include "dal_asic_id.h"
#include "dcn10_clk_mgr.h"
+#include "dc_priv.h"
unsigned int dcn10_dentist_get_divider_from_did(unsigned int did)
{
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 9450b1733f60..a8100d895d61 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -29,6 +29,7 @@
#include "dcn10/dcn10_clk_mgr.h"
#include "rv1_clk_mgr_vbios_smu.h"
#include "rv1_clk_mgr_clk.h"
+#include "dc_priv.h"
static void rv1_init_clocks(struct clk_mgr *clk_mgr)
{
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
index d82a52319088..823748ee0fc0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
@@ -28,6 +28,7 @@
#include "reg_helper.h"
#include "rv1_clk_mgr_vbios_smu.h"
+#include "dc_priv.h"
#define MAX_INSTANCE 5
#define MAX_SEGMENT 5
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 86f3f32768e3..56e90db06a3d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -37,6 +37,7 @@
#include "dcn/dcn_2_0_0_sh_mask.h"
#include "clk/clk_11_0_0_offset.h"
#include "clk/clk_11_0_0_sh_mask.h"
+#include "dc_priv.h"
#undef FN
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
index 7ab548e41b40..a04e26720117 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
@@ -38,6 +38,7 @@
#include "dcn/dcn_2_0_1_sh_mask.h"
#include "clk/clk_11_0_1_offset.h"
#include "clk/clk_11_0_1_sh_mask.h"
+#include "dc_priv.h"
#define REG(reg) \
(clk_mgr->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 488ae92d24fa..b31fadd8a86f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -40,6 +40,7 @@
#include "clk/clk_10_0_2_offset.h"
#include "clk/clk_10_0_2_sh_mask.h"
#include "renoir_ip_offset.h"
+#include "dc_priv.h"
/* Constants */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 5a633333dbb5..722f149babe9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -44,6 +44,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index 80bdaf762a23..f562c5c10ceb 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -44,6 +44,7 @@
#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"
#include "dcn30_smu11_driver_if.h"
+#include "dc_priv.h"
#undef FN
#define FN(reg_name, field_name) \
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index ace3ceb228c6..07d2d542b476 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -45,6 +45,7 @@
#include "vangogh_ip_offset.h"
#include "clk/clk_11_5_0_offset.h"
#include "clk/clk_11_5_0_sh_mask.h"
+#include "dc_priv.h"
/* Constants */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 938bc2bbe6d7..6a74fdd71b4c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -53,6 +53,7 @@
#include "yellow_carp_offset.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
clk_mgr->base.base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index f201628e4e98..e7af83af1a5c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -40,6 +40,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index 2aa3e8e66cb7..a62076820bb4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -53,6 +53,7 @@
#include "logger_types.h"
+#include "dc_priv.h"
#define MAX_INSTANCE 7
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
index c4af406146b7..c986abfe0531 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
@@ -56,6 +56,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 8ca367b72325..a78082876327 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -47,6 +47,7 @@
clk_mgr->base.base.ctx->logger
#include "link_service.h"
+#include "dc_priv.h"
#define TO_CLK_MGR_DCN315(clk_mgr)\
container_of(clk_mgr, struct clk_mgr_dcn315, base)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
index 478b4d6a3544..4997a45064fa 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
@@ -30,6 +30,7 @@
#include "dcn315_smu.h"
#include "mp/mp_13_0_5_offset.h"
#include "logger_types.h"
+#include "dc_priv.h"
#define MAX_INSTANCE 6
#define MAX_SEGMENT 6
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index 96bd653a9b71..efd83e7a52fb 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -40,6 +40,7 @@
#include "dm_helpers.h"
#include "dc_dmub_srv.h"
#include "link_service.h"
+#include "dc_priv.h"
// DCN316 this is CLK1 instance
#define MAX_INSTANCE 7
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
index 8b82092b91cd..fd748f347079 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
@@ -57,6 +57,7 @@ static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E0000
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 7abb13ffd9f4..0da332914e3b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -42,6 +42,7 @@
#include "dcn/dcn_3_2_0_sh_mask.h"
#include "dml/dcn32/dcn32_fpu.h"
+#include "dc_priv.h"
#define DCN_BASE__INST0_SEG1 0x000000C0
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 990c362623d8..a7d2076a827c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -46,6 +46,7 @@
#include "dc_dmub_srv.h"
#include "link_service.h"
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index 9d8f81c3d3f0..faae83f44551 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -56,6 +56,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 03aec7f4df7b..14af6a336329 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -22,6 +22,7 @@
#include "dcn/dcn_4_1_0_offset.h"
#include "dcn/dcn_4_1_0_sh_mask.h"
+#include "dc_priv.h"
#define DCN_BASE__INST0_SEG1 0x000000C0
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index 405145889ba2..2050c6a1ac1e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -35,6 +35,7 @@
#include "clk/clk_15_0_0_sh_mask.h"
#include "dcn/dcn_4_2_0_offset.h"
#include "dcn/dcn_4_2_0_sh_mask.h"
+#include "dc_priv.h"
#undef DC_LOGGER
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
index 5e8d979f25f0..c225d4000d6a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
@@ -38,6 +38,7 @@
FD(reg_name##__##field)
#include "logger_types.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
index 33f0099075c0..d577abdc6ea5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
@@ -36,6 +36,7 @@
#include "dcn/dcn_4_2_1_sh_mask.h"
#include <linux/power_supply.h>
+#include "dc_priv.h"
#define DCN_BASE__INST0_SEG0 0x00000012
#define DCN_BASE__INST0_SEG1 0x000000C0
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index efc02ba740f5..53b6c363f747 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
@@ -25,6 +25,7 @@
#include "dcn/dcn_6_0_0_offset.h"
#include "dcn/dcn_6_0_0_sh_mask.h"
+#include "dc_priv.h"
#undef DC_LOGGER
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 4c583d452446..23aced5d5eef 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -31,6 +31,7 @@
* mapping stays obvious and auditable.
*/
#include "dc.h"
+#include "dc_priv.h"
#include "dm_helpers.h" /* EXPORT_IF_KUNIT */
uint8_t dc_get_link_count(const struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index f3348e0cb1d6..bdc2792d5f88 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -30,6 +30,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_status.h"
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 694c425e22b4..9fa2b5a34d2b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -42,6 +42,7 @@
#include "dce/dmub_hw_lock_mgr.h"
#include "link_service.h"
#include "custom_float.h"
+#include "dc_priv.h"
static union dmub_inbox0_cmd_lock_hw hwss_build_dmub_lock_command(bool lock)
{
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index d2a5e0648fc2..47dc12952f10 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -25,6 +25,7 @@
#include "link_enc_cfg.h"
#include "resource.h"
#include "link_service.h"
+#include "dc_priv.h"
#define DC_LOGGER dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
index d2f52e4839fe..50dc317eed71 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c
@@ -35,6 +35,7 @@
*/
#include "link_service.h"
#include "dce/dce_i2c.h"
+#include "dc_priv.h"
struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
{
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 832286f0c0b1..d5d53491e91c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -78,6 +78,7 @@
#include "dcn321/dcn321_resource.h"
#include "dcn35/dcn35_resource.h"
#include "dcn351/dcn351_resource.h"
+#include "dc_priv.h"
#include "dcn36/dcn36_resource.h"
#include "dcn401/dcn401_resource.h"
#include "dcn42/dcn42_resource.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
index f976ffd6d466..1758c0b9390b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
@@ -25,6 +25,7 @@
#include "dc/dc_stat.h"
#include "dmub/dmub_srv_stat.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
/**
* DOC: DC STAT Interface
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index edb50c23ce24..88ee99bd4494 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -26,6 +26,7 @@
#include "core_types.h"
#include "core_status.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_state.h"
#include "dc_state_priv.h"
#include "dc_stream_priv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 56c7d97733a6..65f305b3c15d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -27,6 +27,7 @@
#include "dm_helpers.h"
#include "basics/dc_common.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "resource.h"
#include "ipp.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index 0b135a9e6c4f..139a934cbf3d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -26,6 +26,7 @@
/* DC interface (public) */
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
/* DC core (private) */
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_test.c b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
index 60fb45f9cfaa..04c799ae33d3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_test.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
@@ -32,6 +32,7 @@
#include <linux/export.h>
#include "dc.h"
+#include "dc_priv.h"
#include "dc_test.h"
struct dc *dc_test_create(void)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
index 3743555133f6..cc0d5ceace5f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
@@ -25,6 +25,7 @@
#include "vm_helper.h"
#include "dc.h"
+#include "dc_priv.h"
void vm_helper_mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uint8_t hubp_idx)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 082435846ee9..d976425c190b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -857,43 +857,6 @@ struct dc_bw_validation_profile {
unsigned long long skip_fail_count;
};
-#define BW_VAL_TRACE_SETUP() \
- unsigned long long end_tick = 0; \
- unsigned long long voltage_level_tick = 0; \
- unsigned long long watermark_tick = 0; \
- unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
- dm_get_timestamp(dc->ctx) : 0
-
-#define BW_VAL_TRACE_COUNT() \
- if (dc->debug.bw_val_profile.enable) \
- dc->debug.bw_val_profile.total_count++
-
-#define BW_VAL_TRACE_SKIP(status) \
- if (dc->debug.bw_val_profile.enable) { \
- if (!voltage_level_tick) \
- voltage_level_tick = dm_get_timestamp(dc->ctx); \
- dc->debug.bw_val_profile.skip_ ## status ## _count++; \
- }
-
-#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
- if (dc->debug.bw_val_profile.enable) \
- voltage_level_tick = dm_get_timestamp(dc->ctx)
-
-#define BW_VAL_TRACE_END_WATERMARKS() \
- if (dc->debug.bw_val_profile.enable) \
- watermark_tick = dm_get_timestamp(dc->ctx)
-
-#define BW_VAL_TRACE_FINISH() \
- if (dc->debug.bw_val_profile.enable) { \
- end_tick = dm_get_timestamp(dc->ctx); \
- dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
- dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
- if (watermark_tick) { \
- dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
- dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
- } \
- }
-
union mem_low_power_enable_options {
struct {
bool vga: 1;
@@ -2020,100 +1983,6 @@ struct dc_scratch_space {
enum backlight_control_type backlight_control_type;
};
-struct dc {
- struct dc_debug_options debug;
- struct dc_versions versions;
- struct dc_caps caps;
- struct dc_check_config check_config;
- struct dc_cap_funcs cap_funcs;
- struct dc_config config;
- struct dc_bounding_box_overrides bb_overrides;
- struct dc_bug_wa work_arounds;
- struct dc_context *ctx;
- struct dc_phy_addr_space_config vm_pa_config;
-
- uint8_t link_count;
- struct dc_link *links[MAX_LINKS];
- uint8_t lowest_dpia_link_index;
- struct link_service *link_srv;
-
- struct dc_state *current_state;
- /**
- * @scratch_dc_context: Pre-allocated states for the no-allocation update
- * path, created only when dc_config.preallocate_scratch_state is set.
- * Two are kept because the commit path installs the new context as
- * @current_state, so a single buffer would alias it and self-copy.
- */
- struct dc_state *scratch_dc_context[2];
- struct resource_pool *res_pool;
-
- /**
- * @update_scratch_pool: Per-commit scratch buffers for dc_update_state.
- */
- struct dc_memory_pool *update_scratch_pool; // MAX_STREAMS + 1
-
- struct clk_mgr *clk_mgr;
-
- /* Display Engine Clock levels */
- struct dm_pp_clock_levels sclk_lvls;
-
- /* Inputs into BW and WM calculations. */
- struct bw_calcs_dceip *bw_dceip;
- struct bw_calcs_vbios *bw_vbios;
- struct dcn_soc_bounding_box *dcn_soc;
- struct dcn_ip_params *dcn_ip;
- struct display_mode_lib dml;
-
- /* HW functions */
- struct hw_sequencer_funcs hwss;
- struct dce_hwseq *hwseq;
-
- /* Require to optimize clocks and bandwidth for added/removed planes */
- bool optimized_required;
- bool idle_optimizations_allowed;
- bool enable_c20_dtm_b0;
-
- /* Require to maintain clocks and bandwidth for UEFI enabled HW */
-
- /* For eDP to know the switching state of SmartMux */
- bool is_switch_in_progress_orig;
- bool is_switch_in_progress_dest;
-
- /* FBC compressor */
- struct compressor *fbc_compressor;
-
- struct dc_debug_data debug_data;
- struct dpcd_vendor_signature vendor_signature;
-
- const char *build_id;
- struct vm_helper *vm_helper;
-
- uint32_t *dcn_reg_offsets;
- uint32_t *nbio_reg_offsets;
- uint32_t *clk_reg_offsets;
-
- /* Scratch memory */
- struct {
- struct {
- /*
- * For matching clock_limits table in driver with table
- * from PMFW.
- */
- struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
- } update_bw_bounding_box;
- struct dc_scratch_space current_state;
- struct dc_scratch_space new_state;
- struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack
- struct dc_link temp_link;
- bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */
- } scratch;
-
- struct dml2_configuration_options dml2_options;
- struct dml2_configuration_options dml2_dc_power_options;
- enum dc_acpi_cm_power_state power_state;
- struct soc_and_ip_translator *soc_and_ip_translator;
-};
-
struct dc_scaling_info {
struct rect src_rect;
struct rect dst_rect;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
index b972ae06663d..7802a18b8caa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
@@ -6,6 +6,7 @@
#pragma once
#include "dc.h"
+#include "dc_priv.h"
#include "inc/dc_core_interface.h"
#include "bls_builder/dmub_abi.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 323e8bec23dc..cde3a6a21de3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_dmub_srv.h"
#include "../dmub/dmub_srv.h"
#include "dm_helpers.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dc_priv.h b/drivers/gpu/drm/amd/display/dc/dc_priv.h
new file mode 100644
index 000000000000..70e4eee9bf0f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dc_priv.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __DC_PRIV_H__
+#define __DC_PRIV_H__
+
+/* FILE POLICY AND INTENDED USAGE:
+ * This header defines struct dc, the DC core state. It is private to the dc
+ * directory and must never be included from DM, DAL modules or any other
+ * code outside DC. Public DC interfaces are declared in dc.h; use the
+ * accessors implemented in dc/core/dc_accessors.c instead of reaching into
+ * struct dc.
+ */
+
+#include "dc.h"
+
+/* Bandwidth validation trace macros. Usable only from DC-internal code
+ * because they dereference the dc-local variable of the including function.
+ */
+#define BW_VAL_TRACE_SETUP() \
+ unsigned long long end_tick = 0; \
+ unsigned long long voltage_level_tick = 0; \
+ unsigned long long watermark_tick = 0; \
+ unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
+ dm_get_timestamp(dc->ctx) : 0
+
+#define BW_VAL_TRACE_COUNT() \
+ do { \
+ if (dc->debug.bw_val_profile.enable) \
+ dc->debug.bw_val_profile.total_count++; \
+ } while (0)
+
+#define BW_VAL_TRACE_SKIP(status) \
+ do { \
+ if (dc->debug.bw_val_profile.enable) { \
+ if (!voltage_level_tick) \
+ voltage_level_tick = dm_get_timestamp(dc->ctx); \
+ dc->debug.bw_val_profile.skip_ ## status ## _count++; \
+ } \
+ } while (0)
+
+#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
+ do { \
+ if (dc->debug.bw_val_profile.enable) \
+ voltage_level_tick = dm_get_timestamp(dc->ctx); \
+ } while (0)
+
+#define BW_VAL_TRACE_END_WATERMARKS() \
+ do { \
+ if (dc->debug.bw_val_profile.enable) \
+ watermark_tick = dm_get_timestamp(dc->ctx); \
+ } while (0)
+
+#define BW_VAL_TRACE_FINISH() \
+ do { \
+ if (dc->debug.bw_val_profile.enable) { \
+ end_tick = dm_get_timestamp(dc->ctx); \
+ dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
+ dc->debug.bw_val_profile.voltage_level_ticks += \
+ voltage_level_tick - start_tick; \
+ if (watermark_tick) { \
+ dc->debug.bw_val_profile.watermark_ticks += \
+ watermark_tick - voltage_level_tick; \
+ dc->debug.bw_val_profile.rq_dlg_ticks += \
+ end_tick - watermark_tick; \
+ } \
+ } \
+ } while (0)
+
+struct dc {
+ struct dc_debug_options debug;
+ struct dc_versions versions;
+ struct dc_caps caps;
+ struct dc_check_config check_config;
+ struct dc_cap_funcs cap_funcs;
+ struct dc_config config;
+ struct dc_bounding_box_overrides bb_overrides;
+ struct dc_bug_wa work_arounds;
+ struct dc_context *ctx;
+ struct dc_phy_addr_space_config vm_pa_config;
+
+ uint8_t link_count;
+ struct dc_link *links[MAX_LINKS];
+ uint8_t lowest_dpia_link_index;
+ struct link_service *link_srv;
+
+ struct dc_state *current_state;
+ /**
+ * @scratch_dc_context: Pre-allocated states for the no-allocation update
+ * path, created only when dc_config.preallocate_scratch_state is set.
+ * Two are kept because the commit path installs the new context as
+ * @current_state, so a single buffer would alias it and self-copy.
+ */
+ struct dc_state *scratch_dc_context[2];
+ struct resource_pool *res_pool;
+
+ /**
+ * @update_scratch_pool: Per-commit scratch buffers for dc_update_state.
+ */
+ struct dc_memory_pool *update_scratch_pool; // MAX_STREAMS + 1
+
+ struct clk_mgr *clk_mgr;
+
+ /* Display Engine Clock levels */
+ struct dm_pp_clock_levels sclk_lvls;
+
+ /* Inputs into BW and WM calculations. */
+ struct bw_calcs_dceip *bw_dceip;
+ struct bw_calcs_vbios *bw_vbios;
+ struct dcn_soc_bounding_box *dcn_soc;
+ struct dcn_ip_params *dcn_ip;
+ struct display_mode_lib dml;
+
+ /* HW functions */
+ struct hw_sequencer_funcs hwss;
+ struct dce_hwseq *hwseq;
+
+ /* Require to optimize clocks and bandwidth for added/removed planes */
+ bool optimized_required;
+ bool idle_optimizations_allowed;
+ bool enable_c20_dtm_b0;
+
+ /* Require to maintain clocks and bandwidth for UEFI enabled HW */
+
+ /* For eDP to know the switching state of SmartMux */
+ bool is_switch_in_progress_orig;
+ bool is_switch_in_progress_dest;
+
+ /* FBC compressor */
+ struct compressor *fbc_compressor;
+
+ struct dc_debug_data debug_data;
+ struct dpcd_vendor_signature vendor_signature;
+
+ const char *build_id;
+ struct vm_helper *vm_helper;
+
+ uint32_t *dcn_reg_offsets;
+ uint32_t *nbio_reg_offsets;
+ uint32_t *clk_reg_offsets;
+
+ /* Scratch memory */
+ struct {
+ struct {
+ /*
+ * For matching clock_limits table in driver with table
+ * from PMFW.
+ */
+ struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
+ } update_bw_bounding_box;
+ struct dc_scratch_space current_state;
+ struct dc_scratch_space new_state;
+ /* Used so we don't need to allocate stream on the stack */
+ struct dc_stream_state temp_stream;
+ struct dc_link temp_link;
+ /* Any of the pipes indicated here should be unlocked first */
+ bool pipes_to_unlock_first[MAX_PIPES];
+ } scratch;
+
+ struct dml2_configuration_options dml2_options;
+ struct dml2_configuration_options dml2_dc_power_options;
+ enum dc_acpi_cm_power_state power_state;
+ struct soc_and_ip_translator *soc_and_ip_translator;
+};
+#endif /* __DC_PRIV_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
index 00e121bb8ef7..124deb723064 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
@@ -6,6 +6,7 @@
#include "dcn20/dcn20_dpp.h"
#include "dcn32/dcn32_dpp.h"
#include "dcn401/dcn401_dpp.h"
+#include "dc_priv.h"
static struct spl_callbacks dcn2_spl_callbacks = {
.spl_calc_lb_num_partitions = dscl2_spl_calc_lb_num_partitions,
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
index 341509ad6f35..e6ac961c11fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
@@ -28,6 +28,7 @@
#include "dcn31_dccg.h"
#include "dcn20/dcn20_dccg.h"
#include "dal_asic_id.h"
+#include "dc_priv.h"
#define TO_DCN_DCCG(dccg)\
container_of(dccg, struct dcn_dccg, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
index 7bfe7be2bc1f..4fc1f27e9300 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
@@ -30,6 +30,7 @@
#include "dcn31/dcn31_dccg.h"
#include "dcn314_dccg.h"
#include "dcn20/dcn20_dccg.h"
+#include "dc_priv.h"
#define TO_DCN_DCCG(dccg)\
container_of(dccg, struct dcn_dccg, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 6dce2a4beca2..a4d05b5a8487 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -41,6 +41,7 @@
#define CTX \
dccg_dcn->base.ctx
#include "logger_types.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dccg->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
index a4ece209d600..c827708e8613 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
@@ -28,6 +28,7 @@
#include "dcn401_dccg.h"
#include "dcn31/dcn31_dccg.h"
#include "dcn20/dcn20_dccg.h"
+#include "dc_priv.h"
/*
#include "dmub_common.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
index b7b84152d623..e4758d48ae12 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
@@ -7,6 +7,7 @@
#include "dcn35/dcn35_dccg.h"
#include "dcn42_dccg.h"
#include "dcn20/dcn20_dccg.h"
+#include "dc_priv.h"
#define TO_DCN_DCCG(dccg)\
container_of(dccg, struct dcn_dccg, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 4abf51c8ab52..0e367433b3d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -46,6 +46,7 @@
#define LOG_FLAG_I2cAux_DceAux LOG_I2C_AUX
#include "reg_helper.h"
+#include "dc_priv.h"
#undef FN
#define FN(reg_name, field_name) \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 145c993342bd..01a78cc38139 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -38,6 +38,7 @@
#include "dccg.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg)\
(clk_src->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 23de1c793ec3..8de051b1c4f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "fixed31_32.h"
#include "dc.h"
+#include "dc_priv.h"
#define TO_DCE_DMCU(dmcu)\
container_of(dmcu, struct dce_dmcu, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
index f5261e8d7678..79c355db22ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
@@ -24,6 +24,7 @@
*/
#include "dce_i2c.h"
#include "reg_helper.h"
+#include "dc_priv.h"
bool dce_i2c_oem_device_present(
struct resource_pool *pool,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 05892ab4529f..3b4aefc0007e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -27,6 +27,7 @@
#include "dce_i2c_hw.h"
#include "reg_helper.h"
#include "include/gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
dce_i2c_hw->ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index c6a20378121b..5819c508d872 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -36,6 +36,7 @@
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#include "dce/dce_11_0_enum.h"
+#include "dc_priv.h"
#ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 168c2d0a5eaa..fe17832f98b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -26,6 +26,7 @@
#include "dce_mem_input.h"
#include "reg_helper.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define CTX \
dce_mi->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 83f819890020..1c5fcd3c99fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -28,6 +28,7 @@
#include "opp.h"
#include "basics/conversion.h"
#include "dc.h"
+#include "dc_priv.h"
#define REG(reg) \
(xfm_dce->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 8cca8599b917..da4de4141e96 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -27,6 +27,7 @@
#include "dmub_abm_lcd.h"
#include "dmub_abm_cacp.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dmub_cmd.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c
index 9f58fa2e25fd..9b8077726b17 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_cacp.c
@@ -4,6 +4,7 @@
#include "dmub_abm_cacp.h"
#include "dce_abm.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
index f60e43ba6060..d0107e87b421 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
@@ -27,6 +27,7 @@
#include "dmub_abm_lcd.h"
#include "dce_abm.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index f5ff61a2e89e..f9a265ff8317 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
@@ -27,6 +27,7 @@
#include "dc_dmub_srv.h"
#include "dc_types.h"
#include "core_types.h"
+#include "dc_priv.h"
static bool dmub_hw_lock_has_inbox0_lock(const struct dc *dc)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 66d8ba73d38b..64b862a0e358 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -25,6 +25,7 @@
#include "dmub_psr.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
#include "core_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index 365c428eae72..e7a7c4d50e01 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -3,6 +3,7 @@
// Copyright 2024 Advanced Micro Devices, Inc.
#include "dc.h"
+#include "dc_priv.h"
#include "link_service.h"
#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 095869912c09..277c9e169a1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -33,6 +33,7 @@
#include "dce/dce_mem_input.h"
#include "dce110_mem_input_v.h"
+#include "dc_priv.h"
static void set_flip_control(
struct dce_mem_input *mem_input110,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
index 6be18665b1f7..97562423b43b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -26,6 +26,7 @@
#include "dce110_transform_v.h"
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index 395bccdd0f1d..ca5803fd2d29 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -45,6 +45,7 @@
#include "dcn10_cm_common.h"
#include "clk_mgr.h"
#include "dsc.h"
+#include "dc_priv.h"
__printf(3, 4)
unsigned int snprintf_count(char *pbuf, unsigned int bufsize, const char *fmt, ...)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
index 9459e8f28338..2e6f398a68c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
@@ -32,6 +32,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
index fcaa3884d705..dda8af8aecfa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
@@ -34,6 +34,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
index d380a8ec2184..37b608ee7ca9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
@@ -29,6 +29,7 @@
#include "dcn31_afmt.h"
#include "reg_helper.h"
#include "dc/dc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
afmt31->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
index d7c3f26777e3..6943e6df9173 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
@@ -29,6 +29,7 @@
#include "dc_dmub_srv.h"
#include "dcn31_panel_cntl.h"
#include "atom.h"
+#include "dc_priv.h"
#define TO_DCN31_PANEL_CNTL(panel_cntl)\
container_of(panel_cntl, struct dcn31_panel_cntl, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
index cfb923d85630..a453cc24d82a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
@@ -28,6 +28,7 @@
#include "dcn31_vpg.h"
#include "reg_helper.h"
#include "dc/dc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
vpg31->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
index 32e12d894e31..85d6b7f15e15 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
@@ -32,6 +32,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
index c937788d0763..de3df77c36a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
@@ -31,6 +31,7 @@
#include "link_service.h"
#include "dpcd_defs.h"
#include "dcn30/dcn30_afmt.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
index dbd4c534c5c3..1596b53d62a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c
@@ -32,6 +32,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
index ac6ca7771d2f..052a5d3a65a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
@@ -31,6 +31,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
index 5fd5158482ea..adbde44e18a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c
@@ -31,6 +31,7 @@
#include "stream_encoder.h"
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
index 9757d3bcdf32..b516f2d9d09b 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
@@ -29,6 +29,7 @@
#include "reg_helper.h"
#include "hw_shared.h"
#include "dc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
index 7106669eab5b..79afaae47791 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c
@@ -31,6 +31,7 @@
#include "stream_encoder.h"
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
index 1b9ba0e9f068..39b97f960da1 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c
@@ -38,6 +38,7 @@
#include "dc_dmub_srv.h"
#include "dal_asic_id.h"
#include "link_service.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
index 482c52c1d7d6..036704e21dac 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c
@@ -32,6 +32,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
index 63990c47ac14..24af37eded70 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c
@@ -36,6 +36,7 @@
#include "dc_dmub_srv.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
index 3dd8fe423232..ca7615dfb11b 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c
@@ -31,6 +31,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
index 67d6050d5163..c09932c3fd2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c
@@ -33,6 +33,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
index 9375c9b939be..25b1e02f1874 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c
@@ -29,6 +29,7 @@
#include "dcn31/dcn31_dio_link_encoder.h"
#include "dcn35_dio_link_encoder.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
#define CTX \
enc10->base.ctx
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
index dabcb45840a7..38eac36b8304 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
@@ -31,6 +31,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
index 6594fbb3fa43..fb9a0c43f599 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c
@@ -35,6 +35,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
index 4616b6f76aeb..e962c544610e 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
@@ -34,6 +34,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c
index 3b11be9991c3..6c64df545aa0 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c
@@ -8,6 +8,7 @@
#include "link_encoder.h"
#include "dcn35/dcn35_dio_link_encoder.h"
#include "dcn42_dio_link_encoder.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
index b7671d41ea24..fe8774845186 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
@@ -14,6 +14,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_link_encoder.c
index f65326a0f6d2..78af49f0e316 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_link_encoder.c
@@ -15,6 +15,7 @@
#include "dc_bios_types.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_stream_encoder.c
index b645914c1c71..5df2b7202917 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn60/dcn60_dio_stream_encoder.c
@@ -13,6 +13,7 @@
#include "hw_shared.h"
#include "link_service.h"
#include "dpcd_defs.h"
+#include "dc_priv.h"
#define DC_LOGGER \
enc1->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
index 2ad4a2635683..59c93dc3fe63 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calcs.h"
#include "dcn_calc_auto.h"
#include "dal_asic_id.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
index ae6b2d47f379..a7fdc0b0a7e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
@@ -28,6 +28,7 @@
#include "dcn10_fpu.h"
#include "resource.h"
+#include "dc_priv.h"
/**
* DOC: DCN10 FPU manipulation Overview
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 38c79239004c..458832a2d2df 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -33,6 +33,7 @@
#include "link_service.h"
#include "dcn20_fpu.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index b8e5985f9307..ac5fcaf96c10 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -34,6 +34,7 @@
#include "dcn30_fpu.h"
#include "../dml1_frl_cap_chk.h"
+#include "dc_priv.h"
#define REG(reg)\
optc1->tg_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index c4b73acd7140..2849ddd42e39 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -30,6 +30,7 @@
#include "dml/dcn20/dcn20_fpu.h"
#include "dcn301_fpu.h"
+#include "dc_priv.h"
#define TO_DCN301_RES_POOL(pool)\
container_of(pool, struct dcn301_resource_pool, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
index 781bc429807f..6b5ab8940a73 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c
@@ -30,6 +30,7 @@
#include "dml/dcn20/dcn20_fpu.h"
#include "dcn302_fpu.h"
+#include "dc_priv.h"
struct _vcs_dpi_ip_params_st dcn3_02_ip = {
.use_min_dcfclk = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
index e6d7d67f06a4..61b2d8e3b7c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
@@ -29,6 +29,7 @@
#include "dml/dcn20/dcn20_fpu.h"
#include "dcn303_fpu.h"
+#include "dc_priv.h"
struct _vcs_dpi_ip_params_st dcn3_03_ip = {
.use_min_dcfclk = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index f9b2da6b2bb8..9289d5ccf5f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -31,6 +31,7 @@
#include "dml/dcn20/dcn20_fpu.h"
#include "dcn31_fpu.h"
+#include "dc_priv.h"
/**
* DOC: DCN31x FPU manipulation Overview
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
index 1854137d5b9e..bc320383ad56 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
@@ -32,6 +32,7 @@
#include "dml/dcn31/dcn31_fpu.h"
#include "dml/display_mode_vba.h"
#include "dml/dml_inline_defs.h"
+#include "dc_priv.h"
struct _vcs_dpi_ip_params_st dcn3_14_ip = {
.VBlankNomDefaultUS = 668,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index b5bd1358fdfd..f15fe3a76ddb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -33,6 +33,7 @@
#include "dcn30/dcn30_resource.h"
#include "link_service.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index f4d826e0d13a..e96d05f9e8c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -30,6 +30,7 @@
#include "dcn32/dcn32_resource.h"
#include "dcn321/dcn321_resource.h"
#include "dml/dcn32/display_mode_vba_util_32.h"
+#include "dc_priv.h"
#define DCN3_2_DEFAULT_DET_SIZE 256
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index c15fbc18bfdf..d03f82ad2108 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -32,6 +32,7 @@
#include "dml/dml_inline_defs.h"
#include "link_service.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
index 0c5a2667d526..762d37c500e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
@@ -11,6 +11,7 @@
#include "dml/dml_inline_defs.h"
#include "link_service.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
index 6a9f822b2b33..d96373c33b31 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
@@ -9,6 +9,7 @@
#include "dml21_utils.h"
#include "dml21_translation_helper.h"
#include "soc_and_ip_translator.h"
+#include "dc_priv.h"
static void dml21_populate_pmo_options(struct dml2_pmo_options *pmo_options,
const struct dc *in_dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_utils.c
index 0aecfa8b909f..62283f36d275 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_utils.c
@@ -10,6 +10,7 @@
#include "dml2_dc_resource_mgmt.h"
#include "dml2_core_dcn4_calcs.h"
+#include "dc_priv.h"
int dml21_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c
index a1525f7e0e61..6e34bfd9b239 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_wrapper_fpu.c
@@ -13,6 +13,7 @@
#include "dml2_wrapper_fpu.h"
#include "dml21_wrapper.h"
#include "dml21_wrapper_fpu.h"
+#include "dc_priv.h"
#define INVALID -1
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_dc_resource_mgmt.c
index 4050b0a47caf..ac23b494e9a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_dc_resource_mgmt.c
@@ -30,6 +30,7 @@
#include "dml2_internal_types.h"
#include "dml2_utils.h"
#include "dml2_dc_resource_mgmt.h"
+#include "dc_priv.h"
#define MAX_ODM_FACTOR 4
#define MAX_MPCC_FACTOR 4
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c
index edc4dcdde952..ec443cef57fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_mall_phantom.c
@@ -29,6 +29,7 @@
#include "dml2_internal_types.h"
#include "dml2_utils.h"
#include "dml2_mall_phantom.h"
+#include "dc_priv.h"
unsigned int dml2_helper_calculate_num_ways_for_subvp(struct dml2_context *ctx, struct dc_state *context)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_translation_helper.c
index a0130bbfc12a..e6960f1df77b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_translation_helper.c
@@ -27,6 +27,7 @@
#include "display_mode_core.h"
#include "dml2_internal_types.h"
#include "dml2_translation_helper.h"
+#include "dc_priv.h"
#define NUM_DCFCLK_STAS 5
#define NUM_DCFCLK_STAS_NEW 8
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_utils.c
index 8688792aa956..a74d6777bbe2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_utils.c
@@ -30,6 +30,7 @@
#include "dml2_internal_types.h"
#include "dml2_translation_helper.h"
#include "dml2_utils.h"
+#include "dc_priv.h"
void dml2_util_copy_dml_timing(struct dml_timing_cfg_st *dml_timing_array, unsigned int dst_index, unsigned int src_index)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c
index 2fe3c4643f58..133bc9e3bfb0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper.c
@@ -12,6 +12,7 @@
#include "dml21_wrapper/dml21_wrapper_fpu.h"
#include "dc_fpu.h"
+#include "dc_priv.h"
#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED)
#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c
index 8a31986bc299..1055764381c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml2_wrapper_fpu.c
@@ -35,6 +35,7 @@
#include "dml2_wrapper_fpu.h"
#include "dml21_wrapper/dml21_wrapper.h"
#include "dml21_wrapper/dml21_wrapper_fpu.h"
+#include "dc_priv.h"
void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
index de420cdf1514..cc893bbafc27 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dcn10/dcn10_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define NUM_PHASES 64
#define HORZ_MAX_TAPS 8
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
index b9adf8433b36..75c8842a4946 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dcn10/dcn10_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define NUM_PHASES 64
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
index 74cc176d9437..e3e31e561b18 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c
@@ -32,6 +32,7 @@
#include "basics/conversion.h"
#include "dcn10/dcn10_cm_common.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
index a2079db62f63..1d2fab6f2081 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dcn201/dcn201_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
index 3db10019fa84..1ca5518255de 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
@@ -29,6 +29,7 @@
#include "dcn30/dcn30_dpp.h"
#include "basics/conversion.h"
#include "dcn30/dcn30_cm_common.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
index 86f47d33ec64..1756f0b504f0 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c
@@ -31,6 +31,7 @@
#include "dcn30/dcn30_dpp.h"
#include "basics/conversion.h"
#include "dcn30/dcn30_cm_common.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
index adb3f155d051..9c2f50331056 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dcn401/dcn401_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define NUM_PHASES 64
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c
index de0d89ac3f8b..62126d5cc86b 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_cm.c
@@ -4,6 +4,7 @@
#include "dcn60/dcn60_dpp.h"
#include "dcn30/dcn30_cm_common.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define REG(reg) \
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c
index d1a81e5616b3..b37a538df6ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c
@@ -9,6 +9,7 @@
#include "reg_helper.h"
#include "dcn60/dcn60_dpp.h"
#include "basics/conversion.h"
+#include "dc_priv.h"
#define REG(reg)\
dpp->tf_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 56db43d1b072..63f069cb0300 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -27,6 +27,7 @@
#include "dc_hw_types.h"
#include "dsc.h"
#include "dc.h"
+#include "dc_priv.h"
#include "rc_calc.h"
#include "fixed31_32.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
index f3413d743107..b2cc2ab39838 100644
--- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
@@ -31,6 +31,7 @@
#include "link_service.h"
#include "link_hwss.h"
#include "link/protocols/link_dpcd.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
index 56e753d2f43d..7ac238c97d69 100644
--- a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_link_encoder.c
@@ -29,6 +29,7 @@
#include "dcn30_hpo_frl_link_encoder.h"
#include "reg_helper.h"
#include "dcn10/dcn10_link_encoder.h"
+#include "dc_priv.h"
#define DC_LOGGER enc3->base.ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
index 4e33648f74bb..f7acc0d75167 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
@@ -27,6 +27,7 @@
#include "dcn10/dcn10_hubp.h"
#include "dcn10_hubbub.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define CTX \
hubbub1->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
index e5b55fe502ca..3cbde1b9e7f0 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
@@ -27,6 +27,7 @@
#include "dcn20_hubbub.h"
#include "reg_helper.h"
#include "clk_mgr.h"
+#include "dc_priv.h"
#define REG(reg)\
hubbub1->regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
index e6b527cd2047..a76a1dc9b797 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c
@@ -26,6 +26,7 @@
#include "dcn20/dcn20_hubbub.h"
#include "dcn201_hubbub.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg)\
hubbub1->regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
index 881e91e9385d..afbee30245be 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
@@ -27,6 +27,7 @@
#include "dcn20/dcn20_hubbub.h"
#include "dcn21_hubbub.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg)\
hubbub1->regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
index 582d647da812..67325f1efeb3 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "reg_helper.h"
#include "dcn30_hubbub.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
index 786843362061..7965d3dc5df6 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
@@ -28,6 +28,7 @@
#include "dcn31_hubbub.h"
#include "dm_services.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
index dd9bc1f08b56..1353650cc650 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
@@ -29,6 +29,7 @@
#include "dm_services.h"
#include "reg_helper.h"
#include "dal_asic_id.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
index ad333cd3241b..b36640a6c1a5 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
@@ -32,6 +32,7 @@
#include "dm_services.h"
#include "reg_helper.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
index 957e8f5a6475..3adf0b16633d 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
@@ -28,6 +28,7 @@
#include "dcn401_hubbub.h"
#include "dm_services.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c
index 244f3f2824ed..fc417e33f467 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c
@@ -10,6 +10,7 @@
#include "dcn42/dcn42_hubbub.h"
#include "dm_services.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define DCN42_CRB_SEGMENT_SIZE_KB 64
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c
index 07282b78972a..3598b20ba1a4 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn60/dcn60_hubbub.c
@@ -6,6 +6,7 @@
#include "dm_services.h"
#include "reg_helper.h"
#include "fixed31_32.h"
+#include "dc_priv.h"
#define CTX \
hubbub2->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
index c667db319baf..ef88d15c9db3 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
@@ -30,6 +30,7 @@
#include "reg_helper.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
index c879f4901c7d..45ee7421cd38 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c
@@ -26,6 +26,7 @@
#include "dcn35_hubp.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg)\
hubp2->hubp_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
index 0c8a23cef1e0..5dfc261bf0cb 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
@@ -5,6 +5,7 @@
#include "dcn401/dcn401_hubp.h"
#include "dcn42_hubp.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg) \
hubp2->hubp_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
index 0f44577572fb..9842778f2758 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
@@ -27,6 +27,7 @@
#include "reg_helper.h"
#include "hw_sequencer_private.h"
#include "core_types.h"
+#include "dc_priv.h"
#define CTX \
hws->ctx
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
index 0d7e28260db1..afcc74da11a5 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
@@ -24,6 +24,7 @@
*/
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "clk_mgr.h"
#include "dce100_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index a08ceaeda91c..6bbf5e89d4c5 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dc_bios_types.h"
#include "core_types.h"
#include "core_status.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
index ed9b0113a7a0..87f9bfb321cd 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce112/dce112_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dce112_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
index fbe34d1bb39a..3b728a590237 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dce120_hwseq.h"
#include "dce/dce_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
index b73a10b0acbd..58c539a908f1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dce60_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
index f44f41b13007..c56ff93be7e2 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#include "dce80_hwseq.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index f1d14b97977f..939f5e4948da 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -59,6 +59,7 @@
#include "dce/dmub_outbox.h"
#include "link_service.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
index bc3ac96de688..442830726b38 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
@@ -28,6 +28,7 @@
#include "dcn10/dcn10_hwseq.h"
#include "dcn20/dcn20_hwseq.h"
#include "dc/hwss/dce/dce_hwseq.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 636cbd947918..90a05af35782 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -57,6 +57,7 @@
#include "link_hwss.h"
#include "link_service.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
index 789bde439192..5b07f4fea9e0 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
@@ -28,6 +28,7 @@
#include "dcn20/dcn20_hwseq.h"
#include "dcn20_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn20_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
index d34f63432c6b..0aa8259297c8 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
@@ -41,6 +41,7 @@
#include "reg_helper.h"
#include "dcn10/dcn10_hubbub.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
index 33c22d9bbd2e..5323c2baf811 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
@@ -29,6 +29,7 @@
#include "dcn20/dcn20_hwseq.h"
#include "dcn201/dcn201_hwseq.h"
#include "dcn201_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn201_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
index 2be68f8dd0fc..19c6b31d7425 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
@@ -37,6 +37,7 @@
#include "dc_dmub_srv.h"
#include "abm.h"
#include "link_service.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
index 39bf0e51ec7c..f5378a40f936 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
@@ -29,6 +29,7 @@
#include "dcn21/dcn21_hwseq.h"
#include "dcn21_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn21_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 35d5cce0a791..2119710c37cf 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -54,6 +54,7 @@
#include "link_service.h"
#include "dc_state_priv.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define TO_DCN_DCCG(dccg)\
container_of(dccg, struct dcn_dccg, base)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
index ce42b8216f3b..4ec42a030dde 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
@@ -30,6 +30,7 @@
#include "dcn30/dcn30_hwseq.h"
#include "dcn30_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn30_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
index 5ed4305e4663..f36136a36bbb 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
@@ -31,6 +31,7 @@
#include "dcn301/dcn301_hwseq.h"
#include "dcn301_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn301_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
index 0a6d58dd8f6d..c2e0ab1e6831 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c
@@ -29,6 +29,7 @@
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c
index 637f9514d37b..9b6f273ced8a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c
@@ -28,6 +28,7 @@
#include "dcn30/dcn30_init.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn302_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c
index edb4d68b8187..77e77a990d12 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c
@@ -26,6 +26,7 @@
#include "dcn303/dcn303_hwseq.h"
#include "dcn30/dcn30_init.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn303_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index b6f3c0480ab6..f5b96c86ca59 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -55,6 +55,7 @@
#include "dce/dmub_abm_lcd.h"
#include "dio/dcn10/dcn10_dio.h"
#include "dce/dmub_abm_cacp.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
index c7055312cc3d..8a0912d7caa8 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
@@ -32,6 +32,7 @@
#include "dcn31/dcn31_hwseq.h"
#include "dcn31_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn31_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index de7dde2b036b..d57f5be5c57f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -54,6 +54,7 @@
#include "dsc.h"
#include "dcn20/dcn20_optc.h"
#include "dcn30/dcn30_cm_common.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
index 69b020e2c4b2..0eefe089b281 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
@@ -34,6 +34,7 @@
#include "dcn314/dcn314_hwseq.h"
#include "dcn314_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn314_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 9135b01fe388..369d77f6d8f6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -53,6 +53,7 @@
#include "../dcn20/dcn20_hwseq.h"
#include "dc_state_priv.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index b755df909871..7c95e1f928c1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -33,6 +33,7 @@
#include "dcn401/dcn401_hwseq.h"
#include "dml/dcn32/dcn32_fpu.h"
#include "dcn32_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn32_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index aa047b5b4939..cd904a28fa12 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -60,6 +60,7 @@
#include "dcn31/dcn31_hwseq.h"
#include "dcn20/dcn20_hwseq.h"
#include "dc_state_priv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index 2119a8e000e9..d16e58427132 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -36,6 +36,7 @@
#include "dcn35/dcn35_hwseq.h"
#include "dcn35_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn35_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
index 8720e47fb33a..5ffae3764894 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
@@ -28,6 +28,7 @@
#include "resource.h"
#include "dcn351_hwseq.h"
#include "dcn35/dcn35_hwseq.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger) \
struct dal_logger *dc_logger = logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index 0e148c6e5c50..a3c6219ff942 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -35,6 +35,7 @@
#include "dcn351/dcn351_hwseq.h"
#include "dcn351_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn351_funcs = {
.program_gamut_remap = dcn30_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 508749496826..bd31d6c2af48 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -41,6 +41,7 @@
#include "../hw_sequencer.h"
#include "dio/dcn10/dcn10_dio.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index 1e79b4945801..8bffcfe2b7b7 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -12,6 +12,7 @@
#include "dcn35/dcn35_hwseq.h"
#include "dcn401/dcn401_hwseq.h"
#include "dcn401_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn401_funcs = {
.program_gamut_remap = dcn401_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
index b1cc09df5e63..9e01cb85c010 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
@@ -36,6 +36,7 @@
#include "dcn35/dcn35_hwseq.h"
#include "dcn42/dcn42_hwseq.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define DC_LOGGER \
ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
index 00fcb2559247..80ba74138cab 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
@@ -14,6 +14,7 @@
#include "dcn401/dcn401_hwseq.h"
#include "dcn42/dcn42_hwseq.h"
#include "dcn42_init.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn42_funcs = {
.program_gamut_remap = dcn401_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
index 167f2e53e1f4..027cdd63913f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c
@@ -16,6 +16,7 @@
#include "opp.h"
#include "mpc.h"
#include "dcn42b_hwseq.h"
+#include "dc_priv.h"
#define CTX \
hws->ctx
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c
index 4210dc7a8eb4..209ae0dbc445 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_init.c
@@ -8,6 +8,7 @@
#include "dcn42/dcn42_init.h"
#include "dcn42b_hwseq.h"
#include "dcn42b_init.h"
+#include "dc_priv.h"
void dcn42b_hw_sequencer_init_functions(struct dc *dc)
{
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c
index 151ec838f613..7d9597ebf4f6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c
@@ -36,6 +36,7 @@
#include "dc_state_priv.h"
#include "link_enc_cfg.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
index f8254dfe1ce7..b3b4135c8af7 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
@@ -39,6 +39,7 @@
#include "dc_state_priv.h"
#include "link_enc_cfg.h"
#include "dio/dcn10/dcn10_dio.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c
index 9fde7d1be3e5..cf205f2c574c 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c
@@ -15,6 +15,7 @@
#include "dcn50/dcn50_hwseq.h"
#include "dcn60_init.h"
#include "dcn60_hwseq.h"
+#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn60_funcs = {
.program_gamut_remap = dcn401_program_gamut_remap,
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index 7f3084c6dd49..129a59dc171b 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -35,6 +35,7 @@
#include "ivsrcid/ivsrcid_vislands30.h"
#include "dc.h"
+#include "dc_priv.h"
#include "core_types.h"
#define DC_LOGGER \
irq_service->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index 83f676a49fd1..b2637ec27cd4 100644
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -35,6 +35,7 @@
#include "dc_dmub_srv.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "clk_mgr.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
index c8c55f196f8d..3a517e174b08 100644
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c
@@ -24,6 +24,7 @@
*/
#include "link_dp_trace.h"
#include "link/protocols/link_dpcd.h"
+#include "dc_priv.h"
void dp_trace_init(struct dc_link *link)
{
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
index befa67b2b2ae..bbbce6cb80b9 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
@@ -25,6 +25,7 @@
#include "link_hwss_dio.h"
#include "core_types.h"
#include "link_enc_cfg.h"
+#include "dc_priv.h"
/**
* DOC: overview
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
index e1dff4e3f446..846890a87826 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
@@ -25,6 +25,7 @@
#include "link_hwss_dio.h"
#include "link_hwss_dio_fixed_vs_pe_retimer.h"
#include "link_enc_cfg.h"
+#include "dc_priv.h"
uint8_t dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg(struct dc_link *link)
{
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
index 2a87b23582f3..8cede496ab4d 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c
@@ -26,6 +26,7 @@
#include "core_types.h"
#include "link_hwss_dio.h"
#include "link_enc_cfg.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
index 811048123401..cfff0029472c 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
@@ -27,6 +27,7 @@
#include "core_types.h"
#include "dccg.h"
#include "clk_mgr.h"
+#include "dc_priv.h"
#define DC_LOGGER link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
index 6d5b7450b205..4b706db98253 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
@@ -25,6 +25,7 @@
#include "link_hwss_hpo_dp.h"
#include "link_hwss_hpo_fixed_vs_pe_retimer_dp.h"
#include "link_hwss_dio_fixed_vs_pe_retimer.h"
+#include "dc_priv.h"
static void dp_hpo_fixed_vs_pe_retimer_set_tx_ffe(struct dc_link *link,
const struct dc_lane_settings *hw_lane_settings)
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c
index 62288133cd55..2ba3958d31b0 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_frl.c
@@ -25,6 +25,7 @@
#include "link_hwss_hpo_frl.h"
#include "core_types.h"
#include "link/hwss/link_hwss_virtual.h"
+#include "dc_priv.h"
static void setup_hpo_frl_stream_attribute(struct pipe_ctx *pipe_ctx)
{
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index b4546f93af0c..5f7b82b39239 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -48,6 +48,7 @@
#include "link_enc_cfg.h"
#include "dm_helpers.h"
#include "clk_mgr.h"
+#include "dc_priv.h"
// Offset DPCD 050Eh == 0x5A
#define MST_HUB_ID_0x5A 0x5A
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 75e232ebffe8..2aff967e73b9 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -58,6 +58,7 @@
#include "clk_mgr.h"
#include "atomfirmware.h"
#include "vpg.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 3b192c539f8b..93eec8a35dda 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -46,6 +46,7 @@
#include "protocols/link_hpd.h"
#include "gpio_service_interface.h"
#include "atomfirmware.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_resource.c b/drivers/gpu/drm/amd/display/dc/link/link_resource.c
index bd42bb273c0c..47659537bc68 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_resource.c
@@ -28,6 +28,7 @@
#include "link_resource.h"
#include "protocols/link_dp_capability.h"
+#include "dc_priv.h"
void link_get_cur_link_res(const struct dc_link *link,
struct link_resource *link_res)
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index d7bd352880b3..ab8a8c6807fe 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -33,6 +33,7 @@
#include "protocols/link_dp_dpia_bw.h"
#include "protocols/link_hdmi_frl.h"
#include "resource.h"
+#include "dc_priv.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
index db798656c8a8..15ff2c7d34de 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
@@ -38,6 +38,7 @@
#include "link_dpcd.h"
#include "dm_helpers.h"
#include "atomfirmware.h"
+#include "dc_priv.h"
#define DC_LOGGER \
ddc_service->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index c487c5b87dfd..c3f840b1a0ce 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -50,6 +50,7 @@
#include "link_enc_cfg.h"
#include "dc_dmub_srv.h"
#include "gpio_service_interface.h"
+#include "dc_priv.h"
#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
index f43fc4b78a8d..f5c4e815c404 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
@@ -29,6 +29,7 @@
#include "link_dp_dpia_bw.h"
#include "link_dpcd.h"
#include "dc_dmub_srv.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
index da679fb7d89c..a4c533ec638b 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
@@ -39,6 +39,7 @@
#include "link/link_dpms.h"
#include "dm_helpers.h"
#include "link_dp_dpia_bw.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
index 65a791ccf6b2..4b7b104bd3a8 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
@@ -30,6 +30,7 @@
#include "dm_helpers.h"
#include "dc/dc_dmub_srv.h"
#include "dce/dmub_replay.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
index 49521ac4b0e8..a3d923aff89c 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c
@@ -38,6 +38,7 @@
#include "resource.h"
#include "link_enc_cfg.h"
#include "atomfirmware.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index 3be36d1063de..2a0137759ef5 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -47,6 +47,7 @@
#include "link_enc_cfg.h"
#include "resource.h"
#include "dm_helpers.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
index 1a6bfc45927d..13b1ff756949 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
@@ -32,6 +32,7 @@
#include "link_dpcd.h"
#include "link_dp_phy.h"
#include "link_dp_capability.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
index 4331e032416f..e4c258434775 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
@@ -31,6 +31,7 @@
#include "link_dpcd.h"
#include "link_dp_phy.h"
#include "link_dp_capability.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
index 34fa76d97b83..f1817c7f0948 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
@@ -28,6 +28,7 @@
*/
#include "link_dp_training_dpia.h"
#include "dc.h"
+#include "dc_priv.h"
#include "inc/core_status.h"
#include "dpcd_defs.h"
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
index 6a7c4a59ff4c..08904bc2b500 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c
@@ -37,6 +37,7 @@
#include "link_dp_phy.h"
#include "link_dp_capability.h"
#include "link_ddc.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 0e9b2b675eac..f88fccf007c0 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -41,6 +41,7 @@
#include "abm.h"
#include "resource.h"
#include "link_dp_panel_replay.h"
+#include "dc_priv.h"
#define DC_LOGGER \
link->ctx->logger
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
index 960f18fe275b..7887d134eb28 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c
@@ -42,6 +42,7 @@
#include "dccg.h"
#include "dml/dml1_frl_cap_chk.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc_logger
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
index 905d4f23f92a..b637cdd3e6af 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c
@@ -27,6 +27,7 @@
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "mem_input.h"
#include "dcn10/dcn10_cm_common.h"
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
index f3213ecb1745..b0af7f219bd2 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
@@ -29,6 +29,7 @@
#include "basics/conversion.h"
#include "dcn10/dcn10_cm_common.h"
#include "dc.h"
+#include "dc_priv.h"
#define REG(reg)\
mpc30->mpc_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
index 61a1e3f06575..d8b8b8cd1bfc 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c
@@ -30,6 +30,7 @@
#include "basics/conversion.h"
#include "dcn10/dcn10_cm_common.h"
#include "dc.h"
+#include "dc_priv.h"
#define REG(reg)\
mpc30->mpc_regs->reg
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
index a485db71c166..2e2412d05a06 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c
@@ -25,6 +25,7 @@
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn401_mpc.h"
#include "dcn10/dcn10_cm_common.h"
#include "basics/conversion.h"
diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c
index 89c4d431a82c..de380c9caecf 100644
--- a/drivers/gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn60/dcn60_mpc.c
@@ -3,6 +3,7 @@
// Copyright 2025 Advanced Micro Devices, Inc.
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn60_mpc.h"
#include "dcn10/dcn10_cm_common.h"
#include "basics/conversion.h"
diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
index 98335a53ca52..7f0bd2cb6272 100644
--- a/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "dcn10_opp.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg) \
(oppn10->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
index 544ff2bf7100..89ad9096d356 100644
--- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "dcn20_opp.h"
#include "reg_helper.h"
+#include "dc_priv.h"
#define REG(reg) \
(oppn20->regs->reg)
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
index 90ec4cb8a9dd..8f345733105a 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
@@ -26,6 +26,7 @@
#include "reg_helper.h"
#include "dcn30_optc.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
index f9e05efcad98..447f37918527 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
@@ -29,6 +29,7 @@
#include "dcn31/dcn31_optc.h"
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
index 406446e5eae5..4e4f6f8b641f 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
@@ -31,6 +31,7 @@
#include "dcn32/dcn32_optc.h"
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
index 5fcdd74eb4a0..7ffb3a82cec5 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
@@ -8,6 +8,7 @@
#include "dcn32/dcn32_optc.h"
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
index 1e4f2051d732..7422c8602b0e 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c
@@ -10,6 +10,7 @@
#include "dcn401/dcn401_optc.h"
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn_calc_math.h"
#include "dc_dmub_srv.h"
#include "dc_trace.h"
diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
index 6e5ea1bbca02..15d09b11a573 100644
--- a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
@@ -28,6 +28,7 @@
#include "core_types.h"
#include "dcn35_pg_cntl.h"
#include "dccg.h"
+#include "dc_priv.h"
#define TO_DCN_PG_CNTL(pg_cntl)\
container_of(pg_cntl, struct dcn_pg_cntl, base)
diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
index e9125d2467fc..21a12a704611 100644
--- a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c
@@ -7,6 +7,7 @@
#include "dcn42_pg_cntl.h"
#include "dccg.h"
#include "resource.h"
+#include "dc_priv.h"
#define TO_DCN_PG_CNTL(pg_cntl)\
container_of(pg_cntl, struct dcn_pg_cntl, base)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
index 97ea22af5d2b..1cd90a68d774 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
@@ -62,6 +62,7 @@
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_8_2_d.h"
#include "gmc/gmc_8_2_sh_mask.h"
+#include "dc_priv.h"
#endif
#ifndef mmDP_DPHY_INTERNAL_CTRL
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
index 19252b25bce0..5f8365ffdf9c 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
@@ -66,6 +66,7 @@
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_8_2_d.h"
#include "gmc/gmc_8_2_sh_mask.h"
+#include "dc_priv.h"
#endif
#ifndef mmDP_DPHY_INTERNAL_CTRL
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
index 2da5d44e5203..dc73bd5528a2 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
@@ -58,6 +58,7 @@
#include "dce100/dce100_resource.h"
#include "dce112_resource.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
index 38d3b87529b0..21a7e176b92e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
@@ -68,6 +68,7 @@
#include "dce100/dce100_resource.h"
#include "link_service.h"
+#include "dc_priv.h"
#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
index 65c7dae3ff66..b8b1eda7ef46 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
@@ -66,6 +66,7 @@
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_6_0_d.h"
#include "gmc/gmc_6_0_sh_mask.h"
+#include "dc_priv.h"
#endif
#ifndef mmDP_DPHY_INTERNAL_CTRL
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
index 2f4de697ec4b..3d7162f82986 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
@@ -64,6 +64,7 @@
#endif
#include "dce80/dce80_resource.h"
+#include "dc_priv.h"
#ifndef mmDP_DPHY_INTERNAL_CTRL
#define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
index 37974c45b44a..47f6eeebb6f9 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
@@ -26,6 +26,7 @@
#include "core_status.h"
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn10/dcn10_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index 996fce26941f..979523c92074 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn20/dcn20_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
index 765c63513a31..f53467f1fe96 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn201/dcn201_init.h"
#include "dml/dcn20/dcn20_fpu.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
index 4095a850ebc6..5f82d6823857 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
@@ -28,6 +28,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn21/dcn21_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
index aecbcd28c2d9..88dc17b1e4d1 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn30/dcn30_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
index 29113f518c53..0008c8a2867b 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn301/dcn301_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
index f67b3e00bd86..ca47e743f5bb 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
@@ -78,6 +78,7 @@
#include "dpcs/dpcs_3_0_0_sh_mask.h"
#include "nbio/nbio_7_4_offset.h"
#include "amdgpu_socbb.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
index 9e1bf34cca2a..df7fbd6180f0 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
@@ -77,6 +77,7 @@
#include "nbio/nbio_2_3_offset.h"
#include "dml/dcn303/dcn303_fpu.h"
+#include "dc_priv.h"
#define DC_LOGGER \
dc->ctx->logger
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index 6359fbb574df..8fa3935df077 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
index 0ddfceca69dd..f6ef9e50110e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
@@ -27,6 +27,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
#include "dcn314/dcn314_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
index a1894be8cbb2..c34017e92242 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
index 4a2d56a196b4..66b02193551d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 619b9b3362fc..49c77d2c0fa1 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -27,6 +27,7 @@
#include "dc_types.h"
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
index 602a0e4e5dc0..9401709009e4 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
@@ -30,6 +30,7 @@
#include "dml/dcn32/dcn32_fpu.h"
#include "dc_state_priv.h"
#include "dc_stream_priv.h"
+#include "dc_priv.h"
static bool is_dual_plane(enum surface_pixel_format format)
{
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index 4097093d9012..5f5203324e5f 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 940dd00e97fa..a0bcba089b49 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -26,6 +26,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
#include "dcn35/dcn35_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index df2aaa46e70c..e8332badd11e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -4,6 +4,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
#include "dcn351/dcn351_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
index e8580f844af9..d517dbbd9558 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
@@ -3,6 +3,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn31/dcn31_init.h"
#include "dcn35/dcn35_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index b78b0541d113..ea7010f18ca0 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -4,6 +4,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
#include "dcn401/dcn401_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index 2ad191ec5c38..0214b6cc09a4 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -4,6 +4,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
#include "dcn42/dcn42_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
index 33b9775420d3..49fdd35454b8 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c
@@ -5,6 +5,7 @@
#include "dc.h"
+#include "dc_priv.h"
#include "dcn42_resource_fpu.h"
#define DC_LOGGER_INIT(logger)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
index e111e7532383..177d575f7fc1 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c
@@ -6,6 +6,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
#include "dcn42/dcn42_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn60/dcn60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn60/dcn60_resource.c
index fbaf4e2d31d1..2f09dfb6418c 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn60/dcn60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn60/dcn60_resource.c
@@ -5,6 +5,7 @@
#include "dm_services.h"
#include "dm_helpers.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn32/dcn32_init.h"
#include "dcn401/dcn401_init.h"
diff --git a/drivers/gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c b/drivers/gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c
index 952f0ade24a5..74fd0008ba62 100644
--- a/drivers/gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c
+++ b/drivers/gpu/drm/amd/display/dc/rmcm/dcn42/dcn42_rmcm.c
@@ -25,6 +25,7 @@
#include "reg_helper.h"
#include "dc.h"
+#include "dc_priv.h"
#include "dcn42_rmcm.h"
#include "dcn10/dcn10_cm_common.h"
#include "basics/conversion.h"
diff --git a/drivers/gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c b/drivers/gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c
index df4d6476d70a..5d7eb93a92d9 100644
--- a/drivers/gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c
+++ b/drivers/gpu/drm/amd/display/dc/rmcm/dcn60/dcn60_rmcm.c
@@ -25,6 +25,7 @@
#include "dm_services.h"
#include "dc.h"
+#include "dc_priv.h"
#include "reg_helper.h"
#include "dcn/dcn_6_0_0_offset.h"
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
index c3dfcf2a73e3..17516048a616 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
@@ -4,6 +4,7 @@
#include "dcn401_soc_and_ip_translator.h"
#include "bounding_boxes/dcn4_soc_bb.h"
+#include "dc_priv.h"
/* soc_and_ip_translator component used to get up-to-date values for bounding box.
* Bounding box values are stored in several locations and locations can vary with DCN revision.
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
index c6c1b19b7370..ba9a686ffda7 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
@@ -5,6 +5,7 @@
#include "dcn42_soc_and_ip_translator.h"
#include "../dcn401/dcn401_soc_and_ip_translator.h"
#include "bounding_boxes/dcn42_soc_bb.h"
+#include "dc_priv.h"
/* soc_and_ip_translator component used to get up-to-date values for bounding box.
* Bounding box values are stored in several locations and locations can vary with DCN revision.
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c
index aef527c7584b..6af8a70188fe 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn60/dcn60_soc_and_ip_translator.c
@@ -6,6 +6,7 @@
#include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h"
#include "bounding_boxes/dcn6_soc_bb.h"
#include "dal_asic_id.h"
+#include "dc_priv.h"
/* soc_and_ip_translator component used to get up-to-date values for bounding box.
* Bounding box values are stored in several locations and locations can vary with DCN revision.
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 14/19] drm/amd/display: Restrict the dc directory root to DC-internal builds
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
The dc directory root holds private headers (dc_priv.h and the other
*_priv.h / internal headers). Remove the global
-I(full-amd-display-path)/dc include flags from amdgpu/Makefile,
amdgpu_dm/Makefile and the amdgpu_dm tests so the root cannot be
reached from outside DC anymore; with this, including dc_priv.h from
DM or the DAL modules fails at compile time.
To keep the many "subdir/header.h" includes inside DC working, give
DC-internal objects the root on their include path through per-object
CFLAGS in dc/Makefile (same mechanism the DML Makefiles already use
for FPU flags) instead of a global ccflags-y entry.
Relocate the public dc-root headers to dc/inc, which was already the
exported interface directory:
dc.h, dc_types.h, dc_state.h, dc_plane.h, dc_probe.h,
dc_memory_pool.h, dc_ddc_types.h, dc_dp_types.h, dc_hdmi_types.h,
dc_hw_types.h, os_types.h, irq_types.h, dm_helpers.h,
dm_services.h, dm_services_types.h, dm_pp_smu.h, dc_dmub_srv.h,
dc_bios_types.h, dc_trace.h, dm_cp_psp.h, dc_fused_io.h,
dc_stat.h, dc_stream.h, dc_dsc.h
No includer outside DC needs to change: bare-name includes resolve
through the existing -Idc/inc. Fix the few headers that referenced
siblings through the old root-relative forms (angle-bracket
inc/hw/*.h includes, inc/, dml/, dml2_wrapper/, sspl/ prefixes), the
handful of DM and dmub path includes, and the dm_pp_smu.h include in
pm/swsmu.
Also drop an unused dcn20_resource.h include from
amdgpu_dm_mst_types.c that only worked by accident.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 1 -
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +++++++++---------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c | 2 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c | 6 +++---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c | 16 ++++++++--------
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +++---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 8 ++++----
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 6 +++---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 4 ++--
drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile | 1 -
.../display/amdgpu_dm/tests/amdgpu_dm_audio_test.c | 4 ++--
.../amdgpu_dm/tests/amdgpu_dm_backlight_test.c | 2 +-
.../amdgpu_dm/tests/amdgpu_dm_connector_test.c | 6 +++---
.../display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c | 8 ++++----
.../display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c | 6 +++---
.../amdgpu_dm/tests/amdgpu_dm_freesync_test.c | 2 +-
.../amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c | 6 +++---
.../amdgpu_dm/tests/amdgpu_dm_mst_types_test.c | 6 +++---
.../drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c | 4 ++--
drivers/gpu/drm/amd/display/dc/Makefile | 10 ++++++++++
.../display/dc/bls_builder/bls_builder_legacy_init.h | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 2 +-
drivers/gpu/drm/amd/display/dc/core2/dc_core2.h | 2 +-
.../drm/amd/display/dc/dc_api_dispatch/api_shim.c | 2 +-
.../drm/amd/display/dc/dc_api_dispatch/api_shim.h | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h | 2 +-
.../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 2 +-
.../drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 2 +-
.../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 16 ++++++++--------
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 8 ++++----
drivers/gpu/drm/amd/display/dc/{ => inc}/dc.h | 20 ++++++++++----------
.../gpu/drm/amd/display/dc/{ => inc}/dc_bios_types.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_ddc_types.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_dmub_srv.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_dp_types.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_dsc.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_fused_io.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_hdmi_types.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_hw_types.h | 0
.../drm/amd/display/dc/{ => inc}/dc_memory_pool.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_plane.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_probe.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_stat.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_state.h | 2 +-
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_stream.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_trace.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_types.h | 0
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +-
drivers/gpu/drm/amd/display/dc/{ => inc}/dm_cp_psp.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dm_helpers.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dm_pp_smu.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dm_services.h | 0
.../drm/amd/display/dc/{ => inc}/dm_services_types.h | 0
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 ++--
drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 ++--
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 2 +-
drivers/gpu/drm/amd/display/dc/{ => inc}/irq_types.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/os_types.h | 0
.../drm/amd/display/dc/link/protocols/link_dp_dpia.c | 2 +-
.../display/dc/link/protocols/link_dp_panel_replay.c | 2 +-
.../dc/link/protocols/link_dp_training_dpia.c | 2 +-
.../dc/link/protocols/link_edp_panel_control.c | 2 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 +-
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 2 +-
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 2 +-
drivers/gpu/drm/amd/display/modules/power/power.c | 2 +-
.../gpu/drm/amd/display/modules/power/power_abm.c | 2 +-
.../gpu/drm/amd/display/modules/power/power_psr.c | 2 +-
.../gpu/drm/amd/display/modules/power/power_replay.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
86 files changed, 130 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 8687afc00c24..55c89f8d764e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -39,7 +39,6 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_DISPLAY_PATH) \
-I$(FULL_AMD_DISPLAY_PATH)/include \
-I$(FULL_AMD_DISPLAY_PATH)/modules/inc \
- -I$(FULL_AMD_DISPLAY_PATH)/dc \
-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
-I$(FULL_AMD_PATH)/amdkfd \
-I$(FULL_AMD_PATH)/ras/ras_mgr
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3458b26846a1..cb122cb32905 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -30,19 +30,19 @@
#include "dm_services_types.h"
#include "dc.h"
#include "link_enc_cfg.h"
-#include "dc/inc/core_types.h"
+#include "core_types.h"
#include "dal_asic_id.h"
#include "dmub/dmub_srv.h"
-#include "dc/inc/hw/dmcu.h"
-#include "dc/inc/hw/abm.h"
-#include "dc/dc_dmub_srv.h"
-#include "dc/dc_stat.h"
-#include "dc/dc_state.h"
+#include "hw/dmcu.h"
+#include "hw/abm.h"
+#include "dc_dmub_srv.h"
+#include "dc_stat.h"
+#include "dc_state.h"
#include "amdgpu_dm_trace.h"
-#include "link/protocols/link_dpcd.h"
+#include "dc/link/protocols/link_dpcd.h"
#include "link_service_types.h"
-#include "link/protocols/link_dp_capability.h"
-#include "link/protocols/link_ddc.h"
+#include "dc/link/protocols/link_dp_capability.h"
+#include "dc/link/protocols/link_ddc.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
index 97cc52f45a2e..23392b229679 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
@@ -36,7 +36,7 @@
#include <drm/drm_edid.h>
#include <drm/drm_eld.h>
-#include "dc/inc/core_types.h"
+#include "core_types.h"
static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
int pipe, bool *enabled,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
index 3d268703c551..194e52fdd9f5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
@@ -24,9 +24,9 @@
*/
#include "dc.h"
-#include "dc/dc_dmub_srv.h"
-#include "dc/dc_state.h"
-#include "dc/dc_stat.h"
+#include "dc_dmub_srv.h"
+#include "dc_state.h"
+#include "dc_stat.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index 134d08207a14..d1a672c721c4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -26,16 +26,16 @@
#include "dm_services_types.h"
#include "dc.h"
-#include "dc/dc_dmub_srv.h"
-#include "dc/dc_stat.h"
-#include "dc/dc_state.h"
-#include "dc/dc_stream.h"
-#include "dc/inc/core_types.h"
+#include "dc_dmub_srv.h"
+#include "dc_stat.h"
+#include "dc_state.h"
+#include "dc_stream.h"
+#include "core_types.h"
#include "link_enc_cfg.h"
-#include "link/protocols/link_dpcd.h"
+#include "dc/link/protocols/link_dpcd.h"
#include "link_service_types.h"
-#include "link/protocols/link_dp_capability.h"
-#include "link/protocols/link_ddc.h"
+#include "dc/link/protocols/link_dp_capability.h"
+#include "dc/link/protocols/link_ddc.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index fddb47a32fb9..8d7ebb636554 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -39,9 +39,9 @@
#include "resource.h"
#include "dsc.h"
#include "link_hwss.h"
-#include "dc/dc_dmub_srv.h"
-#include "link/protocols/link_dp_capability.h"
-#include "inc/hw/dchubbub.h"
+#include "dc_dmub_srv.h"
+#include "dc/link/protocols/link_dp_capability.h"
+#include "dc/inc/hw/dchubbub.h"
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
#include "amdgpu_dm_psr.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index af2cda9080d9..ffe561da24d6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -26,11 +26,11 @@
#include "dm_services_types.h"
#include "dc.h"
-#include "dc/inc/core_types.h"
-#include "dc/dc_dmub_srv.h"
+#include "core_types.h"
+#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
-#include "dc/inc/hw/dmcu.h"
-#include "dc/inc/hw/abm.h"
+#include "hw/dmcu.h"
+#include "hw/abm.h"
#include "dal_asic_id.h"
#include "amdgpu.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 02a8cfde9f1a..b5b3269f3d97 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -43,7 +43,7 @@
#include "amdgpu_dm_irq.h"
#include "amdgpu_dm_mst_types.h"
#include "dpcd_defs.h"
-#include "dc/inc/core_types.h"
+#include "core_types.h"
#include "dm_helpers.h"
#include "ddc_service_types.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 5c3b83f05d2b..57e1dcf6bb45 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -26,8 +26,8 @@
#include "dm_services_types.h"
#include "dc.h"
-#include "dc/dc_dmub_srv.h"
-#include "dc/dc_stat.h"
+#include "dc_dmub_srv.h"
+#include "dc_stat.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
@@ -39,7 +39,7 @@
#include "amdgpu_dm_mst_types.h"
#include "amdgpu_dm_dmub.h"
#include "amdgpu_dm_trace.h"
-#include "link/protocols/link_dpcd.h"
+#include "dc/link/protocols/link_dpcd.h"
#include "link_service_types.h"
#include "ivsrcid/ivsrcid_vislands30.h"
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 2cbe08298706..4f9070579916 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -39,6 +39,7 @@
#include "amdgpu_dm_hdcp.h"
#include "dc.h"
+#include "core_types.h"
#include "dm_helpers.h"
#include "ddc_service_types.h"
@@ -48,7 +49,6 @@
#include "amdgpu_dm_debugfs.h"
#endif
-#include "dc/resource/dcn20/dcn20_resource.h"
#define PEAK_FACTOR_X1000 1006
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
index 6441212f93a1..40b8d60642b6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
@@ -30,7 +30,7 @@
#include "amdgpu_dm.h"
#include "modules/power/power_helpers.h"
#include "dmub/inc/dmub_cmd.h"
-#include "dc/inc/link_service.h"
+#include "link_service.h"
#include "dm_helpers.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
index 9027933cec3f..a1452e58ad73 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
@@ -38,9 +38,9 @@
#include <drm/drm_framebuffer.h>
#include <drm/drm_encoder.h>
#include <drm/drm_atomic.h>
-#include "dc/inc/hw/optc.h"
+#include "hw/optc.h"
-#include "dc/inc/core_types.h"
+#include "core_types.h"
DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,
TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile
index e0549c04c62e..6b953d8fe826 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile
@@ -8,7 +8,6 @@ ccflags-y += -I$(src)/..
ccflags-y += -I$(src)/../..
ccflags-y += -I$(src)/../../include
ccflags-y += -I$(src)/../../modules/inc
-ccflags-y += -I$(src)/../../dc
ccflags-y += -I$(src)/../../../amdgpu
ccflags-y += -I$(src)/../../../amdkfd
ccflags-y += -I$(src)/../../../include
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
index c2ed369f3ca2..56a2afc114b8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
@@ -19,8 +19,8 @@
#include "dc.h"
#include "dc_test.h"
-#include "dc/inc/core_types.h"
-#include "dc/inc/hw/audio.h"
+#include "core_types.h"
+#include "hw/audio.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
index 377b92d84b98..5b8660c938c9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
@@ -24,7 +24,7 @@
#include "amdgpu_dm_kunit_test_helpers.h"
#include "amd_shared.h"
#include "link_service.h"
-#include "dc/inc/hw/panel_cntl.h"
+#include "hw/panel_cntl.h"
struct dm_backlight_connector_fixture {
struct amdgpu_device *adev;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
index 94bb2181d141..44c7324642b5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
@@ -34,9 +34,9 @@
#include "amdgpu_dm_psr.h"
#include "include/grph_object_id.h"
#include "amdgpu_dm_kunit_test_helpers.h"
-#include "inc/link_service.h"
-#include "inc/resource.h"
-#include "inc/hw/timing_generator.h"
+#include "link_service.h"
+#include "resource.h"
+#include "dc/inc/hw/timing_generator.h"
/* Tests for get_subconnector_type() */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
index 96cf015a12d9..c4f703980d1e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
@@ -14,10 +14,10 @@
#include "dc.h"
#include "dc_test.h"
-#include "inc/core_types.h"
-#include "irq/irq_service.h"
-#include "inc/hw/timing_generator.h"
-#include "inc/link_service.h"
+#include "core_types.h"
+#include "dc/irq/irq_service.h"
+#include "dc/inc/hw/timing_generator.h"
+#include "link_service.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
index 449fb6d94f75..b71e1e11e85a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
@@ -11,9 +11,9 @@
#include "dc.h"
#include "dc_test.h"
#include "amdgpu_dm_kunit_test_helpers.h"
-#include "dc/inc/core_types.h"
-#include "dc/inc/hw/dmcu.h"
-#include "dc/inc/hw/abm.h"
+#include "core_types.h"
+#include "hw/dmcu.h"
+#include "hw/abm.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
#include "dal_asic_id.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
index b751c64d88aa..467267d4bcc4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
@@ -14,7 +14,7 @@
#include "dc.h"
#include "dc_test.h"
-#include "inc/core_types.h"
+#include "core_types.h"
#include "amd_shared.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
index b64d63fe15fd..ea467ca45af8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
@@ -16,9 +16,9 @@
#include "dc.h"
#include "dc_test.h"
-#include "inc/core_types.h"
-#include "inc/hw/timing_generator.h"
-#include "irq/irq_service.h"
+#include "core_types.h"
+#include "dc/inc/hw/timing_generator.h"
+#include "dc/irq/irq_service.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
index b8ea85846872..144cb03f504a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
@@ -32,9 +32,9 @@
#include "amdgpu_dm_hdcp.h"
#include "amdgpu_dm_mst_types.h"
#include "amdgpu_dm_kunit_test_helpers.h"
-#include "dsc/dsc.h"
-#include "inc/core_types.h"
-#include "inc/link_service.h"
+#include "dc/dsc/dsc.h"
+#include "core_types.h"
+#include "link_service.h"
/*
* Minimal mock DPCD backing store and AUX transfer callback used to exercise
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
index c0dbab0b7c46..8cf460a4cb9f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
@@ -23,11 +23,11 @@
#include "dc.h"
#include "dc_test.h"
-#include "dc/dc_dmub_srv.h"
+#include "dc_dmub_srv.h"
#include "dal_asic_id.h"
#include "dm_services_types.h"
#include "dmub/dmub_srv.h"
-#include "inc/core_types.h"
+#include "core_types.h"
#include "logger_types.h"
#include "amd_shared.h"
#include "amdgpu.h"
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 440f5d358188..c0fc7f7d241d 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -98,3 +98,13 @@ endif
AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/, $(FILES))
+# The dc directory root holds private headers (dc_priv.h and friends) that
+# must not be reachable outside DC, so the global include path deliberately
+# stops at dc/inc. DC-internal objects still need the root on their include
+# path for the many "subdir/header.h" includes inside DC, so add it per
+# object instead of through a global ccflags-y entry.
+DC_INTERNAL_OBJS := $(filter $(AMDDALPATH)/dc/%,$(AMD_DISPLAY_FILES))
+$(foreach obj,$(DC_INTERNAL_OBJS),\
+ $(eval CFLAGS_$(obj) += -I$(FULL_AMD_DISPLAY_PATH)/dc))
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder_legacy_init.h b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder_legacy_init.h
index e9259699a9c0..bb8fe97fa8f2 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder_legacy_init.h
+++ b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder_legacy_init.h
@@ -8,7 +8,7 @@
#include "dmub_cmd.h"
#include "grph_object_ctrl_defs.h"
#include "bios_parser_types.h"
-#include "inc/hw/hw_shared.h"
+#include "hw/hw_shared.h"
/*
* DC2_DC1_Wrapped hardware init: dcn401_init_hw as twelve BLS stages.
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
index 1758c0b9390b..92466b7664aa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
@@ -22,7 +22,7 @@
* Authors: AMD
*/
-#include "dc/dc_stat.h"
+#include "dc_stat.h"
#include "dmub/dmub_srv_stat.h"
#include "dc_dmub_srv.h"
#include "dc_priv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core2/dc_core2.h b/drivers/gpu/drm/amd/display/dc/core2/dc_core2.h
index a761e85a9973..a7fd4dcf66d8 100644
--- a/drivers/gpu/drm/amd/display/dc/core2/dc_core2.h
+++ b/drivers/gpu/drm/amd/display/dc/core2/dc_core2.h
@@ -5,7 +5,7 @@
#pragma once
-#include "inc/dc_core_interface.h"
+#include "dc_core_interface.h"
struct dc;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.c b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.c
index 3dcfde8308c5..8a90898f5d06 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.c
@@ -7,7 +7,7 @@
#include "dc.h"
#include "dc_api_dispatch/api_shim.h"
#include "core2/dc_core2.h"
-#include "inc/dc_core_interface.h"
+#include "dc_core_interface.h"
void api_shim_construct(struct dc *dc, const struct dc_init_data *init_params)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
index 7802a18b8caa..88d4e2bfa1be 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
@@ -7,7 +7,7 @@
#include "dc.h"
#include "dc_priv.h"
-#include "inc/dc_core_interface.h"
+#include "dc_core_interface.h"
#include "bls_builder/dmub_abi.h"
struct dc2 {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index b2153cb03b51..2e3f9bcc8a51 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -27,7 +27,7 @@
#define __DAL_AUX_ENGINE_DCE110_H__
#include "gpio_service_interface.h"
-#include "inc/hw/aux_engine.h"
+#include "hw/aux_engine.h"
enum aux_return_code_type;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h
index 535fd58de450..0949dd0b5bcb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h
@@ -26,7 +26,7 @@
#ifndef __DCE_I2C_H__
#define __DCE_I2C_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dce_i2c_hw.h"
#include "dce_i2c_sw.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 277c9e169a1f..3dd0e2ef9b80 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -29,7 +29,7 @@
/* TODO: this needs to be looked at, used by Stella's workaround*/
#include "include/logger_interface.h"
-#include "inc/dce_calcs.h"
+#include "dce_calcs.h"
#include "dce/dce_mem_input.h"
#include "dce110_mem_input_v.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
index 37b608ee7ca9..f788c6e7ee52 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
@@ -28,7 +28,7 @@
#include "dcn30/dcn30_afmt.h"
#include "dcn31_afmt.h"
#include "reg_helper.h"
-#include "dc/dc.h"
+#include "dc.h"
#include "dc_priv.h"
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
index a453cc24d82a..ecf30239e0e7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
@@ -27,7 +27,7 @@
#include "dcn30/dcn30_vpg.h"
#include "dcn31_vpg.h"
#include "reg_helper.h"
-#include "dc/dc.h"
+#include "dc.h"
#include "dc_priv.h"
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
index 442830726b38..85fc7c729d46 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
@@ -27,7 +27,7 @@
#include "dce110/dce110_hwseq.h"
#include "dcn10/dcn10_hwseq.h"
#include "dcn20/dcn20_hwseq.h"
-#include "dc/hwss/dce/dce_hwseq.h"
+#include "hwss/dce/dce_hwseq.h"
#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn10_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 90a05af35782..da18577621df 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -53,7 +53,7 @@
#include "dce/dmub_hw_lock_mgr.h"
#include "hw_sequencer.h"
#include "dpcd_defs.h"
-#include "inc/link_enc_cfg.h"
+#include "link_enc_cfg.h"
#include "link_hwss.h"
#include "link_service.h"
#include "dc_state_priv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index f5b96c86ca59..347e23a0cf8f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -49,7 +49,7 @@
#include "link_service.h"
#include "dcn10/dcn10_hwseq.h"
#include "dcn21/dcn21_hwseq.h"
-#include "inc/link_enc_cfg.h"
+#include "link_enc_cfg.h"
#include "dcn30/dcn30_vpg.h"
#include "dce/dce_i2c_hw.h"
#include "dce/dmub_abm_lcd.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index d57f5be5c57f..c0b4e2f62ff1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -48,7 +48,7 @@
#include "dce/dmub_outbox.h"
#include "link_service.h"
#include "dcn10/dcn10_hwseq.h"
-#include "inc/link_enc_cfg.h"
+#include "link_enc_cfg.h"
#include "dcn30/dcn30_vpg.h"
#include "dce/dce_i2c_hw.h"
#include "dsc.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index cd904a28fa12..9f0279d251d9 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -50,7 +50,7 @@
#include "link_service.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "dcn10/dcn10_hwseq.h"
-#include "inc/link_enc_cfg.h"
+#include "link_enc_cfg.h"
#include "dcn30/dcn30_vpg.h"
#include "dce/dce_i2c_hw.h"
#include "dsc.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index 0ae2f44cfb9f..75d09525f014 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -27,7 +27,7 @@
#ifndef __DC_HWSS_DCN35_H__
#define __DC_HWSS_DCN35_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dc.h"
#include "hw_sequencer_private.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index fef0dd59a81f..f80113ebbd0c 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -5,7 +5,7 @@
#ifndef __DC_HWSS_DCN401_H__
#define __DC_HWSS_DCN401_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dc.h"
#include "dc_stream.h"
#include "hw_sequencer_private.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h
index 79b5a4794ac1..2ea189421fb4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h
@@ -5,7 +5,7 @@
#ifndef __DC_HWSS_DCN50_H__
#define __DC_HWSS_DCN50_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dc.h"
#include "dc_stream.h"
#include "hw_sequencer_private.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h
index b880988ff1fc..8f66f9b1854e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h
@@ -5,7 +5,7 @@
#ifndef __DC_HWSS_DCN60_H__
#define __DC_HWSS_DCN60_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dc.h"
#include "dc_stream.h"
#include "hw_sequencer_private.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 6580d13d9041..401b3982a14a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -26,14 +26,14 @@
#ifndef __DC_HW_SEQUENCER_H__
#define __DC_HW_SEQUENCER_H__
#include "dc_types.h"
-#include "inc/clock_source.h"
-#include "inc/hw/timing_generator.h"
-#include "inc/hw/opp.h"
-#include "inc/hw/link_encoder.h"
-#include "inc/core_status.h"
-#include "inc/hw/hw_shared.h"
-#include "inc/hw/dchubbub.h"
-#include "dsc/dsc.h"
+#include "clock_source.h"
+#include "hw/timing_generator.h"
+#include "hw/opp.h"
+#include "hw/link_encoder.h"
+#include "core_status.h"
+#include "hw/hw_shared.h"
+#include "hw/dchubbub.h"
+#include "../dsc/dsc.h"
#include "link_service_types.h"
#include "dmub/inc/dmub_cmd.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 695eaa5cbf65..16145c863cd9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -40,9 +40,9 @@
#include "mcif_wb.h"
#include "panel_cntl.h"
#include "dmub/inc/dmub_cmd.h"
-#include "bls_builder/bls_builder_legacy_init.h"
+#include "../bls_builder/bls_builder_legacy_init.h"
#include "pg_cntl.h"
-#include "sspl/dc_spl.h"
+#include "../sspl/dc_spl.h"
#define MAX_CLOCK_SOURCES 7
#define MAX_SVP_PHANTOM_STREAMS 2
@@ -61,8 +61,8 @@
#include "transform.h"
#include "dpp.h"
-#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
-#include "dml2_0/dml21/inc/dml_top_types.h"
+#include "../dml2_0/dml21/inc/dml_top_dchub_registers.h"
+#include "../dml2_0/dml21/inc/dml_top_types.h"
struct resource_pool;
struct dc_state;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
similarity index 99%
rename from drivers/gpu/drm/amd/display/dc/dc.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc.h
index d976425c190b..d20180a449d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -37,22 +37,22 @@
#include "gpio_types.h"
#include "link_service_types.h"
#include "grph_object_ctrl_defs.h"
-#include <inc/hw/opp.h>
-#include <inc/hw/rmcm.h>
+#include "hw/opp.h"
+#include "hw/rmcm.h"
-#include "hwss/hw_sequencer.h"
-#include "inc/compressor.h"
-#include "inc/hw/dmcu.h"
-#include "dml/display_mode_lib.h"
+#include "../hwss/hw_sequencer.h"
+#include "compressor.h"
+#include "hw/dmcu.h"
+#include "../dml/display_mode_lib.h"
-#include "dml2_wrapper/dml2_wrapper.h"
+#include "../dml2_wrapper/dml2_wrapper.h"
#include "dmub/inc/dmub_cmd.h"
-#include "dml/dml1_frl_cap_chk.h"
+#include "../dml/dml1_frl_cap_chk.h"
-#include "sspl/dc_spl_types.h"
-#include "inc/dc_core_interface.h"
+#include "../sspl/dc_spl_types.h"
+#include "dc_core_interface.h"
struct abm_save_restore;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_bios_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_bios_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_bios_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_ddc_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_ddc_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/inc/dc_dmub_srv.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_dmub_srv.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_dp_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_dp_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_dp_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_dsc.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_dsc.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_dsc.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_fused_io.h b/drivers/gpu/drm/amd/display/dc/inc/dc_fused_io.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_fused_io.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_fused_io.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_hdmi_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_hdmi_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_hw_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_hw_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_hw_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_memory_pool.h b/drivers/gpu/drm/amd/display/dc/inc/dc_memory_pool.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_memory_pool.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_memory_pool.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_plane.h b/drivers/gpu/drm/amd/display/dc/inc/dc_plane.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_plane.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_plane.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_probe.h b/drivers/gpu/drm/amd/display/dc/inc/dc_probe.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_probe.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_probe.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stat.h b/drivers/gpu/drm/amd/display/dc/inc/dc_stat.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_stat.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_stat.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_state.h b/drivers/gpu/drm/amd/display/dc/inc/dc_state.h
similarity index 99%
rename from drivers/gpu/drm/amd/display/dc/dc_state.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_state.h
index acf461225e9d..a8c7296b17e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_state.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_state.h
@@ -26,7 +26,7 @@
#ifndef _DC_STATE_H_
#define _DC_STATE_H_
-#include "inc/core_status.h"
+#include "core_status.h"
struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params);
void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/inc/dc_stream.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_stream.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_stream.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_trace.h b/drivers/gpu/drm/amd/display/dc/inc/dc_trace.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_trace.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_trace.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
index 134091d5842d..845dc8ccd636 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
@@ -31,7 +31,7 @@
#define __DCN_CALCS_H__
#include "bw_fixed.h"
-#include "dml/display_mode_lib.h"
+#include "../dml/display_mode_lib.h"
struct dc;
diff --git a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h b/drivers/gpu/drm/amd/display/dc/inc/dm_cp_psp.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_cp_psp.h
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/inc/dm_helpers.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_helpers.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_helpers.h
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/inc/dm_pp_smu.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_pp_smu.h
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/inc/dm_services.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_services.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_services.h
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/inc/dm_services_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_services_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_services_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index b33273b61abd..030b1ccd90d9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -33,7 +33,7 @@
* blocks for the Data Fabric Interface that are not clock/power gated.
*/
-#include "dc/dc_hw_types.h"
+#include "dc_hw_types.h"
enum dcc_control {
dcc_control__256_256_xxx,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index d1cbcb87d271..6eade7556ffa 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -41,8 +41,8 @@
#include "mem_input.h"
#include "cursor_reg_cache.h"
-#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
-#include "dml2_0/dml21/inc/dml_top_types.h"
+#include "../../dml2_0/dml21/inc/dml_top_dchub_registers.h"
+#include "../../dml2_0/dml21/inc/dml_top_types.h"
#define OPP_ID_INVALID 0xf
#define MAX_TTU 0xffffff
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
index aae0ad7ae835..ad267dc9e505 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
@@ -27,7 +27,7 @@
#include "dc_hw_types.h"
-#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
+#include "../../dml2_0/dml21/inc/dml_top_dchub_registers.h"
enum mmhubbub_wbif_mode {
PACKED_444 = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index d468bc85566a..bb7eed3ddb90 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -28,8 +28,8 @@
#include "dc.h"
#include "include/grph_object_id.h"
-#include "dml/display_mode_structs.h"
-#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
+#include "../../dml/display_mode_structs.h"
+#include "../../dml2_0/dml21/inc/dml_top_dchub_registers.h"
struct dchub_init_data;
struct cstate_pstate_watermarks_st {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index d67373ec8e36..38f6bdd57dc7 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -29,7 +29,7 @@
#include "hw_shared.h"
#include "dc_hw_types.h"
#include "fixed31_32.h"
-#include "sspl/dc_spl_types.h"
+#include "../sspl/dc_spl_types.h"
#define CSC_TEMPERATURE_MATRIX_SIZE 12
diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/inc/irq_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/irq_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/irq_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/inc/os_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/os_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/os_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
index da227889e007..b41e6ad65710 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
@@ -25,7 +25,7 @@
*/
#include "dc.h"
-#include "inc/core_status.h"
+#include "core_status.h"
#include "dpcd_defs.h"
#include "link_dp_dpia.h"
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
index 4b7b104bd3a8..e7b9b735de18 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
@@ -28,7 +28,7 @@
#include "link_ddc.h"
#include "link_dpcd.h"
#include "dm_helpers.h"
-#include "dc/dc_dmub_srv.h"
+#include "dc_dmub_srv.h"
#include "dce/dmub_replay.h"
#include "dc_priv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
index f1817c7f0948..fb972358ecc1 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
@@ -29,7 +29,7 @@
#include "link_dp_training_dpia.h"
#include "dc.h"
#include "dc_priv.h"
-#include "inc/core_status.h"
+#include "core_status.h"
#include "dpcd_defs.h"
#include "link_dp_dpia.h"
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index f88fccf007c0..7d6b8759cb1a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -36,7 +36,7 @@
#include "dal_asic_id.h"
#include "link_dp_phy.h"
#include "dce/dmub_psr.h"
-#include "dc/dc_dmub_srv.h"
+#include "dc_dmub_srv.h"
#include "dce/dmub_replay.h"
#include "abm.h"
#include "resource.h"
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 84f825c924bc..75aaf507d0b7 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -66,7 +66,7 @@
*/
#include "inc/dmub_cmd.h"
-#include "dc/dc_types.h"
+#include "dc_types.h"
#define DMUB_PC_SNAPSHOT_COUNT 10
#define DMUB_TRACE_SNAPSHOT_COUNT 8
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index 0d585dc63364..0911e1e139c1 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -26,7 +26,7 @@
#include "../dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn32.h"
-#include "dc/dc_types.h"
+#include "dc_types.h"
#include "dc_hw_types.h"
#include "dcn/dcn_3_2_0_offset.h"
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index bd7637276aa6..19573e2f48d1 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -27,7 +27,7 @@
#include "dc_types.h"
#include "dmub_reg.h"
#include "dmub_dcn35.h"
-#include "dc/dc_types.h"
+#include "dc_types.h"
#include "dcn/dcn_3_5_0_offset.h"
#include "dcn/dcn_3_5_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c
index 884279696a2d..32c00a515d4f 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power.c
@@ -30,7 +30,7 @@
#include "dmcu.h"
#include "abm.h"
#include "power_helpers.h"
-#include "dce/dmub_psr.h"
+#include "dc/dce/dmub_psr.h"
#include "dal_asic_id.h"
#include "link_service.h"
#include <linux/math.h>
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
index 2b420eac5c56..6dabd30b4956 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_abm.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
@@ -9,7 +9,7 @@
#include "dmcu.h"
#include "abm.h"
#include "power_helpers.h"
-#include "dce/dmub_psr.h"
+#include "dc/dce/dmub_psr.h"
#include "dal_asic_id.h"
#include "link_service.h"
#include <linux/math.h>
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
index af59cf502297..219b199350cd 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_psr.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
@@ -9,7 +9,7 @@
#include "dmcu.h"
#include "abm.h"
#include "power_helpers.h"
-#include "dce/dmub_psr.h"
+#include "dc/dce/dmub_psr.h"
#include "dal_asic_id.h"
#include "link_service.h"
#include <linux/math.h>
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_replay.c b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
index d68f14b18179..ccadbe07f302 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_replay.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
@@ -9,7 +9,7 @@
#include "dmcu.h"
#include "abm.h"
#include "power_helpers.h"
-#include "dce/dmub_psr.h"
+#include "dc/dce/dmub_psr.h"
#include "dal_asic_id.h"
#include "link_service.h"
#include <linux/math.h>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 4e6dc9d41256..d0c0534a7e73 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -28,7 +28,7 @@
#include "amdgpu.h"
#include "kgd_pp_interface.h"
#include "dm_pp_interface.h"
-#include "dm_pp_smu.h"
+#include "dc/inc/dm_pp_smu.h"
#include "smu_types.h"
#include "linux/firmware.h"
#include <linux/ktime.h>
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 14/19] drm/amd/display: Restrict the dc directory root to DC-internal builds
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
The dc directory root holds private headers (dc_priv.h and the other
*_priv.h / internal headers). Remove the global
-I(full-amd-display-path)/dc include flags from amdgpu/Makefile,
amdgpu_dm/Makefile and the amdgpu_dm tests so the root cannot be
reached from outside DC anymore; with this, including dc_priv.h from
DM or the DAL modules fails at compile time.
To keep the many "subdir/header.h" includes inside DC working, give
DC-internal objects the root on their include path through per-object
CFLAGS in dc/Makefile (same mechanism the DML Makefiles already use
for FPU flags) instead of a global ccflags-y entry.
Relocate the public dc-root headers to dc/inc, which was already the
exported interface directory:
dc.h, dc_types.h, dc_state.h, dc_plane.h, dc_probe.h,
dc_memory_pool.h, dc_ddc_types.h, dc_dp_types.h, dc_hdmi_types.h,
dc_hw_types.h, os_types.h, irq_types.h, dm_helpers.h,
dm_services.h, dm_services_types.h, dm_pp_smu.h, dc_dmub_srv.h,
dc_bios_types.h, dc_trace.h, dm_cp_psp.h, dc_fused_io.h,
dc_stat.h, dc_stream.h, dc_dsc.h
No includer outside DC needs to change: bare-name includes resolve
through the existing -Idc/inc. Fix the few headers that referenced
siblings through the old root-relative forms (angle-bracket
inc/hw/*.h includes, inc/, dml/, dml2_wrapper/, sspl/ prefixes), the
handful of DM and dmub path includes, and the dm_pp_smu.h include in
pm/swsmu.
Also drop an unused dcn20_resource.h include from
amdgpu_dm_mst_types.c that only worked by accident.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 1 -
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +++++++++---------
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c | 2 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c | 6 +++---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c | 16 ++++++++--------
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +++---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 8 ++++----
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 6 +++---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 4 ++--
drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile | 1 -
.../display/amdgpu_dm/tests/amdgpu_dm_audio_test.c | 4 ++--
.../amdgpu_dm/tests/amdgpu_dm_backlight_test.c | 2 +-
.../amdgpu_dm/tests/amdgpu_dm_connector_test.c | 6 +++---
.../display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c | 8 ++++----
.../display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c | 6 +++---
.../amdgpu_dm/tests/amdgpu_dm_freesync_test.c | 2 +-
.../amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c | 6 +++---
.../amdgpu_dm/tests/amdgpu_dm_mst_types_test.c | 6 +++---
.../drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c | 4 ++--
drivers/gpu/drm/amd/display/dc/Makefile | 10 ++++++++++
.../display/dc/bls_builder/bls_builder_legacy_init.h | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 2 +-
drivers/gpu/drm/amd/display/dc/core2/dc_core2.h | 2 +-
.../drm/amd/display/dc/dc_api_dispatch/api_shim.c | 2 +-
.../drm/amd/display/dc/dc_api_dispatch/api_shim.h | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 2 +-
drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h | 2 +-
.../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 2 +-
.../drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 2 +-
.../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 16 ++++++++--------
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 8 ++++----
drivers/gpu/drm/amd/display/dc/{ => inc}/dc.h | 20 ++++++++++----------
.../gpu/drm/amd/display/dc/{ => inc}/dc_bios_types.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_ddc_types.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_dmub_srv.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_dp_types.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_dsc.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_fused_io.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_hdmi_types.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dc_hw_types.h | 0
.../drm/amd/display/dc/{ => inc}/dc_memory_pool.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_plane.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_probe.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_stat.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_state.h | 2 +-
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_stream.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_trace.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dc_types.h | 0
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 2 +-
drivers/gpu/drm/amd/display/dc/{ => inc}/dm_cp_psp.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dm_helpers.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/dm_pp_smu.h | 0
.../gpu/drm/amd/display/dc/{ => inc}/dm_services.h | 0
.../drm/amd/display/dc/{ => inc}/dm_services_types.h | 0
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 ++--
drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 ++--
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 2 +-
drivers/gpu/drm/amd/display/dc/{ => inc}/irq_types.h | 0
drivers/gpu/drm/amd/display/dc/{ => inc}/os_types.h | 0
.../drm/amd/display/dc/link/protocols/link_dp_dpia.c | 2 +-
.../display/dc/link/protocols/link_dp_panel_replay.c | 2 +-
.../dc/link/protocols/link_dp_training_dpia.c | 2 +-
.../dc/link/protocols/link_edp_panel_control.c | 2 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 +-
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 2 +-
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 2 +-
drivers/gpu/drm/amd/display/modules/power/power.c | 2 +-
.../gpu/drm/amd/display/modules/power/power_abm.c | 2 +-
.../gpu/drm/amd/display/modules/power/power_psr.c | 2 +-
.../gpu/drm/amd/display/modules/power/power_replay.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
86 files changed, 130 insertions(+), 122 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 8687afc00c24..55c89f8d764e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -39,7 +39,6 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_DISPLAY_PATH) \
-I$(FULL_AMD_DISPLAY_PATH)/include \
-I$(FULL_AMD_DISPLAY_PATH)/modules/inc \
- -I$(FULL_AMD_DISPLAY_PATH)/dc \
-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
-I$(FULL_AMD_PATH)/amdkfd \
-I$(FULL_AMD_PATH)/ras/ras_mgr
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3458b26846a1..cb122cb32905 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -30,19 +30,19 @@
#include "dm_services_types.h"
#include "dc.h"
#include "link_enc_cfg.h"
-#include "dc/inc/core_types.h"
+#include "core_types.h"
#include "dal_asic_id.h"
#include "dmub/dmub_srv.h"
-#include "dc/inc/hw/dmcu.h"
-#include "dc/inc/hw/abm.h"
-#include "dc/dc_dmub_srv.h"
-#include "dc/dc_stat.h"
-#include "dc/dc_state.h"
+#include "hw/dmcu.h"
+#include "hw/abm.h"
+#include "dc_dmub_srv.h"
+#include "dc_stat.h"
+#include "dc_state.h"
#include "amdgpu_dm_trace.h"
-#include "link/protocols/link_dpcd.h"
+#include "dc/link/protocols/link_dpcd.h"
#include "link_service_types.h"
-#include "link/protocols/link_dp_capability.h"
-#include "link/protocols/link_ddc.h"
+#include "dc/link/protocols/link_dp_capability.h"
+#include "dc/link/protocols/link_ddc.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
index 97cc52f45a2e..23392b229679 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
@@ -36,7 +36,7 @@
#include <drm/drm_edid.h>
#include <drm/drm_eld.h>
-#include "dc/inc/core_types.h"
+#include "core_types.h"
static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
int pipe, bool *enabled,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
index 3d268703c551..194e52fdd9f5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
@@ -24,9 +24,9 @@
*/
#include "dc.h"
-#include "dc/dc_dmub_srv.h"
-#include "dc/dc_state.h"
-#include "dc/dc_stat.h"
+#include "dc_dmub_srv.h"
+#include "dc_state.h"
+#include "dc_stat.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index 134d08207a14..d1a672c721c4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -26,16 +26,16 @@
#include "dm_services_types.h"
#include "dc.h"
-#include "dc/dc_dmub_srv.h"
-#include "dc/dc_stat.h"
-#include "dc/dc_state.h"
-#include "dc/dc_stream.h"
-#include "dc/inc/core_types.h"
+#include "dc_dmub_srv.h"
+#include "dc_stat.h"
+#include "dc_state.h"
+#include "dc_stream.h"
+#include "core_types.h"
#include "link_enc_cfg.h"
-#include "link/protocols/link_dpcd.h"
+#include "dc/link/protocols/link_dpcd.h"
#include "link_service_types.h"
-#include "link/protocols/link_dp_capability.h"
-#include "link/protocols/link_ddc.h"
+#include "dc/link/protocols/link_dp_capability.h"
+#include "dc/link/protocols/link_ddc.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index fddb47a32fb9..8d7ebb636554 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -39,9 +39,9 @@
#include "resource.h"
#include "dsc.h"
#include "link_hwss.h"
-#include "dc/dc_dmub_srv.h"
-#include "link/protocols/link_dp_capability.h"
-#include "inc/hw/dchubbub.h"
+#include "dc_dmub_srv.h"
+#include "dc/link/protocols/link_dp_capability.h"
+#include "dc/inc/hw/dchubbub.h"
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
#include "amdgpu_dm_psr.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index af2cda9080d9..ffe561da24d6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -26,11 +26,11 @@
#include "dm_services_types.h"
#include "dc.h"
-#include "dc/inc/core_types.h"
-#include "dc/dc_dmub_srv.h"
+#include "core_types.h"
+#include "dc_dmub_srv.h"
#include "dmub/dmub_srv.h"
-#include "dc/inc/hw/dmcu.h"
-#include "dc/inc/hw/abm.h"
+#include "hw/dmcu.h"
+#include "hw/abm.h"
#include "dal_asic_id.h"
#include "amdgpu.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 02a8cfde9f1a..b5b3269f3d97 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -43,7 +43,7 @@
#include "amdgpu_dm_irq.h"
#include "amdgpu_dm_mst_types.h"
#include "dpcd_defs.h"
-#include "dc/inc/core_types.h"
+#include "core_types.h"
#include "dm_helpers.h"
#include "ddc_service_types.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 5c3b83f05d2b..57e1dcf6bb45 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -26,8 +26,8 @@
#include "dm_services_types.h"
#include "dc.h"
-#include "dc/dc_dmub_srv.h"
-#include "dc/dc_stat.h"
+#include "dc_dmub_srv.h"
+#include "dc_stat.h"
#include "amdgpu.h"
#include "amdgpu_display.h"
@@ -39,7 +39,7 @@
#include "amdgpu_dm_mst_types.h"
#include "amdgpu_dm_dmub.h"
#include "amdgpu_dm_trace.h"
-#include "link/protocols/link_dpcd.h"
+#include "dc/link/protocols/link_dpcd.h"
#include "link_service_types.h"
#include "ivsrcid/ivsrcid_vislands30.h"
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 2cbe08298706..4f9070579916 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -39,6 +39,7 @@
#include "amdgpu_dm_hdcp.h"
#include "dc.h"
+#include "core_types.h"
#include "dm_helpers.h"
#include "ddc_service_types.h"
@@ -48,7 +49,6 @@
#include "amdgpu_dm_debugfs.h"
#endif
-#include "dc/resource/dcn20/dcn20_resource.h"
#define PEAK_FACTOR_X1000 1006
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
index 6441212f93a1..40b8d60642b6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
@@ -30,7 +30,7 @@
#include "amdgpu_dm.h"
#include "modules/power/power_helpers.h"
#include "dmub/inc/dmub_cmd.h"
-#include "dc/inc/link_service.h"
+#include "link_service.h"
#include "dm_helpers.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
index 9027933cec3f..a1452e58ad73 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
@@ -38,9 +38,9 @@
#include <drm/drm_framebuffer.h>
#include <drm/drm_encoder.h>
#include <drm/drm_atomic.h>
-#include "dc/inc/hw/optc.h"
+#include "hw/optc.h"
-#include "dc/inc/core_types.h"
+#include "core_types.h"
DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,
TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile
index e0549c04c62e..6b953d8fe826 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/Makefile
@@ -8,7 +8,6 @@ ccflags-y += -I$(src)/..
ccflags-y += -I$(src)/../..
ccflags-y += -I$(src)/../../include
ccflags-y += -I$(src)/../../modules/inc
-ccflags-y += -I$(src)/../../dc
ccflags-y += -I$(src)/../../../amdgpu
ccflags-y += -I$(src)/../../../amdkfd
ccflags-y += -I$(src)/../../../include
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
index c2ed369f3ca2..56a2afc114b8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_audio_test.c
@@ -19,8 +19,8 @@
#include "dc.h"
#include "dc_test.h"
-#include "dc/inc/core_types.h"
-#include "dc/inc/hw/audio.h"
+#include "core_types.h"
+#include "hw/audio.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
index 377b92d84b98..5b8660c938c9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_backlight_test.c
@@ -24,7 +24,7 @@
#include "amdgpu_dm_kunit_test_helpers.h"
#include "amd_shared.h"
#include "link_service.h"
-#include "dc/inc/hw/panel_cntl.h"
+#include "hw/panel_cntl.h"
struct dm_backlight_connector_fixture {
struct amdgpu_device *adev;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
index 94bb2181d141..44c7324642b5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
@@ -34,9 +34,9 @@
#include "amdgpu_dm_psr.h"
#include "include/grph_object_id.h"
#include "amdgpu_dm_kunit_test_helpers.h"
-#include "inc/link_service.h"
-#include "inc/resource.h"
-#include "inc/hw/timing_generator.h"
+#include "link_service.h"
+#include "resource.h"
+#include "dc/inc/hw/timing_generator.h"
/* Tests for get_subconnector_type() */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
index 96cf015a12d9..c4f703980d1e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
@@ -14,10 +14,10 @@
#include "dc.h"
#include "dc_test.h"
-#include "inc/core_types.h"
-#include "irq/irq_service.h"
-#include "inc/hw/timing_generator.h"
-#include "inc/link_service.h"
+#include "core_types.h"
+#include "dc/irq/irq_service.h"
+#include "dc/inc/hw/timing_generator.h"
+#include "link_service.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
index 449fb6d94f75..b71e1e11e85a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
@@ -11,9 +11,9 @@
#include "dc.h"
#include "dc_test.h"
#include "amdgpu_dm_kunit_test_helpers.h"
-#include "dc/inc/core_types.h"
-#include "dc/inc/hw/dmcu.h"
-#include "dc/inc/hw/abm.h"
+#include "core_types.h"
+#include "hw/dmcu.h"
+#include "hw/abm.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
#include "dal_asic_id.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
index b751c64d88aa..467267d4bcc4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_freesync_test.c
@@ -14,7 +14,7 @@
#include "dc.h"
#include "dc_test.h"
-#include "inc/core_types.h"
+#include "core_types.h"
#include "amd_shared.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
index b64d63fe15fd..ea467ca45af8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
@@ -16,9 +16,9 @@
#include "dc.h"
#include "dc_test.h"
-#include "inc/core_types.h"
-#include "inc/hw/timing_generator.h"
-#include "irq/irq_service.h"
+#include "core_types.h"
+#include "dc/inc/hw/timing_generator.h"
+#include "dc/irq/irq_service.h"
#include "amdgpu.h"
#include "amdgpu_mode.h"
#include "amdgpu_dm.h"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
index b8ea85846872..144cb03f504a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
@@ -32,9 +32,9 @@
#include "amdgpu_dm_hdcp.h"
#include "amdgpu_dm_mst_types.h"
#include "amdgpu_dm_kunit_test_helpers.h"
-#include "dsc/dsc.h"
-#include "inc/core_types.h"
-#include "inc/link_service.h"
+#include "dc/dsc/dsc.h"
+#include "core_types.h"
+#include "link_service.h"
/*
* Minimal mock DPCD backing store and AUX transfer callback used to exercise
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
index c0dbab0b7c46..8cf460a4cb9f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
@@ -23,11 +23,11 @@
#include "dc.h"
#include "dc_test.h"
-#include "dc/dc_dmub_srv.h"
+#include "dc_dmub_srv.h"
#include "dal_asic_id.h"
#include "dm_services_types.h"
#include "dmub/dmub_srv.h"
-#include "inc/core_types.h"
+#include "core_types.h"
#include "logger_types.h"
#include "amd_shared.h"
#include "amdgpu.h"
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 440f5d358188..c0fc7f7d241d 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -98,3 +98,13 @@ endif
AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/, $(FILES))
+# The dc directory root holds private headers (dc_priv.h and friends) that
+# must not be reachable outside DC, so the global include path deliberately
+# stops at dc/inc. DC-internal objects still need the root on their include
+# path for the many "subdir/header.h" includes inside DC, so add it per
+# object instead of through a global ccflags-y entry.
+DC_INTERNAL_OBJS := $(filter $(AMDDALPATH)/dc/%,$(AMD_DISPLAY_FILES))
+$(foreach obj,$(DC_INTERNAL_OBJS),\
+ $(eval CFLAGS_$(obj) += -I$(FULL_AMD_DISPLAY_PATH)/dc))
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder_legacy_init.h b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder_legacy_init.h
index e9259699a9c0..bb8fe97fa8f2 100644
--- a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder_legacy_init.h
+++ b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder_legacy_init.h
@@ -8,7 +8,7 @@
#include "dmub_cmd.h"
#include "grph_object_ctrl_defs.h"
#include "bios_parser_types.h"
-#include "inc/hw/hw_shared.h"
+#include "hw/hw_shared.h"
/*
* DC2_DC1_Wrapped hardware init: dcn401_init_hw as twelve BLS stages.
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
index 1758c0b9390b..92466b7664aa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c
@@ -22,7 +22,7 @@
* Authors: AMD
*/
-#include "dc/dc_stat.h"
+#include "dc_stat.h"
#include "dmub/dmub_srv_stat.h"
#include "dc_dmub_srv.h"
#include "dc_priv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core2/dc_core2.h b/drivers/gpu/drm/amd/display/dc/core2/dc_core2.h
index a761e85a9973..a7fd4dcf66d8 100644
--- a/drivers/gpu/drm/amd/display/dc/core2/dc_core2.h
+++ b/drivers/gpu/drm/amd/display/dc/core2/dc_core2.h
@@ -5,7 +5,7 @@
#pragma once
-#include "inc/dc_core_interface.h"
+#include "dc_core_interface.h"
struct dc;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.c b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.c
index 3dcfde8308c5..8a90898f5d06 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.c
@@ -7,7 +7,7 @@
#include "dc.h"
#include "dc_api_dispatch/api_shim.h"
#include "core2/dc_core2.h"
-#include "inc/dc_core_interface.h"
+#include "dc_core_interface.h"
void api_shim_construct(struct dc *dc, const struct dc_init_data *init_params)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
index 7802a18b8caa..88d4e2bfa1be 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_api_dispatch/api_shim.h
@@ -7,7 +7,7 @@
#include "dc.h"
#include "dc_priv.h"
-#include "inc/dc_core_interface.h"
+#include "dc_core_interface.h"
#include "bls_builder/dmub_abi.h"
struct dc2 {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index b2153cb03b51..2e3f9bcc8a51 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -27,7 +27,7 @@
#define __DAL_AUX_ENGINE_DCE110_H__
#include "gpio_service_interface.h"
-#include "inc/hw/aux_engine.h"
+#include "hw/aux_engine.h"
enum aux_return_code_type;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h
index 535fd58de450..0949dd0b5bcb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h
@@ -26,7 +26,7 @@
#ifndef __DCE_I2C_H__
#define __DCE_I2C_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dce_i2c_hw.h"
#include "dce_i2c_sw.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 277c9e169a1f..3dd0e2ef9b80 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -29,7 +29,7 @@
/* TODO: this needs to be looked at, used by Stella's workaround*/
#include "include/logger_interface.h"
-#include "inc/dce_calcs.h"
+#include "dce_calcs.h"
#include "dce/dce_mem_input.h"
#include "dce110_mem_input_v.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
index 37b608ee7ca9..f788c6e7ee52 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.c
@@ -28,7 +28,7 @@
#include "dcn30/dcn30_afmt.h"
#include "dcn31_afmt.h"
#include "reg_helper.h"
-#include "dc/dc.h"
+#include "dc.h"
#include "dc_priv.h"
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
index a453cc24d82a..ecf30239e0e7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c
@@ -27,7 +27,7 @@
#include "dcn30/dcn30_vpg.h"
#include "dcn31_vpg.h"
#include "reg_helper.h"
-#include "dc/dc.h"
+#include "dc.h"
#include "dc_priv.h"
#define DC_LOGGER \
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
index 442830726b38..85fc7c729d46 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
@@ -27,7 +27,7 @@
#include "dce110/dce110_hwseq.h"
#include "dcn10/dcn10_hwseq.h"
#include "dcn20/dcn20_hwseq.h"
-#include "dc/hwss/dce/dce_hwseq.h"
+#include "hwss/dce/dce_hwseq.h"
#include "dc_priv.h"
static const struct hw_sequencer_funcs dcn10_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 90a05af35782..da18577621df 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -53,7 +53,7 @@
#include "dce/dmub_hw_lock_mgr.h"
#include "hw_sequencer.h"
#include "dpcd_defs.h"
-#include "inc/link_enc_cfg.h"
+#include "link_enc_cfg.h"
#include "link_hwss.h"
#include "link_service.h"
#include "dc_state_priv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index f5b96c86ca59..347e23a0cf8f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -49,7 +49,7 @@
#include "link_service.h"
#include "dcn10/dcn10_hwseq.h"
#include "dcn21/dcn21_hwseq.h"
-#include "inc/link_enc_cfg.h"
+#include "link_enc_cfg.h"
#include "dcn30/dcn30_vpg.h"
#include "dce/dce_i2c_hw.h"
#include "dce/dmub_abm_lcd.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index d57f5be5c57f..c0b4e2f62ff1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -48,7 +48,7 @@
#include "dce/dmub_outbox.h"
#include "link_service.h"
#include "dcn10/dcn10_hwseq.h"
-#include "inc/link_enc_cfg.h"
+#include "link_enc_cfg.h"
#include "dcn30/dcn30_vpg.h"
#include "dce/dce_i2c_hw.h"
#include "dsc.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index cd904a28fa12..9f0279d251d9 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -50,7 +50,7 @@
#include "link_service.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "dcn10/dcn10_hwseq.h"
-#include "inc/link_enc_cfg.h"
+#include "link_enc_cfg.h"
#include "dcn30/dcn30_vpg.h"
#include "dce/dce_i2c_hw.h"
#include "dsc.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index 0ae2f44cfb9f..75d09525f014 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -27,7 +27,7 @@
#ifndef __DC_HWSS_DCN35_H__
#define __DC_HWSS_DCN35_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dc.h"
#include "hw_sequencer_private.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index fef0dd59a81f..f80113ebbd0c 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -5,7 +5,7 @@
#ifndef __DC_HWSS_DCN401_H__
#define __DC_HWSS_DCN401_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dc.h"
#include "dc_stream.h"
#include "hw_sequencer_private.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h
index 79b5a4794ac1..2ea189421fb4 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.h
@@ -5,7 +5,7 @@
#ifndef __DC_HWSS_DCN50_H__
#define __DC_HWSS_DCN50_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dc.h"
#include "dc_stream.h"
#include "hw_sequencer_private.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h
index b880988ff1fc..8f66f9b1854e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h
@@ -5,7 +5,7 @@
#ifndef __DC_HWSS_DCN60_H__
#define __DC_HWSS_DCN60_H__
-#include "inc/core_types.h"
+#include "core_types.h"
#include "dc.h"
#include "dc_stream.h"
#include "hw_sequencer_private.h"
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 6580d13d9041..401b3982a14a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -26,14 +26,14 @@
#ifndef __DC_HW_SEQUENCER_H__
#define __DC_HW_SEQUENCER_H__
#include "dc_types.h"
-#include "inc/clock_source.h"
-#include "inc/hw/timing_generator.h"
-#include "inc/hw/opp.h"
-#include "inc/hw/link_encoder.h"
-#include "inc/core_status.h"
-#include "inc/hw/hw_shared.h"
-#include "inc/hw/dchubbub.h"
-#include "dsc/dsc.h"
+#include "clock_source.h"
+#include "hw/timing_generator.h"
+#include "hw/opp.h"
+#include "hw/link_encoder.h"
+#include "core_status.h"
+#include "hw/hw_shared.h"
+#include "hw/dchubbub.h"
+#include "../dsc/dsc.h"
#include "link_service_types.h"
#include "dmub/inc/dmub_cmd.h"
#include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 695eaa5cbf65..16145c863cd9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -40,9 +40,9 @@
#include "mcif_wb.h"
#include "panel_cntl.h"
#include "dmub/inc/dmub_cmd.h"
-#include "bls_builder/bls_builder_legacy_init.h"
+#include "../bls_builder/bls_builder_legacy_init.h"
#include "pg_cntl.h"
-#include "sspl/dc_spl.h"
+#include "../sspl/dc_spl.h"
#define MAX_CLOCK_SOURCES 7
#define MAX_SVP_PHANTOM_STREAMS 2
@@ -61,8 +61,8 @@
#include "transform.h"
#include "dpp.h"
-#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
-#include "dml2_0/dml21/inc/dml_top_types.h"
+#include "../dml2_0/dml21/inc/dml_top_dchub_registers.h"
+#include "../dml2_0/dml21/inc/dml_top_types.h"
struct resource_pool;
struct dc_state;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
similarity index 99%
rename from drivers/gpu/drm/amd/display/dc/dc.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc.h
index d976425c190b..d20180a449d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -37,22 +37,22 @@
#include "gpio_types.h"
#include "link_service_types.h"
#include "grph_object_ctrl_defs.h"
-#include <inc/hw/opp.h>
-#include <inc/hw/rmcm.h>
+#include "hw/opp.h"
+#include "hw/rmcm.h"
-#include "hwss/hw_sequencer.h"
-#include "inc/compressor.h"
-#include "inc/hw/dmcu.h"
-#include "dml/display_mode_lib.h"
+#include "../hwss/hw_sequencer.h"
+#include "compressor.h"
+#include "hw/dmcu.h"
+#include "../dml/display_mode_lib.h"
-#include "dml2_wrapper/dml2_wrapper.h"
+#include "../dml2_wrapper/dml2_wrapper.h"
#include "dmub/inc/dmub_cmd.h"
-#include "dml/dml1_frl_cap_chk.h"
+#include "../dml/dml1_frl_cap_chk.h"
-#include "sspl/dc_spl_types.h"
-#include "inc/dc_core_interface.h"
+#include "../sspl/dc_spl_types.h"
+#include "dc_core_interface.h"
struct abm_save_restore;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_bios_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_bios_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_bios_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_ddc_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_ddc_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/inc/dc_dmub_srv.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_dmub_srv.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_dp_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_dp_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_dp_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_dsc.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_dsc.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_dsc.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_fused_io.h b/drivers/gpu/drm/amd/display/dc/inc/dc_fused_io.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_fused_io.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_fused_io.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_hdmi_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_hdmi_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_hw_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_hw_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_hw_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_memory_pool.h b/drivers/gpu/drm/amd/display/dc/inc/dc_memory_pool.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_memory_pool.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_memory_pool.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_plane.h b/drivers/gpu/drm/amd/display/dc/inc/dc_plane.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_plane.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_plane.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_probe.h b/drivers/gpu/drm/amd/display/dc/inc/dc_probe.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_probe.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_probe.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stat.h b/drivers/gpu/drm/amd/display/dc/inc/dc_stat.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_stat.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_stat.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_state.h b/drivers/gpu/drm/amd/display/dc/inc/dc_state.h
similarity index 99%
rename from drivers/gpu/drm/amd/display/dc/dc_state.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_state.h
index acf461225e9d..a8c7296b17e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_state.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_state.h
@@ -26,7 +26,7 @@
#ifndef _DC_STATE_H_
#define _DC_STATE_H_
-#include "inc/core_status.h"
+#include "core_status.h"
struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params);
void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/inc/dc_stream.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_stream.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_stream.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_trace.h b/drivers/gpu/drm/amd/display/dc/inc/dc_trace.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_trace.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_trace.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/inc/dc_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dc_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dc_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
index 134091d5842d..845dc8ccd636 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
@@ -31,7 +31,7 @@
#define __DCN_CALCS_H__
#include "bw_fixed.h"
-#include "dml/display_mode_lib.h"
+#include "../dml/display_mode_lib.h"
struct dc;
diff --git a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h b/drivers/gpu/drm/amd/display/dc/inc/dm_cp_psp.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_cp_psp.h
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/inc/dm_helpers.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_helpers.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_helpers.h
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/inc/dm_pp_smu.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_pp_smu.h
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/inc/dm_services.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_services.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_services.h
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/inc/dm_services_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dm_services_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/dm_services_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index b33273b61abd..030b1ccd90d9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -33,7 +33,7 @@
* blocks for the Data Fabric Interface that are not clock/power gated.
*/
-#include "dc/dc_hw_types.h"
+#include "dc_hw_types.h"
enum dcc_control {
dcc_control__256_256_xxx,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index d1cbcb87d271..6eade7556ffa 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -41,8 +41,8 @@
#include "mem_input.h"
#include "cursor_reg_cache.h"
-#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
-#include "dml2_0/dml21/inc/dml_top_types.h"
+#include "../../dml2_0/dml21/inc/dml_top_dchub_registers.h"
+#include "../../dml2_0/dml21/inc/dml_top_types.h"
#define OPP_ID_INVALID 0xf
#define MAX_TTU 0xffffff
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
index aae0ad7ae835..ad267dc9e505 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
@@ -27,7 +27,7 @@
#include "dc_hw_types.h"
-#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
+#include "../../dml2_0/dml21/inc/dml_top_dchub_registers.h"
enum mmhubbub_wbif_mode {
PACKED_444 = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index d468bc85566a..bb7eed3ddb90 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -28,8 +28,8 @@
#include "dc.h"
#include "include/grph_object_id.h"
-#include "dml/display_mode_structs.h"
-#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
+#include "../../dml/display_mode_structs.h"
+#include "../../dml2_0/dml21/inc/dml_top_dchub_registers.h"
struct dchub_init_data;
struct cstate_pstate_watermarks_st {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index d67373ec8e36..38f6bdd57dc7 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -29,7 +29,7 @@
#include "hw_shared.h"
#include "dc_hw_types.h"
#include "fixed31_32.h"
-#include "sspl/dc_spl_types.h"
+#include "../sspl/dc_spl_types.h"
#define CSC_TEMPERATURE_MATRIX_SIZE 12
diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/inc/irq_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/irq_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/irq_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/inc/os_types.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/os_types.h
rename to drivers/gpu/drm/amd/display/dc/inc/os_types.h
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
index da227889e007..b41e6ad65710 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
@@ -25,7 +25,7 @@
*/
#include "dc.h"
-#include "inc/core_status.h"
+#include "core_status.h"
#include "dpcd_defs.h"
#include "link_dp_dpia.h"
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
index 4b7b104bd3a8..e7b9b735de18 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
@@ -28,7 +28,7 @@
#include "link_ddc.h"
#include "link_dpcd.h"
#include "dm_helpers.h"
-#include "dc/dc_dmub_srv.h"
+#include "dc_dmub_srv.h"
#include "dce/dmub_replay.h"
#include "dc_priv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
index f1817c7f0948..fb972358ecc1 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c
@@ -29,7 +29,7 @@
#include "link_dp_training_dpia.h"
#include "dc.h"
#include "dc_priv.h"
-#include "inc/core_status.h"
+#include "core_status.h"
#include "dpcd_defs.h"
#include "link_dp_dpia.h"
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index f88fccf007c0..7d6b8759cb1a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -36,7 +36,7 @@
#include "dal_asic_id.h"
#include "link_dp_phy.h"
#include "dce/dmub_psr.h"
-#include "dc/dc_dmub_srv.h"
+#include "dc_dmub_srv.h"
#include "dce/dmub_replay.h"
#include "abm.h"
#include "resource.h"
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 84f825c924bc..75aaf507d0b7 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -66,7 +66,7 @@
*/
#include "inc/dmub_cmd.h"
-#include "dc/dc_types.h"
+#include "dc_types.h"
#define DMUB_PC_SNAPSHOT_COUNT 10
#define DMUB_TRACE_SNAPSHOT_COUNT 8
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index 0d585dc63364..0911e1e139c1 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -26,7 +26,7 @@
#include "../dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn32.h"
-#include "dc/dc_types.h"
+#include "dc_types.h"
#include "dc_hw_types.h"
#include "dcn/dcn_3_2_0_offset.h"
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index bd7637276aa6..19573e2f48d1 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -27,7 +27,7 @@
#include "dc_types.h"
#include "dmub_reg.h"
#include "dmub_dcn35.h"
-#include "dc/dc_types.h"
+#include "dc_types.h"
#include "dcn/dcn_3_5_0_offset.h"
#include "dcn/dcn_3_5_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c
index 884279696a2d..32c00a515d4f 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power.c
@@ -30,7 +30,7 @@
#include "dmcu.h"
#include "abm.h"
#include "power_helpers.h"
-#include "dce/dmub_psr.h"
+#include "dc/dce/dmub_psr.h"
#include "dal_asic_id.h"
#include "link_service.h"
#include <linux/math.h>
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
index 2b420eac5c56..6dabd30b4956 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_abm.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
@@ -9,7 +9,7 @@
#include "dmcu.h"
#include "abm.h"
#include "power_helpers.h"
-#include "dce/dmub_psr.h"
+#include "dc/dce/dmub_psr.h"
#include "dal_asic_id.h"
#include "link_service.h"
#include <linux/math.h>
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
index af59cf502297..219b199350cd 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_psr.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
@@ -9,7 +9,7 @@
#include "dmcu.h"
#include "abm.h"
#include "power_helpers.h"
-#include "dce/dmub_psr.h"
+#include "dc/dce/dmub_psr.h"
#include "dal_asic_id.h"
#include "link_service.h"
#include <linux/math.h>
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_replay.c b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
index d68f14b18179..ccadbe07f302 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_replay.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
@@ -9,7 +9,7 @@
#include "dmcu.h"
#include "abm.h"
#include "power_helpers.h"
-#include "dce/dmub_psr.h"
+#include "dc/dce/dmub_psr.h"
#include "dal_asic_id.h"
#include "link_service.h"
#include <linux/math.h>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 4e6dc9d41256..d0c0534a7e73 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -28,7 +28,7 @@
#include "amdgpu.h"
#include "kgd_pp_interface.h"
#include "dm_pp_interface.h"
-#include "dm_pp_smu.h"
+#include "dc/inc/dm_pp_smu.h"
#include "smu_types.h"
#include "linux/firmware.h"
#include <linux/ktime.h>
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 14/19] drm/amd/display: Restrict the dc directory root to DC-internal builds
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 2:08 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 2:08 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found 3 potential
issues to consider:
- [High] drm/amdgpu: build failure with CONFIG_DRM_AMD_DC=n due to
missing dc/inc path
- [Medium] drm/amd/display: dc root include flag left in
amdgpu_dm/Makefile
- [Low] drm/amd/display: stale dc.h path in display-manager.rst
kernel-doc directives
--
commit a3254d30f8e563b4854ad67277856c56f8a96107
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display: Restrict the dc directory root to DC-internal builds
This commit moves public headers from drivers/gpu/drm/amd/display/dc/ into
drivers/gpu/drm/amd/display/dc/inc/ and restricts the dc root include path
to DC-internal objects.
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 8687afc00c24c..55c89f8d764e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -39,7 +39,6 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
> -I$(FULL_AMD_DISPLAY_PATH) \
> -I$(FULL_AMD_DISPLAY_PATH)/include \
> -I$(FULL_AMD_DISPLAY_PATH)/modules/inc \
> - -I$(FULL_AMD_DISPLAY_PATH)/dc \
> -I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
> -I$(FULL_AMD_PATH)/amdkfd \
> -I$(FULL_AMD_PATH)/ras/ras_mgr
[Severity: High]
Does removing -I$(FULL_AMD_DISPLAY_PATH)/dc without replacing it with
-I$(FULL_AMD_DISPLAY_PATH)/dc/inc break the build when CONFIG_DRM_AMD_DC is
disabled?
-I$(FULL_AMD_DISPLAY_PATH)/dc/inc/ is only added in
drivers/gpu/drm/amd/display/Makefile, which is included conditionally on
CONFIG_DRM_AMD_DC. However, drivers/gpu/drm/amd/amdgpu/amdgpu.h
unconditionally includes dm_pp_interface.h and amdgpu_dm.h, which pull in
dm_services_types.h, os_types.h, dc_types.h, irq_types.h, and dm_services.h
that this patch moves into dc/inc/.
[ ... ]
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
> index 440f5d3581887..c0fc7f7d241d8 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -98,3 +98,13 @@ endif
>
> AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/, $(FILES))
>
> +# The dc directory root holds private headers (dc_priv.h and friends) that
> +# must not be reachable outside DC, so the global include path deliberately
> +# stops at dc/inc. DC-internal objects still need the root on their include
> +# path for the many "subdir/header.h" includes inside DC, so add it per
> +# object instead of through a global ccflags-y entry.
> +DC_INTERNAL_OBJS := $(filter $(AMDDALPATH)/dc/%,$(AMD_DISPLAY_FILES))
> +$(foreach obj,$(DC_INTERNAL_OBJS),\
> + $(eval CFLAGS_$(obj) += -I$(FULL_AMD_DISPLAY_PATH)/dc))
> +
> +
[Severity: Medium]
Does drivers/gpu/drm/amd/display/amdgpu_dm/Makefile still export the dc
root include path globally?
The commit message notes that -I$(FULL_AMD_DISPLAY_PATH)/dc is removed from
amdgpu_dm/Makefile, but that file is not modified by this patch and still
has:
drivers/gpu/drm/amd/display/amdgpu_dm/Makefile:
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc
Because drivers/gpu/drm/amd/display/Makefile includes amdgpu_dm/Makefile in
the top-level amdgpu build, Kbuild adds subdir-ccflags-y to KBUILD_CFLAGS
for all objects in amdgpu, amdgpu_dm, DAL modules, and tests, leaving
dc_priv.h and other dc root headers reachable outside DC.
[ ... ]
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
> similarity index 99%
> rename from drivers/gpu/drm/amd/display/dc/dc.h
> rename to drivers/gpu/drm/amd/display/dc/inc/dc.h
[Severity: Low]
Should Documentation/gpu/amdgpu/display/display-manager.rst also be updated
for the new path of dc.h? It has two kernel-doc directives that still
reference drivers/gpu/drm/amd/display/dc/dc.h, which will cause htmldocs
builds to fail to locate the file.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=14
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 15/19] drm/amd/display: Add dc_force_max_dramclk for the DP compliance workaround
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
The DP compliance test pattern workaround in
dm_helpers_dp_handle_test_pattern_request() reached into the clock
manager (dc_get_clk_mgr) to read the softmax memory clock limits and
to invoke the clock update. Move the whole sequence into DC as
dc_force_max_dramclk() and drop the dc_get_clk_mgr accessor; no code
outside DC references struct clk_mgr anymore.
Part of making the struct dc sub-structures opaque outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 10 +---------
.../display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c | 1 -
drivers/gpu/drm/amd/display/dc/core/dc.c | 23 ++++++++++++++++++++++
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 5 -----
drivers/gpu/drm/amd/display/dc/inc/dc.h | 8 ++++++--
5 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index b5b3269f3d97..542f9c4cb7e4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -1559,7 +1559,6 @@ bool dm_helpers_dp_handle_test_pattern_request(
struct amdgpu_dm_connector *aconnector = link->priv;
struct drm_device *dev = aconnector->base.dev;
struct dc_state *dc_state = dc_get_current_state(ctx->dc);
- struct clk_mgr *clk_mgr = dc_get_clk_mgr(ctx->dc);
int i;
for (i = 0; i < MAX_PIPES; i++) {
@@ -1661,14 +1660,7 @@ bool dm_helpers_dp_handle_test_pattern_request(
pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;
/* Temp W/A for compliance test failure */
- dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;
- dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?
- clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;
- dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;
- dc_get_clk_mgr(ctx->dc)->funcs->update_clocks(
- dc_get_clk_mgr(ctx->dc),
- dc_state,
- false);
+ dc_force_max_dramclk(ctx->dc, dc_state);
dc_link_dp_set_test_pattern(
(struct dc_link *) link,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
index c4f703980d1e..4543b0b0f993 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
@@ -732,7 +732,6 @@ static void dm_test_idle_worker_enabled_runs_body(struct kunit *test)
dc_get_ctx(adev->dm.dc)->logger = logger;
/* dc_allow() only flips the flag when clk_mgr and apply() are present. */
dc_test_set_clk_mgr(adev->dm.dc, dm_kunit_alloc_clk_mgr(test));
- KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc_get_clk_mgr(adev->dm.dc));
dc_test_hwss(adev->dm.dc)->apply_idle_power_optimizations = dm_test_idle_apply_flip;
idle_work = kunit_kzalloc(test, sizeof(*idle_work), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8344d821d2e8..15379b186a91 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -7357,6 +7357,29 @@ void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn);
}
+/**
+ * dc_force_max_dramclk() - raise the memory clock for DP compliance tests
+ * @dc: Current DC state
+ * @context: The state whose clocks are programmed
+ *
+ * Temporary workaround for DP compliance test failures: disallow p-state
+ * switching for the given state, raise the memory clock to the maximum
+ * supported level and apply the resulting clocks immediately.
+ */
+void dc_force_max_dramclk(struct dc *dc, struct dc_state *context)
+{
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
+ context->bw_ctx.bw.dcn.clk.dramclk_khz =
+ dc->clk_mgr->dc_mode_softmax_enabled ?
+ dc->clk_mgr->bw_params->dc_mode_softmax_memclk :
+ dc->clk_mgr->bw_params->max_memclk_mhz;
+ context->bw_ctx.bw.dcn.clk.idle_dramclk_khz =
+ context->bw_ctx.bw.dcn.clk.dramclk_khz;
+
+ if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
+ dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, context, false);
+}
+
/**
* dc_get_power_profile_for_dc_state() - extracts power profile from dc state
*
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 23aced5d5eef..9e8dffadfaec 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -94,11 +94,6 @@ struct resource_pool *dc_get_res_pool(const struct dc *dc)
}
EXPORT_IF_KUNIT(dc_get_res_pool);
-struct clk_mgr *dc_get_clk_mgr(struct dc *dc)
-{
- return dc->clk_mgr;
-}
-EXPORT_IF_KUNIT(dc_get_clk_mgr);
bool dc_get_dcc_compression_cap(const struct dc *dc,
const struct dc_dcc_surface_param *input,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index d20180a449d5..1cb97c7b6c16 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2382,8 +2382,12 @@ bool dc_is_idle_optimizations_allowed(const struct dc *dc);
*/
struct resource_pool *dc_get_res_pool(const struct dc *dc);
-/* The clock manager. Interim accessor. */
-struct clk_mgr *dc_get_clk_mgr(struct dc *dc);
+/*
+ * Temporary workaround for DP compliance test failures: disallow p-state
+ * switching for the given state, raise the memory clock to the maximum
+ * supported level and apply the resulting clocks immediately.
+ */
+void dc_force_max_dramclk(struct dc *dc, struct dc_state *context);
/*
* Query DCC compression support for a surface.
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 15/19] drm/amd/display: Add dc_force_max_dramclk for the DP compliance workaround
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
The DP compliance test pattern workaround in
dm_helpers_dp_handle_test_pattern_request() reached into the clock
manager (dc_get_clk_mgr) to read the softmax memory clock limits and
to invoke the clock update. Move the whole sequence into DC as
dc_force_max_dramclk() and drop the dc_get_clk_mgr accessor; no code
outside DC references struct clk_mgr anymore.
Part of making the struct dc sub-structures opaque outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 10 +---------
.../display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c | 1 -
drivers/gpu/drm/amd/display/dc/core/dc.c | 23 ++++++++++++++++++++++
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 5 -----
drivers/gpu/drm/amd/display/dc/inc/dc.h | 8 ++++++--
5 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index b5b3269f3d97..542f9c4cb7e4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -1559,7 +1559,6 @@ bool dm_helpers_dp_handle_test_pattern_request(
struct amdgpu_dm_connector *aconnector = link->priv;
struct drm_device *dev = aconnector->base.dev;
struct dc_state *dc_state = dc_get_current_state(ctx->dc);
- struct clk_mgr *clk_mgr = dc_get_clk_mgr(ctx->dc);
int i;
for (i = 0; i < MAX_PIPES; i++) {
@@ -1661,14 +1660,7 @@ bool dm_helpers_dp_handle_test_pattern_request(
pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;
/* Temp W/A for compliance test failure */
- dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;
- dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?
- clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;
- dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;
- dc_get_clk_mgr(ctx->dc)->funcs->update_clocks(
- dc_get_clk_mgr(ctx->dc),
- dc_state,
- false);
+ dc_force_max_dramclk(ctx->dc, dc_state);
dc_link_dp_set_test_pattern(
(struct dc_link *) link,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
index c4f703980d1e..4543b0b0f993 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
@@ -732,7 +732,6 @@ static void dm_test_idle_worker_enabled_runs_body(struct kunit *test)
dc_get_ctx(adev->dm.dc)->logger = logger;
/* dc_allow() only flips the flag when clk_mgr and apply() are present. */
dc_test_set_clk_mgr(adev->dm.dc, dm_kunit_alloc_clk_mgr(test));
- KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dc_get_clk_mgr(adev->dm.dc));
dc_test_hwss(adev->dm.dc)->apply_idle_power_optimizations = dm_test_idle_apply_flip;
idle_work = kunit_kzalloc(test, sizeof(*idle_work), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8344d821d2e8..15379b186a91 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -7357,6 +7357,29 @@ void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn);
}
+/**
+ * dc_force_max_dramclk() - raise the memory clock for DP compliance tests
+ * @dc: Current DC state
+ * @context: The state whose clocks are programmed
+ *
+ * Temporary workaround for DP compliance test failures: disallow p-state
+ * switching for the given state, raise the memory clock to the maximum
+ * supported level and apply the resulting clocks immediately.
+ */
+void dc_force_max_dramclk(struct dc *dc, struct dc_state *context)
+{
+ context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
+ context->bw_ctx.bw.dcn.clk.dramclk_khz =
+ dc->clk_mgr->dc_mode_softmax_enabled ?
+ dc->clk_mgr->bw_params->dc_mode_softmax_memclk :
+ dc->clk_mgr->bw_params->max_memclk_mhz;
+ context->bw_ctx.bw.dcn.clk.idle_dramclk_khz =
+ context->bw_ctx.bw.dcn.clk.dramclk_khz;
+
+ if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
+ dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, context, false);
+}
+
/**
* dc_get_power_profile_for_dc_state() - extracts power profile from dc state
*
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 23aced5d5eef..9e8dffadfaec 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -94,11 +94,6 @@ struct resource_pool *dc_get_res_pool(const struct dc *dc)
}
EXPORT_IF_KUNIT(dc_get_res_pool);
-struct clk_mgr *dc_get_clk_mgr(struct dc *dc)
-{
- return dc->clk_mgr;
-}
-EXPORT_IF_KUNIT(dc_get_clk_mgr);
bool dc_get_dcc_compression_cap(const struct dc *dc,
const struct dc_dcc_surface_param *input,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index d20180a449d5..1cb97c7b6c16 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2382,8 +2382,12 @@ bool dc_is_idle_optimizations_allowed(const struct dc *dc);
*/
struct resource_pool *dc_get_res_pool(const struct dc *dc);
-/* The clock manager. Interim accessor. */
-struct clk_mgr *dc_get_clk_mgr(struct dc *dc);
+/*
+ * Temporary workaround for DP compliance test failures: disallow p-state
+ * switching for the given state, raise the memory clock to the maximum
+ * supported level and apply the resulting clocks immediately.
+ */
+void dc_force_max_dramclk(struct dc *dc, struct dc_state *context);
/*
* Query DCC compression support for a surface.
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 15/19] drm/amd/display: Add dc_force_max_dramclk for the DP compliance workaround
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 2:02 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 2:02 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] drm/amd/display: NULL pointer dereference in
dc_force_max_dramclk()
--
commit b8f4fd55c6e73f430098a070c075751210c4007a
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display: Add dc_force_max_dramclk for the DP compliance workaround
This commit moves the DP compliance test pattern memory clock workaround from
dm_helpers_dp_handle_test_pattern_request() into a new dc_force_max_dramclk()
helper in DC and removes the dc_get_clk_mgr() accessor.
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 8344d821d2e87..15379b186a91f 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -7357,6 +7357,29 @@ void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
> edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn);
> }
>
> +/**
> + * dc_force_max_dramclk() - raise the memory clock for DP compliance tests
> + * @dc: Current DC state
> + * @context: The state whose clocks are programmed
> + *
> + * Temporary workaround for DP compliance test failures: disallow p-state
> + * switching for the given state, raise the memory clock to the maximum
> + * supported level and apply the resulting clocks immediately.
> + */
> +void dc_force_max_dramclk(struct dc *dc, struct dc_state *context)
> +{
> + context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
> + context->bw_ctx.bw.dcn.clk.dramclk_khz =
> + dc->clk_mgr->dc_mode_softmax_enabled ?
> + dc->clk_mgr->bw_params->dc_mode_softmax_memclk :
> + dc->clk_mgr->bw_params->max_memclk_mhz;
> + context->bw_ctx.bw.dcn.clk.idle_dramclk_khz =
> + context->bw_ctx.bw.dcn.clk.dramclk_khz;
> +
> + if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
> + dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, context, false);
> +}
[Severity: High]
Can this dereference a NULL dc->clk_mgr or dc->clk_mgr->bw_params?
dc->clk_mgr is dereferenced before the NULL check on dc->clk_mgr below, and
dc->clk_mgr->bw_params is not checked at all. In dc_clk_mgr_create(),
bw_params is only populated on DCN 2.1 and DCN 3.0+ and remains NULL on DCE,
DCN 1.0, and DCN 2.0/2.01 (which is why dc_refresh_memclk_states() in this
file checks both !dc->clk_mgr and !dc->clk_mgr->bw_params). A DP link test
pattern request via dm_helpers_dp_handle_test_pattern_request() on those
ASICs will crash with a NULL pointer dereference.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=15
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 16/19] drm/amd/display: Add DC primitives for ABM hardware programming
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
The ABM code in modules/power programmed the DMCU iRAM and the DMCUB
ABM configuration through struct resource_pool, forcing the power
module and DM to reach into DC internals.
Keep the ABM curve and iRAM table baking in modules/power where it
belongs, and add thin DC-side hardware primitives that the module
drives with baked blobs:
- dc_has_dmcu(), dc_get_dmcu_abm_version(), dc_dmcu_is_initialized()
for the dispatch decisions
- dc_dmcu_load_iram() to load a baked iRAM blob at a given offset
- dc_abm_program_config() to program a baked ABM configuration table
- dc_abm_is_supported(), dc_abm_set_event() and dc_abm_set_strength()
for the ABM event/strength dispatch
dmcu_load_iram() and dmub_init_abm_config() stay in modules/power and
now take struct dc; struct dmcu_iram_parameters and enum abm_defines
stay in power_helpers.h with them. The module no longer references
struct resource_pool.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +-
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_abm.c | 121 ++++++++++++++++
drivers/gpu/drm/amd/display/dc/inc/dc.h | 42 ++++++
drivers/gpu/drm/amd/display/modules/power/power.c | 3 +-
.../gpu/drm/amd/display/modules/power/power_abm.c | 153 +++++++--------------
.../drm/amd/display/modules/power/power_helpers.h | 17 +--
7 files changed, 218 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cb122cb32905..b601ec00ba05 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1207,9 +1207,6 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
struct dmcu_iram_parameters params;
unsigned int linear_lut[16];
int i;
- struct dmcu *dmcu = NULL;
-
- dmcu = dc_get_res_pool(adev->dm.dc)->dmcu;
/* Init the boot time CRC (skip in resume) */
if ((adev->in_suspend == 0) &&
@@ -1234,8 +1231,8 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
* dmcu object will be null.
* ABM 2.4 and up are implemented on dmcub.
*/
- if (dmcu) {
- if (!dmcu_load_iram(dmcu, params))
+ if (dc_has_dmcu(adev->dm.dc)) {
+ if (!dmcu_load_iram(adev->dm.dc, params))
return -EINVAL;
} else if (dc_get_ctx(adev->dm.dc)->dmub_srv) {
struct dc_link *edp_links[MAX_NUM_EDP];
@@ -1243,7 +1240,7 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
for (i = 0; i < edp_num; i++) {
- if (!dmub_init_abm_config(dc_get_res_pool(adev->dm.dc), params, i))
+ if (!dmub_init_abm_config(adev->dm.dc, params, i))
return -EINVAL;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index c0fc7f7d241d..2ff025af0f92 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -69,6 +69,7 @@ FILES += dc_helper.o
FILES += dc_memory_pool.o
FILES += core/dc.o
FILES += core/dc_accessors.o
+FILES += core/dc_abm.o
FILES += dc_api_dispatch/api_shim.o
FILES += core/dc_debug.o
FILES += core/dc_hw_sequencer.o
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_abm.c b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
new file mode 100644
index 000000000000..1ed4b5fb6f93
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: MIT
+//
+// Copyright 2026 Advanced Micro Devices, Inc.
+//
+/* FILE POLICY AND INTENDED USAGE:
+ * DC-side ABM (Adaptive Backlight Management) hardware primitives. DC
+ * owns the ABM and DMCU objects in the resource pool, so the dispatch to
+ * their function tables lives here; the ABM curve and iRAM table baking
+ * is policy and stays in modules/power, which hands over opaque blobs
+ * through these entry points.
+ */
+#include "dm_services.h"
+#include "dc.h"
+#include "dc_priv.h"
+#include "core_types.h"
+#include "hw/dmcu.h"
+#include "hw/abm.h"
+
+bool dc_has_dmcu(const struct dc *dc)
+{
+ return dc->res_pool && dc->res_pool->dmcu != NULL;
+}
+
+bool dc_dmcu_is_initialized(struct dc *dc)
+{
+ if (!dc->res_pool || !dc->res_pool->dmcu)
+ return false;
+
+ return dc->res_pool->dmcu->funcs->is_dmcu_initialized(
+ dc->res_pool->dmcu);
+}
+
+bool dc_dmcu_load_iram(struct dc *dc, unsigned int start_offset,
+ const char *src, unsigned int bytes)
+{
+ if (!dc->res_pool || !dc->res_pool->dmcu)
+ return false;
+
+ return dc->res_pool->dmcu->funcs->load_iram(
+ dc->res_pool->dmcu, start_offset, src, bytes);
+}
+
+bool dc_abm_is_supported(struct dc *dc, unsigned int inst)
+{
+ if (dc->res_pool->abm == NULL && dc->res_pool->multiple_abms[inst] == NULL)
+ return false;
+
+ return true;
+}
+
+bool dc_abm_program_config(struct dc *dc, const char *config,
+ unsigned int size, unsigned int inst)
+{
+ if (dc->res_pool->abm == NULL && dc->res_pool->multiple_abms[inst] == NULL)
+ return false;
+
+ if (dc->res_pool->multiple_abms[inst])
+ return dc->res_pool->multiple_abms[inst]->funcs->init_abm_config(
+ dc->res_pool->multiple_abms[inst], config, size, inst);
+
+ return dc->res_pool->abm->funcs->init_abm_config(
+ dc->res_pool->abm, config, size, 0);
+}
+
+bool dc_abm_set_event(struct dc *dc,
+ unsigned int full_screen, unsigned int trans_info,
+ unsigned int hdr_mode, unsigned int scaling_enable,
+ unsigned int scaling_strength_map,
+ unsigned int inst)
+{
+ struct resource_pool *res_pool = dc->res_pool;
+ bool result = false;
+
+ if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
+ return false;
+
+ if (res_pool->multiple_abms[inst]) {
+ if (res_pool->multiple_abms[inst]->funcs->set_abm_event)
+ result = res_pool->multiple_abms[inst]->funcs->set_abm_event(
+ res_pool->multiple_abms[inst], full_screen, trans_info,
+ hdr_mode, scaling_enable, scaling_strength_map, inst);
+ } else {
+ if (res_pool->abm->funcs->set_abm_event)
+ result = res_pool->abm->funcs->set_abm_event(
+ res_pool->abm, full_screen, trans_info,
+ hdr_mode, scaling_enable, scaling_strength_map, inst);
+ }
+
+ return result;
+}
+
+bool dc_abm_set_strength(struct dc *dc,
+ unsigned int strength,
+ unsigned int inst)
+{
+ struct resource_pool *res_pool = dc->res_pool;
+ bool result = false;
+
+ if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
+ return false;
+
+ if (res_pool->multiple_abms[inst]) {
+ if (res_pool->multiple_abms[inst]->funcs->set_abm_level)
+ result = res_pool->multiple_abms[inst]->funcs->set_abm_level(
+ res_pool->multiple_abms[inst], strength);
+ } else {
+ if (res_pool->abm->funcs->set_abm_level)
+ result = res_pool->abm->funcs->set_abm_level(
+ res_pool->abm, strength);
+ }
+
+ return result;
+}
+
+unsigned int dc_get_dmcu_abm_version(const struct dc *dc)
+{
+ if (!dc->res_pool || !dc->res_pool->dmcu)
+ return 0;
+
+ return dc->res_pool->dmcu->dmcu_version.abm_version;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index 1cb97c7b6c16..28cd052e0727 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2389,6 +2389,48 @@ struct resource_pool *dc_get_res_pool(const struct dc *dc);
*/
void dc_force_max_dramclk(struct dc *dc, struct dc_state *context);
+/*
+ * ABM (Adaptive Backlight Management) hardware primitives.
+ *
+ * The ABM curve and iRAM table baking is module policy and lives in
+ * modules/power; these entry points program the baked blobs through the
+ * ABM/DMCU objects that DC owns. Callers pick the DMCU path with
+ * dc_has_dmcu().
+ */
+
+/* Whether ABM is implemented in the DMCU block on this ASIC. */
+bool dc_has_dmcu(const struct dc *dc);
+
+/* The DMCU firmware ABM version, 0 when there is no DMCU. */
+unsigned int dc_get_dmcu_abm_version(const struct dc *dc);
+
+/* Whether the DMCU firmware finished initializing. */
+bool dc_dmcu_is_initialized(struct dc *dc);
+
+/* Load a baked iRAM blob into the DMCU at the given offset. */
+bool dc_dmcu_load_iram(struct dc *dc, unsigned int start_offset,
+ const char *src, unsigned int bytes);
+
+/* Whether ABM is supported for the given eDP panel instance. */
+bool dc_abm_is_supported(struct dc *dc, unsigned int panel_inst);
+
+/*
+ * Program a baked ABM configuration table for the given eDP panel
+ * instance.
+ */
+bool dc_abm_program_config(struct dc *dc, const char *config,
+ unsigned int size, unsigned int panel_inst);
+
+/* Queue an ABM event (fullscreen transition info) for a panel instance. */
+bool dc_abm_set_event(struct dc *dc, unsigned int full_screen,
+ unsigned int trans_info, unsigned int hdr_mode,
+ unsigned int scaling_enable, unsigned int scaling_strength_map,
+ unsigned int panel_inst);
+
+/* Set the ABM strength for a panel instance. */
+bool dc_abm_set_strength(struct dc *dc, unsigned int strength,
+ unsigned int panel_inst);
+
/*
* Query DCC compression support for a surface.
* return false - when the asic does not implement the query.
diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c
index 32c00a515d4f..ebedcd9eb892 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power.c
@@ -192,8 +192,7 @@ struct mod_power *mod_power_create(struct dc *dc,
}
// ABM used to contain 4 different configs. There is only 3 since ABM 2.3.
- if (dc_get_res_pool(dc)->dmcu != NULL &&
- dc_get_res_pool(dc)->dmcu->dmcu_version.abm_version < 0x23)
+ if (dc_has_dmcu(dc) && dc_get_dmcu_abm_version(dc) < 0x23)
abm_max_config = 4;
else
abm_max_config = 3;
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
index 6dabd30b4956..ae2fa3b12e1a 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_abm.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
@@ -14,13 +14,27 @@
#include "link_service.h"
#include <linux/math.h>
-#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
-#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */
-
#define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b))
#define bswap16_based_on_endian(big_endian, value) \
((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value))
+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */
+
+
+#define MOD_POWER_MAX_CONCURRENT_STREAMS 32
+#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500
+
+/* If system or panel does not report some sort of brightness percent to nits
+ * mapping, we will use following default values so backlight control using
+ * nits based interfaces will still work, but might not describe panel
+ * correctly. In this case percentage based backlight control should ideally
+ * be used.
+ * Min = 5 nits
+ * Max = 300 nits
+ */
+
+
/* Possible Min Reduction config from least aggressive to most aggressive
* 0 1 2 3 4 5 6 7 8 9 10 11 12
* 100 98.0 94.1 94.1 85.1 80.3 75.3 69.4 60.0 57.6 50.2 49.8 40.0 %
@@ -230,17 +244,6 @@ struct iram_table_v_2_2 {
};
#pragma pack(pop)
-#define MOD_POWER_MAX_CONCURRENT_STREAMS 32
-#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500
-
-/* If system or panel does not report some sort of brightness percent to nits
- * mapping, we will use following default values so backlight control using
- * nits based interfaces will still work, but might not describe panel
- * correctly. In this case percentage based backlight control should ideally
- * be used.
- * Min = 5 nits
- * Max = 300 nits
- */
#define MOD_POWER_TO_CORE(mod_power)\
container_of(mod_power, struct core_power, mod_public)
@@ -849,7 +852,6 @@ bool mod_power_hw_init_backlight(struct mod_power *mod_power)
{
struct core_power *core_power = NULL;
struct dc *dc = NULL;
- struct dmcu *dmcu = NULL;
struct dmcu_iram_parameters params;
unsigned int i;
@@ -868,16 +870,14 @@ bool mod_power_hw_init_backlight(struct mod_power *mod_power)
params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels;
params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight;
- dmcu = dc_get_res_pool(dc)->dmcu;
-
// In the case where abm is implemented on dmcub,
// dmcu object will be null.
// ABM 2.4 and up are implemented on dmcub.
- if (dmcu) {
+ if (dc_has_dmcu(dc)) {
//DMCU does not support multiple eDP
- return dmcu_load_iram(dmcu, params);
+ return dmcu_load_iram(dc, params);
} else if (dc_get_ctx(dc)->dmub_srv) {
- if (!dmub_init_abm_config(dc_get_res_pool(dc), params, i))
+ if (!dmub_init_abm_config(dc, params, i))
return false;
} else
return false;
@@ -1659,7 +1659,7 @@ bool mod_power_is_abm_supported(struct mod_power *mod_power,
// It's only implemented on dmcub.
if (dc_get_ctx(dc)->dmub_srv) {
- if (!dmub_is_abm_supported(dc_get_res_pool(dc), inst))
+ if (!dc_abm_is_supported(dc, inst))
return false;
} else
return false;
@@ -1683,9 +1683,8 @@ bool mod_power_abm_set_event(struct mod_power *mod_power,
// It's only implemented on dmcub.
if (dc_get_ctx(dc)->dmub_srv) {
- if (!dmub_set_abm_event(dc_get_res_pool(dc), full_screen,
- trans_info, hdr_mode, scaling_enable,
- scaling_strength_map, inst))
+ if (!dc_abm_set_event(dc, full_screen, trans_info,
+ hdr_mode, scaling_enable, scaling_strength_map, inst))
return false;
} else
return false;
@@ -1708,7 +1707,7 @@ bool mod_power_abm_set_strength(struct mod_power *mod_power,
// It's only implemented on dmcub.
if (dc_get_ctx(dc)->dmub_srv) {
- if (!dmub_set_abm_strength(dc_get_res_pool(dc), strength, inst))
+ if (!dc_abm_set_strength(dc, strength, inst))
return false;
} else
return false;
@@ -2176,17 +2175,17 @@ static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram
params, ram_table, big_endian);
}
-bool dmub_init_abm_config(struct resource_pool *res_pool,
+
+bool dmub_init_abm_config(struct dc *dc,
struct dmcu_iram_parameters params,
unsigned int inst)
{
struct iram_table_v_2_2 ram_table;
struct abm_config_table config;
unsigned int set = params.set;
- bool result = false;
uint32_t i, j = 0;
- if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
+ if (!dc_abm_is_supported(dc, inst))
return false;
memset(&ram_table, 0, sizeof(ram_table));
@@ -2243,109 +2242,49 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
config.min_abm_backlight = ram_table.min_abm_backlight;
- if (res_pool->multiple_abms[inst]) {
- result = res_pool->multiple_abms[inst]->funcs->init_abm_config(
- res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);
- } else
- result = res_pool->abm->funcs->init_abm_config(
- res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0);
-
- return result;
-}
-
-bool dmub_is_abm_supported(struct resource_pool *res_pool, unsigned int inst)
-{
-
- if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
- return false;
-
- return true;
-}
-
-bool dmub_set_abm_event(struct resource_pool *res_pool,
- unsigned int full_screen, unsigned int trans_info,
- unsigned int hdr_mode, unsigned int scaling_enable, unsigned int scaling_strength_map,
- unsigned int inst)
-{
- bool result = false;
-
- if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
- return false;
-
- if (res_pool->multiple_abms[inst]) {
- if (res_pool->multiple_abms[inst]->funcs->set_abm_event)
- result = res_pool->multiple_abms[inst]->funcs->set_abm_event(
- res_pool->multiple_abms[inst], full_screen, trans_info,
- hdr_mode, scaling_enable, scaling_strength_map, inst);
- } else {
- if (res_pool->abm->funcs->set_abm_event)
- result = res_pool->abm->funcs->set_abm_event(
- res_pool->abm, full_screen, trans_info,
- hdr_mode, scaling_enable, scaling_strength_map, inst);
- }
-
- return result;
-}
-
-bool dmub_set_abm_strength(struct resource_pool *res_pool,
- unsigned int strength,
- unsigned int inst)
-{
- bool result = false;
-
- if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
- return false;
-
- if (res_pool->multiple_abms[inst]) {
- if (res_pool->multiple_abms[inst]->funcs->set_abm_level)
- result = res_pool->multiple_abms[inst]->funcs->set_abm_level(
- res_pool->multiple_abms[inst], strength);
- } else {
- if (res_pool->abm->funcs->set_abm_level)
- result = res_pool->abm->funcs->set_abm_level(
- res_pool->abm, strength);
- }
-
- return result;
+ return dc_abm_program_config(dc, (const char *)&config,
+ sizeof(struct abm_config_table), inst);
}
-bool dmcu_load_iram(struct dmcu *dmcu,
+bool dmcu_load_iram(struct dc *dc,
struct dmcu_iram_parameters params)
{
unsigned char ram_table[IRAM_SIZE];
+ unsigned int abm_version;
bool result = false;
- if (dmcu == NULL)
+ if (!dc_has_dmcu(dc))
return false;
- if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu))
+ if (!dc_dmcu_is_initialized(dc))
return true;
memset(&ram_table, 0, sizeof(ram_table));
- if (dmcu->dmcu_version.abm_version == 0x24) {
+ abm_version = dc_get_dmcu_abm_version(dc);
+ if (abm_version == 0x24) {
fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
- result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table),
+ result = dc_dmcu_load_iram(dc, 0, (char *)(&ram_table),
IRAM_RESERVE_AREA_START_V2_2);
- } else if (dmcu->dmcu_version.abm_version == 0x23) {
+ } else if (abm_version == 0x23) {
fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
- result = dmcu->funcs->load_iram(
- dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
- } else if (dmcu->dmcu_version.abm_version == 0x22) {
+ result = dc_dmcu_load_iram(
+ dc, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
+ } else if (abm_version == 0x22) {
fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
- result = dmcu->funcs->load_iram(
- dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
+ result = dc_dmcu_load_iram(
+ dc, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
} else {
fill_iram_v_2((struct iram_table_v_2 *)ram_table, params);
- result = dmcu->funcs->load_iram(
- dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
+ result = dc_dmcu_load_iram(
+ dc, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
if (result)
- result = dmcu->funcs->load_iram(
- dmcu, IRAM_RESERVE_AREA_END_V2 + 1,
+ result = dc_dmcu_load_iram(
+ dc, IRAM_RESERVE_AREA_END_V2 + 1,
(char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1,
sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1);
}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
index 68679fa10946..c16a265e2a46 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -30,7 +30,7 @@
#include "dc/inc/core_types.h"
#include "mod_power.h"
-struct resource_pool;
+struct dc;
enum abm_defines {
@@ -47,6 +47,7 @@ struct dmcu_iram_parameters {
unsigned int min_abm_backlight;
unsigned int set;
};
+
struct backlight_state {
/* HW uses u16.16 format for backlight PWM */
unsigned int backlight_pwm;
@@ -147,22 +148,12 @@ union dmcu_abm_set_bl_params {
} bits;
unsigned int u32All;
};
-bool dmcu_load_iram(struct dmcu *dmcu,
+bool dmcu_load_iram(struct dc *dc,
struct dmcu_iram_parameters params);
-bool dmub_init_abm_config(struct resource_pool *res_pool,
+bool dmub_init_abm_config(struct dc *dc,
struct dmcu_iram_parameters params,
unsigned int inst);
-bool dmub_is_abm_supported(struct resource_pool *res_pool,
- unsigned int inst);
-bool dmub_set_abm_event(struct resource_pool *res_pool,
- unsigned int full_screen, unsigned int trans_info,
- unsigned int hdr_mode, unsigned int scaling_enable,
- unsigned int scaling_strength_map, unsigned int inst);
-bool dmub_set_abm_strength(struct resource_pool *res_pool,
- unsigned int strength,
- unsigned int inst);
-
void init_replay_config(struct dc_link *link, struct replay_config *pr_config);
void set_replay_coasting_vtotal(struct dc_link *link,
enum replay_coasting_vtotal_type type,
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 16/19] drm/amd/display: Add DC primitives for ABM hardware programming
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
The ABM code in modules/power programmed the DMCU iRAM and the DMCUB
ABM configuration through struct resource_pool, forcing the power
module and DM to reach into DC internals.
Keep the ABM curve and iRAM table baking in modules/power where it
belongs, and add thin DC-side hardware primitives that the module
drives with baked blobs:
- dc_has_dmcu(), dc_get_dmcu_abm_version(), dc_dmcu_is_initialized()
for the dispatch decisions
- dc_dmcu_load_iram() to load a baked iRAM blob at a given offset
- dc_abm_program_config() to program a baked ABM configuration table
- dc_abm_is_supported(), dc_abm_set_event() and dc_abm_set_strength()
for the ABM event/strength dispatch
dmcu_load_iram() and dmub_init_abm_config() stay in modules/power and
now take struct dc; struct dmcu_iram_parameters and enum abm_defines
stay in power_helpers.h with them. The module no longer references
struct resource_pool.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +-
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
drivers/gpu/drm/amd/display/dc/core/dc_abm.c | 121 ++++++++++++++++
drivers/gpu/drm/amd/display/dc/inc/dc.h | 42 ++++++
drivers/gpu/drm/amd/display/modules/power/power.c | 3 +-
.../gpu/drm/amd/display/modules/power/power_abm.c | 153 +++++++--------------
.../drm/amd/display/modules/power/power_helpers.h | 17 +--
7 files changed, 218 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cb122cb32905..b601ec00ba05 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1207,9 +1207,6 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
struct dmcu_iram_parameters params;
unsigned int linear_lut[16];
int i;
- struct dmcu *dmcu = NULL;
-
- dmcu = dc_get_res_pool(adev->dm.dc)->dmcu;
/* Init the boot time CRC (skip in resume) */
if ((adev->in_suspend == 0) &&
@@ -1234,8 +1231,8 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
* dmcu object will be null.
* ABM 2.4 and up are implemented on dmcub.
*/
- if (dmcu) {
- if (!dmcu_load_iram(dmcu, params))
+ if (dc_has_dmcu(adev->dm.dc)) {
+ if (!dmcu_load_iram(adev->dm.dc, params))
return -EINVAL;
} else if (dc_get_ctx(adev->dm.dc)->dmub_srv) {
struct dc_link *edp_links[MAX_NUM_EDP];
@@ -1243,7 +1240,7 @@ STATIC_IFN_KUNIT int dm_late_init(struct amdgpu_ip_block *ip_block)
dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
for (i = 0; i < edp_num; i++) {
- if (!dmub_init_abm_config(dc_get_res_pool(adev->dm.dc), params, i))
+ if (!dmub_init_abm_config(adev->dm.dc, params, i))
return -EINVAL;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index c0fc7f7d241d..2ff025af0f92 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -69,6 +69,7 @@ FILES += dc_helper.o
FILES += dc_memory_pool.o
FILES += core/dc.o
FILES += core/dc_accessors.o
+FILES += core/dc_abm.o
FILES += dc_api_dispatch/api_shim.o
FILES += core/dc_debug.o
FILES += core/dc_hw_sequencer.o
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_abm.c b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
new file mode 100644
index 000000000000..1ed4b5fb6f93
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: MIT
+//
+// Copyright 2026 Advanced Micro Devices, Inc.
+//
+/* FILE POLICY AND INTENDED USAGE:
+ * DC-side ABM (Adaptive Backlight Management) hardware primitives. DC
+ * owns the ABM and DMCU objects in the resource pool, so the dispatch to
+ * their function tables lives here; the ABM curve and iRAM table baking
+ * is policy and stays in modules/power, which hands over opaque blobs
+ * through these entry points.
+ */
+#include "dm_services.h"
+#include "dc.h"
+#include "dc_priv.h"
+#include "core_types.h"
+#include "hw/dmcu.h"
+#include "hw/abm.h"
+
+bool dc_has_dmcu(const struct dc *dc)
+{
+ return dc->res_pool && dc->res_pool->dmcu != NULL;
+}
+
+bool dc_dmcu_is_initialized(struct dc *dc)
+{
+ if (!dc->res_pool || !dc->res_pool->dmcu)
+ return false;
+
+ return dc->res_pool->dmcu->funcs->is_dmcu_initialized(
+ dc->res_pool->dmcu);
+}
+
+bool dc_dmcu_load_iram(struct dc *dc, unsigned int start_offset,
+ const char *src, unsigned int bytes)
+{
+ if (!dc->res_pool || !dc->res_pool->dmcu)
+ return false;
+
+ return dc->res_pool->dmcu->funcs->load_iram(
+ dc->res_pool->dmcu, start_offset, src, bytes);
+}
+
+bool dc_abm_is_supported(struct dc *dc, unsigned int inst)
+{
+ if (dc->res_pool->abm == NULL && dc->res_pool->multiple_abms[inst] == NULL)
+ return false;
+
+ return true;
+}
+
+bool dc_abm_program_config(struct dc *dc, const char *config,
+ unsigned int size, unsigned int inst)
+{
+ if (dc->res_pool->abm == NULL && dc->res_pool->multiple_abms[inst] == NULL)
+ return false;
+
+ if (dc->res_pool->multiple_abms[inst])
+ return dc->res_pool->multiple_abms[inst]->funcs->init_abm_config(
+ dc->res_pool->multiple_abms[inst], config, size, inst);
+
+ return dc->res_pool->abm->funcs->init_abm_config(
+ dc->res_pool->abm, config, size, 0);
+}
+
+bool dc_abm_set_event(struct dc *dc,
+ unsigned int full_screen, unsigned int trans_info,
+ unsigned int hdr_mode, unsigned int scaling_enable,
+ unsigned int scaling_strength_map,
+ unsigned int inst)
+{
+ struct resource_pool *res_pool = dc->res_pool;
+ bool result = false;
+
+ if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
+ return false;
+
+ if (res_pool->multiple_abms[inst]) {
+ if (res_pool->multiple_abms[inst]->funcs->set_abm_event)
+ result = res_pool->multiple_abms[inst]->funcs->set_abm_event(
+ res_pool->multiple_abms[inst], full_screen, trans_info,
+ hdr_mode, scaling_enable, scaling_strength_map, inst);
+ } else {
+ if (res_pool->abm->funcs->set_abm_event)
+ result = res_pool->abm->funcs->set_abm_event(
+ res_pool->abm, full_screen, trans_info,
+ hdr_mode, scaling_enable, scaling_strength_map, inst);
+ }
+
+ return result;
+}
+
+bool dc_abm_set_strength(struct dc *dc,
+ unsigned int strength,
+ unsigned int inst)
+{
+ struct resource_pool *res_pool = dc->res_pool;
+ bool result = false;
+
+ if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
+ return false;
+
+ if (res_pool->multiple_abms[inst]) {
+ if (res_pool->multiple_abms[inst]->funcs->set_abm_level)
+ result = res_pool->multiple_abms[inst]->funcs->set_abm_level(
+ res_pool->multiple_abms[inst], strength);
+ } else {
+ if (res_pool->abm->funcs->set_abm_level)
+ result = res_pool->abm->funcs->set_abm_level(
+ res_pool->abm, strength);
+ }
+
+ return result;
+}
+
+unsigned int dc_get_dmcu_abm_version(const struct dc *dc)
+{
+ if (!dc->res_pool || !dc->res_pool->dmcu)
+ return 0;
+
+ return dc->res_pool->dmcu->dmcu_version.abm_version;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index 1cb97c7b6c16..28cd052e0727 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2389,6 +2389,48 @@ struct resource_pool *dc_get_res_pool(const struct dc *dc);
*/
void dc_force_max_dramclk(struct dc *dc, struct dc_state *context);
+/*
+ * ABM (Adaptive Backlight Management) hardware primitives.
+ *
+ * The ABM curve and iRAM table baking is module policy and lives in
+ * modules/power; these entry points program the baked blobs through the
+ * ABM/DMCU objects that DC owns. Callers pick the DMCU path with
+ * dc_has_dmcu().
+ */
+
+/* Whether ABM is implemented in the DMCU block on this ASIC. */
+bool dc_has_dmcu(const struct dc *dc);
+
+/* The DMCU firmware ABM version, 0 when there is no DMCU. */
+unsigned int dc_get_dmcu_abm_version(const struct dc *dc);
+
+/* Whether the DMCU firmware finished initializing. */
+bool dc_dmcu_is_initialized(struct dc *dc);
+
+/* Load a baked iRAM blob into the DMCU at the given offset. */
+bool dc_dmcu_load_iram(struct dc *dc, unsigned int start_offset,
+ const char *src, unsigned int bytes);
+
+/* Whether ABM is supported for the given eDP panel instance. */
+bool dc_abm_is_supported(struct dc *dc, unsigned int panel_inst);
+
+/*
+ * Program a baked ABM configuration table for the given eDP panel
+ * instance.
+ */
+bool dc_abm_program_config(struct dc *dc, const char *config,
+ unsigned int size, unsigned int panel_inst);
+
+/* Queue an ABM event (fullscreen transition info) for a panel instance. */
+bool dc_abm_set_event(struct dc *dc, unsigned int full_screen,
+ unsigned int trans_info, unsigned int hdr_mode,
+ unsigned int scaling_enable, unsigned int scaling_strength_map,
+ unsigned int panel_inst);
+
+/* Set the ABM strength for a panel instance. */
+bool dc_abm_set_strength(struct dc *dc, unsigned int strength,
+ unsigned int panel_inst);
+
/*
* Query DCC compression support for a surface.
* return false - when the asic does not implement the query.
diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c
index 32c00a515d4f..ebedcd9eb892 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power.c
@@ -192,8 +192,7 @@ struct mod_power *mod_power_create(struct dc *dc,
}
// ABM used to contain 4 different configs. There is only 3 since ABM 2.3.
- if (dc_get_res_pool(dc)->dmcu != NULL &&
- dc_get_res_pool(dc)->dmcu->dmcu_version.abm_version < 0x23)
+ if (dc_has_dmcu(dc) && dc_get_dmcu_abm_version(dc) < 0x23)
abm_max_config = 4;
else
abm_max_config = 3;
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
index 6dabd30b4956..ae2fa3b12e1a 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_abm.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
@@ -14,13 +14,27 @@
#include "link_service.h"
#include <linux/math.h>
-#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
-#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */
-
#define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b))
#define bswap16_based_on_endian(big_endian, value) \
((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value))
+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */
+
+
+#define MOD_POWER_MAX_CONCURRENT_STREAMS 32
+#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500
+
+/* If system or panel does not report some sort of brightness percent to nits
+ * mapping, we will use following default values so backlight control using
+ * nits based interfaces will still work, but might not describe panel
+ * correctly. In this case percentage based backlight control should ideally
+ * be used.
+ * Min = 5 nits
+ * Max = 300 nits
+ */
+
+
/* Possible Min Reduction config from least aggressive to most aggressive
* 0 1 2 3 4 5 6 7 8 9 10 11 12
* 100 98.0 94.1 94.1 85.1 80.3 75.3 69.4 60.0 57.6 50.2 49.8 40.0 %
@@ -230,17 +244,6 @@ struct iram_table_v_2_2 {
};
#pragma pack(pop)
-#define MOD_POWER_MAX_CONCURRENT_STREAMS 32
-#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500
-
-/* If system or panel does not report some sort of brightness percent to nits
- * mapping, we will use following default values so backlight control using
- * nits based interfaces will still work, but might not describe panel
- * correctly. In this case percentage based backlight control should ideally
- * be used.
- * Min = 5 nits
- * Max = 300 nits
- */
#define MOD_POWER_TO_CORE(mod_power)\
container_of(mod_power, struct core_power, mod_public)
@@ -849,7 +852,6 @@ bool mod_power_hw_init_backlight(struct mod_power *mod_power)
{
struct core_power *core_power = NULL;
struct dc *dc = NULL;
- struct dmcu *dmcu = NULL;
struct dmcu_iram_parameters params;
unsigned int i;
@@ -868,16 +870,14 @@ bool mod_power_hw_init_backlight(struct mod_power *mod_power)
params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels;
params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight;
- dmcu = dc_get_res_pool(dc)->dmcu;
-
// In the case where abm is implemented on dmcub,
// dmcu object will be null.
// ABM 2.4 and up are implemented on dmcub.
- if (dmcu) {
+ if (dc_has_dmcu(dc)) {
//DMCU does not support multiple eDP
- return dmcu_load_iram(dmcu, params);
+ return dmcu_load_iram(dc, params);
} else if (dc_get_ctx(dc)->dmub_srv) {
- if (!dmub_init_abm_config(dc_get_res_pool(dc), params, i))
+ if (!dmub_init_abm_config(dc, params, i))
return false;
} else
return false;
@@ -1659,7 +1659,7 @@ bool mod_power_is_abm_supported(struct mod_power *mod_power,
// It's only implemented on dmcub.
if (dc_get_ctx(dc)->dmub_srv) {
- if (!dmub_is_abm_supported(dc_get_res_pool(dc), inst))
+ if (!dc_abm_is_supported(dc, inst))
return false;
} else
return false;
@@ -1683,9 +1683,8 @@ bool mod_power_abm_set_event(struct mod_power *mod_power,
// It's only implemented on dmcub.
if (dc_get_ctx(dc)->dmub_srv) {
- if (!dmub_set_abm_event(dc_get_res_pool(dc), full_screen,
- trans_info, hdr_mode, scaling_enable,
- scaling_strength_map, inst))
+ if (!dc_abm_set_event(dc, full_screen, trans_info,
+ hdr_mode, scaling_enable, scaling_strength_map, inst))
return false;
} else
return false;
@@ -1708,7 +1707,7 @@ bool mod_power_abm_set_strength(struct mod_power *mod_power,
// It's only implemented on dmcub.
if (dc_get_ctx(dc)->dmub_srv) {
- if (!dmub_set_abm_strength(dc_get_res_pool(dc), strength, inst))
+ if (!dc_abm_set_strength(dc, strength, inst))
return false;
} else
return false;
@@ -2176,17 +2175,17 @@ static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram
params, ram_table, big_endian);
}
-bool dmub_init_abm_config(struct resource_pool *res_pool,
+
+bool dmub_init_abm_config(struct dc *dc,
struct dmcu_iram_parameters params,
unsigned int inst)
{
struct iram_table_v_2_2 ram_table;
struct abm_config_table config;
unsigned int set = params.set;
- bool result = false;
uint32_t i, j = 0;
- if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
+ if (!dc_abm_is_supported(dc, inst))
return false;
memset(&ram_table, 0, sizeof(ram_table));
@@ -2243,109 +2242,49 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
config.min_abm_backlight = ram_table.min_abm_backlight;
- if (res_pool->multiple_abms[inst]) {
- result = res_pool->multiple_abms[inst]->funcs->init_abm_config(
- res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);
- } else
- result = res_pool->abm->funcs->init_abm_config(
- res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0);
-
- return result;
-}
-
-bool dmub_is_abm_supported(struct resource_pool *res_pool, unsigned int inst)
-{
-
- if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
- return false;
-
- return true;
-}
-
-bool dmub_set_abm_event(struct resource_pool *res_pool,
- unsigned int full_screen, unsigned int trans_info,
- unsigned int hdr_mode, unsigned int scaling_enable, unsigned int scaling_strength_map,
- unsigned int inst)
-{
- bool result = false;
-
- if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
- return false;
-
- if (res_pool->multiple_abms[inst]) {
- if (res_pool->multiple_abms[inst]->funcs->set_abm_event)
- result = res_pool->multiple_abms[inst]->funcs->set_abm_event(
- res_pool->multiple_abms[inst], full_screen, trans_info,
- hdr_mode, scaling_enable, scaling_strength_map, inst);
- } else {
- if (res_pool->abm->funcs->set_abm_event)
- result = res_pool->abm->funcs->set_abm_event(
- res_pool->abm, full_screen, trans_info,
- hdr_mode, scaling_enable, scaling_strength_map, inst);
- }
-
- return result;
-}
-
-bool dmub_set_abm_strength(struct resource_pool *res_pool,
- unsigned int strength,
- unsigned int inst)
-{
- bool result = false;
-
- if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
- return false;
-
- if (res_pool->multiple_abms[inst]) {
- if (res_pool->multiple_abms[inst]->funcs->set_abm_level)
- result = res_pool->multiple_abms[inst]->funcs->set_abm_level(
- res_pool->multiple_abms[inst], strength);
- } else {
- if (res_pool->abm->funcs->set_abm_level)
- result = res_pool->abm->funcs->set_abm_level(
- res_pool->abm, strength);
- }
-
- return result;
+ return dc_abm_program_config(dc, (const char *)&config,
+ sizeof(struct abm_config_table), inst);
}
-bool dmcu_load_iram(struct dmcu *dmcu,
+bool dmcu_load_iram(struct dc *dc,
struct dmcu_iram_parameters params)
{
unsigned char ram_table[IRAM_SIZE];
+ unsigned int abm_version;
bool result = false;
- if (dmcu == NULL)
+ if (!dc_has_dmcu(dc))
return false;
- if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu))
+ if (!dc_dmcu_is_initialized(dc))
return true;
memset(&ram_table, 0, sizeof(ram_table));
- if (dmcu->dmcu_version.abm_version == 0x24) {
+ abm_version = dc_get_dmcu_abm_version(dc);
+ if (abm_version == 0x24) {
fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
- result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table),
+ result = dc_dmcu_load_iram(dc, 0, (char *)(&ram_table),
IRAM_RESERVE_AREA_START_V2_2);
- } else if (dmcu->dmcu_version.abm_version == 0x23) {
+ } else if (abm_version == 0x23) {
fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true);
- result = dmcu->funcs->load_iram(
- dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
- } else if (dmcu->dmcu_version.abm_version == 0x22) {
+ result = dc_dmcu_load_iram(
+ dc, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
+ } else if (abm_version == 0x22) {
fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
- result = dmcu->funcs->load_iram(
- dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
+ result = dc_dmcu_load_iram(
+ dc, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
} else {
fill_iram_v_2((struct iram_table_v_2 *)ram_table, params);
- result = dmcu->funcs->load_iram(
- dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
+ result = dc_dmcu_load_iram(
+ dc, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);
if (result)
- result = dmcu->funcs->load_iram(
- dmcu, IRAM_RESERVE_AREA_END_V2 + 1,
+ result = dc_dmcu_load_iram(
+ dc, IRAM_RESERVE_AREA_END_V2 + 1,
(char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1,
sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1);
}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
index 68679fa10946..c16a265e2a46 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
@@ -30,7 +30,7 @@
#include "dc/inc/core_types.h"
#include "mod_power.h"
-struct resource_pool;
+struct dc;
enum abm_defines {
@@ -47,6 +47,7 @@ struct dmcu_iram_parameters {
unsigned int min_abm_backlight;
unsigned int set;
};
+
struct backlight_state {
/* HW uses u16.16 format for backlight PWM */
unsigned int backlight_pwm;
@@ -147,22 +148,12 @@ union dmcu_abm_set_bl_params {
} bits;
unsigned int u32All;
};
-bool dmcu_load_iram(struct dmcu *dmcu,
+bool dmcu_load_iram(struct dc *dc,
struct dmcu_iram_parameters params);
-bool dmub_init_abm_config(struct resource_pool *res_pool,
+bool dmub_init_abm_config(struct dc *dc,
struct dmcu_iram_parameters params,
unsigned int inst);
-bool dmub_is_abm_supported(struct resource_pool *res_pool,
- unsigned int inst);
-bool dmub_set_abm_event(struct resource_pool *res_pool,
- unsigned int full_screen, unsigned int trans_info,
- unsigned int hdr_mode, unsigned int scaling_enable,
- unsigned int scaling_strength_map, unsigned int inst);
-bool dmub_set_abm_strength(struct resource_pool *res_pool,
- unsigned int strength,
- unsigned int inst);
-
void init_replay_config(struct dc_link *link, struct replay_config *pr_config);
void set_replay_coasting_vtotal(struct dc_link *link,
enum replay_coasting_vtotal_type type,
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 16/19] drm/amd/display: Add DC primitives for ABM hardware programming
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 2:01 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 2:01 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] drm/amd/display: dc_dmcu_is_initialized() duplicates
dc_is_dmcu_initialized()
--
commit 73f1ba49a5d9e363674e88529801b1a9200d901c
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display: Add DC primitives for ABM hardware programming
This commit adds DC-side hardware primitives for DMCU iRAM loading and ABM
configuration and event programming so that modules/power and amdgpu_dm no
longer access struct resource_pool directly.
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_abm.c b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
> new file mode 100644
> index 0000000000000..1ed4b5fb6f937
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
> @@ -0,0 +1,121 @@
[ ... ]
> +bool dc_dmcu_is_initialized(struct dc *dc)
> +{
> + if (!dc->res_pool || !dc->res_pool->dmcu)
> + return false;
> +
> + return dc->res_pool->dmcu->funcs->is_dmcu_initialized(
> + dc->res_pool->dmcu);
> +}
[Severity: Low]
Does dc_dmcu_is_initialized() duplicate the existing dc_is_dmcu_initialized()
helper?
drivers/gpu/drm/amd/display/dc/core/dc.c:dc_is_dmcu_initialized() {
struct dmcu *dmcu = dc->res_pool->dmcu;
if (dmcu)
return dmcu->funcs->is_dmcu_initialized(dmcu);
return false;
}
dc_is_dmcu_initialized() is already declared in dc.h and has no other callers
in the tree, so these two public helpers could be consolidated.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=16
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 17/19] drm/amd/display: Replace the dc_get_res_pool accessor with purpose APIs
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Add the last purpose-built interfaces for the data DM was reading
through dc_get_res_pool() and drop the accessor entirely:
- dc_get_audio_instances() fills the audio instance id array for
amdgpu_dm_audio_init()
- dc_get_pipe_count() for the debugfs DCC bits dump
- dc_get_usb4_dpia_count() for the DMUB DPIA enablement
- dc_get_dmcu_psp_version() and dc_dmcu_init_abm() for the DMUB
hardware init path
- dc_get_mall_en() for the debugfs capabilities dump
- dc_remove_stream_from_ctx() for the MST DSC recomputation
No code outside the dc directory references struct resource_pool in
production anymore; only the KUnit tests keep installing fake pools
through dc_test_set_res_pool() / dm_kunit_alloc_res_pool().
Part of making the struct dc sub-structures opaque outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c | 8 +---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 7 +---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 14 ++-----
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 +--
.../display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c | 12 ++++--
.../display/amdgpu_dm/tests/amdgpu_dm_irq_test.c | 2 +-
.../amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c | 13 +++++++
.../amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h | 2 +
.../amdgpu_dm/tests/amdgpu_dm_mst_types_test.c | 5 ++-
.../amd/display/amdgpu_dm/tests/amdgpu_dm_test.c | 6 +--
drivers/gpu/drm/amd/display/dc/core/dc_abm.c | 11 ++++++
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 44 ++++++++++++++++++++--
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 10 +++++
drivers/gpu/drm/amd/display/dc/inc/dc.h | 38 ++++++++++++++++---
14 files changed, 135 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
index 23392b229679..0301081e040e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
@@ -140,19 +140,15 @@ EXPORT_IF_KUNIT(amdgpu_dm_audio_init_pins);
int amdgpu_dm_audio_init(struct amdgpu_device *adev)
{
unsigned int inst_array[MAX_AUDIOS];
- struct resource_pool *res_pool;
int audio_count;
- int i, ret;
+ int ret;
if (!amdgpu_audio)
return 0;
adev->mode_info.audio.enabled = true;
- res_pool = dc_get_res_pool(adev->dm.dc);
- audio_count = res_pool->audio_count;
- for (i = 0; i < audio_count; i++)
- inst_array[i] = res_pool->audios[i]->inst;
+ audio_count = dc_get_audio_instances(adev->dm.dc, inst_array);
amdgpu_dm_audio_init_pins(adev, audio_count, inst_array);
ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 8d7ebb636554..8bc737117db9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -4464,10 +4464,7 @@ static int capabilities_show(struct seq_file *m, void *unused)
unsigned int mall_in_use = false;
unsigned int subvp_in_use = false;
- struct hubbub *hubbub = dc_get_res_pool(dc)->hubbub;
-
- if (hubbub && hubbub->funcs->get_mall_en)
- hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
+ dc_get_mall_en(dc, &mall_in_use);
subvp_in_use = dc_get_subvp_en(dc, dc_get_current_state(dc));
@@ -4609,7 +4606,7 @@ static ssize_t dcc_en_bits_read(
const uint32_t rd_buf_size = 32;
uint32_t result = 0;
int offset = 0;
- int num_pipes = dc_get_res_pool(dc)->pipe_count;
+ int num_pipes = dc_get_pipe_count(dc);
int *dcc_en_bits;
int i, r;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index ffe561da24d6..3ed6a9318931 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -232,9 +232,6 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
const struct firmware *dmub_fw = adev->dm.dmub_fw;
struct dc *dc = adev->dm.dc;
- struct resource_pool *res_pool = dc_get_res_pool(dc);
- struct dmcu *dmcu = res_pool->dmcu;
- struct abm *abm = res_pool->abm;
struct dc_context *ctx = dc_get_ctx(adev->dm.dc);
struct dmub_srv_hw_params hw_params;
enum dmub_status status;
@@ -333,14 +330,14 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
hw_params.load_inst_const = true;
- if (dmcu)
- hw_params.psp_version = dmcu->psp_version;
+ if (dc_has_dmcu(dc))
+ hw_params.psp_version = dc_get_dmcu_psp_version(dc);
hw_params.fb_info = fb_info;
/* Enable usb4 dpia in the FW APU */
if (dc_get_caps(dc)->is_apu &&
- dc_get_res_pool(dc)->usb4_dpia_count != 0 &&
+ dc_get_usb4_dpia_count(dc) != 0 &&
!dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia) {
hw_params.dpia_supported = true;
hw_params.disable_dpia = dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia;
@@ -375,10 +372,7 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
drm_warn(adev_to_drm(adev), "Wait for DMUB auto-load failed: %d\n", status);
/* Init DMCU and ABM if available. */
- if (dmcu && abm) {
- dmcu->funcs->dmcu_init(dmcu);
- abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
- }
+ dc_dmcu_init_abm(dc);
if (!dc_get_ctx(adev->dm.dc)->dmub_srv)
dc_get_ctx(adev->dm.dc)->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 4f9070579916..d533b72f1861 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1643,7 +1643,6 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
bool computed_streams[MAX_PIPES];
struct amdgpu_dm_connector *aconnector;
struct drm_dp_mst_topology_mgr *mst_mgr;
- struct resource_pool *res_pool;
int link_vars_start_index = 0;
int ret = 0;
@@ -1652,7 +1651,7 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
for (i = 0; i < dc_state->stream_count; i++) {
stream = dc_state->streams[i];
- res_pool = dc_get_res_pool(stream->ctx->dc);
+
if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
continue;
@@ -1671,8 +1670,7 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
if (computed_streams[i])
continue;
- if (res_pool->funcs->remove_stream_from_ctx &&
- res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
+ if (dc_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
return -EINVAL;
if (!is_dsc_need_re_compute(state, dc_state, stream->link))
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
index b71e1e11e85a..e1360a97ec26 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
@@ -731,11 +731,14 @@ static void dm_test_dmub_hw_init_auto_load_timeout(struct kunit *test)
*/
static void dm_test_dmub_hw_init_apu_dpia_dcn35(struct kunit *test)
{
+ struct resource_pool *res_pool;
+
struct amdgpu_device *adev = dm_test_alloc_adev_with_dmub(test);
adev->ip_versions[DCE_HWIP][0] = IP_VERSION(3, 5, 0);
dc_test_caps(adev->dm.dc)->is_apu = true;
- dc_get_res_pool(adev->dm.dc)->usb4_dpia_count = 1;
+ res_pool = dm_kunit_alloc_res_pool(test, adev->dm.dc);
+ res_pool->usb4_dpia_count = 1;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, adev->dm.dmub_srv->hw_init);
@@ -787,6 +790,8 @@ static void dm_test_dmub_hw_init_sanity_checks_dcn314(struct kunit *test)
*/
static void dm_test_dmub_hw_init_dmcu_abm(struct kunit *test)
{
+ struct resource_pool *res_pool;
+
struct amdgpu_device *adev = dm_test_alloc_adev_with_dmub(test);
struct dmcu *dmcu;
struct abm *abm;
@@ -799,8 +804,9 @@ static void dm_test_dmub_hw_init_dmcu_abm(struct kunit *test)
dmcu->funcs = &dm_test_dmcu_funcs;
dmcu->psp_version = 0x12345678;
- dc_get_res_pool(adev->dm.dc)->dmcu = dmcu;
- dc_get_res_pool(adev->dm.dc)->abm = abm;
+ res_pool = dm_kunit_alloc_res_pool(test, adev->dm.dc);
+ res_pool->dmcu = dmcu;
+ res_pool->abm = abm;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, abm->dmcu_is_running);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
index ea467ca45af8..2ae534c4c252 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
@@ -4188,7 +4188,7 @@ static void dm_test_crtc_high_irq_writeback_disables(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, drm_vblank_init(&adev->ddev, 1), 0);
- /* dc_stream_fc_disable_writeback() dereferences dc_get_res_pool(dc). */
+ /* dc_stream_fc_disable_writeback() dereferences the DC resource pool. */
dc = dm_test_alloc_dc_with_irq_service(test,
&dm_test_irq_service_funcs_dcn10);
adev->dm.dc = dc;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
index 9954cbab6541..e4bea9fbad52 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
@@ -136,6 +136,19 @@ struct dc_state *dm_kunit_alloc_dc_state(struct kunit *test)
}
EXPORT_SYMBOL(dm_kunit_alloc_dc_state);
+struct resource_pool *dm_kunit_alloc_res_pool(struct kunit *test, struct dc *dc)
+{
+ struct resource_pool *res_pool;
+
+ res_pool = kunit_kzalloc(test, sizeof(*res_pool), GFP_KERNEL);
+ KUNIT_ASSERT_NOT_NULL(test, res_pool);
+
+ dc_test_set_res_pool(dc, res_pool);
+
+ return res_pool;
+}
+EXPORT_SYMBOL(dm_kunit_alloc_res_pool);
+
struct clk_mgr *dm_kunit_alloc_clk_mgr(struct kunit *test)
{
struct clk_mgr *clk_mgr;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
index b4bbf4a3750d..279d6eb79ad5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
@@ -28,6 +28,8 @@ struct dc_link *dm_kunit_alloc_link_with_ctx(struct kunit *test);
struct amdgpu_display_manager *dm_kunit_alloc_dm(struct kunit *test);
struct drm_device *dm_kunit_alloc_drm_with_connector_list(struct kunit *test);
struct dc_state *dm_kunit_alloc_dc_state(struct kunit *test);
+struct resource_pool;
+struct resource_pool *dm_kunit_alloc_res_pool(struct kunit *test, struct dc *dc);
struct clk_mgr *dm_kunit_alloc_clk_mgr(struct kunit *test);
struct dc_stream_state *dm_kunit_alloc_stream(struct kunit *test,
struct dc_link *link);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
index 144cb03f504a..da5c2f958bf1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
@@ -2783,6 +2783,8 @@ static const struct dsc_funcs dm_mst_test_dsc_funcs = {
/* Install the DSC encoder fake and matching sink decoder capabilities. */
static void dm_mst_test_setup_dsc_caps(struct kunit *test, struct dc *dc, struct dc_sink *sink)
{
+ struct resource_pool *res_pool;
+
struct dsc_dec_dpcd_caps *dec = &sink->dsc_caps.dsc_dec_caps;
struct display_stream_compressor *dsc;
@@ -2791,7 +2793,8 @@ static void dm_mst_test_setup_dsc_caps(struct kunit *test, struct dc *dc, struct
dsc->funcs = &dm_mst_test_dsc_funcs;
dsc->ctx = dc_get_ctx(dc);
- dc_get_res_pool(dc)->dscs[0] = dsc;
+ res_pool = dm_kunit_alloc_res_pool(test, dc);
+ res_pool->dscs[0] = dsc;
dec->is_dsc_supported = true;
dec->dsc_version = 0x21;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
index 8cf460a4cb9f..0c27422cb8cf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
@@ -3388,8 +3388,7 @@ static void dm_test_oem_i2c_hw_init_no_device(struct kunit *test)
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc_test_set_res_pool(dc, kunit_kzalloc(test, sizeof(*dc_get_res_pool(dc)), GFP_KERNEL));
- KUNIT_ASSERT_NOT_NULL(test, dc_get_res_pool(dc));
+ dm_kunit_alloc_res_pool(test, dc);
adev->dm.dc = dc;
KUNIT_EXPECT_EQ(test, dm_oem_i2c_hw_init(adev), 0);
@@ -4981,8 +4980,7 @@ static struct amdgpu_device *dm_test_late_init_adev(struct kunit *test)
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc_test_set_res_pool(dc, kunit_kzalloc(test, sizeof(*dc_get_res_pool(dc)), GFP_KERNEL));
- KUNIT_ASSERT_NOT_NULL(test, dc_get_res_pool(dc));
+ dm_kunit_alloc_res_pool(test, dc);
adev->dm.dc = dc;
return adev;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_abm.c b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
index 1ed4b5fb6f93..28427e03289b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
@@ -119,3 +119,14 @@ unsigned int dc_get_dmcu_abm_version(const struct dc *dc)
return dc->res_pool->dmcu->dmcu_version.abm_version;
}
+
+void dc_dmcu_init_abm(struct dc *dc)
+{
+ struct dmcu *dmcu = dc->res_pool ? dc->res_pool->dmcu : NULL;
+ struct abm *abm = dc->res_pool ? dc->res_pool->abm : NULL;
+
+ if (dmcu && abm) {
+ dmcu->funcs->dmcu_init(dmcu);
+ abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 9e8dffadfaec..163884db0294 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -32,6 +32,8 @@
*/
#include "dc.h"
#include "dc_priv.h"
+#include "core_types.h"
+#include "hw/dchubbub.h"
#include "dm_helpers.h" /* EXPORT_IF_KUNIT */
uint8_t dc_get_link_count(const struct dc *dc)
@@ -88,11 +90,47 @@ bool dc_is_idle_optimizations_allowed(const struct dc *dc)
}
EXPORT_IF_KUNIT(dc_is_idle_optimizations_allowed);
-struct resource_pool *dc_get_res_pool(const struct dc *dc)
+unsigned int dc_get_audio_instances(const struct dc *dc,
+ unsigned int *inst_array)
{
- return dc->res_pool;
+ unsigned int i;
+
+ for (i = 0; i < dc->res_pool->audio_count; i++)
+ inst_array[i] = dc->res_pool->audios[i]->inst;
+
+ return dc->res_pool->audio_count;
+}
+EXPORT_IF_KUNIT(dc_get_audio_instances);
+
+unsigned int dc_get_pipe_count(const struct dc *dc)
+{
+ return dc->res_pool->pipe_count;
+}
+EXPORT_IF_KUNIT(dc_get_pipe_count);
+
+unsigned int dc_get_usb4_dpia_count(const struct dc *dc)
+{
+ return dc->res_pool->usb4_dpia_count;
+}
+EXPORT_IF_KUNIT(dc_get_usb4_dpia_count);
+
+unsigned int dc_get_dmcu_psp_version(const struct dc *dc)
+{
+ if (!dc->res_pool || !dc->res_pool->dmcu)
+ return 0;
+
+ return dc->res_pool->dmcu->psp_version;
+}
+
+void dc_get_mall_en(struct dc *dc, unsigned int *mall_in_use)
+{
+ struct hubbub *hubbub = dc->res_pool ? dc->res_pool->hubbub : NULL;
+
+ *mall_in_use = false;
+
+ if (hubbub && hubbub->funcs->get_mall_en)
+ hubbub->funcs->get_mall_en(hubbub, mall_in_use);
}
-EXPORT_IF_KUNIT(dc_get_res_pool);
bool dc_get_dcc_compression_cap(const struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d5d53491e91c..11b5647ca032 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -6349,3 +6349,13 @@ bool resource_is_hpo_acquired(struct dc_state *context)
return false;
}
+
+enum dc_status dc_remove_stream_from_ctx(struct dc *dc,
+ struct dc_state *context, struct dc_stream_state *stream)
+{
+ if (dc->res_pool->funcs->remove_stream_from_ctx)
+ return dc->res_pool->funcs->remove_stream_from_ctx(
+ dc, context, stream);
+
+ return DC_OK;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index 28cd052e0727..65705f4941c1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2376,12 +2376,6 @@ struct dc_state *dc_get_current_state(const struct dc *dc);
/* Whether DC may enter idle power optimizations right now. */
bool dc_is_idle_optimizations_allowed(const struct dc *dc);
-/*
- * The hardware resource pool (DSC engines, audio instances, DMCU/ABM...).
- * Interim accessor; prefer purpose-built DC interfaces where available.
- */
-struct resource_pool *dc_get_res_pool(const struct dc *dc);
-
/*
* Temporary workaround for DP compliance test failures: disallow p-state
* switching for the given state, raise the memory clock to the maximum
@@ -2431,6 +2425,38 @@ bool dc_abm_set_event(struct dc *dc, unsigned int full_screen,
bool dc_abm_set_strength(struct dc *dc, unsigned int strength,
unsigned int panel_inst);
+/*
+ * Fill inst_array with the instance ids of the DIO audio blocks and
+ * return their count. inst_array must have room for MAX_AUDIOS entries.
+ */
+unsigned int dc_get_audio_instances(const struct dc *dc,
+ unsigned int *inst_array);
+
+/* Number of pipes available for rendering. */
+unsigned int dc_get_pipe_count(const struct dc *dc);
+
+/* Number of USB4 DPIA endpoints. */
+unsigned int dc_get_usb4_dpia_count(const struct dc *dc);
+
+/* Read the DMCU PSP version; 0 when there is no DMCU. */
+unsigned int dc_get_dmcu_psp_version(const struct dc *dc);
+
+/*
+ * Initialize the DMCU and update the ABM "DMCU running" state.
+ * No-op when the ASIC has no DMCU or ABM.
+ */
+void dc_dmcu_init_abm(struct dc *dc);
+
+/* Whether MALL is currently enabled. */
+void dc_get_mall_en(struct dc *dc, unsigned int *mall_in_use);
+
+/*
+ * Remove the resources assigned to a stream in the given state.
+ * Returns DC_OK when the ASIC does not implement the removal.
+ */
+enum dc_status dc_remove_stream_from_ctx(struct dc *dc,
+ struct dc_state *context, struct dc_stream_state *stream);
+
/*
* Query DCC compression support for a surface.
* return false - when the asic does not implement the query.
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 17/19] drm/amd/display: Replace the dc_get_res_pool accessor with purpose APIs
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Add the last purpose-built interfaces for the data DM was reading
through dc_get_res_pool() and drop the accessor entirely:
- dc_get_audio_instances() fills the audio instance id array for
amdgpu_dm_audio_init()
- dc_get_pipe_count() for the debugfs DCC bits dump
- dc_get_usb4_dpia_count() for the DMUB DPIA enablement
- dc_get_dmcu_psp_version() and dc_dmcu_init_abm() for the DMUB
hardware init path
- dc_get_mall_en() for the debugfs capabilities dump
- dc_remove_stream_from_ctx() for the MST DSC recomputation
No code outside the dc directory references struct resource_pool in
production anymore; only the KUnit tests keep installing fake pools
through dc_test_set_res_pool() / dm_kunit_alloc_res_pool().
Part of making the struct dc sub-structures opaque outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c | 8 +---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 7 +---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 14 ++-----
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 +--
.../display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c | 12 ++++--
.../display/amdgpu_dm/tests/amdgpu_dm_irq_test.c | 2 +-
.../amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c | 13 +++++++
.../amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h | 2 +
.../amdgpu_dm/tests/amdgpu_dm_mst_types_test.c | 5 ++-
.../amd/display/amdgpu_dm/tests/amdgpu_dm_test.c | 6 +--
drivers/gpu/drm/amd/display/dc/core/dc_abm.c | 11 ++++++
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 44 ++++++++++++++++++++--
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 10 +++++
drivers/gpu/drm/amd/display/dc/inc/dc.h | 38 ++++++++++++++++---
14 files changed, 135 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
index 23392b229679..0301081e040e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_audio.c
@@ -140,19 +140,15 @@ EXPORT_IF_KUNIT(amdgpu_dm_audio_init_pins);
int amdgpu_dm_audio_init(struct amdgpu_device *adev)
{
unsigned int inst_array[MAX_AUDIOS];
- struct resource_pool *res_pool;
int audio_count;
- int i, ret;
+ int ret;
if (!amdgpu_audio)
return 0;
adev->mode_info.audio.enabled = true;
- res_pool = dc_get_res_pool(adev->dm.dc);
- audio_count = res_pool->audio_count;
- for (i = 0; i < audio_count; i++)
- inst_array[i] = res_pool->audios[i]->inst;
+ audio_count = dc_get_audio_instances(adev->dm.dc, inst_array);
amdgpu_dm_audio_init_pins(adev, audio_count, inst_array);
ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 8d7ebb636554..8bc737117db9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -4464,10 +4464,7 @@ static int capabilities_show(struct seq_file *m, void *unused)
unsigned int mall_in_use = false;
unsigned int subvp_in_use = false;
- struct hubbub *hubbub = dc_get_res_pool(dc)->hubbub;
-
- if (hubbub && hubbub->funcs->get_mall_en)
- hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
+ dc_get_mall_en(dc, &mall_in_use);
subvp_in_use = dc_get_subvp_en(dc, dc_get_current_state(dc));
@@ -4609,7 +4606,7 @@ static ssize_t dcc_en_bits_read(
const uint32_t rd_buf_size = 32;
uint32_t result = 0;
int offset = 0;
- int num_pipes = dc_get_res_pool(dc)->pipe_count;
+ int num_pipes = dc_get_pipe_count(dc);
int *dcc_en_bits;
int i, r;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index ffe561da24d6..3ed6a9318931 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -232,9 +232,6 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
const struct firmware *dmub_fw = adev->dm.dmub_fw;
struct dc *dc = adev->dm.dc;
- struct resource_pool *res_pool = dc_get_res_pool(dc);
- struct dmcu *dmcu = res_pool->dmcu;
- struct abm *abm = res_pool->abm;
struct dc_context *ctx = dc_get_ctx(adev->dm.dc);
struct dmub_srv_hw_params hw_params;
enum dmub_status status;
@@ -333,14 +330,14 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
hw_params.load_inst_const = true;
- if (dmcu)
- hw_params.psp_version = dmcu->psp_version;
+ if (dc_has_dmcu(dc))
+ hw_params.psp_version = dc_get_dmcu_psp_version(dc);
hw_params.fb_info = fb_info;
/* Enable usb4 dpia in the FW APU */
if (dc_get_caps(dc)->is_apu &&
- dc_get_res_pool(dc)->usb4_dpia_count != 0 &&
+ dc_get_usb4_dpia_count(dc) != 0 &&
!dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia) {
hw_params.dpia_supported = true;
hw_params.disable_dpia = dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia;
@@ -375,10 +372,7 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
drm_warn(adev_to_drm(adev), "Wait for DMUB auto-load failed: %d\n", status);
/* Init DMCU and ABM if available. */
- if (dmcu && abm) {
- dmcu->funcs->dmcu_init(dmcu);
- abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
- }
+ dc_dmcu_init_abm(dc);
if (!dc_get_ctx(adev->dm.dc)->dmub_srv)
dc_get_ctx(adev->dm.dc)->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 4f9070579916..d533b72f1861 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1643,7 +1643,6 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
bool computed_streams[MAX_PIPES];
struct amdgpu_dm_connector *aconnector;
struct drm_dp_mst_topology_mgr *mst_mgr;
- struct resource_pool *res_pool;
int link_vars_start_index = 0;
int ret = 0;
@@ -1652,7 +1651,7 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
for (i = 0; i < dc_state->stream_count; i++) {
stream = dc_state->streams[i];
- res_pool = dc_get_res_pool(stream->ctx->dc);
+
if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
continue;
@@ -1671,8 +1670,7 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_commit *state,
if (computed_streams[i])
continue;
- if (res_pool->funcs->remove_stream_from_ctx &&
- res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
+ if (dc_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
return -EINVAL;
if (!is_dsc_need_re_compute(state, dc_state, stream->link))
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
index b71e1e11e85a..e1360a97ec26 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_dmub_test.c
@@ -731,11 +731,14 @@ static void dm_test_dmub_hw_init_auto_load_timeout(struct kunit *test)
*/
static void dm_test_dmub_hw_init_apu_dpia_dcn35(struct kunit *test)
{
+ struct resource_pool *res_pool;
+
struct amdgpu_device *adev = dm_test_alloc_adev_with_dmub(test);
adev->ip_versions[DCE_HWIP][0] = IP_VERSION(3, 5, 0);
dc_test_caps(adev->dm.dc)->is_apu = true;
- dc_get_res_pool(adev->dm.dc)->usb4_dpia_count = 1;
+ res_pool = dm_kunit_alloc_res_pool(test, adev->dm.dc);
+ res_pool->usb4_dpia_count = 1;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, adev->dm.dmub_srv->hw_init);
@@ -787,6 +790,8 @@ static void dm_test_dmub_hw_init_sanity_checks_dcn314(struct kunit *test)
*/
static void dm_test_dmub_hw_init_dmcu_abm(struct kunit *test)
{
+ struct resource_pool *res_pool;
+
struct amdgpu_device *adev = dm_test_alloc_adev_with_dmub(test);
struct dmcu *dmcu;
struct abm *abm;
@@ -799,8 +804,9 @@ static void dm_test_dmub_hw_init_dmcu_abm(struct kunit *test)
dmcu->funcs = &dm_test_dmcu_funcs;
dmcu->psp_version = 0x12345678;
- dc_get_res_pool(adev->dm.dc)->dmcu = dmcu;
- dc_get_res_pool(adev->dm.dc)->abm = abm;
+ res_pool = dm_kunit_alloc_res_pool(test, adev->dm.dc);
+ res_pool->dmcu = dmcu;
+ res_pool->abm = abm;
KUNIT_EXPECT_EQ(test, dm_dmub_hw_init(adev), 0);
KUNIT_EXPECT_TRUE(test, abm->dmcu_is_running);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
index ea467ca45af8..2ae534c4c252 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c
@@ -4188,7 +4188,7 @@ static void dm_test_crtc_high_irq_writeback_disables(struct kunit *test)
adev = dm_kunit_alloc_adev(test);
KUNIT_ASSERT_EQ(test, drm_vblank_init(&adev->ddev, 1), 0);
- /* dc_stream_fc_disable_writeback() dereferences dc_get_res_pool(dc). */
+ /* dc_stream_fc_disable_writeback() dereferences the DC resource pool. */
dc = dm_test_alloc_dc_with_irq_service(test,
&dm_test_irq_service_funcs_dcn10);
adev->dm.dc = dc;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
index 9954cbab6541..e4bea9fbad52 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_helpers.c
@@ -136,6 +136,19 @@ struct dc_state *dm_kunit_alloc_dc_state(struct kunit *test)
}
EXPORT_SYMBOL(dm_kunit_alloc_dc_state);
+struct resource_pool *dm_kunit_alloc_res_pool(struct kunit *test, struct dc *dc)
+{
+ struct resource_pool *res_pool;
+
+ res_pool = kunit_kzalloc(test, sizeof(*res_pool), GFP_KERNEL);
+ KUNIT_ASSERT_NOT_NULL(test, res_pool);
+
+ dc_test_set_res_pool(dc, res_pool);
+
+ return res_pool;
+}
+EXPORT_SYMBOL(dm_kunit_alloc_res_pool);
+
struct clk_mgr *dm_kunit_alloc_clk_mgr(struct kunit *test)
{
struct clk_mgr *clk_mgr;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
index b4bbf4a3750d..279d6eb79ad5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_kunit_test_helpers.h
@@ -28,6 +28,8 @@ struct dc_link *dm_kunit_alloc_link_with_ctx(struct kunit *test);
struct amdgpu_display_manager *dm_kunit_alloc_dm(struct kunit *test);
struct drm_device *dm_kunit_alloc_drm_with_connector_list(struct kunit *test);
struct dc_state *dm_kunit_alloc_dc_state(struct kunit *test);
+struct resource_pool;
+struct resource_pool *dm_kunit_alloc_res_pool(struct kunit *test, struct dc *dc);
struct clk_mgr *dm_kunit_alloc_clk_mgr(struct kunit *test);
struct dc_stream_state *dm_kunit_alloc_stream(struct kunit *test,
struct dc_link *link);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
index 144cb03f504a..da5c2f958bf1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c
@@ -2783,6 +2783,8 @@ static const struct dsc_funcs dm_mst_test_dsc_funcs = {
/* Install the DSC encoder fake and matching sink decoder capabilities. */
static void dm_mst_test_setup_dsc_caps(struct kunit *test, struct dc *dc, struct dc_sink *sink)
{
+ struct resource_pool *res_pool;
+
struct dsc_dec_dpcd_caps *dec = &sink->dsc_caps.dsc_dec_caps;
struct display_stream_compressor *dsc;
@@ -2791,7 +2793,8 @@ static void dm_mst_test_setup_dsc_caps(struct kunit *test, struct dc *dc, struct
dsc->funcs = &dm_mst_test_dsc_funcs;
dsc->ctx = dc_get_ctx(dc);
- dc_get_res_pool(dc)->dscs[0] = dsc;
+ res_pool = dm_kunit_alloc_res_pool(test, dc);
+ res_pool->dscs[0] = dsc;
dec->is_dsc_supported = true;
dec->dsc_version = 0x21;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
index 8cf460a4cb9f..0c27422cb8cf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
@@ -3388,8 +3388,7 @@ static void dm_test_oem_i2c_hw_init_no_device(struct kunit *test)
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc_test_set_res_pool(dc, kunit_kzalloc(test, sizeof(*dc_get_res_pool(dc)), GFP_KERNEL));
- KUNIT_ASSERT_NOT_NULL(test, dc_get_res_pool(dc));
+ dm_kunit_alloc_res_pool(test, dc);
adev->dm.dc = dc;
KUNIT_EXPECT_EQ(test, dm_oem_i2c_hw_init(adev), 0);
@@ -4981,8 +4980,7 @@ static struct amdgpu_device *dm_test_late_init_adev(struct kunit *test)
struct amdgpu_device *adev = dm_kunit_alloc_adev(test);
struct dc *dc = dm_kunit_alloc_dc_with_ctx(test);
- dc_test_set_res_pool(dc, kunit_kzalloc(test, sizeof(*dc_get_res_pool(dc)), GFP_KERNEL));
- KUNIT_ASSERT_NOT_NULL(test, dc_get_res_pool(dc));
+ dm_kunit_alloc_res_pool(test, dc);
adev->dm.dc = dc;
return adev;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_abm.c b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
index 1ed4b5fb6f93..28427e03289b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_abm.c
@@ -119,3 +119,14 @@ unsigned int dc_get_dmcu_abm_version(const struct dc *dc)
return dc->res_pool->dmcu->dmcu_version.abm_version;
}
+
+void dc_dmcu_init_abm(struct dc *dc)
+{
+ struct dmcu *dmcu = dc->res_pool ? dc->res_pool->dmcu : NULL;
+ struct abm *abm = dc->res_pool ? dc->res_pool->abm : NULL;
+
+ if (dmcu && abm) {
+ dmcu->funcs->dmcu_init(dmcu);
+ abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 9e8dffadfaec..163884db0294 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -32,6 +32,8 @@
*/
#include "dc.h"
#include "dc_priv.h"
+#include "core_types.h"
+#include "hw/dchubbub.h"
#include "dm_helpers.h" /* EXPORT_IF_KUNIT */
uint8_t dc_get_link_count(const struct dc *dc)
@@ -88,11 +90,47 @@ bool dc_is_idle_optimizations_allowed(const struct dc *dc)
}
EXPORT_IF_KUNIT(dc_is_idle_optimizations_allowed);
-struct resource_pool *dc_get_res_pool(const struct dc *dc)
+unsigned int dc_get_audio_instances(const struct dc *dc,
+ unsigned int *inst_array)
{
- return dc->res_pool;
+ unsigned int i;
+
+ for (i = 0; i < dc->res_pool->audio_count; i++)
+ inst_array[i] = dc->res_pool->audios[i]->inst;
+
+ return dc->res_pool->audio_count;
+}
+EXPORT_IF_KUNIT(dc_get_audio_instances);
+
+unsigned int dc_get_pipe_count(const struct dc *dc)
+{
+ return dc->res_pool->pipe_count;
+}
+EXPORT_IF_KUNIT(dc_get_pipe_count);
+
+unsigned int dc_get_usb4_dpia_count(const struct dc *dc)
+{
+ return dc->res_pool->usb4_dpia_count;
+}
+EXPORT_IF_KUNIT(dc_get_usb4_dpia_count);
+
+unsigned int dc_get_dmcu_psp_version(const struct dc *dc)
+{
+ if (!dc->res_pool || !dc->res_pool->dmcu)
+ return 0;
+
+ return dc->res_pool->dmcu->psp_version;
+}
+
+void dc_get_mall_en(struct dc *dc, unsigned int *mall_in_use)
+{
+ struct hubbub *hubbub = dc->res_pool ? dc->res_pool->hubbub : NULL;
+
+ *mall_in_use = false;
+
+ if (hubbub && hubbub->funcs->get_mall_en)
+ hubbub->funcs->get_mall_en(hubbub, mall_in_use);
}
-EXPORT_IF_KUNIT(dc_get_res_pool);
bool dc_get_dcc_compression_cap(const struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d5d53491e91c..11b5647ca032 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -6349,3 +6349,13 @@ bool resource_is_hpo_acquired(struct dc_state *context)
return false;
}
+
+enum dc_status dc_remove_stream_from_ctx(struct dc *dc,
+ struct dc_state *context, struct dc_stream_state *stream)
+{
+ if (dc->res_pool->funcs->remove_stream_from_ctx)
+ return dc->res_pool->funcs->remove_stream_from_ctx(
+ dc, context, stream);
+
+ return DC_OK;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index 28cd052e0727..65705f4941c1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2376,12 +2376,6 @@ struct dc_state *dc_get_current_state(const struct dc *dc);
/* Whether DC may enter idle power optimizations right now. */
bool dc_is_idle_optimizations_allowed(const struct dc *dc);
-/*
- * The hardware resource pool (DSC engines, audio instances, DMCU/ABM...).
- * Interim accessor; prefer purpose-built DC interfaces where available.
- */
-struct resource_pool *dc_get_res_pool(const struct dc *dc);
-
/*
* Temporary workaround for DP compliance test failures: disallow p-state
* switching for the given state, raise the memory clock to the maximum
@@ -2431,6 +2425,38 @@ bool dc_abm_set_event(struct dc *dc, unsigned int full_screen,
bool dc_abm_set_strength(struct dc *dc, unsigned int strength,
unsigned int panel_inst);
+/*
+ * Fill inst_array with the instance ids of the DIO audio blocks and
+ * return their count. inst_array must have room for MAX_AUDIOS entries.
+ */
+unsigned int dc_get_audio_instances(const struct dc *dc,
+ unsigned int *inst_array);
+
+/* Number of pipes available for rendering. */
+unsigned int dc_get_pipe_count(const struct dc *dc);
+
+/* Number of USB4 DPIA endpoints. */
+unsigned int dc_get_usb4_dpia_count(const struct dc *dc);
+
+/* Read the DMCU PSP version; 0 when there is no DMCU. */
+unsigned int dc_get_dmcu_psp_version(const struct dc *dc);
+
+/*
+ * Initialize the DMCU and update the ABM "DMCU running" state.
+ * No-op when the ASIC has no DMCU or ABM.
+ */
+void dc_dmcu_init_abm(struct dc *dc);
+
+/* Whether MALL is currently enabled. */
+void dc_get_mall_en(struct dc *dc, unsigned int *mall_in_use);
+
+/*
+ * Remove the resources assigned to a stream in the given state.
+ * Returns DC_OK when the ASIC does not implement the removal.
+ */
+enum dc_status dc_remove_stream_from_ctx(struct dc *dc,
+ struct dc_state *context, struct dc_stream_state *stream);
+
/*
* Query DCC compression support for a surface.
* return false - when the asic does not implement the query.
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 18/19] drm/amd/display: Replace dc_get_config with per-option config reads
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
The only external reads of struct dc_config were five runtime-mutable
options. Give each a purpose-built getter (dc_get_disable_ips,
dc_get_enable_frl, dc_get_consolidated_dpia_dp_lt,
dc_get_usb4_bw_alloc_support, dc_get_allow_edp_hotplug_detection,
complementing the existing setter) and drop the dc_get_config view.
KUnit tests install the options through dc_test_set_* setters.
No code outside the dc directory references struct dc_config in
production anymore.
Part of making the struct dc sub-structures opaque outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 14 ++++++-----
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 +--
.../display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c | 4 +--
.../amdgpu_dm/tests/amdgpu_dm_helpers_test.c | 4 +--
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 25 +++++++++++++++++--
drivers/gpu/drm/amd/display/dc/core/dc_test.c | 29 ++++++++++++++++++----
drivers/gpu/drm/amd/display/dc/inc/dc.h | 10 +++++---
drivers/gpu/drm/amd/display/dc/inc/dc_test.h | 6 ++++-
11 files changed, 77 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b601ec00ba05..6bfa3e9fe5ae 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -761,7 +761,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
}
if (dc_get_caps(adev->dm.dc)->ips_support &&
- dc_get_config(adev->dm.dc)->disable_ips != DMUB_IPS_DISABLE_ALL)
+ dc_get_disable_ips(adev->dm.dc) != DMUB_IPS_DISABLE_ALL)
adev->dm.idle_workqueue = idle_create_workqueue(adev);
if (dc_get_caps(adev->dm.dc)->max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 9c607ecc4bd6..a10f374f16df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -309,7 +309,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
* update the vblank counter in DRM.
*/
if (dc_get_caps(dc)->ips_support &&
- dc_get_config(dc)->disable_ips != DMUB_IPS_DISABLE_ALL &&
+ dc_get_disable_ips(dc) != DMUB_IPS_DISABLE_ALL &&
sr_supported && vblank->config.disable_immediate)
drm_crtc_vblank_restore(crtc);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 8bc737117db9..99400740cd66 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2701,7 +2701,7 @@ static int ips_status_show(struct seq_file *m, void *unused)
struct dc *dc = adev->dm.dc;
struct dc_dmub_srv *dc_dmub_srv;
- seq_printf(m, "IPS config: %d\n", dc_get_config(dc)->disable_ips);
+ seq_printf(m, "IPS config: %d\n", dc_get_disable_ips(dc));
seq_printf(m, "Idle optimization: %d\n", dc_is_idle_optimizations_allowed(dc));
if (adev->dm.idle_workqueue) {
@@ -3379,7 +3379,7 @@ static int allow_edp_hotplug_detection_get(void *data, u64 *val)
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- *val = dc_get_config(adev->dm.dc)->allow_edp_hotplug_detection;
+ *val = dc_get_allow_edp_hotplug_detection(adev->dm.dc);
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index 3ed6a9318931..9aee6fe047ba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -340,11 +340,11 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
dc_get_usb4_dpia_count(dc) != 0 &&
!dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia) {
hw_params.dpia_supported = true;
- hw_params.disable_dpia = dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia;
+ hw_params.disable_dpia =
+ dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia;
hw_params.dpia_hpd_int_enable_supported = false;
- hw_params.enable_non_transparent_setconfig =
- dc_get_config(dc)->consolidated_dpia_dp_lt;
- hw_params.disable_dpia_bw_allocation = !dc_get_config(dc)->usb4_bw_alloc_support;
+ hw_params.enable_non_transparent_setconfig = dc_get_consolidated_dpia_dp_lt(dc);
+ hw_params.disable_dpia_bw_allocation = !dc_get_usb4_bw_alloc_support(dc);
}
switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
@@ -399,14 +399,16 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
case IP_VERSION(3, 1, 3):
if (adev->dm.dmcub_fw_version &&
adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
- adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59))
+ adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59)) {
dc_get_debug_options_mutable(adev->dm.dc)->sanity_checks = true;
+ }
break;
case IP_VERSION(3, 1, 4):
if (adev->dm.dmcub_fw_version &&
adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
- adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16))
+ adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16)) {
dc_get_debug_options_mutable(adev->dm.dc)->sanity_checks = true;
+ }
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 542f9c4cb7e4..5a92e0a2b086 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -229,8 +229,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
if (edid_caps->edid_hdmi) {
edid_caps->qs_bit = connector->display_info.rgb_quant_range_selectable;
populate_hdmi_info_from_connector(
- dc_get_config(link->dc)->enable_frl,
- &connector->display_info.hdmi, edid_caps);
+ dc_get_enable_frl(link->dc),
+ &connector->display_info.hdmi, edid_caps);
drm_dbg_driver(connector->dev, "%s: HDMI_FRL [%s] max_frl_rate %d\n", __func__, connector->name, edid_caps->max_frl_rate);
if (edid_caps->frl_dsc_support)
drm_dbg_driver(connector->dev, "%s: HDMI_FRL_DSC [%s] frl_dsc_10bpc %d, frl_dsc_12bpc %d, frl_dsc_all_bpp %d, frl_dsc_native_420 %d, frl_dsc_max_slices %d, frl_dsc_max_frl_rate %d, frl_dsc_total_chunk_kbytes %d\n",
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
index 4543b0b0f993..1ebe9bef2c96 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
@@ -1194,7 +1194,7 @@ static void dm_test_crtc_enable_vblank_ips_restore(struct kunit *test)
/* IPS enabled and not fully disabled -> first restore condition holds. */
dc_test_caps(adev->dm.dc)->ips_support = true;
- dc_test_config(adev->dm.dc)->disable_ips = DMUB_IPS_ENABLE;
+ dc_test_set_disable_ips(adev->dm.dc, DMUB_IPS_ENABLE);
/* Supported PSR version makes self-refresh supported. */
link = acrtc_state->stream->link;
@@ -1241,7 +1241,7 @@ static void dm_test_crtc_enable_vblank_ips_restore_replay(struct kunit *test)
/* IPS enabled and not fully disabled -> first restore condition holds. */
dc_test_caps(adev->dm.dc)->ips_support = true;
- dc_test_config(adev->dm.dc)->disable_ips = DMUB_IPS_ENABLE;
+ dc_test_set_disable_ips(adev->dm.dc, DMUB_IPS_ENABLE);
/*
* PSR unsupported but replay supported -> sr_supported is driven by the
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
index 65bffc57ea40..e5145902d7d6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
@@ -435,7 +435,7 @@ static void dm_test_parse_edid_caps_hdmi_frl(struct kunit *test)
dc = dm_kunit_alloc_dc(test);
link->dc = dc;
- dc_test_config(dc)->enable_frl = true;
+ dc_test_set_enable_frl(dc, true);
dm_test_fill_base_edid(dc_edid, true);
@@ -477,7 +477,7 @@ static void dm_test_parse_edid_caps_hdmi_frl_dsc(struct kunit *test)
dc = dm_kunit_alloc_dc(test);
link->dc = dc;
- dc_test_config(dc)->enable_frl = true;
+ dc_test_set_enable_frl(dc, true);
dm_test_fill_base_edid(dc_edid, true);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 163884db0294..eb34a76262b1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -57,9 +57,25 @@ const struct dc_caps *dc_get_caps(const struct dc *dc)
return &dc->caps;
}
-const struct dc_config *dc_get_config(const struct dc *dc)
+unsigned int dc_get_disable_ips(const struct dc *dc)
{
- return &dc->config;
+ return dc->config.disable_ips;
+}
+EXPORT_IF_KUNIT(dc_get_disable_ips);
+
+bool dc_get_enable_frl(const struct dc *dc)
+{
+ return dc->config.enable_frl;
+}
+
+bool dc_get_consolidated_dpia_dp_lt(const struct dc *dc)
+{
+ return dc->config.consolidated_dpia_dp_lt;
+}
+
+bool dc_get_usb4_bw_alloc_support(const struct dc *dc)
+{
+ return dc->config.usb4_bw_alloc_support;
}
void dc_set_allow_edp_hotplug_detection(struct dc *dc,
@@ -68,6 +84,11 @@ void dc_set_allow_edp_hotplug_detection(struct dc *dc,
dc->config.allow_edp_hotplug_detection = hpd_select;
}
+unsigned int dc_get_allow_edp_hotplug_detection(const struct dc *dc)
+{
+ return dc->config.allow_edp_hotplug_detection;
+}
+
const struct dc_debug_options *dc_get_debug_options(const struct dc *dc)
{
return &dc->debug;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_test.c b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
index 04c799ae33d3..6431afb2b5b1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_test.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
@@ -105,17 +105,36 @@ void dc_test_set_idle_optimizations_allowed(struct dc *dc, bool allowed)
}
EXPORT_SYMBOL(dc_test_set_idle_optimizations_allowed);
+void dc_test_set_disable_ips(struct dc *dc, unsigned int disable_ips)
+{
+ dc->config.disable_ips = disable_ips;
+}
+EXPORT_SYMBOL(dc_test_set_disable_ips);
+
+void dc_test_set_enable_frl(struct dc *dc, bool enable)
+{
+ dc->config.enable_frl = enable;
+}
+EXPORT_SYMBOL(dc_test_set_enable_frl);
+
+void dc_test_set_consolidated_dpia_dp_lt(struct dc *dc, bool enable)
+{
+ dc->config.consolidated_dpia_dp_lt = enable;
+}
+EXPORT_SYMBOL(dc_test_set_consolidated_dpia_dp_lt);
+
+void dc_test_set_usb4_bw_alloc_support(struct dc *dc, bool enable)
+{
+ dc->config.usb4_bw_alloc_support = enable;
+}
+EXPORT_SYMBOL(dc_test_set_usb4_bw_alloc_support);
+
struct dc_caps *dc_test_caps(struct dc *dc)
{
return &dc->caps;
}
EXPORT_SYMBOL(dc_test_caps);
-struct dc_config *dc_test_config(struct dc *dc)
-{
- return &dc->config;
-}
-EXPORT_SYMBOL(dc_test_config);
struct dc_debug_options *dc_test_debug_options(struct dc *dc)
{
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index 65705f4941c1..31baba820f6c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2354,9 +2354,6 @@ enum dce_version dc_get_dce_version(const struct dc *dc);
/* Capabilities detected at dc_create() time. Read-only. */
const struct dc_caps *dc_get_caps(const struct dc *dc);
-/* Configuration captured at dc_create() time. Read-only. */
-const struct dc_config *dc_get_config(const struct dc *dc);
-
/*
* Select which eDP connectors get hotplug detection enabled; see
* enum dc_hpd_enable_select. Runtime configurable (debugfs).
@@ -2364,6 +2361,13 @@ const struct dc_config *dc_get_config(const struct dc *dc);
void dc_set_allow_edp_hotplug_detection(struct dc *dc,
enum dc_hpd_enable_select hpd_select);
+/* Configuration reads for the runtime-mutable options. */
+unsigned int dc_get_disable_ips(const struct dc *dc);
+bool dc_get_enable_frl(const struct dc *dc);
+bool dc_get_consolidated_dpia_dp_lt(const struct dc *dc);
+bool dc_get_usb4_bw_alloc_support(const struct dc *dc);
+unsigned int dc_get_allow_edp_hotplug_detection(const struct dc *dc);
+
/* Debug overrides (module parameters, debugfs). Read-only view. */
const struct dc_debug_options *dc_get_debug_options(const struct dc *dc);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_test.h b/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
index 61911de9da05..80f97e29246f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
@@ -69,9 +69,13 @@ void dc_test_set_link(struct dc *dc, unsigned int index, struct dc_link *link);
void dc_test_set_link_count(struct dc *dc, unsigned int count);
void dc_test_set_idle_optimizations_allowed(struct dc *dc, bool allowed);
+void dc_test_set_disable_ips(struct dc *dc, unsigned int disable_ips);
+void dc_test_set_enable_frl(struct dc *dc, bool enable);
+void dc_test_set_consolidated_dpia_dp_lt(struct dc *dc, bool enable);
+void dc_test_set_usb4_bw_alloc_support(struct dc *dc, bool enable);
+
/* Mutable views of embedded sub-structures, for test faking only. */
struct dc_caps *dc_test_caps(struct dc *dc);
-struct dc_config *dc_test_config(struct dc *dc);
struct dc_debug_options *dc_test_debug_options(struct dc *dc);
struct dc_cap_funcs *dc_test_cap_funcs(struct dc *dc);
struct hw_sequencer_funcs *dc_test_hwss(struct dc *dc);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 18/19] drm/amd/display: Replace dc_get_config with per-option config reads
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
The only external reads of struct dc_config were five runtime-mutable
options. Give each a purpose-built getter (dc_get_disable_ips,
dc_get_enable_frl, dc_get_consolidated_dpia_dp_lt,
dc_get_usb4_bw_alloc_support, dc_get_allow_edp_hotplug_detection,
complementing the existing setter) and drop the dc_get_config view.
KUnit tests install the options through dc_test_set_* setters.
No code outside the dc directory references struct dc_config in
production anymore.
Part of making the struct dc sub-structures opaque outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 4 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 14 ++++++-----
.../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 +--
.../display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c | 4 +--
.../amdgpu_dm/tests/amdgpu_dm_helpers_test.c | 4 +--
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 25 +++++++++++++++++--
drivers/gpu/drm/amd/display/dc/core/dc_test.c | 29 ++++++++++++++++++----
drivers/gpu/drm/amd/display/dc/inc/dc.h | 10 +++++---
drivers/gpu/drm/amd/display/dc/inc/dc_test.h | 6 ++++-
11 files changed, 77 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b601ec00ba05..6bfa3e9fe5ae 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -761,7 +761,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
}
if (dc_get_caps(adev->dm.dc)->ips_support &&
- dc_get_config(adev->dm.dc)->disable_ips != DMUB_IPS_DISABLE_ALL)
+ dc_get_disable_ips(adev->dm.dc) != DMUB_IPS_DISABLE_ALL)
adev->dm.idle_workqueue = idle_create_workqueue(adev);
if (dc_get_caps(adev->dm.dc)->max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 9c607ecc4bd6..a10f374f16df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -309,7 +309,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
* update the vblank counter in DRM.
*/
if (dc_get_caps(dc)->ips_support &&
- dc_get_config(dc)->disable_ips != DMUB_IPS_DISABLE_ALL &&
+ dc_get_disable_ips(dc) != DMUB_IPS_DISABLE_ALL &&
sr_supported && vblank->config.disable_immediate)
drm_crtc_vblank_restore(crtc);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 8bc737117db9..99400740cd66 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2701,7 +2701,7 @@ static int ips_status_show(struct seq_file *m, void *unused)
struct dc *dc = adev->dm.dc;
struct dc_dmub_srv *dc_dmub_srv;
- seq_printf(m, "IPS config: %d\n", dc_get_config(dc)->disable_ips);
+ seq_printf(m, "IPS config: %d\n", dc_get_disable_ips(dc));
seq_printf(m, "Idle optimization: %d\n", dc_is_idle_optimizations_allowed(dc));
if (adev->dm.idle_workqueue) {
@@ -3379,7 +3379,7 @@ static int allow_edp_hotplug_detection_get(void *data, u64 *val)
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- *val = dc_get_config(adev->dm.dc)->allow_edp_hotplug_detection;
+ *val = dc_get_allow_edp_hotplug_detection(adev->dm.dc);
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index 3ed6a9318931..9aee6fe047ba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -340,11 +340,11 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
dc_get_usb4_dpia_count(dc) != 0 &&
!dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia) {
hw_params.dpia_supported = true;
- hw_params.disable_dpia = dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia;
+ hw_params.disable_dpia =
+ dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia;
hw_params.dpia_hpd_int_enable_supported = false;
- hw_params.enable_non_transparent_setconfig =
- dc_get_config(dc)->consolidated_dpia_dp_lt;
- hw_params.disable_dpia_bw_allocation = !dc_get_config(dc)->usb4_bw_alloc_support;
+ hw_params.enable_non_transparent_setconfig = dc_get_consolidated_dpia_dp_lt(dc);
+ hw_params.disable_dpia_bw_allocation = !dc_get_usb4_bw_alloc_support(dc);
}
switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
@@ -399,14 +399,16 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
case IP_VERSION(3, 1, 3):
if (adev->dm.dmcub_fw_version &&
adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
- adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59))
+ adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59)) {
dc_get_debug_options_mutable(adev->dm.dc)->sanity_checks = true;
+ }
break;
case IP_VERSION(3, 1, 4):
if (adev->dm.dmcub_fw_version &&
adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
- adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16))
+ adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16)) {
dc_get_debug_options_mutable(adev->dm.dc)->sanity_checks = true;
+ }
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 542f9c4cb7e4..5a92e0a2b086 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -229,8 +229,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
if (edid_caps->edid_hdmi) {
edid_caps->qs_bit = connector->display_info.rgb_quant_range_selectable;
populate_hdmi_info_from_connector(
- dc_get_config(link->dc)->enable_frl,
- &connector->display_info.hdmi, edid_caps);
+ dc_get_enable_frl(link->dc),
+ &connector->display_info.hdmi, edid_caps);
drm_dbg_driver(connector->dev, "%s: HDMI_FRL [%s] max_frl_rate %d\n", __func__, connector->name, edid_caps->max_frl_rate);
if (edid_caps->frl_dsc_support)
drm_dbg_driver(connector->dev, "%s: HDMI_FRL_DSC [%s] frl_dsc_10bpc %d, frl_dsc_12bpc %d, frl_dsc_all_bpp %d, frl_dsc_native_420 %d, frl_dsc_max_slices %d, frl_dsc_max_frl_rate %d, frl_dsc_total_chunk_kbytes %d\n",
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
index 4543b0b0f993..1ebe9bef2c96 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_crtc_test.c
@@ -1194,7 +1194,7 @@ static void dm_test_crtc_enable_vblank_ips_restore(struct kunit *test)
/* IPS enabled and not fully disabled -> first restore condition holds. */
dc_test_caps(adev->dm.dc)->ips_support = true;
- dc_test_config(adev->dm.dc)->disable_ips = DMUB_IPS_ENABLE;
+ dc_test_set_disable_ips(adev->dm.dc, DMUB_IPS_ENABLE);
/* Supported PSR version makes self-refresh supported. */
link = acrtc_state->stream->link;
@@ -1241,7 +1241,7 @@ static void dm_test_crtc_enable_vblank_ips_restore_replay(struct kunit *test)
/* IPS enabled and not fully disabled -> first restore condition holds. */
dc_test_caps(adev->dm.dc)->ips_support = true;
- dc_test_config(adev->dm.dc)->disable_ips = DMUB_IPS_ENABLE;
+ dc_test_set_disable_ips(adev->dm.dc, DMUB_IPS_ENABLE);
/*
* PSR unsupported but replay supported -> sr_supported is driven by the
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
index 65bffc57ea40..e5145902d7d6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_helpers_test.c
@@ -435,7 +435,7 @@ static void dm_test_parse_edid_caps_hdmi_frl(struct kunit *test)
dc = dm_kunit_alloc_dc(test);
link->dc = dc;
- dc_test_config(dc)->enable_frl = true;
+ dc_test_set_enable_frl(dc, true);
dm_test_fill_base_edid(dc_edid, true);
@@ -477,7 +477,7 @@ static void dm_test_parse_edid_caps_hdmi_frl_dsc(struct kunit *test)
dc = dm_kunit_alloc_dc(test);
link->dc = dc;
- dc_test_config(dc)->enable_frl = true;
+ dc_test_set_enable_frl(dc, true);
dm_test_fill_base_edid(dc_edid, true);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index 163884db0294..eb34a76262b1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -57,9 +57,25 @@ const struct dc_caps *dc_get_caps(const struct dc *dc)
return &dc->caps;
}
-const struct dc_config *dc_get_config(const struct dc *dc)
+unsigned int dc_get_disable_ips(const struct dc *dc)
{
- return &dc->config;
+ return dc->config.disable_ips;
+}
+EXPORT_IF_KUNIT(dc_get_disable_ips);
+
+bool dc_get_enable_frl(const struct dc *dc)
+{
+ return dc->config.enable_frl;
+}
+
+bool dc_get_consolidated_dpia_dp_lt(const struct dc *dc)
+{
+ return dc->config.consolidated_dpia_dp_lt;
+}
+
+bool dc_get_usb4_bw_alloc_support(const struct dc *dc)
+{
+ return dc->config.usb4_bw_alloc_support;
}
void dc_set_allow_edp_hotplug_detection(struct dc *dc,
@@ -68,6 +84,11 @@ void dc_set_allow_edp_hotplug_detection(struct dc *dc,
dc->config.allow_edp_hotplug_detection = hpd_select;
}
+unsigned int dc_get_allow_edp_hotplug_detection(const struct dc *dc)
+{
+ return dc->config.allow_edp_hotplug_detection;
+}
+
const struct dc_debug_options *dc_get_debug_options(const struct dc *dc)
{
return &dc->debug;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_test.c b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
index 04c799ae33d3..6431afb2b5b1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_test.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
@@ -105,17 +105,36 @@ void dc_test_set_idle_optimizations_allowed(struct dc *dc, bool allowed)
}
EXPORT_SYMBOL(dc_test_set_idle_optimizations_allowed);
+void dc_test_set_disable_ips(struct dc *dc, unsigned int disable_ips)
+{
+ dc->config.disable_ips = disable_ips;
+}
+EXPORT_SYMBOL(dc_test_set_disable_ips);
+
+void dc_test_set_enable_frl(struct dc *dc, bool enable)
+{
+ dc->config.enable_frl = enable;
+}
+EXPORT_SYMBOL(dc_test_set_enable_frl);
+
+void dc_test_set_consolidated_dpia_dp_lt(struct dc *dc, bool enable)
+{
+ dc->config.consolidated_dpia_dp_lt = enable;
+}
+EXPORT_SYMBOL(dc_test_set_consolidated_dpia_dp_lt);
+
+void dc_test_set_usb4_bw_alloc_support(struct dc *dc, bool enable)
+{
+ dc->config.usb4_bw_alloc_support = enable;
+}
+EXPORT_SYMBOL(dc_test_set_usb4_bw_alloc_support);
+
struct dc_caps *dc_test_caps(struct dc *dc)
{
return &dc->caps;
}
EXPORT_SYMBOL(dc_test_caps);
-struct dc_config *dc_test_config(struct dc *dc)
-{
- return &dc->config;
-}
-EXPORT_SYMBOL(dc_test_config);
struct dc_debug_options *dc_test_debug_options(struct dc *dc)
{
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index 65705f4941c1..31baba820f6c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2354,9 +2354,6 @@ enum dce_version dc_get_dce_version(const struct dc *dc);
/* Capabilities detected at dc_create() time. Read-only. */
const struct dc_caps *dc_get_caps(const struct dc *dc);
-/* Configuration captured at dc_create() time. Read-only. */
-const struct dc_config *dc_get_config(const struct dc *dc);
-
/*
* Select which eDP connectors get hotplug detection enabled; see
* enum dc_hpd_enable_select. Runtime configurable (debugfs).
@@ -2364,6 +2361,13 @@ const struct dc_config *dc_get_config(const struct dc *dc);
void dc_set_allow_edp_hotplug_detection(struct dc *dc,
enum dc_hpd_enable_select hpd_select);
+/* Configuration reads for the runtime-mutable options. */
+unsigned int dc_get_disable_ips(const struct dc *dc);
+bool dc_get_enable_frl(const struct dc *dc);
+bool dc_get_consolidated_dpia_dp_lt(const struct dc *dc);
+bool dc_get_usb4_bw_alloc_support(const struct dc *dc);
+unsigned int dc_get_allow_edp_hotplug_detection(const struct dc *dc);
+
/* Debug overrides (module parameters, debugfs). Read-only view. */
const struct dc_debug_options *dc_get_debug_options(const struct dc *dc);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_test.h b/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
index 61911de9da05..80f97e29246f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_test.h
@@ -69,9 +69,13 @@ void dc_test_set_link(struct dc *dc, unsigned int index, struct dc_link *link);
void dc_test_set_link_count(struct dc *dc, unsigned int count);
void dc_test_set_idle_optimizations_allowed(struct dc *dc, bool allowed);
+void dc_test_set_disable_ips(struct dc *dc, unsigned int disable_ips);
+void dc_test_set_enable_frl(struct dc *dc, bool enable);
+void dc_test_set_consolidated_dpia_dp_lt(struct dc *dc, bool enable);
+void dc_test_set_usb4_bw_alloc_support(struct dc *dc, bool enable);
+
/* Mutable views of embedded sub-structures, for test faking only. */
struct dc_caps *dc_test_caps(struct dc *dc);
-struct dc_config *dc_test_config(struct dc *dc);
struct dc_debug_options *dc_test_debug_options(struct dc *dc);
struct dc_cap_funcs *dc_test_cap_funcs(struct dc *dc);
struct hw_sequencer_funcs *dc_test_hwss(struct dc *dc);
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 18/19] drm/amd/display: Replace dc_get_config with per-option config reads
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 20:31 ` Harry Wentland
-1 siblings, 0 replies; 52+ messages in thread
From: Harry Wentland @ 2026-11-12 20:31 UTC (permalink / raw)
To: airlied
Cc: Leo Li, Rodrigo Siqueira, Alex Deucher, Christian König,
David Airlie, Austin Zheng, Jun Lei, Kenneth Feng, amd-gfx,
dri-devel
On 11/11/26 20:43, Dave Airlie via B4 Relay wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> The only external reads of struct dc_config were five runtime-mutable
> options. Give each a purpose-built getter (dc_get_disable_ips,
> dc_get_enable_frl, dc_get_consolidated_dpia_dp_lt,
> dc_get_usb4_bw_alloc_support, dc_get_allow_edp_hotplug_detection,
> complementing the existing setter) and drop the dc_get_config view.
> KUnit tests install the options through dc_test_set_* setters.
>
> No code outside the dc directory references struct dc_config in
> production anymore.
>
> Part of making the struct dc sub-structures opaque outside DC.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
> ---
<snip>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_test.c b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
> index 04c799ae33d3..6431afb2b5b1 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_test.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_test.c
> @@ -105,17 +105,36 @@ void dc_test_set_idle_optimizations_allowed(struct dc *dc, bool allowed)
> }
> EXPORT_SYMBOL(dc_test_set_idle_optimizations_allowed);
>
> +void dc_test_set_disable_ips(struct dc *dc, unsigned int disable_ips)
> +{
> + dc->config.disable_ips = disable_ips;
> +}
> +EXPORT_SYMBOL(dc_test_set_disable_ips);
> +
> +void dc_test_set_enable_frl(struct dc *dc, bool enable)
> +{
> + dc->config.enable_frl = enable;
> +}
> +EXPORT_SYMBOL(dc_test_set_enable_frl);
> +
> +void dc_test_set_consolidated_dpia_dp_lt(struct dc *dc, bool enable)
> +{
> + dc->config.consolidated_dpia_dp_lt = enable;
> +}
> +EXPORT_SYMBOL(dc_test_set_consolidated_dpia_dp_lt);
> +
> +void dc_test_set_usb4_bw_alloc_support(struct dc *dc, bool enable)
> +{
> + dc->config.usb4_bw_alloc_support = enable;
> +}
> +EXPORT_SYMBOL(dc_test_set_usb4_bw_alloc_support);
> +
Similar to the comment on Patch 19/19, this creates a bit of API
bloat. Something like `dc_test_set_config(dc, config)` might be
better.
Harry
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 19/19] drm/amd/display: Replace dc_get_caps with purpose-built capability queries
2026-11-12 1:43 ` Dave Airlie via B4 Relay
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
-1 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
Split the caps view accessor into per-capability queries so DM and the
DAL modules no longer read through struct dc_caps:
- scalar getters for is_apu, ips/dmcub support, max links/streams/
planes/slave planes/cursor size/v_total, vtotal_limited_by_fp2,
i2c speed, PCON/DSC/fused-io support, SubVP processing delay and
MALL size
- dc_dmub_supports_psr()/dc_dmub_supports_aux_backlight() for the
DMUB capability bits
- dc_get_color_caps() copies out the color pipeline capabilities
- dc_get_plane_caps() returns the static plane capability array
The KUnit tests keep installing fake capabilities through the
dc_test_caps() view of their own fake DC.
No production code outside the dc directory reads struct dc members
through a caps view anymore.
Part of making the struct dc sub-structures opaque outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 48 +++++-----
.../amd/display/amdgpu_dm/amdgpu_dm_backlight.c | 4 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 38 ++++----
.../drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 7 +-
.../amd/display/amdgpu_dm/amdgpu_dm_connector.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 17 ++--
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 10 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 10 +-
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 26 ++++--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 4 +-
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 103 ++++++++++++++++++++-
drivers/gpu/drm/amd/display/dc/inc/dc.h | 36 ++++++-
.../drm/amd/display/modules/freesync/freesync.c | 6 +-
.../gpu/drm/amd/display/modules/power/power_abm.c | 2 +-
.../gpu/drm/amd/display/modules/power/power_psr.c | 2 +-
18 files changed, 241 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6bfa3e9fe5ae..bc3f9f5f8565 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -204,7 +204,7 @@ STATIC_IFN_KUNIT int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc
return 0;
}
- if (dc && dc_get_caps(dc)->ips_support && dc_is_idle_optimizations_allowed(dc))
+ if (dc && dc_get_ips_support(dc) && dc_is_idle_optimizations_allowed(dc))
dc_allow_idle_optimizations(dc, false);
/*
@@ -709,7 +709,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
/* temporary enable immediate restore for FAMS2 */
debug_opts->fams2_imm_restore_drr = true;
- if (dc_get_caps(adev->dm.dc)->dp_hdmi21_pcon_support)
+ if (dc_get_dp_hdmi21_pcon_support(adev->dm.dc))
drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n");
r = dm_dmub_hw_init(adev);
@@ -753,18 +753,18 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
amdgpu_dm_init_color_mod();
- if (dc_get_caps(adev->dm.dc)->max_links > 0) {
+ if (dc_get_max_links(adev->dm.dc) > 0) {
adev->dm.vblank_control_workqueue =
create_singlethread_workqueue("dm_vblank_control_workqueue");
if (!adev->dm.vblank_control_workqueue)
drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n");
}
- if (dc_get_caps(adev->dm.dc)->ips_support &&
+ if (dc_get_ips_support(adev->dm.dc) &&
dc_get_disable_ips(adev->dm.dc) != DMUB_IPS_DISABLE_ALL)
adev->dm.idle_workqueue = idle_create_workqueue(adev);
- if (dc_get_caps(adev->dm.dc)->max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
+ if (dc_get_max_links(adev->dm.dc) > 0 && adev->family >= AMDGPU_FAMILY_RV) {
adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
if (!adev->dm.hdcp_workqueue)
@@ -776,7 +776,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
dc_init_callbacks(adev->dm.dc, &init_params);
}
- if (dc_get_caps(adev->dm.dc)->max_links > 0) {
+ if (dc_get_max_links(adev->dm.dc) > 0) {
adev->dm.hdmi_frl_status_polling_wq =
create_singlethread_workqueue("hdmi_frl_status_polling_wq");
if (!adev->dm.hdmi_frl_status_polling_wq)
@@ -840,8 +840,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
/* TODO: Add_display_info? */
/* TODO use dynamic cursor width */
- adev_to_drm(adev)->mode_config.cursor_width = dc_get_caps(adev->dm.dc)->max_cursor_size;
- adev_to_drm(adev)->mode_config.cursor_height = dc_get_caps(adev->dm.dc)->max_cursor_size;
+ adev_to_drm(adev)->mode_config.cursor_width = dc_get_max_cursor_size(adev->dm.dc);
+ adev_to_drm(adev)->mode_config.cursor_height = dc_get_max_cursor_size(adev->dm.dc);
if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
drm_err(adev_to_drm(adev),
@@ -949,7 +949,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
&adev->dm.boot_time_crc_info.cpu_addr);
if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {
- for (i = 0; i < dc_get_caps(adev->dm.dc)->max_links; i++) {
+ for (i = 0; i < dc_get_max_links(adev->dm.dc); i++) {
if (adev->dm.hpd_rx_offload_wq[i].wq) {
destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
adev->dm.hpd_rx_offload_wq[i].wq = NULL;
@@ -1672,7 +1672,7 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block)
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
- if (dc_get_caps(dm->dc)->ips_support && adev->in_s0ix)
+ if (dc_get_ips_support(dm->dc) && adev->in_s0ix)
dc_allow_idle_optimizations(dm->dc, true);
dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
@@ -1897,7 +1897,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
int i, r, j;
struct dc_commit_streams_params commit_params = {};
- if (dc_get_caps(dm->dc)->ips_support) {
+ if (dc_get_ips_support(dm->dc)) {
if (!amdgpu_in_reset(adev))
mutex_lock(&dm->dc_lock);
@@ -2343,7 +2343,7 @@ STATIC_IFN_KUNIT int initialize_plane(struct amdgpu_display_manager *dm,
* for a CRTC - like overlay or underlay planes.
*/
possible_crtcs = 1 << plane_id;
- if (plane_id >= dc_get_caps(dm->dc)->max_streams)
+ if (plane_id >= dc_get_max_streams(dm->dc))
possible_crtcs = 0xff;
ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
@@ -2380,25 +2380,28 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
u32 link_cnt;
s32 primary_planes;
enum dc_connection_type new_connection_type = dc_connection_none;
+ const struct dc_plane_cap *plane_caps;
+ unsigned int plane_count;
const struct dc_plane_cap *plane;
bool psr_feature_enabled = false;
bool replay_feature_enabled = false;
- int max_overlay = dc_get_caps(dm->dc)->max_slave_planes;
+ int max_overlay = dc_get_max_slave_planes(dm->dc);
- dm->display_indexes_num = dc_get_caps(dm->dc)->max_streams;
+ dm->display_indexes_num = dc_get_max_streams(dm->dc);
/* Update the actual used number of crtc */
adev->mode_info.num_crtc = adev->dm.display_indexes_num;
amdgpu_dm_set_irq_funcs(adev);
- link_cnt = dc_get_caps(dm->dc)->max_links;
+ link_cnt = dc_get_max_links(dm->dc);
+ plane_caps = dc_get_plane_caps(dm->dc, &plane_count);
if (amdgpu_dm_mode_config_init(dm->adev)) {
drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n");
return -EINVAL;
}
/* There is one primary plane per CRTC */
- primary_planes = dc_get_caps(dm->dc)->max_streams;
+ primary_planes = dc_get_max_streams(dm->dc);
if (primary_planes > AMDGPU_MAX_PLANES) {
drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n");
return -EINVAL;
@@ -2409,7 +2412,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
* Order is reversed to match iteration order in atomic check.
*/
for (i = (primary_planes - 1); i >= 0; i--) {
- plane = &dc_get_caps(dm->dc)->planes[i];
+ plane = &plane_caps[i];
if (initialize_plane(dm, mode_info, i,
DRM_PLANE_TYPE_PRIMARY, plane)) {
@@ -2427,8 +2430,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
* Only support DCN for now, and only expose one so we don't encourage
* userspace to use up all the pipes.
*/
- for (i = 0; i < dc_get_caps(dm->dc)->max_planes; ++i) {
- const struct dc_plane_cap *plane = &dc_get_caps(dm->dc)->planes[i];
+ for (i = 0; i < plane_count; ++i) {
+ const struct dc_plane_cap *plane = &plane_caps[i];
/* Do not create overlay if MPO disabled */
if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
@@ -2450,7 +2453,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
}
}
- for (i = 0; i < dc_get_caps(dm->dc)->max_streams; i++)
+ for (i = 0; i < dc_get_max_streams(dm->dc); i++)
if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n");
goto fail;
@@ -3681,6 +3684,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_update_cursor(struct drm_plane *plane,
uint64_t address = afb ? afb->address : 0;
struct dc_cursor_position position = {0};
struct dc_cursor_attributes attributes;
+ struct dc_color_caps color_caps;
int ret;
if (!plane->state->fb && !old_plane_state->fb)
@@ -3707,6 +3711,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_update_cursor(struct drm_plane *plane,
amdgpu_crtc->cursor_width = plane->state->crtc_w;
amdgpu_crtc->cursor_height = plane->state->crtc_h;
+ dc_get_color_caps(adev->dm.dc, &color_caps);
memset(&attributes, 0, sizeof(attributes));
attributes.address.high_part = upper_32_bits(address);
attributes.address.low_part = lower_32_bits(address);
@@ -3719,8 +3724,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_update_cursor(struct drm_plane *plane,
/* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM
* legacy gamma setup.
*/
- if (crtc_state->cm_is_degamma_srgb &&
- dc_get_caps(adev->dm.dc)->color.dpp.gamma_corr)
+ if (crtc_state->cm_is_degamma_srgb && color_caps.dpp.gamma_corr)
attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
if (afb)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
index 194e52fdd9f5..efa1fe24d952 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
@@ -383,7 +383,7 @@ void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
}
mutex_lock(&dm->dc_lock);
- if (dc_get_caps(dm->dc)->ips_support && dc_get_ctx(dm->dc)->dmub_srv->idle_allowed) {
+ if (dc_get_ips_support(dm->dc) && dc_get_ctx(dm->dc)->dmub_srv->idle_allowed) {
dc_allow_idle_optimizations(dm->dc, false);
reallow_idle = true;
}
@@ -415,7 +415,7 @@ void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
amdgpu_dm_replay_set_event(dm, stream, true,
replay_event_hw_programming, true);
- if (dc_get_caps(dm->dc)->ips_support && reallow_idle)
+ if (dc_get_ips_support(dm->dc) && reallow_idle)
dc_allow_idle_optimizations(dm->dc, true);
mutex_unlock(&dm->dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index d86b9611568b..fd547e64f5d1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -1168,9 +1168,11 @@ int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
const struct drm_color_lut *shaper = NULL, *lut3d = NULL;
uint32_t exp_size, size, dim_size = MAX_COLOR_3DLUT_SIZE;
- const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
- bool has_3dlut =
- caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
+ struct dc_color_caps color_caps;
+ bool has_3dlut;
+
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+ has_3dlut = color_caps.dpp.hw_3d_lut || color_caps.mpc.preblend;
/* shaper LUT is only available if 3D LUT color caps */
exp_size = has_3dlut ? MAX_COLOR_LUT_ENTRIES : 0;
@@ -1553,7 +1555,7 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state,
struct dc_transfer_func *tf = &dc_plane_state->in_transfer_func;
struct drm_colorop *colorop = colorop_state->colorop;
struct drm_device *drm = colorop->dev;
- const struct dc_color_caps *color_caps = NULL;
+ struct dc_color_caps color_caps = { };
bool is_subsampled_format;
if (colorop->type != DRM_COLOROP_1D_CURVE)
@@ -1577,9 +1579,9 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state,
tf->tf = amdgpu_colorop_tf_to_dc_tf(colorop_state->curve_1d_type);
if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
- color_caps = &dc_get_caps(dc_plane_state->ctx->dc)->color;
+ dc_get_color_caps(dc_plane_state->ctx->dc, &color_caps);
- if (!mod_color_calculate_degamma_params(color_caps, tf, NULL,
+ if (!mod_color_calculate_degamma_params(&color_caps, tf, NULL,
is_subsampled_format)) {
drm_err(drm, "Failed to calculate degamma params\n");
return -EINVAL;
@@ -1867,9 +1869,11 @@ __set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state,
struct dc_transfer_func *tf = &dc_plane_state->cm.shaper_func;
struct drm_atomic_commit *state = plane_state->state;
const struct amdgpu_device *adev = drm_to_adev(colorop->dev);
- const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
- bool has_3dlut =
- caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
+ struct dc_color_caps color_caps;
+ bool has_3dlut;
+
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+ has_3dlut = color_caps.dpp.hw_3d_lut || color_caps.mpc.preblend;
const struct drm_device *dev = colorop->dev;
const struct drm_color_lut32 *lut3d;
uint32_t lut3d_size;
@@ -2048,9 +2052,11 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,
struct drm_colorop *colorop = plane_state->color_pipeline;
struct drm_device *dev = plane_state->plane->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
- bool has_3dlut =
- caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
+ struct dc_color_caps color_caps;
+ bool has_3dlut;
+
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+ has_3dlut = color_caps.dpp.hw_3d_lut || color_caps.mpc.preblend;
int ret;
/* Fixed Matrix (YUV to RGB) */
@@ -2162,7 +2168,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
struct amdgpu_device *adev = drm_to_adev(crtc->base.state->dev);
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
struct drm_color_ctm_3x4 *ctm = NULL;
- const struct dc_color_caps *color_caps = NULL;
+ struct dc_color_caps color_caps = { };
bool has_crtc_cm_degamma;
int ret;
@@ -2173,7 +2179,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
}
if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
- color_caps = &dc_get_caps(dc_plane_state->ctx->dc)->color;
+ dc_get_color_caps(dc_plane_state->ctx->dc, &color_caps);
/* Initially, we can just bypass the DGM block. */
dc_plane_state->in_transfer_func.type = TF_TYPE_BYPASS;
@@ -2182,7 +2188,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
/* After, we start to update values according to color props */
has_crtc_cm_degamma = (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb);
- ret = __set_dm_plane_degamma(plane_state, dc_plane_state, color_caps);
+ ret = __set_dm_plane_degamma(plane_state, dc_plane_state, &color_caps);
if (ret == -ENOMEM)
return ret;
@@ -2209,7 +2215,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
* linearize (implicit degamma) from sRGB/BT709 according to
* the input space.
*/
- ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state, color_caps);
+ ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state, &color_caps);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
index e912256eebb3..bf0294682f93 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
@@ -299,8 +299,11 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr
{
struct drm_device *dev = plane->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- bool hw_3d_lut = dc_get_caps(adev->dm.dc)->color.dpp.hw_3d_lut ||
- dc_get_caps(adev->dm.dc)->color.mpc.preblend;
+ struct dc_color_caps color_caps;
+ bool hw_3d_lut;
+
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+ hw_3d_lut = color_caps.dpp.hw_3d_lut || color_caps.mpc.preblend;
return amdgpu_dm_build_default_pipeline(dev, plane, hw_3d_lut, list);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index d1a672c721c4..814d9380890a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -1303,7 +1303,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
if (sink->sink_signal == SIGNAL_TYPE_EDP &&
!aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
- dc_get_caps(dc)->edp_dsc_support &&
+ dc_get_edp_dsc_support(dc) &&
aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index a10f374f16df..283de9ef8108 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -308,7 +308,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
* Call this function to estimate missed vblanks by using timestamps and
* update the vblank counter in DRM.
*/
- if (dc_get_caps(dc)->ips_support &&
+ if (dc_get_ips_support(dc) &&
dc_get_disable_ips(dc) != DMUB_IPS_DISABLE_ALL &&
sr_supported && vblank->config.disable_immediate)
drm_crtc_vblank_restore(crtc);
@@ -529,8 +529,11 @@ static void
dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
{
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
+ struct dc_color_caps color_caps;
- if (dc_get_caps(adev->dm.dc)->color.mpc.ogam_ram)
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+
+ if (color_caps.mpc.ogam_ram)
drm_object_attach_property(&crtc->base,
adev->mode_info.regamma_tf_property,
AMDGPU_TRANSFER_FUNCTION_DEFAULT);
@@ -770,9 +773,12 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
{
struct amdgpu_crtc *acrtc = NULL;
struct drm_plane *cursor_plane;
+ struct dc_color_caps color_caps;
bool has_degamma;
int res = -ENOMEM;
+ dc_get_color_caps(dm->dc, &color_caps);
+
cursor_plane = kzalloc_obj(*cursor_plane);
if (!cursor_plane)
goto fail;
@@ -809,12 +815,11 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
res = PTR_ERR(crtc_state);
goto error_ism_fini;
}
-
acrtc->base.state = crtc_state;
}
- acrtc->max_cursor_width = dc_get_caps(dm->adev->dm.dc)->max_cursor_size;
- acrtc->max_cursor_height = dc_get_caps(dm->adev->dm.dc)->max_cursor_size;
+ acrtc->max_cursor_width = dc_get_max_cursor_size(dm->adev->dm.dc);
+ acrtc->max_cursor_height = dc_get_max_cursor_size(dm->adev->dm.dc);
acrtc->crtc_id = crtc_index;
acrtc->base.enabled = false;
@@ -830,7 +835,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
* or the COLOR_PIPELINE property. An atomic commit which attempts to enable
* both is rejected.
*/
- has_degamma = dc_get_caps(dm->adev->dm.dc)->color.dpp.dcn_arch &&
+ has_degamma = color_caps.dpp.dcn_arch &&
dc_get_dce_version(dm->adev->dm.dc) != DCN_VERSION_4_01;
drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 99400740cd66..d2e9559af417 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -4459,8 +4459,8 @@ static int capabilities_show(struct seq_file *m, void *unused)
{
struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
struct dc *dc = adev->dm.dc;
- bool mall_supported = dc_get_caps(dc)->mall_size_total;
- bool subvp_supported = dc_get_caps(dc)->subvp_fw_processing_delay_us;
+ bool mall_supported = dc_get_mall_size_total(dc);
+ bool subvp_supported = dc_get_subvp_fw_processing_delay_us(dc);
unsigned int mall_in_use = false;
unsigned int subvp_in_use = false;
@@ -4708,7 +4708,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
&disable_hpd_ops);
- if (dc_get_caps(adev->dm.dc)->ips_support) {
+ if (dc_get_ips_support(adev->dm.dc)) {
debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,
&ips_status_fops);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index 9aee6fe047ba..4310cb6cca3f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -336,7 +336,7 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
hw_params.fb_info = fb_info;
/* Enable usb4 dpia in the FW APU */
- if (dc_get_caps(dc)->is_apu &&
+ if (dc_is_apu(dc) &&
dc_get_usb4_dpia_count(dc) != 0 &&
!dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia) {
hw_params.dpia_supported = true;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 73b56e078cbe..c71adc10c67e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -43,7 +43,7 @@ STATIC_IFN_KUNIT bool lp_write_i2c(void *handle, uint32_t address, const uint8_t
struct dc_link *link = handle;
struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };
struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW,
- dc_get_caps(link->dc)->i2c_speed_in_khz};
+ dc_get_i2c_speed_in_khz(link->dc)};
return dm_helpers_submit_i2c(link->ctx, link, &cmd);
}
@@ -56,7 +56,7 @@ STATIC_IFN_KUNIT bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset
struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset},
{false, address, size, data} };
struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW,
- dc_get_caps(link->dc)->i2c_speed_in_khz};
+ dc_get_i2c_speed_in_khz(link->dc)};
return dm_helpers_submit_i2c(link->ctx, link, &cmd);
}
@@ -308,7 +308,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
hdcp_w->aconnector[conn_index] = aconnector;
hdcp_get_link_display_adjustments(enable_encryption, content_type,
- dc_get_caps(dc)->fused_io_supported,
+ dc_get_fused_io_support(dc),
dc_get_debug_options(dc)->hdcp_lc_force_fw_enable,
dc_get_debug_options(dc)->hdcp_lc_enable_sw_fallback,
&link_adjust, &display_adjust);
@@ -677,7 +677,7 @@ void update_config(void *handle, struct cp_psp_stream_config *config)
link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS;
link->adjust.hdcp1.disable = 0;
link->adjust.hdcp2.use_fw_locality_check =
- (dc_get_caps(dc)->fused_io_supported ||
+ (dc_get_fused_io_support(dc) ||
dc_get_debug_options(dc)->hdcp_lc_force_fw_enable);
link->adjust.hdcp2.use_sw_locality_fallback =
dc_get_debug_options(dc)->hdcp_lc_enable_sw_fallback;
@@ -842,7 +842,7 @@ static const struct bin_attribute data_attr = {
struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev,
struct cp_psp *cp_psp, struct dc *dc)
{
- int max_caps = dc_get_caps(dc)->max_links;
+ int max_caps = dc_get_max_links(dc);
struct hdcp_workqueue *hdcp_work;
int i = 0;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 57e1dcf6bb45..375826ef16e9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -808,7 +808,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
st = (state == AMDGPU_IRQ_STATE_ENABLE);
- if (dc && dc_get_caps(dc)->ips_support && dc_is_idle_optimizations_allowed(dc))
+ if (dc && dc_get_ips_support(dc) && dc_is_idle_optimizations_allowed(dc))
dc_allow_idle_optimizations(dc, false);
amdgpu_dm_irq_set(adev, irq_source, st);
@@ -1226,7 +1226,7 @@ EXPORT_IF_KUNIT(dm_handle_hpd_rx_offload_work);
struct hpd_rx_irq_offload_work_queue *amdgpu_dm_hpd_rx_irq_create_workqueue(struct amdgpu_device *adev)
{
struct dc *dc = adev->dm.dc;
- int max_caps = dc_get_caps(dc)->max_links;
+ int max_caps = dc_get_max_links(dc);
int i = 0;
struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
@@ -1265,7 +1265,7 @@ void amdgpu_dm_hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
int i;
if (dm->hpd_rx_offload_wq) {
- for (i = 0; i < dc_get_caps(dm->dc)->max_links; i++)
+ for (i = 0; i < dc_get_max_links(dm->dc); i++)
flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
}
}
@@ -1321,7 +1321,7 @@ void amdgpu_dm_hdmi_hpd_debounce_work(struct work_struct *work)
/* Re-detect the display */
scoped_guard(mutex, &adev->dm.dc_lock) {
- if (dc_get_caps(dc)->ips_support && dc_get_ctx(dc)->dmub_srv->idle_allowed) {
+ if (dc_get_ips_support(dc) && dc_get_ctx(dc)->dmub_srv->idle_allowed) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
@@ -1359,7 +1359,7 @@ void amdgpu_dm_hdmi_hpd_debounce_work(struct work_struct *work)
}
scoped_guard(mutex, &adev->dm.dc_lock) {
- if (reallow_idle && dc_get_caps(dc)->ips_support)
+ if (reallow_idle && dc_get_ips_support(dc))
dc_allow_idle_optimizations(dc, true);
}
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index d533b72f1861..b3fd02867f92 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1239,7 +1239,7 @@ STATIC_IFN_KUNIT bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector,
unsigned int dsc_max_sink_bw_in_kbps = 0;
if (aconnector->dc_sink &&
- dc_get_caps(aconnector->dc_link->dc)->dp_hdmi21_pcon_support &&
+ dc_get_dp_hdmi21_pcon_support(aconnector->dc_link->dc) &&
aconnector->mst_downstream_port_caps.bytes.byte0.bits.DWN_STRM_PORTX_TYPE == DOWN_STREAM_DETAILED_HDMI) {
max_conv_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(
aconnector->dc_link->dc,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index eba044bc47df..206071965b44 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1333,8 +1333,13 @@ STATIC_IFN_KUNIT void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_de
{
struct amdgpu_device *adev = drm_to_adev(dev);
struct dc *dc = adev->dm.dc;
+ const struct dc_plane_cap *plane_caps;
+ unsigned int plane_count;
/* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
- const struct dc_plane_cap *plane_cap = &dc_get_caps(dc)->planes[0];
+ const struct dc_plane_cap *plane_cap;
+
+ plane_caps = dc_get_plane_caps(dc, &plane_count);
+ plane_cap = &plane_caps[0];
switch (fb->format->format) {
case DRM_FORMAT_P010:
@@ -1646,6 +1651,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
uint64_t address = afb ? afb->address : 0;
struct dc_cursor_position position = {0};
struct dc_cursor_attributes attributes;
+ struct dc_color_caps color_caps;
int ret;
if (!plane->state->fb && !old_plane_state->fb)
@@ -1681,6 +1687,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
amdgpu_crtc->cursor_width = plane->state->crtc_w;
amdgpu_crtc->cursor_height = plane->state->crtc_h;
+ dc_get_color_caps(adev->dm.dc, &color_caps);
memset(&attributes, 0, sizeof(attributes));
attributes.address.high_part = upper_32_bits(address);
attributes.address.low_part = lower_32_bits(address);
@@ -1693,8 +1700,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
/* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM
* legacy gamma setup.
*/
- if (crtc_state->cm_is_degamma_srgb &&
- dc_get_caps(adev->dm.dc)->color.dpp.gamma_corr)
+ if (crtc_state->cm_is_degamma_srgb && color_caps.dpp.gamma_corr)
attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
if (afb)
@@ -1974,7 +1980,11 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
struct drm_plane *plane)
{
struct amdgpu_mode_info mode_info = dm->adev->mode_info;
- struct dpp_color_caps dpp_color_caps = dc_get_caps(dm->dc)->color.dpp;
+ struct dc_color_caps color_caps;
+ struct dpp_color_caps dpp_color_caps;
+
+ dc_get_color_caps(dm->dc, &color_caps);
+ dpp_color_caps = color_caps.dpp;
/* Check HW color pipeline capabilities on DPP block (pre-blending)
* before exposing related properties.
@@ -1996,11 +2006,11 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
AMDGPU_HDR_MULT_DEFAULT);
/* Only enable plane CTM if both DPP and MPC gamut remap is available. */
- if (dc_get_caps(dm->dc)->color.mpc.gamut_remap)
+ if (color_caps.mpc.gamut_remap)
drm_object_attach_property(&plane->base,
dm->adev->mode_info.plane_ctm_property, 0);
- if (dpp_color_caps.hw_3d_lut || dc_get_caps(dm->dc)->color.mpc.preblend) {
+ if (dpp_color_caps.hw_3d_lut || color_caps.mpc.preblend) {
drm_object_attach_property(&plane->base,
mode_info.plane_shaper_lut_property, 0);
drm_object_attach_property(&plane->base,
@@ -2016,7 +2026,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
MAX_COLOR_3DLUT_SIZE);
}
- if (dpp_color_caps.ogam_ram || dc_get_caps(dm->dc)->color.mpc.preblend) {
+ if (dpp_color_caps.ogam_ram || color_caps.mpc.preblend) {
drm_object_attach_property(&plane->base,
mode_info.plane_blend_lut_property, 0);
drm_object_attach_property(&plane->base,
@@ -2215,7 +2225,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
int res = -EPERM;
unsigned int supported_rotations;
uint64_t *modifiers = NULL;
- unsigned int primary_zpos = dc_get_caps(dm->dc)->max_slave_planes;
+ unsigned int primary_zpos = dc_get_max_slave_planes(dm->dc);
num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,
ARRAY_SIZE(formats));
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index f71f66b04d5e..271ea6fe05d1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -37,7 +37,7 @@ bool link_supports_psrsu(struct dc_link *link)
{
struct dc *dc = link->ctx->dc;
- if (!dc_get_caps(dc)->dmcub_support)
+ if (!dc_get_dmcub_support(dc))
return false;
if (dc_get_dce_version(dc) < DCN_VERSION_3_1)
@@ -111,7 +111,7 @@ bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *ac
/* Reset psr version first */
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
- if (!dc_get_caps(dc)->dmub_caps.psr)
+ if (!dc_dmub_supports_psr(dc))
return false;
if (!(link->connector_signal & SIGNAL_TYPE_EDP))
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index eb34a76262b1..c2f1d428a8d7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -52,9 +52,108 @@ enum dce_version dc_get_dce_version(const struct dc *dc)
return dc->ctx->dce_version;
}
-const struct dc_caps *dc_get_caps(const struct dc *dc)
+bool dc_is_apu(const struct dc *dc)
{
- return &dc->caps;
+ return dc->caps.is_apu;
+}
+
+bool dc_get_ips_support(const struct dc *dc)
+{
+ return dc->caps.ips_support;
+}
+
+bool dc_get_dmcub_support(const struct dc *dc)
+{
+ return dc->caps.dmcub_support;
+}
+
+unsigned int dc_get_max_links(const struct dc *dc)
+{
+ return dc->caps.max_links;
+}
+
+unsigned int dc_get_max_streams(const struct dc *dc)
+{
+ return dc->caps.max_streams;
+}
+
+unsigned int dc_get_max_planes(const struct dc *dc)
+{
+ return dc->caps.max_planes;
+}
+
+unsigned int dc_get_max_slave_planes(const struct dc *dc)
+{
+ return dc->caps.max_slave_planes;
+}
+
+unsigned int dc_get_max_cursor_size(const struct dc *dc)
+{
+ return dc->caps.max_cursor_size;
+}
+
+unsigned int dc_get_max_v_total(const struct dc *dc)
+{
+ return dc->caps.max_v_total;
+}
+
+bool dc_get_vtotal_limited_by_fp2(const struct dc *dc)
+{
+ return dc->caps.vtotal_limited_by_fp2;
+}
+
+unsigned int dc_get_i2c_speed_in_khz(const struct dc *dc)
+{
+ return dc->caps.i2c_speed_in_khz;
+}
+
+bool dc_get_dp_hdmi21_pcon_support(const struct dc *dc)
+{
+ return dc->caps.dp_hdmi21_pcon_support;
+}
+
+bool dc_get_edp_dsc_support(const struct dc *dc)
+{
+ return dc->caps.edp_dsc_support;
+}
+
+bool dc_get_fused_io_support(const struct dc *dc)
+{
+ return dc->caps.fused_io_supported;
+}
+
+unsigned int dc_get_subvp_fw_processing_delay_us(const struct dc *dc)
+{
+ return dc->caps.subvp_fw_processing_delay_us;
+}
+
+unsigned int dc_get_mall_size_total(const struct dc *dc)
+{
+ return dc->caps.mall_size_total;
+}
+
+bool dc_dmub_supports_psr(const struct dc *dc)
+{
+ return dc->caps.dmub_caps.psr;
+}
+
+bool dc_dmub_supports_aux_backlight(const struct dc *dc)
+{
+ return dc->caps.dmub_caps.aux_backlight_support;
+}
+
+void dc_get_color_caps(const struct dc *dc, struct dc_color_caps *caps)
+{
+ *caps = dc->caps.color;
+}
+
+const struct dc_plane_cap *dc_get_plane_caps(const struct dc *dc,
+ unsigned int *count)
+{
+ if (count)
+ *count = dc->caps.max_planes;
+
+ return dc->caps.planes;
}
unsigned int dc_get_disable_ips(const struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index 31baba820f6c..7a49f2ee1d77 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2351,8 +2351,38 @@ struct dc_context *dc_get_ctx(const struct dc *dc);
/* The ASIC display engine version. */
enum dce_version dc_get_dce_version(const struct dc *dc);
-/* Capabilities detected at dc_create() time. Read-only. */
-const struct dc_caps *dc_get_caps(const struct dc *dc);
+/*
+ * Capabilities detected at dc_create() time. Read-only; prefer the
+ * purpose-built queries below over reaching into the caps structure.
+ */
+bool dc_is_apu(const struct dc *dc);
+bool dc_get_ips_support(const struct dc *dc);
+bool dc_get_dmcub_support(const struct dc *dc);
+unsigned int dc_get_max_links(const struct dc *dc);
+unsigned int dc_get_max_streams(const struct dc *dc);
+unsigned int dc_get_max_planes(const struct dc *dc);
+unsigned int dc_get_max_slave_planes(const struct dc *dc);
+unsigned int dc_get_max_cursor_size(const struct dc *dc);
+unsigned int dc_get_max_v_total(const struct dc *dc);
+bool dc_get_vtotal_limited_by_fp2(const struct dc *dc);
+unsigned int dc_get_i2c_speed_in_khz(const struct dc *dc);
+bool dc_get_dp_hdmi21_pcon_support(const struct dc *dc);
+bool dc_get_edp_dsc_support(const struct dc *dc);
+bool dc_get_fused_io_support(const struct dc *dc);
+unsigned int dc_get_subvp_fw_processing_delay_us(const struct dc *dc);
+unsigned int dc_get_mall_size_total(const struct dc *dc);
+bool dc_dmub_supports_psr(const struct dc *dc);
+bool dc_dmub_supports_aux_backlight(const struct dc *dc);
+
+/* Copy out the color pipeline capabilities. */
+void dc_get_color_caps(const struct dc *dc, struct dc_color_caps *caps);
+
+/*
+ * Return the static plane capability array and its entry count.
+ * Valid until the DC is destroyed.
+ */
+const struct dc_plane_cap *dc_get_plane_caps(const struct dc *dc,
+ unsigned int *count);
/*
* Select which eDP connectors get hotplug detection enabled; see
@@ -2512,7 +2542,7 @@ void dc_set_dml2_alt_ch_cfg(struct dc *dc,
/* Return an enumerated dc_link.
* dc_link order is constant and determined at
* boot time. They cannot be created or destroyed.
- * Use dc_get_caps() to get number of links.
+ * Use dc_get_max_links() to get number of links.
*/
struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index dafcb42504f8..7deb641c7ae8 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -125,9 +125,9 @@ static unsigned int calc_duration_in_us_from_v_total(
static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)
{
- unsigned int max_hw_v_total = dc_get_caps(stream->ctx->dc)->max_v_total;
+ unsigned int max_hw_v_total = dc_get_max_v_total(stream->ctx->dc);
- if (dc_get_caps(stream->ctx->dc)->vtotal_limited_by_fp2)
+ if (dc_get_vtotal_limited_by_fp2(stream->ctx->dc))
max_hw_v_total -= stream->timing.v_front_porch + 1;
return max_hw_v_total;
@@ -1007,7 +1007,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
nominal_field_rate_in_uhz =
mod_freesync_calc_nominal_field_rate(stream);
- if (dc_get_caps(stream->ctx->dc)->max_v_total != 0 && stream->timing.h_total != 0) {
+ if (dc_get_max_v_total(stream->ctx->dc) != 0 && stream->timing.h_total != 0) {
min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
(stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));
}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
index ae2fa3b12e1a..652b7ad198f3 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_abm.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
@@ -935,7 +935,7 @@ static bool set_backlight_millinits_aux(struct core_power *core_power,
// only use internal backlight control if dmub capabilities are not present
if (link->backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX &&
- dc_get_caps(link->dc)->dmub_caps.aux_backlight_support)
+ dc_dmub_supports_aux_backlight(link->dc))
return true;
return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR,
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
index 219b199350cd..3cd06e0d267b 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_psr.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
@@ -645,7 +645,7 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
config->dsc_slice_height = 0;
if (!(link->connector_signal & SIGNAL_TYPE_EDP) ||
- !dc_get_caps(dc)->edp_dsc_support ||
+ !dc_get_edp_dsc_support(dc) ||
link->panel_config.dsc.disable_dsc_edp ||
!link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
!stream->timing.dsc_cfg.num_slices_v)
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 19/19] drm/amd/display: Replace dc_get_caps with purpose-built capability queries
@ 2026-11-12 1:43 ` Dave Airlie via B4 Relay
0 siblings, 0 replies; 52+ messages in thread
From: Dave Airlie via B4 Relay @ 2026-11-12 1:43 UTC (permalink / raw)
To: Harry Wentland, Leo Li, Rodrigo Siqueira, Alex Deucher,
Christian König, David Airlie, Austin Zheng, Jun Lei,
Kenneth Feng
Cc: amd-gfx, dri-devel, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Split the caps view accessor into per-capability queries so DM and the
DAL modules no longer read through struct dc_caps:
- scalar getters for is_apu, ips/dmcub support, max links/streams/
planes/slave planes/cursor size/v_total, vtotal_limited_by_fp2,
i2c speed, PCON/DSC/fused-io support, SubVP processing delay and
MALL size
- dc_dmub_supports_psr()/dc_dmub_supports_aux_backlight() for the
DMUB capability bits
- dc_get_color_caps() copies out the color pipeline capabilities
- dc_get_plane_caps() returns the static plane capability array
The KUnit tests keep installing fake capabilities through the
dc_test_caps() view of their own fake DC.
No production code outside the dc directory reads struct dc members
through a caps view anymore.
Part of making the struct dc sub-structures opaque outside DC.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 48 +++++-----
.../amd/display/amdgpu_dm/amdgpu_dm_backlight.c | 4 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 38 ++++----
.../drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c | 7 +-
.../amd/display/amdgpu_dm/amdgpu_dm_connector.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 17 ++--
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 10 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 10 +-
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 26 ++++--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 4 +-
drivers/gpu/drm/amd/display/dc/core/dc_accessors.c | 103 ++++++++++++++++++++-
drivers/gpu/drm/amd/display/dc/inc/dc.h | 36 ++++++-
.../drm/amd/display/modules/freesync/freesync.c | 6 +-
.../gpu/drm/amd/display/modules/power/power_abm.c | 2 +-
.../gpu/drm/amd/display/modules/power/power_psr.c | 2 +-
18 files changed, 241 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6bfa3e9fe5ae..bc3f9f5f8565 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -204,7 +204,7 @@ STATIC_IFN_KUNIT int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc
return 0;
}
- if (dc && dc_get_caps(dc)->ips_support && dc_is_idle_optimizations_allowed(dc))
+ if (dc && dc_get_ips_support(dc) && dc_is_idle_optimizations_allowed(dc))
dc_allow_idle_optimizations(dc, false);
/*
@@ -709,7 +709,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
/* temporary enable immediate restore for FAMS2 */
debug_opts->fams2_imm_restore_drr = true;
- if (dc_get_caps(adev->dm.dc)->dp_hdmi21_pcon_support)
+ if (dc_get_dp_hdmi21_pcon_support(adev->dm.dc))
drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n");
r = dm_dmub_hw_init(adev);
@@ -753,18 +753,18 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
amdgpu_dm_init_color_mod();
- if (dc_get_caps(adev->dm.dc)->max_links > 0) {
+ if (dc_get_max_links(adev->dm.dc) > 0) {
adev->dm.vblank_control_workqueue =
create_singlethread_workqueue("dm_vblank_control_workqueue");
if (!adev->dm.vblank_control_workqueue)
drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n");
}
- if (dc_get_caps(adev->dm.dc)->ips_support &&
+ if (dc_get_ips_support(adev->dm.dc) &&
dc_get_disable_ips(adev->dm.dc) != DMUB_IPS_DISABLE_ALL)
adev->dm.idle_workqueue = idle_create_workqueue(adev);
- if (dc_get_caps(adev->dm.dc)->max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
+ if (dc_get_max_links(adev->dm.dc) > 0 && adev->family >= AMDGPU_FAMILY_RV) {
adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
if (!adev->dm.hdcp_workqueue)
@@ -776,7 +776,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
dc_init_callbacks(adev->dm.dc, &init_params);
}
- if (dc_get_caps(adev->dm.dc)->max_links > 0) {
+ if (dc_get_max_links(adev->dm.dc) > 0) {
adev->dm.hdmi_frl_status_polling_wq =
create_singlethread_workqueue("hdmi_frl_status_polling_wq");
if (!adev->dm.hdmi_frl_status_polling_wq)
@@ -840,8 +840,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
/* TODO: Add_display_info? */
/* TODO use dynamic cursor width */
- adev_to_drm(adev)->mode_config.cursor_width = dc_get_caps(adev->dm.dc)->max_cursor_size;
- adev_to_drm(adev)->mode_config.cursor_height = dc_get_caps(adev->dm.dc)->max_cursor_size;
+ adev_to_drm(adev)->mode_config.cursor_width = dc_get_max_cursor_size(adev->dm.dc);
+ adev_to_drm(adev)->mode_config.cursor_height = dc_get_max_cursor_size(adev->dm.dc);
if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
drm_err(adev_to_drm(adev),
@@ -949,7 +949,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
&adev->dm.boot_time_crc_info.cpu_addr);
if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) {
- for (i = 0; i < dc_get_caps(adev->dm.dc)->max_links; i++) {
+ for (i = 0; i < dc_get_max_links(adev->dm.dc); i++) {
if (adev->dm.hpd_rx_offload_wq[i].wq) {
destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
adev->dm.hpd_rx_offload_wq[i].wq = NULL;
@@ -1672,7 +1672,7 @@ static int dm_suspend(struct amdgpu_ip_block *ip_block)
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
- if (dc_get_caps(dm->dc)->ips_support && adev->in_s0ix)
+ if (dc_get_ips_support(dm->dc) && adev->in_s0ix)
dc_allow_idle_optimizations(dm->dc, true);
dc_dmub_srv_set_power_state(dc_get_ctx(dm->dc)->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);
@@ -1897,7 +1897,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
int i, r, j;
struct dc_commit_streams_params commit_params = {};
- if (dc_get_caps(dm->dc)->ips_support) {
+ if (dc_get_ips_support(dm->dc)) {
if (!amdgpu_in_reset(adev))
mutex_lock(&dm->dc_lock);
@@ -2343,7 +2343,7 @@ STATIC_IFN_KUNIT int initialize_plane(struct amdgpu_display_manager *dm,
* for a CRTC - like overlay or underlay planes.
*/
possible_crtcs = 1 << plane_id;
- if (plane_id >= dc_get_caps(dm->dc)->max_streams)
+ if (plane_id >= dc_get_max_streams(dm->dc))
possible_crtcs = 0xff;
ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
@@ -2380,25 +2380,28 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
u32 link_cnt;
s32 primary_planes;
enum dc_connection_type new_connection_type = dc_connection_none;
+ const struct dc_plane_cap *plane_caps;
+ unsigned int plane_count;
const struct dc_plane_cap *plane;
bool psr_feature_enabled = false;
bool replay_feature_enabled = false;
- int max_overlay = dc_get_caps(dm->dc)->max_slave_planes;
+ int max_overlay = dc_get_max_slave_planes(dm->dc);
- dm->display_indexes_num = dc_get_caps(dm->dc)->max_streams;
+ dm->display_indexes_num = dc_get_max_streams(dm->dc);
/* Update the actual used number of crtc */
adev->mode_info.num_crtc = adev->dm.display_indexes_num;
amdgpu_dm_set_irq_funcs(adev);
- link_cnt = dc_get_caps(dm->dc)->max_links;
+ link_cnt = dc_get_max_links(dm->dc);
+ plane_caps = dc_get_plane_caps(dm->dc, &plane_count);
if (amdgpu_dm_mode_config_init(dm->adev)) {
drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n");
return -EINVAL;
}
/* There is one primary plane per CRTC */
- primary_planes = dc_get_caps(dm->dc)->max_streams;
+ primary_planes = dc_get_max_streams(dm->dc);
if (primary_planes > AMDGPU_MAX_PLANES) {
drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n");
return -EINVAL;
@@ -2409,7 +2412,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
* Order is reversed to match iteration order in atomic check.
*/
for (i = (primary_planes - 1); i >= 0; i--) {
- plane = &dc_get_caps(dm->dc)->planes[i];
+ plane = &plane_caps[i];
if (initialize_plane(dm, mode_info, i,
DRM_PLANE_TYPE_PRIMARY, plane)) {
@@ -2427,8 +2430,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
* Only support DCN for now, and only expose one so we don't encourage
* userspace to use up all the pipes.
*/
- for (i = 0; i < dc_get_caps(dm->dc)->max_planes; ++i) {
- const struct dc_plane_cap *plane = &dc_get_caps(dm->dc)->planes[i];
+ for (i = 0; i < plane_count; ++i) {
+ const struct dc_plane_cap *plane = &plane_caps[i];
/* Do not create overlay if MPO disabled */
if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
@@ -2450,7 +2453,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
}
}
- for (i = 0; i < dc_get_caps(dm->dc)->max_streams; i++)
+ for (i = 0; i < dc_get_max_streams(dm->dc); i++)
if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n");
goto fail;
@@ -3681,6 +3684,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_update_cursor(struct drm_plane *plane,
uint64_t address = afb ? afb->address : 0;
struct dc_cursor_position position = {0};
struct dc_cursor_attributes attributes;
+ struct dc_color_caps color_caps;
int ret;
if (!plane->state->fb && !old_plane_state->fb)
@@ -3707,6 +3711,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_update_cursor(struct drm_plane *plane,
amdgpu_crtc->cursor_width = plane->state->crtc_w;
amdgpu_crtc->cursor_height = plane->state->crtc_h;
+ dc_get_color_caps(adev->dm.dc, &color_caps);
memset(&attributes, 0, sizeof(attributes));
attributes.address.high_part = upper_32_bits(address);
attributes.address.low_part = lower_32_bits(address);
@@ -3719,8 +3724,7 @@ STATIC_IFN_KUNIT void amdgpu_dm_update_cursor(struct drm_plane *plane,
/* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM
* legacy gamma setup.
*/
- if (crtc_state->cm_is_degamma_srgb &&
- dc_get_caps(adev->dm.dc)->color.dpp.gamma_corr)
+ if (crtc_state->cm_is_degamma_srgb && color_caps.dpp.gamma_corr)
attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
if (afb)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
index 194e52fdd9f5..efa1fe24d952 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_backlight.c
@@ -383,7 +383,7 @@ void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
}
mutex_lock(&dm->dc_lock);
- if (dc_get_caps(dm->dc)->ips_support && dc_get_ctx(dm->dc)->dmub_srv->idle_allowed) {
+ if (dc_get_ips_support(dm->dc) && dc_get_ctx(dm->dc)->dmub_srv->idle_allowed) {
dc_allow_idle_optimizations(dm->dc, false);
reallow_idle = true;
}
@@ -415,7 +415,7 @@ void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
amdgpu_dm_replay_set_event(dm, stream, true,
replay_event_hw_programming, true);
- if (dc_get_caps(dm->dc)->ips_support && reallow_idle)
+ if (dc_get_ips_support(dm->dc) && reallow_idle)
dc_allow_idle_optimizations(dm->dc, true);
mutex_unlock(&dm->dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index d86b9611568b..fd547e64f5d1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -1168,9 +1168,11 @@ int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
const struct drm_color_lut *shaper = NULL, *lut3d = NULL;
uint32_t exp_size, size, dim_size = MAX_COLOR_3DLUT_SIZE;
- const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
- bool has_3dlut =
- caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
+ struct dc_color_caps color_caps;
+ bool has_3dlut;
+
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+ has_3dlut = color_caps.dpp.hw_3d_lut || color_caps.mpc.preblend;
/* shaper LUT is only available if 3D LUT color caps */
exp_size = has_3dlut ? MAX_COLOR_LUT_ENTRIES : 0;
@@ -1553,7 +1555,7 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state,
struct dc_transfer_func *tf = &dc_plane_state->in_transfer_func;
struct drm_colorop *colorop = colorop_state->colorop;
struct drm_device *drm = colorop->dev;
- const struct dc_color_caps *color_caps = NULL;
+ struct dc_color_caps color_caps = { };
bool is_subsampled_format;
if (colorop->type != DRM_COLOROP_1D_CURVE)
@@ -1577,9 +1579,9 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state,
tf->tf = amdgpu_colorop_tf_to_dc_tf(colorop_state->curve_1d_type);
if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
- color_caps = &dc_get_caps(dc_plane_state->ctx->dc)->color;
+ dc_get_color_caps(dc_plane_state->ctx->dc, &color_caps);
- if (!mod_color_calculate_degamma_params(color_caps, tf, NULL,
+ if (!mod_color_calculate_degamma_params(&color_caps, tf, NULL,
is_subsampled_format)) {
drm_err(drm, "Failed to calculate degamma params\n");
return -EINVAL;
@@ -1867,9 +1869,11 @@ __set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state,
struct dc_transfer_func *tf = &dc_plane_state->cm.shaper_func;
struct drm_atomic_commit *state = plane_state->state;
const struct amdgpu_device *adev = drm_to_adev(colorop->dev);
- const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
- bool has_3dlut =
- caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
+ struct dc_color_caps color_caps;
+ bool has_3dlut;
+
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+ has_3dlut = color_caps.dpp.hw_3d_lut || color_caps.mpc.preblend;
const struct drm_device *dev = colorop->dev;
const struct drm_color_lut32 *lut3d;
uint32_t lut3d_size;
@@ -2048,9 +2052,11 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,
struct drm_colorop *colorop = plane_state->color_pipeline;
struct drm_device *dev = plane_state->plane->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- const struct dc_caps *caps = dc_get_caps(adev->dm.dc);
- bool has_3dlut =
- caps->color.dpp.hw_3d_lut || caps->color.mpc.preblend;
+ struct dc_color_caps color_caps;
+ bool has_3dlut;
+
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+ has_3dlut = color_caps.dpp.hw_3d_lut || color_caps.mpc.preblend;
int ret;
/* Fixed Matrix (YUV to RGB) */
@@ -2162,7 +2168,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
struct amdgpu_device *adev = drm_to_adev(crtc->base.state->dev);
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
struct drm_color_ctm_3x4 *ctm = NULL;
- const struct dc_color_caps *color_caps = NULL;
+ struct dc_color_caps color_caps = { };
bool has_crtc_cm_degamma;
int ret;
@@ -2173,7 +2179,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
}
if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
- color_caps = &dc_get_caps(dc_plane_state->ctx->dc)->color;
+ dc_get_color_caps(dc_plane_state->ctx->dc, &color_caps);
/* Initially, we can just bypass the DGM block. */
dc_plane_state->in_transfer_func.type = TF_TYPE_BYPASS;
@@ -2182,7 +2188,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
/* After, we start to update values according to color props */
has_crtc_cm_degamma = (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb);
- ret = __set_dm_plane_degamma(plane_state, dc_plane_state, color_caps);
+ ret = __set_dm_plane_degamma(plane_state, dc_plane_state, &color_caps);
if (ret == -ENOMEM)
return ret;
@@ -2209,7 +2215,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
* linearize (implicit degamma) from sRGB/BT709 according to
* the input space.
*/
- ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state, color_caps);
+ ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state, &color_caps);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
index e912256eebb3..bf0294682f93 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
@@ -299,8 +299,11 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr
{
struct drm_device *dev = plane->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
- bool hw_3d_lut = dc_get_caps(adev->dm.dc)->color.dpp.hw_3d_lut ||
- dc_get_caps(adev->dm.dc)->color.mpc.preblend;
+ struct dc_color_caps color_caps;
+ bool hw_3d_lut;
+
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+ hw_3d_lut = color_caps.dpp.hw_3d_lut || color_caps.mpc.preblend;
return amdgpu_dm_build_default_pipeline(dev, plane, hw_3d_lut, list);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index d1a672c721c4..814d9380890a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -1303,7 +1303,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
if (sink->sink_signal == SIGNAL_TYPE_EDP &&
!aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
- dc_get_caps(dc)->edp_dsc_support &&
+ dc_get_edp_dsc_support(dc) &&
aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index a10f374f16df..283de9ef8108 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -308,7 +308,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
* Call this function to estimate missed vblanks by using timestamps and
* update the vblank counter in DRM.
*/
- if (dc_get_caps(dc)->ips_support &&
+ if (dc_get_ips_support(dc) &&
dc_get_disable_ips(dc) != DMUB_IPS_DISABLE_ALL &&
sr_supported && vblank->config.disable_immediate)
drm_crtc_vblank_restore(crtc);
@@ -529,8 +529,11 @@ static void
dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
{
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
+ struct dc_color_caps color_caps;
- if (dc_get_caps(adev->dm.dc)->color.mpc.ogam_ram)
+ dc_get_color_caps(adev->dm.dc, &color_caps);
+
+ if (color_caps.mpc.ogam_ram)
drm_object_attach_property(&crtc->base,
adev->mode_info.regamma_tf_property,
AMDGPU_TRANSFER_FUNCTION_DEFAULT);
@@ -770,9 +773,12 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
{
struct amdgpu_crtc *acrtc = NULL;
struct drm_plane *cursor_plane;
+ struct dc_color_caps color_caps;
bool has_degamma;
int res = -ENOMEM;
+ dc_get_color_caps(dm->dc, &color_caps);
+
cursor_plane = kzalloc_obj(*cursor_plane);
if (!cursor_plane)
goto fail;
@@ -809,12 +815,11 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
res = PTR_ERR(crtc_state);
goto error_ism_fini;
}
-
acrtc->base.state = crtc_state;
}
- acrtc->max_cursor_width = dc_get_caps(dm->adev->dm.dc)->max_cursor_size;
- acrtc->max_cursor_height = dc_get_caps(dm->adev->dm.dc)->max_cursor_size;
+ acrtc->max_cursor_width = dc_get_max_cursor_size(dm->adev->dm.dc);
+ acrtc->max_cursor_height = dc_get_max_cursor_size(dm->adev->dm.dc);
acrtc->crtc_id = crtc_index;
acrtc->base.enabled = false;
@@ -830,7 +835,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
* or the COLOR_PIPELINE property. An atomic commit which attempts to enable
* both is rejected.
*/
- has_degamma = dc_get_caps(dm->adev->dm.dc)->color.dpp.dcn_arch &&
+ has_degamma = color_caps.dpp.dcn_arch &&
dc_get_dce_version(dm->adev->dm.dc) != DCN_VERSION_4_01;
drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 99400740cd66..d2e9559af417 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -4459,8 +4459,8 @@ static int capabilities_show(struct seq_file *m, void *unused)
{
struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
struct dc *dc = adev->dm.dc;
- bool mall_supported = dc_get_caps(dc)->mall_size_total;
- bool subvp_supported = dc_get_caps(dc)->subvp_fw_processing_delay_us;
+ bool mall_supported = dc_get_mall_size_total(dc);
+ bool subvp_supported = dc_get_subvp_fw_processing_delay_us(dc);
unsigned int mall_in_use = false;
unsigned int subvp_in_use = false;
@@ -4708,7 +4708,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
&disable_hpd_ops);
- if (dc_get_caps(adev->dm.dc)->ips_support) {
+ if (dc_get_ips_support(adev->dm.dc)) {
debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,
&ips_status_fops);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
index 9aee6fe047ba..4310cb6cca3f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c
@@ -336,7 +336,7 @@ int dm_dmub_hw_init(struct amdgpu_device *adev)
hw_params.fb_info = fb_info;
/* Enable usb4 dpia in the FW APU */
- if (dc_get_caps(dc)->is_apu &&
+ if (dc_is_apu(dc) &&
dc_get_usb4_dpia_count(dc) != 0 &&
!dc_get_debug_options(dc)->dpia_debug.bits.disable_dpia) {
hw_params.dpia_supported = true;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 73b56e078cbe..c71adc10c67e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -43,7 +43,7 @@ STATIC_IFN_KUNIT bool lp_write_i2c(void *handle, uint32_t address, const uint8_t
struct dc_link *link = handle;
struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };
struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW,
- dc_get_caps(link->dc)->i2c_speed_in_khz};
+ dc_get_i2c_speed_in_khz(link->dc)};
return dm_helpers_submit_i2c(link->ctx, link, &cmd);
}
@@ -56,7 +56,7 @@ STATIC_IFN_KUNIT bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset
struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset},
{false, address, size, data} };
struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW,
- dc_get_caps(link->dc)->i2c_speed_in_khz};
+ dc_get_i2c_speed_in_khz(link->dc)};
return dm_helpers_submit_i2c(link->ctx, link, &cmd);
}
@@ -308,7 +308,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
hdcp_w->aconnector[conn_index] = aconnector;
hdcp_get_link_display_adjustments(enable_encryption, content_type,
- dc_get_caps(dc)->fused_io_supported,
+ dc_get_fused_io_support(dc),
dc_get_debug_options(dc)->hdcp_lc_force_fw_enable,
dc_get_debug_options(dc)->hdcp_lc_enable_sw_fallback,
&link_adjust, &display_adjust);
@@ -677,7 +677,7 @@ void update_config(void *handle, struct cp_psp_stream_config *config)
link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS;
link->adjust.hdcp1.disable = 0;
link->adjust.hdcp2.use_fw_locality_check =
- (dc_get_caps(dc)->fused_io_supported ||
+ (dc_get_fused_io_support(dc) ||
dc_get_debug_options(dc)->hdcp_lc_force_fw_enable);
link->adjust.hdcp2.use_sw_locality_fallback =
dc_get_debug_options(dc)->hdcp_lc_enable_sw_fallback;
@@ -842,7 +842,7 @@ static const struct bin_attribute data_attr = {
struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev,
struct cp_psp *cp_psp, struct dc *dc)
{
- int max_caps = dc_get_caps(dc)->max_links;
+ int max_caps = dc_get_max_links(dc);
struct hdcp_workqueue *hdcp_work;
int i = 0;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 57e1dcf6bb45..375826ef16e9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -808,7 +808,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev,
st = (state == AMDGPU_IRQ_STATE_ENABLE);
- if (dc && dc_get_caps(dc)->ips_support && dc_is_idle_optimizations_allowed(dc))
+ if (dc && dc_get_ips_support(dc) && dc_is_idle_optimizations_allowed(dc))
dc_allow_idle_optimizations(dc, false);
amdgpu_dm_irq_set(adev, irq_source, st);
@@ -1226,7 +1226,7 @@ EXPORT_IF_KUNIT(dm_handle_hpd_rx_offload_work);
struct hpd_rx_irq_offload_work_queue *amdgpu_dm_hpd_rx_irq_create_workqueue(struct amdgpu_device *adev)
{
struct dc *dc = adev->dm.dc;
- int max_caps = dc_get_caps(dc)->max_links;
+ int max_caps = dc_get_max_links(dc);
int i = 0;
struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
@@ -1265,7 +1265,7 @@ void amdgpu_dm_hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
int i;
if (dm->hpd_rx_offload_wq) {
- for (i = 0; i < dc_get_caps(dm->dc)->max_links; i++)
+ for (i = 0; i < dc_get_max_links(dm->dc); i++)
flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
}
}
@@ -1321,7 +1321,7 @@ void amdgpu_dm_hdmi_hpd_debounce_work(struct work_struct *work)
/* Re-detect the display */
scoped_guard(mutex, &adev->dm.dc_lock) {
- if (dc_get_caps(dc)->ips_support && dc_get_ctx(dc)->dmub_srv->idle_allowed) {
+ if (dc_get_ips_support(dc) && dc_get_ctx(dc)->dmub_srv->idle_allowed) {
dc_allow_idle_optimizations(dc, false);
reallow_idle = true;
}
@@ -1359,7 +1359,7 @@ void amdgpu_dm_hdmi_hpd_debounce_work(struct work_struct *work)
}
scoped_guard(mutex, &adev->dm.dc_lock) {
- if (reallow_idle && dc_get_caps(dc)->ips_support)
+ if (reallow_idle && dc_get_ips_support(dc))
dc_allow_idle_optimizations(dc, true);
}
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index d533b72f1861..b3fd02867f92 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1239,7 +1239,7 @@ STATIC_IFN_KUNIT bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector,
unsigned int dsc_max_sink_bw_in_kbps = 0;
if (aconnector->dc_sink &&
- dc_get_caps(aconnector->dc_link->dc)->dp_hdmi21_pcon_support &&
+ dc_get_dp_hdmi21_pcon_support(aconnector->dc_link->dc) &&
aconnector->mst_downstream_port_caps.bytes.byte0.bits.DWN_STRM_PORTX_TYPE == DOWN_STREAM_DETAILED_HDMI) {
max_conv_bw_in_kbps = dc_link_bw_kbps_from_raw_frl_link_rate_data(
aconnector->dc_link->dc,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index eba044bc47df..206071965b44 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1333,8 +1333,13 @@ STATIC_IFN_KUNIT void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_de
{
struct amdgpu_device *adev = drm_to_adev(dev);
struct dc *dc = adev->dm.dc;
+ const struct dc_plane_cap *plane_caps;
+ unsigned int plane_count;
/* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
- const struct dc_plane_cap *plane_cap = &dc_get_caps(dc)->planes[0];
+ const struct dc_plane_cap *plane_cap;
+
+ plane_caps = dc_get_plane_caps(dc, &plane_count);
+ plane_cap = &plane_caps[0];
switch (fb->format->format) {
case DRM_FORMAT_P010:
@@ -1646,6 +1651,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
uint64_t address = afb ? afb->address : 0;
struct dc_cursor_position position = {0};
struct dc_cursor_attributes attributes;
+ struct dc_color_caps color_caps;
int ret;
if (!plane->state->fb && !old_plane_state->fb)
@@ -1681,6 +1687,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
amdgpu_crtc->cursor_width = plane->state->crtc_w;
amdgpu_crtc->cursor_height = plane->state->crtc_h;
+ dc_get_color_caps(adev->dm.dc, &color_caps);
memset(&attributes, 0, sizeof(attributes));
attributes.address.high_part = upper_32_bits(address);
attributes.address.low_part = lower_32_bits(address);
@@ -1693,8 +1700,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
/* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM
* legacy gamma setup.
*/
- if (crtc_state->cm_is_degamma_srgb &&
- dc_get_caps(adev->dm.dc)->color.dpp.gamma_corr)
+ if (crtc_state->cm_is_degamma_srgb && color_caps.dpp.gamma_corr)
attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;
if (afb)
@@ -1974,7 +1980,11 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
struct drm_plane *plane)
{
struct amdgpu_mode_info mode_info = dm->adev->mode_info;
- struct dpp_color_caps dpp_color_caps = dc_get_caps(dm->dc)->color.dpp;
+ struct dc_color_caps color_caps;
+ struct dpp_color_caps dpp_color_caps;
+
+ dc_get_color_caps(dm->dc, &color_caps);
+ dpp_color_caps = color_caps.dpp;
/* Check HW color pipeline capabilities on DPP block (pre-blending)
* before exposing related properties.
@@ -1996,11 +2006,11 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
AMDGPU_HDR_MULT_DEFAULT);
/* Only enable plane CTM if both DPP and MPC gamut remap is available. */
- if (dc_get_caps(dm->dc)->color.mpc.gamut_remap)
+ if (color_caps.mpc.gamut_remap)
drm_object_attach_property(&plane->base,
dm->adev->mode_info.plane_ctm_property, 0);
- if (dpp_color_caps.hw_3d_lut || dc_get_caps(dm->dc)->color.mpc.preblend) {
+ if (dpp_color_caps.hw_3d_lut || color_caps.mpc.preblend) {
drm_object_attach_property(&plane->base,
mode_info.plane_shaper_lut_property, 0);
drm_object_attach_property(&plane->base,
@@ -2016,7 +2026,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
MAX_COLOR_3DLUT_SIZE);
}
- if (dpp_color_caps.ogam_ram || dc_get_caps(dm->dc)->color.mpc.preblend) {
+ if (dpp_color_caps.ogam_ram || color_caps.mpc.preblend) {
drm_object_attach_property(&plane->base,
mode_info.plane_blend_lut_property, 0);
drm_object_attach_property(&plane->base,
@@ -2215,7 +2225,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
int res = -EPERM;
unsigned int supported_rotations;
uint64_t *modifiers = NULL;
- unsigned int primary_zpos = dc_get_caps(dm->dc)->max_slave_planes;
+ unsigned int primary_zpos = dc_get_max_slave_planes(dm->dc);
num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,
ARRAY_SIZE(formats));
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index f71f66b04d5e..271ea6fe05d1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -37,7 +37,7 @@ bool link_supports_psrsu(struct dc_link *link)
{
struct dc *dc = link->ctx->dc;
- if (!dc_get_caps(dc)->dmcub_support)
+ if (!dc_get_dmcub_support(dc))
return false;
if (dc_get_dce_version(dc) < DCN_VERSION_3_1)
@@ -111,7 +111,7 @@ bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *ac
/* Reset psr version first */
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
- if (!dc_get_caps(dc)->dmub_caps.psr)
+ if (!dc_dmub_supports_psr(dc))
return false;
if (!(link->connector_signal & SIGNAL_TYPE_EDP))
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
index eb34a76262b1..c2f1d428a8d7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_accessors.c
@@ -52,9 +52,108 @@ enum dce_version dc_get_dce_version(const struct dc *dc)
return dc->ctx->dce_version;
}
-const struct dc_caps *dc_get_caps(const struct dc *dc)
+bool dc_is_apu(const struct dc *dc)
{
- return &dc->caps;
+ return dc->caps.is_apu;
+}
+
+bool dc_get_ips_support(const struct dc *dc)
+{
+ return dc->caps.ips_support;
+}
+
+bool dc_get_dmcub_support(const struct dc *dc)
+{
+ return dc->caps.dmcub_support;
+}
+
+unsigned int dc_get_max_links(const struct dc *dc)
+{
+ return dc->caps.max_links;
+}
+
+unsigned int dc_get_max_streams(const struct dc *dc)
+{
+ return dc->caps.max_streams;
+}
+
+unsigned int dc_get_max_planes(const struct dc *dc)
+{
+ return dc->caps.max_planes;
+}
+
+unsigned int dc_get_max_slave_planes(const struct dc *dc)
+{
+ return dc->caps.max_slave_planes;
+}
+
+unsigned int dc_get_max_cursor_size(const struct dc *dc)
+{
+ return dc->caps.max_cursor_size;
+}
+
+unsigned int dc_get_max_v_total(const struct dc *dc)
+{
+ return dc->caps.max_v_total;
+}
+
+bool dc_get_vtotal_limited_by_fp2(const struct dc *dc)
+{
+ return dc->caps.vtotal_limited_by_fp2;
+}
+
+unsigned int dc_get_i2c_speed_in_khz(const struct dc *dc)
+{
+ return dc->caps.i2c_speed_in_khz;
+}
+
+bool dc_get_dp_hdmi21_pcon_support(const struct dc *dc)
+{
+ return dc->caps.dp_hdmi21_pcon_support;
+}
+
+bool dc_get_edp_dsc_support(const struct dc *dc)
+{
+ return dc->caps.edp_dsc_support;
+}
+
+bool dc_get_fused_io_support(const struct dc *dc)
+{
+ return dc->caps.fused_io_supported;
+}
+
+unsigned int dc_get_subvp_fw_processing_delay_us(const struct dc *dc)
+{
+ return dc->caps.subvp_fw_processing_delay_us;
+}
+
+unsigned int dc_get_mall_size_total(const struct dc *dc)
+{
+ return dc->caps.mall_size_total;
+}
+
+bool dc_dmub_supports_psr(const struct dc *dc)
+{
+ return dc->caps.dmub_caps.psr;
+}
+
+bool dc_dmub_supports_aux_backlight(const struct dc *dc)
+{
+ return dc->caps.dmub_caps.aux_backlight_support;
+}
+
+void dc_get_color_caps(const struct dc *dc, struct dc_color_caps *caps)
+{
+ *caps = dc->caps.color;
+}
+
+const struct dc_plane_cap *dc_get_plane_caps(const struct dc *dc,
+ unsigned int *count)
+{
+ if (count)
+ *count = dc->caps.max_planes;
+
+ return dc->caps.planes;
}
unsigned int dc_get_disable_ips(const struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
index 31baba820f6c..7a49f2ee1d77 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
@@ -2351,8 +2351,38 @@ struct dc_context *dc_get_ctx(const struct dc *dc);
/* The ASIC display engine version. */
enum dce_version dc_get_dce_version(const struct dc *dc);
-/* Capabilities detected at dc_create() time. Read-only. */
-const struct dc_caps *dc_get_caps(const struct dc *dc);
+/*
+ * Capabilities detected at dc_create() time. Read-only; prefer the
+ * purpose-built queries below over reaching into the caps structure.
+ */
+bool dc_is_apu(const struct dc *dc);
+bool dc_get_ips_support(const struct dc *dc);
+bool dc_get_dmcub_support(const struct dc *dc);
+unsigned int dc_get_max_links(const struct dc *dc);
+unsigned int dc_get_max_streams(const struct dc *dc);
+unsigned int dc_get_max_planes(const struct dc *dc);
+unsigned int dc_get_max_slave_planes(const struct dc *dc);
+unsigned int dc_get_max_cursor_size(const struct dc *dc);
+unsigned int dc_get_max_v_total(const struct dc *dc);
+bool dc_get_vtotal_limited_by_fp2(const struct dc *dc);
+unsigned int dc_get_i2c_speed_in_khz(const struct dc *dc);
+bool dc_get_dp_hdmi21_pcon_support(const struct dc *dc);
+bool dc_get_edp_dsc_support(const struct dc *dc);
+bool dc_get_fused_io_support(const struct dc *dc);
+unsigned int dc_get_subvp_fw_processing_delay_us(const struct dc *dc);
+unsigned int dc_get_mall_size_total(const struct dc *dc);
+bool dc_dmub_supports_psr(const struct dc *dc);
+bool dc_dmub_supports_aux_backlight(const struct dc *dc);
+
+/* Copy out the color pipeline capabilities. */
+void dc_get_color_caps(const struct dc *dc, struct dc_color_caps *caps);
+
+/*
+ * Return the static plane capability array and its entry count.
+ * Valid until the DC is destroyed.
+ */
+const struct dc_plane_cap *dc_get_plane_caps(const struct dc *dc,
+ unsigned int *count);
/*
* Select which eDP connectors get hotplug detection enabled; see
@@ -2512,7 +2542,7 @@ void dc_set_dml2_alt_ch_cfg(struct dc *dc,
/* Return an enumerated dc_link.
* dc_link order is constant and determined at
* boot time. They cannot be created or destroyed.
- * Use dc_get_caps() to get number of links.
+ * Use dc_get_max_links() to get number of links.
*/
struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index dafcb42504f8..7deb641c7ae8 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -125,9 +125,9 @@ static unsigned int calc_duration_in_us_from_v_total(
static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)
{
- unsigned int max_hw_v_total = dc_get_caps(stream->ctx->dc)->max_v_total;
+ unsigned int max_hw_v_total = dc_get_max_v_total(stream->ctx->dc);
- if (dc_get_caps(stream->ctx->dc)->vtotal_limited_by_fp2)
+ if (dc_get_vtotal_limited_by_fp2(stream->ctx->dc))
max_hw_v_total -= stream->timing.v_front_porch + 1;
return max_hw_v_total;
@@ -1007,7 +1007,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
nominal_field_rate_in_uhz =
mod_freesync_calc_nominal_field_rate(stream);
- if (dc_get_caps(stream->ctx->dc)->max_v_total != 0 && stream->timing.h_total != 0) {
+ if (dc_get_max_v_total(stream->ctx->dc) != 0 && stream->timing.h_total != 0) {
min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
(stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));
}
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
index ae2fa3b12e1a..652b7ad198f3 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_abm.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c
@@ -935,7 +935,7 @@ static bool set_backlight_millinits_aux(struct core_power *core_power,
// only use internal backlight control if dmub capabilities are not present
if (link->backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX &&
- dc_get_caps(link->dc)->dmub_caps.aux_backlight_support)
+ dc_dmub_supports_aux_backlight(link->dc))
return true;
return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR,
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
index 219b199350cd..3cd06e0d267b 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_psr.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
@@ -645,7 +645,7 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
config->dsc_slice_height = 0;
if (!(link->connector_signal & SIGNAL_TYPE_EDP) ||
- !dc_get_caps(dc)->edp_dsc_support ||
+ !dc_get_edp_dsc_support(dc) ||
link->panel_config.dsc.disable_dsc_edp ||
!link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
!stream->timing.dsc_cfg.num_slices_v)
--
2.56.0
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 19/19] drm/amd/display: Replace dc_get_caps with purpose-built capability queries
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
@ 2026-11-12 2:14 ` sashiko-bot
-1 siblings, 0 replies; 52+ messages in thread
From: sashiko-bot @ 2026-11-12 2:14 UTC (permalink / raw)
To: Dave Airlie; +Cc: amd-gfx, dri-devel
Thank you for your contribution! Sashiko AI review found no new issues
in this patch, but noticed 1 related pre-existing issue it does not
introduce:
- [High] drm/amd/display: missing fused_io and hdcp_lc_force_fw_enable
checks in dc_is_dmub_outbox_supported() [1]
--
commit c8a21aad95119e6c5fca592bbd2394b8b1a780d9
Author: Dave Airlie <airlied@redhat.com>
drm/amd/display: Replace dc_get_caps with purpose-built capability queries
This commit replaces the dc_get_caps() view accessor with dedicated
capability query functions so callers outside DC no longer access struct
dc_caps directly.
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
> index 73b56e078cbed..c71adc10c67ee 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
[ ... ]
> @@ -677,7 +677,7 @@ void update_config(void *handle, struct cp_psp_stream_config *config)
> link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS;
> link->adjust.hdcp1.disable = 0;
> link->adjust.hdcp2.use_fw_locality_check =
> - (dc_get_caps(dc)->fused_io_supported ||
> + (dc_get_fused_io_support(dc) ||
> dc_get_debug_options(dc)->hdcp_lc_force_fw_enable);
> link->adjust.hdcp2.use_sw_locality_fallback =
> dc_get_debug_options(dc)->hdcp_lc_enable_sw_fallback;
[Severity: High]
This problem wasn't introduced by this patch, but can enabling
use_fw_locality_check here cause a NULL pointer dereference in
execute_fused_io() [1]?
amdgpu_dm_init() only initializes adev->dm.fused_io[].replied and enables
the DMUB outbox when dc_is_dmub_outbox_supported() returns true:
drivers/gpu/drm/amd/display/dc/core/dc.c:dc_is_dmub_outbox_supported() {
if (!dc->caps.dmcub_support)
return false;
switch (dc->ctx->asic_id.chip_family) {
...
}
/* dmub aux needs dmub notifications to be enabled */
return dc->debug.enable_dmub_aux_for_legacy_ddc;
}
Because dc_is_dmub_outbox_supported() does not check fused_io_supported or
hdcp_lc_force_fw_enable, it returns false on ASICs such as
AMDGPU_FAMILY_GC_13_0_1 where Fused IO is supported without DPIA or legacy
DDC DMUB AUX notifications. When an HDCP2 locality check runs,
execute_fused_io() calls wait_for_completion_timeout() on the
uninitialized completion.
[1] https://sashiko.dev/#/bug/linux-dc486f6b-5c5b-43d8-842b-cdc1ed0770b0
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-amdgpu-dc-cleanup-v1-0-0fae41718ad2@redhat.com?part=19
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 19/19] drm/amd/display: Replace dc_get_caps with purpose-built capability queries
2026-11-12 1:43 ` Dave Airlie via B4 Relay
(?)
(?)
@ 2026-11-12 19:41 ` Harry Wentland
-1 siblings, 0 replies; 52+ messages in thread
From: Harry Wentland @ 2026-11-12 19:41 UTC (permalink / raw)
To: airlied
Cc: Leo Li, Rodrigo Siqueira, Alex Deucher, Christian König,
David Airlie, Austin Zheng, Jun Lei, Kenneth Feng, amd-gfx,
dri-devel
On 11/11/26 20:43, Dave Airlie via B4 Relay wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> Split the caps view accessor into per-capability queries so DM and the
> DAL modules no longer read through struct dc_caps:
>
> - scalar getters for is_apu, ips/dmcub support, max links/streams/
> planes/slave planes/cursor size/v_total, vtotal_limited_by_fp2,
> i2c speed, PCON/DSC/fused-io support, SubVP processing delay and
> MALL size
> - dc_dmub_supports_psr()/dc_dmub_supports_aux_backlight() for the
> DMUB capability bits
> - dc_get_color_caps() copies out the color pipeline capabilities
> - dc_get_plane_caps() returns the static plane capability array
>
> The KUnit tests keep installing fake capabilities through the
> dc_test_caps() view of their own fake DC.
>
> No production code outside the dc directory reads struct dc members
> through a caps view anymore.
>
> Part of making the struct dc sub-structures opaque outside DC.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
> ---
<snip>
>
> unsigned int dc_get_disable_ips(const struct dc *dc)
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc.h b/drivers/gpu/drm/amd/display/dc/inc/dc.h
> index 31baba820f6c..7a49f2ee1d77 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/dc.h
> @@ -2351,8 +2351,38 @@ struct dc_context *dc_get_ctx(const struct dc *dc);
> /* The ASIC display engine version. */
> enum dce_version dc_get_dce_version(const struct dc *dc);
>
> -/* Capabilities detected at dc_create() time. Read-only. */
> -const struct dc_caps *dc_get_caps(const struct dc *dc);
> +/*
> + * Capabilities detected at dc_create() time. Read-only; prefer the
> + * purpose-built queries below over reaching into the caps structure.
> + */
> +bool dc_is_apu(const struct dc *dc);
> +bool dc_get_ips_support(const struct dc *dc);
> +bool dc_get_dmcub_support(const struct dc *dc);
> +unsigned int dc_get_max_links(const struct dc *dc);
> +unsigned int dc_get_max_streams(const struct dc *dc);
> +unsigned int dc_get_max_planes(const struct dc *dc);
> +unsigned int dc_get_max_slave_planes(const struct dc *dc);
> +unsigned int dc_get_max_cursor_size(const struct dc *dc);
> +unsigned int dc_get_max_v_total(const struct dc *dc);
> +bool dc_get_vtotal_limited_by_fp2(const struct dc *dc);
> +unsigned int dc_get_i2c_speed_in_khz(const struct dc *dc);
> +bool dc_get_dp_hdmi21_pcon_support(const struct dc *dc);
> +bool dc_get_edp_dsc_support(const struct dc *dc);
> +bool dc_get_fused_io_support(const struct dc *dc);
> +unsigned int dc_get_subvp_fw_processing_delay_us(const struct dc *dc);
> +unsigned int dc_get_mall_size_total(const struct dc *dc);
> +bool dc_dmub_supports_psr(const struct dc *dc);
> +bool dc_dmub_supports_aux_backlight(const struct dc *dc);
> +
> +/* Copy out the color pipeline capabilities. */
> +void dc_get_color_caps(const struct dc *dc, struct dc_color_caps *caps);
> +
> +/*
> + * Return the static plane capability array and its entry count.
> + * Valid until the DC is destroyed.
> + */
> +const struct dc_plane_cap *dc_get_plane_caps(const struct dc *dc,
> + unsigned int *count);
>
This creates some API bloat.
What about creating a new public struct header and throwing dc_caps
(or a subset of it) in there?
The intent to decouple how DC stores and reports caps is valid.
Harry
^ permalink raw reply [flat|nested] 52+ messages in thread