Re: [PATCH v16 6/9] clk: realtek: Add support for MMC-tuned PLL clocks

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] clk: realtek: misplaced linux/limits.h include in
  freq_table.c breaks bisect
--

commit bb40f458c667a0d1463f9b5c0600dafb76a332e7
Author: Cheng-Yu Lee <cylee12@realtek.com>

clk: realtek: Add support for MMC-tuned PLL clocks

This commit adds clock operations for Realtek MMC-tuned PLL clocks,
supporting rate control, enable/disable, and phase get/set operations.

> diff --git a/drivers/clk/realtek/freq_table.c b/drivers/clk/realtek/freq_table.c
> index 0f977a3fc9021..d0e015131e57a 100644
> --- a/drivers/clk/realtek/freq_table.c
> +++ b/drivers/clk/realtek/freq_table.c
> @@ -1,5 +1,6 @@
>  // SPDX-License-Identifier: GPL-2.0-only
>  
> +#include <linux/limits.h>
>  #include <linux/types.h>
>  #include "freq_table.h"

[Severity: Medium]
Should this #include <linux/limits.h> be folded into earlier commit
"clk: realtek: Add support for phase locked loops (PLLs)" instead?

That earlier patch introduces ftbl_find_closest_by_rate() in
drivers/clk/realtek/freq_table.c using ULONG_MAX without including
linux/limits.h, so building at the intermediate commits in this series
fails and breaks git bisect.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112052544.555563-1-eleanor.lin@realtek.com?part=6