From: sashiko-bot@kernel.org
To: "Yu-Chun Lin" <eleanor.lin@realtek.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v16 7/9] clk: realtek: Add RTD1625-CRT clock controller driver
Date: Thu, 12 Nov 2026 05:41:24 +0000 [thread overview]
Message-ID: <sashiko-outbox-210471@kernel.org> (raw)
In-Reply-To: <20261112052544.555563-8-eleanor.lin@realtek.com>
Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Medium] clk: realtek: FREQ_MNO_MASK omits bit 19 of O divider for
pll_vodma
- [Medium] clk: realtek: static clk_hw.init cleared without
suppress_bind_attrs
--
commit 127e3b9f9c4378fa7aaceda027d1d3b761330569
Author: Cheng-Yu Lee <cylee12@realtek.com>
clk: realtek: Add RTD1625-CRT clock controller driver
This commit adds the CRT domain clock controller driver for the Realtek
RTD1625 SoC and registers the associated reset controller on the auxiliary
bus.
> diff --git a/drivers/clk/realtek/clk-rtd1625-crt.c b/drivers/clk/realtek/clk-rtd1625-crt.c
> new file mode 100644
> index 0000000000000..b0cccf5c7af2d
> --- /dev/null
> +++ b/drivers/clk/realtek/clk-rtd1625-crt.c
> @@ -0,0 +1,878 @@
[ ... ]
> +/* PLL VODMA: M (11:4) / N (13:12) / O (19:17) */
> +#define FREQ_MNO_MASK 0x63ff0
> +#define FREQ_MNO(_r, _m, _n, _o) { .rate = (_r), .val = ((_m) << 4) | \
> + ((_n) << 12) | ((_o) << 17), }
[Severity: Medium]
Should FREQ_MNO_MASK be 0xe3ff0 instead of 0x63ff0? 0x63ff0 only covers
bits 18:17 for the O divider field, so rtk_clk_regmap_pll_recalc_rate()
masks off bit 19 when reading RTD1625_REG_PLL_VODMA1 for pll_vodma and can
match the wrong entry in pll_vodma_tbl if O >= 4.
[ ... ]
> +static struct platform_driver rtd1625_crt_driver = {
> + .probe = rtd1625_crt_probe,
> + .driver = {
> + .name = "rtk-rtd1625-crt-clk",
> + .of_match_table = rtd1625_crt_match,
> + },
> +};
[Severity: Medium]
Does rtd1625_crt_driver need .suppress_bind_attrs = true? During probe,
rtk_clk_probe() registers the static clk_hw structures in
rtd1625_crt_hw_data via devm_clk_hw_register() -> __clk_register(), which
clears hw->init to NULL. Unbinding and rebinding the driver via sysfs (or
re-probing after a late failure in rtk_clk_probe()) will pass those same
static clk_hw structures to __clk_register() with hw->init == NULL and hit
a NULL pointer dereference. Unbinding also unregisters CLK_IS_CRITICAL
clocks while they remain prepared and enabled, triggering WARN_ON() in
clk_unregister().
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112052544.555563-1-eleanor.lin@realtek.com?part=7
next prev parent reply other threads:[~2026-11-12 5:41 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-12 5:25 [PATCH v16 0/9] clk: realtek: Add RTD1625 clock support Yu-Chun Lin
2026-11-12 5:25 ` [PATCH v16 1/9] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin
2026-11-12 9:23 ` Krzysztof Kozlowski
2026-11-12 5:25 ` [PATCH v16 2/9] clk: realtek: Introduce common probe() Yu-Chun Lin
2026-11-12 17:14 ` Brian Masney
2026-11-12 5:25 ` [PATCH v16 3/9] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin
2026-11-12 5:40 ` sashiko-bot
2026-11-12 17:14 ` Brian Masney
2026-11-12 5:25 ` [PATCH v16 4/9] clk: realtek: Add support for gate clock Yu-Chun Lin
2026-11-12 17:14 ` Brian Masney
2026-11-12 5:25 ` [PATCH v16 5/9] clk: realtek: Add support for mux clock Yu-Chun Lin
2026-11-12 5:25 ` [PATCH v16 6/9] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin
2026-11-12 5:41 ` sashiko-bot
2026-11-12 17:14 ` Brian Masney
2026-11-12 5:25 ` [PATCH v16 7/9] clk: realtek: Add RTD1625-CRT clock controller driver Yu-Chun Lin
2026-11-12 5:41 ` sashiko-bot [this message]
2026-11-12 17:14 ` Brian Masney
2026-11-12 5:25 ` [PATCH v16 8/9] clk: realtek: Add RTD1625-ISO " Yu-Chun Lin
2026-11-12 5:25 ` [PATCH v16 9/9] arm64: dts: realtek: Add clock support for RTD1625 Yu-Chun Lin
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