* [PATCH] drm/amdgpu: bring back the ring parameter for update_spm_vmid()
@ 2026-11-12 21:24 Alex Deucher
2026-11-12 22:34 ` sashiko-bot
2026-11-12 22:49 ` Alex Deucher
0 siblings, 2 replies; 5+ messages in thread
From: Alex Deucher @ 2026-11-12 21:24 UTC (permalink / raw)
To: amd-gfx
Cc: Alex Deucher, Vitaly Prosyak, Pierre-Eric Pelloux-Prayer,
Sunil Khatri, Christian König
This largely reverts commit 90b1b26bb030d6c666f8cad52cd3d8019d404ad9.
Not emitting the spm update via the ring causes CI flakeyness on
gfx11. Add back the SPM ring emission, but skip the MMIO path
if ring is specified.
Cc: Vitaly Prosyak <vitaly.prosyak@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Sunil Khatri <sunil.khatri@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Fixes: d44428868e5b ("drm/amdgpu: re-enable SPM updates in the the IB path")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 16 +++++++++++++---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 15 +++++++++++++--
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 15 ++++++++++++---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++--
11 files changed, 49 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 324d25c77897a..1ff5d5cfb141d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -750,7 +750,7 @@ void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring,
ring->reemit = true;
amdgpu_ring_alloc(ring, ring->ring_backup_entries_to_copy);
if (emit_spm_needed)
- ring->adev->gfx.rlc.funcs->update_spm_vmid(ring->adev, ring->xcc_id,
+ ring->adev->gfx.rlc.funcs->update_spm_vmid(ring->adev, ring->xcc_id, NULL,
ring->adev->vm_manager.spm_vmid);
spin_lock_irqsave(&ring->fence_drv.lock, flags);
do {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 6210edf1937aa..a24cdf5852a32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -213,7 +213,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, struct amdgpu_job *job,
amdgpu_ring_emit_pipeline_sync(ring);
if (emit_spm_needed)
- adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id,
+ adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring,
adev->vm_manager.spm_vmid);
if (emit_gds_needed)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index e38a8ea02c520..2ae2c1d0f702b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -292,7 +292,7 @@ struct amdgpu_rlc_funcs {
void (*reset)(struct amdgpu_device *adev);
void (*start)(struct amdgpu_device *adev);
void (*update_spm_vmid)(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid);
+ struct amdgpu_ring *ring, unsigned vmid);
bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7683e8a0a4380..f226758b15467 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8187,7 +8187,7 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
}
static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned int vmid)
{
amdgpu_gfx_off_ctrl(adev, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 5d068a9d9c72c..ac814c12d60f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -363,6 +363,7 @@ static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
+ struct amdgpu_ring *ring,
unsigned int vmid);
static void gfx_v11_0_userq_priv_fault_work(struct work_struct *work);
static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
@@ -2606,7 +2607,7 @@ static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
* The RLC comes up with RLC_SPM_MC_CNTL cleared, program the SPM VMID
* once it runs, also after a GPU reset or a resume.
*/
- gfx_v11_0_update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ gfx_v11_0_update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -5615,12 +5616,21 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
}
static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned vmid)
{
u32 reg, pre_data, data;
- amdgpu_gfx_off_ctrl(adev, false);
reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
+
+ if (ring && amdgpu_sriov_is_pp_one_vf(adev) &&
+ ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) ||
+ (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
+ data = (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
+ amdgpu_ring_emit_wreg(ring, reg, data);
+ return;
+ }
+
+ amdgpu_gfx_off_ctrl(adev, false);
if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
pre_data = RREG32_NO_KIQ(reg);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index df2fb09bbcd86..07f981f27bcc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -287,6 +287,7 @@ static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
+ struct amdgpu_ring *ring,
unsigned int vmid);
static void gfx_v12_0_userq_priv_fault_work(struct work_struct *work);
static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
@@ -2158,7 +2159,7 @@ static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev)
* The RLC comes up with RLC_SPM_MC_CNTL cleared, program the SPM VMID
* once it runs, also after a GPU reset or a resume.
*/
- gfx_v12_0_update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ gfx_v12_0_update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -3978,12 +3979,22 @@ static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
int xcc_id,
+ struct amdgpu_ring *ring,
unsigned vmid)
{
u32 reg, data;
- amdgpu_gfx_off_ctrl(adev, false);
reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
+
+ if (ring && amdgpu_sriov_is_pp_one_vf(adev) &&
+ ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) ||
+ (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
+ data = (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
+ amdgpu_ring_emit_wreg(ring, reg, data);
+ return;
+ }
+
+ amdgpu_gfx_off_ctrl(adev, false);
if (amdgpu_sriov_is_pp_one_vf(adev))
data = RREG32_NO_KIQ(reg);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 1f57d0fa2c044..2bbe83d98563a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -217,7 +217,7 @@ static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev);
static void gfx_v12_1_xcc_update_medium_grain_clock_gating(
struct amdgpu_device *adev, bool enable, int xcc_id, bool force);
static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid);
+ struct amdgpu_ring *ring, unsigned vmid);
static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
int mem_space, int opt, uint32_t addr0,
@@ -1866,7 +1866,7 @@ static int gfx_v12_1_xcc_rlc_resume(struct amdgpu_device *adev,
int r;
/* init spm vmid with 0xf */
- gfx_v12_1_update_spm_vmid(adev, xcc_id, adev->vm_manager.spm_vmid);
+ gfx_v12_1_update_spm_vmid(adev, xcc_id, NULL, adev->vm_manager.spm_vmid);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
gfx_v12_1_xcc_init_csb(adev, xcc_id);
@@ -2945,7 +2945,8 @@ static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev,
static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev,
int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring,
+ unsigned vmid)
{
u32 reg, data;
@@ -2962,6 +2963,14 @@ static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev,
WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);
else
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);
+
+ if (ring
+ && amdgpu_sriov_is_pp_one_vf(adev)
+ && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
+ || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
+ uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL);
+ amdgpu_ring_emit_wreg(ring, reg, data);
+ }
}
static const struct amdgpu_rlc_funcs gfx_v12_1_rlc_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 72c84b61fda16..43dea0810137b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3256,7 +3256,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
- adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -3483,7 +3483,7 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
}
static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned vmid)
{
u32 data;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4666aa5b38c75..360a958f7577d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1276,7 +1276,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
- adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -5484,7 +5484,7 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
}
static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned vmid)
{
u32 data;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2e2673a6dbbf5..0b01801b0571b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5227,7 +5227,7 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
}
static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned int vmid)
{
amdgpu_gfx_off_ctrl(adev, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index da031caa4e9e6..30c8b751849cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1397,7 +1397,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
{
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
- adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -1609,7 +1609,7 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
}
static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
- int inst, unsigned int vmid)
+ int inst, struct amdgpu_ring *ring, unsigned int vmid)
{
u32 reg, pre_data, data;
--
2.56.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/amdgpu: bring back the ring parameter for update_spm_vmid()
2026-11-12 21:24 [PATCH] drm/amdgpu: bring back the ring parameter for update_spm_vmid() Alex Deucher
@ 2026-11-12 22:34 ` sashiko-bot
2026-11-12 22:49 ` Alex Deucher
1 sibling, 0 replies; 5+ messages in thread
From: sashiko-bot @ 2026-11-12 22:34 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [High] drm/amdgpu: update_spm_vmid() ring emission gated on SR-IOV
one-VF mode
- [Medium] drm/amdgpu: unskipped MMIO path and shadowed reg in
gfx_v12_1_update_spm_vmid()
It also noticed 1 related pre-existing issue this patch does not
introduce:
- [Critical] drm/amdgpu: null pointer dereference in amdgpu_vm_flush()
[1]
--
commit 6992ee0f5dfcb4a6c2339de5ec059b2331ca4d48
Author: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: bring back the ring parameter for update_spm_vmid()
This commit restores the ring parameter to the RLC update_spm_vmid() callback
so that amdgpu_ib_schedule() can emit the SPM VMID update on the ring instead
of via MMIO.
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index 6210edf1937aa..a24cdf5852a32 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -213,7 +213,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, struct amdgpu_job *job,
> amdgpu_ring_emit_pipeline_sync(ring);
>
> if (emit_spm_needed)
> - adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id,
> + adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring,
> adev->vm_manager.spm_vmid);
>
> if (emit_gds_needed)
[Severity: Critical]
This problem wasn't introduced by this patch, but can [1]
amdgpu_ib_schedule() dereference a NULL adev->gfx.rlc.funcs pointer when
initializing emit_spm_needed?
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c:amdgpu_ib_schedule() {
...
bool emit_spm_needed = adev->gfx.rlc.funcs->update_spm_vmid &&
(ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ||
ring->funcs->type == AMDGPU_RING_TYPE_GFX);
...
}
On hardware configurations where adev->gfx.rlc.funcs is not initialized,
evaluating adev->gfx.rlc.funcs->update_spm_vmid during IB submission causes a
NULL pointer dereference and kernel panic.
[ ... ]
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 5d068a9d9c72c..ac814c12d60f2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
[ ... ]
> @@ -5615,12 +5616,21 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> }
>
> static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> - unsigned int vmid)
> + struct amdgpu_ring *ring, unsigned vmid)
> {
> u32 reg, pre_data, data;
>
> - amdgpu_gfx_off_ctrl(adev, false);
> reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
> +
> + if (ring && amdgpu_sriov_is_pp_one_vf(adev) &&
> + ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) ||
> + (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
> + data = (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
> + amdgpu_ring_emit_wreg(ring, reg, data);
> + return;
> + }
> +
> + amdgpu_gfx_off_ctrl(adev, false);
[Severity: High]
Does gating the ring emission on amdgpu_sriov_is_pp_one_vf(adev) prevent
gfx_v11_0_update_spm_vmid(), gfx_v12_0_update_spm_vmid(), and
gfx_v12_1_update_spm_vmid() from ever emitting the SPM update on the ring or
skipping the MMIO path on bare metal?
amdgpu_sriov_is_pp_one_vf(adev) checks AMDGIM_FEATURE_PP_ONE_VF, which is
only set in SR-IOV single-VF mode and is false on bare metal. When
amdgpu_ib_schedule() passes a non-NULL ring on bare-metal systems, this
condition evaluates to false and execution falls through to the synchronous
amdgpu_gfx_off_ctrl() and MMIO path on every GFX and compute IB submission.
If GFXOFF engages after amdgpu_ib_schedule() re-enables GFXOFF on the CPU and
before the GPU executes the queued IB, regRLC_SPM_MC_CNTL is cleared by
GFXOFF and never restored by the ring.
[ ... ]
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
> index 1f57d0fa2c044..2bbe83d98563a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
[ ... ]
> @@ -2945,7 +2945,8 @@ static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev,
>
> static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev,
> int xcc_id,
> - unsigned int vmid)
> + struct amdgpu_ring *ring,
> + unsigned vmid)
> {
> u32 reg, data;
>
> @@ -2962,6 +2963,14 @@ static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev,
> WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);
> else
> WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);
> +
> + if (ring
> + && amdgpu_sriov_is_pp_one_vf(adev)
> + && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
> + || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
> + uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL);
> + amdgpu_ring_emit_wreg(ring, reg, data);
> + }
> }
[Severity: Medium]
Should the ring emission check in gfx_v12_1_update_spm_vmid() run and return
before the MMIO read and write, as in gfx_v11_0_update_spm_vmid() and
gfx_v12_0_update_spm_vmid()?
Placing the ring check at the end of the function leaves the MMIO accesses to
regRLC_SPM_MC_CNTL unconditional whenever a ring is passed from
amdgpu_ib_schedule(). The inner uint32_t reg declaration also shadows the
outer u32 reg variable that is already initialized to the same offset.
[1] https://sashiko.dev/#/bug/linux-c7bb3824-c8ad-4019-945c-0cd80d5a9da3
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112212417.1769071-1-alexander.deucher@amd.com?part=1
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/amdgpu: bring back the ring parameter for update_spm_vmid()
2026-11-12 21:24 [PATCH] drm/amdgpu: bring back the ring parameter for update_spm_vmid() Alex Deucher
2026-11-12 22:34 ` sashiko-bot
@ 2026-11-12 22:49 ` Alex Deucher
1 sibling, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2026-11-12 22:49 UTC (permalink / raw)
To: Alex Deucher
Cc: amd-gfx, Vitaly Prosyak, Pierre-Eric Pelloux-Prayer, Sunil Khatri,
Christian König
Ignore this patch and the v2. They need to be reworked.
Alex
On Thu, Nov 12, 2026 at 5:21 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> This largely reverts commit 90b1b26bb030d6c666f8cad52cd3d8019d404ad9.
>
> Not emitting the spm update via the ring causes CI flakeyness on
> gfx11. Add back the SPM ring emission, but skip the MMIO path
> if ring is specified.
>
> Cc: Vitaly Prosyak <vitaly.prosyak@amd.com>
> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> Cc: Sunil Khatri <sunil.khatri@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Fixes: d44428868e5b ("drm/amdgpu: re-enable SPM updates in the the IB path")
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 16 +++++++++++++---
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 15 +++++++++++++--
> drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 15 ++++++++++++---
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++--
> 11 files changed, 49 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> index 324d25c77897a..1ff5d5cfb141d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> @@ -750,7 +750,7 @@ void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring,
> ring->reemit = true;
> amdgpu_ring_alloc(ring, ring->ring_backup_entries_to_copy);
> if (emit_spm_needed)
> - ring->adev->gfx.rlc.funcs->update_spm_vmid(ring->adev, ring->xcc_id,
> + ring->adev->gfx.rlc.funcs->update_spm_vmid(ring->adev, ring->xcc_id, NULL,
> ring->adev->vm_manager.spm_vmid);
> spin_lock_irqsave(&ring->fence_drv.lock, flags);
> do {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index 6210edf1937aa..a24cdf5852a32 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -213,7 +213,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, struct amdgpu_job *job,
> amdgpu_ring_emit_pipeline_sync(ring);
>
> if (emit_spm_needed)
> - adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id,
> + adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring,
> adev->vm_manager.spm_vmid);
>
> if (emit_gds_needed)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> index e38a8ea02c520..2ae2c1d0f702b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> @@ -292,7 +292,7 @@ struct amdgpu_rlc_funcs {
> void (*reset)(struct amdgpu_device *adev);
> void (*start)(struct amdgpu_device *adev);
> void (*update_spm_vmid)(struct amdgpu_device *adev, int xcc_id,
> - unsigned int vmid);
> + struct amdgpu_ring *ring, unsigned vmid);
> bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
> };
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 7683e8a0a4380..f226758b15467 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -8187,7 +8187,7 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
> }
>
> static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> - unsigned int vmid)
> + struct amdgpu_ring *ring, unsigned int vmid)
> {
> amdgpu_gfx_off_ctrl(adev, false);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 5d068a9d9c72c..ac814c12d60f2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -363,6 +363,7 @@ static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
> static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
> static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
> static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> + struct amdgpu_ring *ring,
> unsigned int vmid);
> static void gfx_v11_0_userq_priv_fault_work(struct work_struct *work);
> static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
> @@ -2606,7 +2607,7 @@ static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
> * The RLC comes up with RLC_SPM_MC_CNTL cleared, program the SPM VMID
> * once it runs, also after a GPU reset or a resume.
> */
> - gfx_v11_0_update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
> + gfx_v11_0_update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
>
> return 0;
> }
> @@ -5615,12 +5616,21 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> }
>
> static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> - unsigned int vmid)
> + struct amdgpu_ring *ring, unsigned vmid)
> {
> u32 reg, pre_data, data;
>
> - amdgpu_gfx_off_ctrl(adev, false);
> reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
> +
> + if (ring && amdgpu_sriov_is_pp_one_vf(adev) &&
> + ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) ||
> + (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
> + data = (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
> + amdgpu_ring_emit_wreg(ring, reg, data);
> + return;
> + }
> +
> + amdgpu_gfx_off_ctrl(adev, false);
> if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
> pre_data = RREG32_NO_KIQ(reg);
> else
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index df2fb09bbcd86..07f981f27bcc8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -287,6 +287,7 @@ static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
> static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
> static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
> static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> + struct amdgpu_ring *ring,
> unsigned int vmid);
> static void gfx_v12_0_userq_priv_fault_work(struct work_struct *work);
> static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
> @@ -2158,7 +2159,7 @@ static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev)
> * The RLC comes up with RLC_SPM_MC_CNTL cleared, program the SPM VMID
> * once it runs, also after a GPU reset or a resume.
> */
> - gfx_v12_0_update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
> + gfx_v12_0_update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
>
> return 0;
> }
> @@ -3978,12 +3979,22 @@ static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
>
> static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
> int xcc_id,
> + struct amdgpu_ring *ring,
> unsigned vmid)
> {
> u32 reg, data;
>
> - amdgpu_gfx_off_ctrl(adev, false);
> reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
> +
> + if (ring && amdgpu_sriov_is_pp_one_vf(adev) &&
> + ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) ||
> + (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
> + data = (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
> + amdgpu_ring_emit_wreg(ring, reg, data);
> + return;
> + }
> +
> + amdgpu_gfx_off_ctrl(adev, false);
> if (amdgpu_sriov_is_pp_one_vf(adev))
> data = RREG32_NO_KIQ(reg);
> else
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
> index 1f57d0fa2c044..2bbe83d98563a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
> @@ -217,7 +217,7 @@ static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev);
> static void gfx_v12_1_xcc_update_medium_grain_clock_gating(
> struct amdgpu_device *adev, bool enable, int xcc_id, bool force);
> static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> - unsigned int vmid);
> + struct amdgpu_ring *ring, unsigned vmid);
>
> static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
> int mem_space, int opt, uint32_t addr0,
> @@ -1866,7 +1866,7 @@ static int gfx_v12_1_xcc_rlc_resume(struct amdgpu_device *adev,
> int r;
>
> /* init spm vmid with 0xf */
> - gfx_v12_1_update_spm_vmid(adev, xcc_id, adev->vm_manager.spm_vmid);
> + gfx_v12_1_update_spm_vmid(adev, xcc_id, NULL, adev->vm_manager.spm_vmid);
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> gfx_v12_1_xcc_init_csb(adev, xcc_id);
> @@ -2945,7 +2945,8 @@ static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev,
>
> static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev,
> int xcc_id,
> - unsigned int vmid)
> + struct amdgpu_ring *ring,
> + unsigned vmid)
> {
> u32 reg, data;
>
> @@ -2962,6 +2963,14 @@ static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev,
> WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);
> else
> WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data);
> +
> + if (ring
> + && amdgpu_sriov_is_pp_one_vf(adev)
> + && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
> + || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
> + uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL);
> + amdgpu_ring_emit_wreg(ring, reg, data);
> + }
> }
>
> static const struct amdgpu_rlc_funcs gfx_v12_1_rlc_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 72c84b61fda16..43dea0810137b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -3256,7 +3256,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
>
> /* init spm vmid with 0xf */
> if (adev->gfx.rlc.funcs->update_spm_vmid)
> - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
> + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
>
> return 0;
> }
> @@ -3483,7 +3483,7 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
> }
>
> static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> - unsigned int vmid)
> + struct amdgpu_ring *ring, unsigned vmid)
> {
> u32 data;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 4666aa5b38c75..360a958f7577d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1276,7 +1276,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
>
> /* init spm vmid with 0xf */
> if (adev->gfx.rlc.funcs->update_spm_vmid)
> - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
> + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
>
> return 0;
> }
> @@ -5484,7 +5484,7 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
> }
>
> static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> - unsigned int vmid)
> + struct amdgpu_ring *ring, unsigned vmid)
> {
> u32 data;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 2e2673a6dbbf5..0b01801b0571b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -5227,7 +5227,7 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
> }
>
> static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> - unsigned int vmid)
> + struct amdgpu_ring *ring, unsigned int vmid)
> {
> amdgpu_gfx_off_ctrl(adev, false);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index da031caa4e9e6..30c8b751849cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -1397,7 +1397,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
> {
> /* init spm vmid with 0xf */
> if (adev->gfx.rlc.funcs->update_spm_vmid)
> - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
> + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
>
> return 0;
> }
> @@ -1609,7 +1609,7 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
> }
>
> static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
> - int inst, unsigned int vmid)
> + int inst, struct amdgpu_ring *ring, unsigned int vmid)
> {
> u32 reg, pre_data, data;
>
> --
> 2.56.0
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] drm/amdgpu: bring back the ring parameter for update_spm_vmid()
@ 2026-11-12 21:48 Alex Deucher
2026-11-12 23:57 ` sashiko-bot
0 siblings, 1 reply; 5+ messages in thread
From: Alex Deucher @ 2026-11-12 21:48 UTC (permalink / raw)
To: amd-gfx
Cc: Alex Deucher, Vitaly Prosyak, Pierre-Eric Pelloux-Prayer,
Sunil Khatri, Christian König
This largely reverts commit 90b1b26bb030d6c666f8cad52cd3d8019d404ad9.
Not emitting the spm update via the ring causes CI flakeyness on
gfx11. Add back the SPM ring emission, but skip the MMIO path
if ring is specified.
v2: drop ring code in gfx 12.1. We aren't supporting KCQs on 12.1
so the code is not used.
Cc: Vitaly Prosyak <vitaly.prosyak@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Sunil Khatri <sunil.khatri@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Fixes: d44428868e5b ("drm/amdgpu: re-enable SPM updates in the the IB path")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 16 +++++++++++++---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 15 +++++++++++++--
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 7 ++++---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++--
11 files changed, 41 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 324d25c77897a..1ff5d5cfb141d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -750,7 +750,7 @@ void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring,
ring->reemit = true;
amdgpu_ring_alloc(ring, ring->ring_backup_entries_to_copy);
if (emit_spm_needed)
- ring->adev->gfx.rlc.funcs->update_spm_vmid(ring->adev, ring->xcc_id,
+ ring->adev->gfx.rlc.funcs->update_spm_vmid(ring->adev, ring->xcc_id, NULL,
ring->adev->vm_manager.spm_vmid);
spin_lock_irqsave(&ring->fence_drv.lock, flags);
do {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 6210edf1937aa..a24cdf5852a32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -213,7 +213,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, struct amdgpu_job *job,
amdgpu_ring_emit_pipeline_sync(ring);
if (emit_spm_needed)
- adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id,
+ adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring,
adev->vm_manager.spm_vmid);
if (emit_gds_needed)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index e38a8ea02c520..2ae2c1d0f702b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -292,7 +292,7 @@ struct amdgpu_rlc_funcs {
void (*reset)(struct amdgpu_device *adev);
void (*start)(struct amdgpu_device *adev);
void (*update_spm_vmid)(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid);
+ struct amdgpu_ring *ring, unsigned vmid);
bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7683e8a0a4380..f226758b15467 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8187,7 +8187,7 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
}
static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned int vmid)
{
amdgpu_gfx_off_ctrl(adev, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 5d068a9d9c72c..ac814c12d60f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -363,6 +363,7 @@ static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
+ struct amdgpu_ring *ring,
unsigned int vmid);
static void gfx_v11_0_userq_priv_fault_work(struct work_struct *work);
static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
@@ -2606,7 +2607,7 @@ static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
* The RLC comes up with RLC_SPM_MC_CNTL cleared, program the SPM VMID
* once it runs, also after a GPU reset or a resume.
*/
- gfx_v11_0_update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ gfx_v11_0_update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -5615,12 +5616,21 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
}
static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned vmid)
{
u32 reg, pre_data, data;
- amdgpu_gfx_off_ctrl(adev, false);
reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
+
+ if (ring && amdgpu_sriov_is_pp_one_vf(adev) &&
+ ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) ||
+ (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
+ data = (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
+ amdgpu_ring_emit_wreg(ring, reg, data);
+ return;
+ }
+
+ amdgpu_gfx_off_ctrl(adev, false);
if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
pre_data = RREG32_NO_KIQ(reg);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index df2fb09bbcd86..07f981f27bcc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -287,6 +287,7 @@ static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
+ struct amdgpu_ring *ring,
unsigned int vmid);
static void gfx_v12_0_userq_priv_fault_work(struct work_struct *work);
static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
@@ -2158,7 +2159,7 @@ static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev)
* The RLC comes up with RLC_SPM_MC_CNTL cleared, program the SPM VMID
* once it runs, also after a GPU reset or a resume.
*/
- gfx_v12_0_update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ gfx_v12_0_update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -3978,12 +3979,22 @@ static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
int xcc_id,
+ struct amdgpu_ring *ring,
unsigned vmid)
{
u32 reg, data;
- amdgpu_gfx_off_ctrl(adev, false);
reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
+
+ if (ring && amdgpu_sriov_is_pp_one_vf(adev) &&
+ ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) ||
+ (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
+ data = (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
+ amdgpu_ring_emit_wreg(ring, reg, data);
+ return;
+ }
+
+ amdgpu_gfx_off_ctrl(adev, false);
if (amdgpu_sriov_is_pp_one_vf(adev))
data = RREG32_NO_KIQ(reg);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 1f57d0fa2c044..bf69d71e6b065 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -217,7 +217,7 @@ static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev);
static void gfx_v12_1_xcc_update_medium_grain_clock_gating(
struct amdgpu_device *adev, bool enable, int xcc_id, bool force);
static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid);
+ struct amdgpu_ring *ring, unsigned vmid);
static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
int mem_space, int opt, uint32_t addr0,
@@ -1866,7 +1866,7 @@ static int gfx_v12_1_xcc_rlc_resume(struct amdgpu_device *adev,
int r;
/* init spm vmid with 0xf */
- gfx_v12_1_update_spm_vmid(adev, xcc_id, adev->vm_manager.spm_vmid);
+ gfx_v12_1_update_spm_vmid(adev, xcc_id, NULL, adev->vm_manager.spm_vmid);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
gfx_v12_1_xcc_init_csb(adev, xcc_id);
@@ -2945,7 +2945,8 @@ static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev,
static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev,
int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring,
+ unsigned vmid)
{
u32 reg, data;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 72c84b61fda16..43dea0810137b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3256,7 +3256,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
- adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -3483,7 +3483,7 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
}
static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned vmid)
{
u32 data;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4666aa5b38c75..360a958f7577d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1276,7 +1276,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
- adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -5484,7 +5484,7 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
}
static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned vmid)
{
u32 data;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2e2673a6dbbf5..0b01801b0571b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5227,7 +5227,7 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,
}
static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
- unsigned int vmid)
+ struct amdgpu_ring *ring, unsigned int vmid)
{
amdgpu_gfx_off_ctrl(adev, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index da031caa4e9e6..30c8b751849cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1397,7 +1397,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
{
/* init spm vmid with 0xf */
if (adev->gfx.rlc.funcs->update_spm_vmid)
- adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, adev->vm_manager.spm_vmid);
+ adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, adev->vm_manager.spm_vmid);
return 0;
}
@@ -1609,7 +1609,7 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
}
static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
- int inst, unsigned int vmid)
+ int inst, struct amdgpu_ring *ring, unsigned int vmid)
{
u32 reg, pre_data, data;
--
2.56.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/amdgpu: bring back the ring parameter for update_spm_vmid()
2026-11-12 21:48 Alex Deucher
@ 2026-11-12 23:57 ` sashiko-bot
0 siblings, 0 replies; 5+ messages in thread
From: sashiko-bot @ 2026-11-12 23:57 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] drm/amdgpu: ring emission in update_spm_vmid() gated on SR-IOV
1-VF mode
--
commit 90ca59b6e99e6b8e5c6b2f133b97efb1b24aedb0
Author: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: bring back the ring parameter for update_spm_vmid()
This commit restores the ring parameter to the update_spm_vmid() callback
and passes the ring from amdgpu_ib_schedule() so that GFX11 and GFX12 can
emit the SPM VMID update on the ring instead of using MMIO.
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index 6210edf1937aa..a24cdf5852a32 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -213,7 +213,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, struct amdgpu_job *job,
> amdgpu_ring_emit_pipeline_sync(ring);
>
> if (emit_spm_needed)
> - adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id,
> + adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring,
> adev->vm_manager.spm_vmid);
>
> if (emit_gds_needed)
[ ... ]
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 5d068a9d9c72c..ac814c12d60f2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
[ ... ]
> @@ -5615,12 +5616,21 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> }
>
> static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id,
> - unsigned int vmid)
> + struct amdgpu_ring *ring, unsigned vmid)
> {
> u32 reg, pre_data, data;
>
> - amdgpu_gfx_off_ctrl(adev, false);
> reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
> +
> + if (ring && amdgpu_sriov_is_pp_one_vf(adev) &&
> + ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) ||
> + (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
> + data = (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
> + amdgpu_ring_emit_wreg(ring, reg, data);
> + return;
> + }
> +
> + amdgpu_gfx_off_ctrl(adev, false);
> if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
> pre_data = RREG32_NO_KIQ(reg);
> else
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index df2fb09bbcd86..07f981f27bcc8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
[ ... ]
> @@ -3978,12 +3979,22 @@ static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
>
> static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
> int xcc_id,
> + struct amdgpu_ring *ring,
> unsigned vmid)
> {
> u32 reg, data;
>
> - amdgpu_gfx_off_ctrl(adev, false);
> reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
> +
> + if (ring && amdgpu_sriov_is_pp_one_vf(adev) &&
> + ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) ||
> + (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
> + data = (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
> + amdgpu_ring_emit_wreg(ring, reg, data);
> + return;
> + }
> +
> + amdgpu_gfx_off_ctrl(adev, false);
[Severity: High]
Does gating the ring emission on amdgpu_sriov_is_pp_one_vf(adev) prevent
gfx_v11_0_update_spm_vmid() and gfx_v12_0_update_spm_vmid() from emitting
regRLC_SPM_MC_CNTL on bare-metal systems?
amdgpu_sriov_is_pp_one_vf(adev) checks AMDGIM_FEATURE_PP_ONE_VF, which is
only set on SR-IOV single-VF guests:
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h:
#define amdgpu_sriov_is_pp_one_vf(adev) \
((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
On bare metal, calling update_spm_vmid() with a non-NULL ring from
amdgpu_ib_schedule() skips amdgpu_ring_emit_wreg() and falls through to
amdgpu_gfx_off_ctrl() and CPU MMIO on every GFX and compute IB submission.
Because GFXOFF is re-enabled on the CPU before the ring is committed and
executed by the GPU, GFXOFF can re-engage and clear regRLC_SPM_MC_CNTL
without any packet on the ring to restore it.
In addition, the update_spm_vmid() callbacks in gfx_v7_0, gfx_v8_0,
gfx_v9_0, gfx_v9_4_3, and gfx_v10_0 ignore the ring parameter and run the
MMIO path on every IB submission, while the ring path in gfx_v11_0 and
gfx_v12_0 overwrites regRLC_SPM_MC_CNTL without preserving other bits in
the register.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112214802.1774412-1-alexander.deucher@amd.com?part=1
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-11-12 23:57 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2026-11-12 21:24 [PATCH] drm/amdgpu: bring back the ring parameter for update_spm_vmid() Alex Deucher
2026-11-12 22:34 ` sashiko-bot
2026-11-12 22:49 ` Alex Deucher
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2026-11-12 21:48 Alex Deucher
2026-11-12 23:57 ` sashiko-bot
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