Re: [PATCH v4 1/3] dt-bindings: display: msm: mdss-common: describe additional block resets

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: display: msm: misdescribed MDSS_CORE_INT2 reset in
  mdss-common
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commit a487330ddb2e36a5355178c8c4bcbb0f50bae826
Author: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>

dt-bindings: display: msm: mdss-common: describe additional block resets

This commit allows the MDSS resets property in mdss-common.yaml to accept
one or two reset entries and updates the SM8750 MDSS binding example
accordingly.

> diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> index c6305a6e03346..51ef4cc74e818 100644
> --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> @@ -84,8 +84,10 @@ properties:
>            - const: cpu-cfg
>  
>    resets:
> +    minItems: 1
>      items:
> -      - description: MDSS_CORE reset
> +      - description: MDSS core reset
> +      - description: MDSS core INT2 interrupt controller reset

[Severity: Low]
Is the second reset entry an interrupt controller reset?

In drivers/clk/qcom/dispcc-sm8750.c (and earlier dispcc drivers such as
dispcc-sm8450.c and dispcc-sm8550.c), DISP_CC_MDSS_CORE_INT2_BCR at 0xa000
and its paired MDSS_INT2_GDSC at 0xb000 control the secondary internal MDSS
core clock and power domain (disp_cc_mdss_mdp1_clk,
disp_cc_mdss_mdp_lut1_clk, disp_cc_mdss_vsync1_clk, and
disp_cc_mdss_ahb1_clk), while the MDSS interrupt controller registers
(HW_INTR_STATUS at offset 0x00010) are part of the primary MDSS core block.
Should this description and the commit message refer to the secondary
internal MDSS core block reset instead?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1794558882.git.xiaqinghuan@mail.ustc.edu.cn?part=1