[PATCH v4 0/3] drm/msm/mdss: reset all block resets described in DT

[PATCH v4 0/3] drm/msm/mdss: reset all block resets described in DT

[Qianhui Xu]

*** AI-assistance disclosure ***
This cover letter and the three patches were prepared with the help of an
LLM coding assistant.  The author reviewed every line, checked every
statement against the tree and his own logs, and takes full responsibility
for the content.

This is v4 of the MDSS block-reset series.  It supersedes v3
(<20261102055026.438521-1-xiaqinghuan@mail.ustc.edu.cn>) and changes only
the last commit message, in response to Dmitry's three questions on v3 2/3
(<awb7bslhrhemsgvu7ubaejvurk6fecotgvqlwtvsoe2benqdgq@tvh2sfjbuzyu>).

What changed in v4
==================

v3 3/3 claimed that command-mode panel initialisation "fails with command
DMA timeouts and the display comes up as backlight only" because INT2 was
left out of reset.  That is a causal statement the data does not support:
the failure is intermittent (~50%) and we never isolated INT2 as a single
variable.  v4 drops the claim.  The commit now says only what holds: MDSS
is an interrupt controller in DT and the DPU takes its IRQ from it, the
display clock controller provides both block resets, and firmware can hand
over with the block running, so DT describes both of them.

The two Reviewed-by tags received on v3 3/3 are carried over; the diff of
all three patches is byte-identical to v3 except for that commit message.

Answers to the three questions, for the record:

- it is an interrupt controller: sm8750.dtsi's mdss node has
  "interrupt-controller;" and "#interrupt-cells = <1>", and the DPU child
  uses "interrupts-extended = <&mdss 0>"; dispcc-sm8750 exposes INT2 as
  MDSS_INT2_GDSC plus DISP_CC_MDSS_CORE_INT2_BCR (0xa000);
- side effect: msm_mdss_reset() runs in msm_mdss_probe() (msm_mdss.c:372)
  before the irq domain is created (:417) and before of_platform_populate()
  (:537), the group is held for the existing 20 ms and released, and dispcc
  PLLs/clocks are untouched;
- testing: the reset at this position, with core+INT2+RSCC as one bulk
  group, ran 5/5 cold POR and 2/2 warm resets without a bad boot, against
  5 STORM in 9 cold boots when only the core was reset.  The exact v4 shape
  (array API, two resets) has not been booted, and there is no per-reset
  A/B.

2/3 exists only so the driver honours a DT listing more than one MDSS
reset.  If you would rather take 3/3 alone, we can drop it; say so and v5
will be 3/3 by itself.

Gates for v4
============

- git am of the three patches onto pristine v7.3-rc7 (24a19b953e) applies
  cleanly, no fuzz.
- checkpatch --strict on the rewritten 0003: 0 errors, 0 warnings, 0 checks.
- dt_binding_check and the W=1 build are unchanged from v3 (no code or DT
  diff in v4).


Qianhui Xu (3):
  dt-bindings: display: msm: mdss-common: describe additional block
    resets
  drm/msm/mdss: reset all block resets described in DT
  arm64: dts: qcom: sm8750: describe all MDSS block resets

 .../devicetree/bindings/display/msm/mdss-common.yaml         | 4 +++-
 .../devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml    | 3 ++-
 arch/arm64/boot/dts/qcom/sm8750.dtsi                         | 3 ++-
 drivers/gpu/drm/msm/msm_mdss.c                               | 5 ++---
 4 files changed, 9 insertions(+), 6 deletions(-)

-- 
2.53.0

[PATCH v4 1/3] dt-bindings: display: msm: mdss-common: describe additional block resets

[Qianhui Xu]

Some platforms provide more than one reset for the MDSS hardware block:
beside the MDSS core reset, the SM8750 display clock controller also
exposes a block reset for the MDSS core INT2 interrupt controller.

Allow the resets property to list one or two resets, keeping the MDSS
core reset as the first entry so that existing device trees describing
a single reset remain valid.

Signed-off-by: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>
---
 .../devicetree/bindings/display/msm/mdss-common.yaml          | 4 +++-
 .../devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml     | 3 ++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
index c6305a6e033..51ef4cc74e8 100644
--- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
@@ -84,8 +84,10 @@ properties:
           - const: cpu-cfg
 
   resets:
+    minItems: 1
     items:
-      - description: MDSS_CORE reset
+      - description: MDSS core reset
+      - description: MDSS core INT2 interrupt controller reset
 
   memory-region:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
index 46dc0d28da2..729de45ec86 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
@@ -101,7 +101,8 @@ examples:
             interconnect-names = "mdp0-mem",
                                  "cpu-cfg";
 
-            resets = <&disp_cc_mdss_core_bcr>;
+            resets = <&disp_cc_mdss_core_bcr>,
+                     <&disp_cc_mdss_core_int2_bcr>;
 
             power-domains = <&mdss_gdsc>;
 
-- 
2.53.0

Re: [PATCH v4 1/3] dt-bindings: display: msm: mdss-common: describe additional block resets

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: display: msm: misdescribed MDSS_CORE_INT2 reset in
  mdss-common
--

commit a487330ddb2e36a5355178c8c4bcbb0f50bae826
Author: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>

dt-bindings: display: msm: mdss-common: describe additional block resets

This commit allows the MDSS resets property in mdss-common.yaml to accept
one or two reset entries and updates the SM8750 MDSS binding example
accordingly.

> diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> index c6305a6e03346..51ef4cc74e818 100644
> --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> @@ -84,8 +84,10 @@ properties:
>            - const: cpu-cfg
>  
>    resets:
> +    minItems: 1
>      items:
> -      - description: MDSS_CORE reset
> +      - description: MDSS core reset
> +      - description: MDSS core INT2 interrupt controller reset

[Severity: Low]
Is the second reset entry an interrupt controller reset?

In drivers/clk/qcom/dispcc-sm8750.c (and earlier dispcc drivers such as
dispcc-sm8450.c and dispcc-sm8550.c), DISP_CC_MDSS_CORE_INT2_BCR at 0xa000
and its paired MDSS_INT2_GDSC at 0xb000 control the secondary internal MDSS
core clock and power domain (disp_cc_mdss_mdp1_clk,
disp_cc_mdss_mdp_lut1_clk, disp_cc_mdss_vsync1_clk, and
disp_cc_mdss_ahb1_clk), while the MDSS interrupt controller registers
(HW_INTR_STATUS at offset 0x00010) are part of the primary MDSS core block.
Should this description and the commit message refer to the secondary
internal MDSS core block reset instead?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1794558882.git.xiaqinghuan@mail.ustc.edu.cn?part=1

[PATCH v4 2/3] drm/msm/mdss: reset all block resets described in DT

[Qianhui Xu]

msm_mdss_reset() acquires only the first reset listed in the MDSS
device node.  Platforms can describe more than one MDSS block reset: the
SM8750 display clock controller also provides a reset for the MDSS core
INT2 interrupt controller, which is left out of reset when the
bootloader hands over with the display block still running.

Switch to the reset control array API so that every reset listed in the
device node is asserted and released as one group.  Devices without a
reset in DT are unaffected, and for devices describing a single reset
the assert/deassert sequence is unchanged.

Signed-off-by: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>
---
 drivers/gpu/drm/msm/msm_mdss.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 9087c4b290d..84b8b4bc9b1 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -310,7 +310,8 @@ static int msm_mdss_reset(struct device *dev)
 {
 	struct reset_control *reset;
 
-	reset = reset_control_get_optional_exclusive(dev, NULL);
+	reset = devm_reset_control_array_get(dev,
+					     RESET_CONTROL_OPTIONAL_EXCLUSIVE);
 	if (!reset) {
 		/* Optional reset not specified */
 		return 0;
@@ -327,8 +328,6 @@ static int msm_mdss_reset(struct device *dev)
 	msleep(20);
 	reset_control_deassert(reset);
 
-	reset_control_put(reset);
-
 	return 0;
 }
 
-- 
2.53.0

[PATCH v4 3/3] arm64: dts: qcom: sm8750: describe all MDSS block resets

[Qianhui Xu]

The SM8750 display clock controller provides, beside the MDSS core
reset, a block reset for the MDSS core INT2 interrupt controller.  The
MDSS node is an interrupt controller in DT and the DPU takes its IRQ
from it, so INT2 is part of the same block, not a separate device.

Bootloaders hand over with the display block still running, so describe
both block resets and let the MDSS reset return the whole group to a
known state before any display hardware is programmed.

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index dd738d13df8..e8e2832f918 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3071,7 +3071,8 @@ mdss: display-subsystem@ae00000 {
 				 <&gcc GCC_DISP_HF_AXI_CLK>,
 				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
 
-			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>,
+				 <&dispcc DISP_CC_MDSS_CORE_INT2_BCR>;
 
 			interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
 					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
-- 
2.53.0

Re: [PATCH v4 3/3] arm64: dts: qcom: sm8750: describe all MDSS block resets

[Konrad Dybcio]

On 11/13/26 9:36 AM, Qianhui Xu wrote:
> The SM8750 display clock controller provides, beside the MDSS core
> reset, a block reset for the MDSS core INT2 interrupt controller.  The
> MDSS node is an interrupt controller in DT and the DPU takes its IRQ
> from it, so INT2 is part of the same block, not a separate device.
> 
> Bootloaders hand over with the display block still running, so describe
> both block resets and let the MDSS reset return the whole group to a
> known state before any display hardware is programmed.
> 
> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v4 3/3] arm64: dts: qcom: sm8750: describe all MDSS block resets

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: sm8750: wrong DISP_CC_MDSS_CORE_INT2_BCR
  reset on mdss
--

commit 40e1c76742905572ea3b661e7e1c52df77536978
Author: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>

arm64: dts: qcom: sm8750: describe all MDSS block resets

This commit adds a second display clock controller reset to the mdss node in
the sm8750 device tree.

> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index cf947acc57602..0f3e649787315 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -3359,7 +3359,8 @@ mdss: display-subsystem@ae00000 {
>  				 <&gcc GCC_DISP_HF_AXI_CLK>,
>  				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
>  
> -			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>,
> +				 <&dispcc DISP_CC_MDSS_CORE_INT2_BCR>;

[Severity: Medium]
Is the second reset entry actually for an interrupt controller rather than a
separate secondary display core domain?

In drivers/clk/qcom/dispcc-sm8750.c, the 0x8000..0x9000 register block holds
the primary display core reset, primary clocks (disp_cc_mdss_mdp_clk,
disp_cc_mdss_ahb_clk) and mdss_gdsc, whereas 0xa000..0xb000 is a secondary
domain with its own clocks (disp_cc_mdss_mdp1_clk, disp_cc_mdss_ahb1_clk,
etc.) and dedicated power domain (mdss_int2_gdsc at 0xb000):

drivers/clk/qcom/dispcc-sm8750.c:
static const struct qcom_reset_map disp_cc_sm8750_resets[] = {
	[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
	[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
	[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
};

static struct gdsc *disp_cc_sm8750_gdscs[] = {
	[MDSS_GDSC] = &mdss_gdsc,
	[MDSS_INT2_GDSC] = &mdss_int2_gdsc,
};

The mdss interrupt controller in drivers/gpu/drm/msm/msm_mdss.c lives at
offset 0x10 in the primary mdss register space, which is powered by
mdss_gdsc and reset by the primary core reset.  Wiring the second reset here
causes msm_mdss_reset() to assert and deassert the block reset of a separate
clock and power domain whose gdsc and clocks are not attached to the mdss
device.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1794558882.git.xiaqinghuan@mail.ustc.edu.cn?part=3