[PATCH 0/5] sunxi: A523: Add SPI support

[PATCH 0/5] sunxi: A523: Add SPI support

[Andre Przywara]

This series adds SPI support to the A523 family of SoCs. The SPI
controller is very similar to the previous generation, to a degree where
we don't need actual code changes, but just to add the new DT compatible
string to the driver (patch 1/5).
Patch 3/5 adds support for SPL SPI booting, again no real driver changes,
just adding the required pinmux settings for the A523. To make this
easier, patch 2/5 reworks the SPI pinmux setting. That doesn't look as
pretty as I hoped for, but is still better than what we have now.
The last two patches enable SPI and SPI booting on two boards with NOR
flash. 

I could successfully boot U-Boot from SPI on the Radxa A5E with that.
The OrangePi 4A also has a NOR SPI, but I couldn't test this, as I don't
have that board.

Please have a look and test!

Cheers,
Andre

Andre Przywara (5):
  spi: sunxi: add support for A523 SPI controller
  sunxi: spl: spi: Clean up SPI0 pinmux setting
  sunxi: spl: spi: Add support for Allwinner A523
  sunxi: configs: Radxa Cubie A5E: enable SPI
  sunxi: configs: OrangePi 4A: enable SPI

 arch/arm/mach-sunxi/spl_spi_sunxi.c | 48 +++++++++++++----------------
 configs/orangepi_4a_defconfig       |  4 +++
 configs/radxa-cubie-a5e_defconfig   |  6 +++-
 drivers/spi/spi-sunxi.c             |  4 +++
 4 files changed, 35 insertions(+), 27 deletions(-)

-- 
2.46.4

[PATCH 1/5] spi: sunxi: add support for A523 SPI controller

[Andre Przywara]

The SPI controllers in the Allwinner A523/A527/T527 SoCs is very close
to the one used in the R329 and D1 generation, definitely as far as our
driver is concerned.

Add the new compatible string, but use the existing config section from
the previous SoC generation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/spi/spi-sunxi.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index 08b603f04a2..4e91cf6b7fd 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -587,6 +587,10 @@ static const struct udevice_id sun4i_spi_ids[] = {
 	  .compatible = "allwinner,sun50i-r329-spi",
 	  .data = (ulong)&sun50i_r329_spi_variant,
 	},
+	{
+	  .compatible = "allwinner,sun55i-a523-spi",
+	  .data = (ulong)&sun50i_r329_spi_variant,
+	},
 	{ /* sentinel */ }
 };
 
-- 
2.46.4

Re: [PATCH 1/5] spi: sunxi: add support for A523 SPI controller

[Jernej Škrabec]

Dne ponedeljek, 11. maj 2026 ob 23:37:09 Srednjeevropski poletni čas je Andre Przywara napisal(a):
> The SPI controllers in the Allwinner A523/A527/T527 SoCs is very close
> to the one used in the R329 and D1 generation, definitely as far as our
> driver is concerned.
> 
> Add the new compatible string, but use the existing config section from
> the previous SoC generation.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

[PATCH 2/5] sunxi: spl: spi: Clean up SPI0 pinmux setting

[Andre Przywara]

The function to set the pinmux for the Port C SPI0 pins was looking more
like a logic puzzle from a magazine than something that readers could
understand and extend.

Replace the convoluted pinmux setup, grouped by pin, with a simple array
of the four pins involved, and just initialise this array at build time,
based on the selected SoC.

This makes it easy to see which pins are needed, and even easier to extend.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/mach-sunxi/spl_spi_sunxi.c | 43 ++++++++++++-----------------
 1 file changed, 18 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 5f72e809952..905a7db2a77 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -105,35 +105,28 @@
 
 /*
  * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
- * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
- * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4.
+ * from SPI Flash, later SoCs are using pins PC0,PC1,PC2,PC3.
+ * Newer SoCs are all over the place.
  */
 static void spi0_pinmux_setup(unsigned int pin_function)
 {
-	/* All chips use PC2. And all chips use PC0, except R528/T113 */
-	if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528))
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
-
-	sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
+	const u16 spi0_pc_pins[4] = {
+#if IS_ENABLED(CONFIG_MACH_SUN8I_R528)
+		SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5)
+#elif IS_ENABLED(CONFIG_MACH_SUN50I_H616)
+		SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4)
+#elif IS_ENABLED(CONFIG_MACH_SUN50I_H6)
+		SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(5)
+#elif IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN5I) || \
+      IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40)
+		SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(23)
+#else
+		SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(3)
+#endif
+	};
 
-	/* All chips except H6/H616/R528/T113 use PC1. */
-	if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) &&
-	    !IS_ENABLED(CONFIG_MACH_SUN8I_R528))
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
-
-	if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) ||
-	    IS_ENABLED(CONFIG_MACH_SUN8I_R528))
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
-	if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
-	    IS_ENABLED(CONFIG_MACH_SUN8I_R528))
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function);
-
-	/* Older generations use PC23 for CS, newer ones use PC3. */
-	if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
-	    IS_ENABLED(CONFIG_MACH_SUN8I_R40))
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
-	else
-		sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
+	for (int i = 0; i < 4; i++)
+		sunxi_gpio_set_cfgpin(spi0_pc_pins[i], pin_function);
 }
 
 static bool is_sun6i_gen_spi(void)
-- 
2.46.4

Re: [PATCH 2/5] sunxi: spl: spi: Clean up SPI0 pinmux setting

[Jernej Škrabec]

Dne ponedeljek, 11. maj 2026 ob 23:37:10 Srednjeevropski poletni čas je Andre Przywara napisal(a):
> The function to set the pinmux for the Port C SPI0 pins was looking more
> like a logic puzzle from a magazine than something that readers could
> understand and extend.
> 
> Replace the convoluted pinmux setup, grouped by pin, with a simple array
> of the four pins involved, and just initialise this array at build time,
> based on the selected SoC.
> 
> This makes it easy to see which pins are needed, and even easier to extend.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/mach-sunxi/spl_spi_sunxi.c | 43 ++++++++++++-----------------
>  1 file changed, 18 insertions(+), 25 deletions(-)
> 
> diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> index 5f72e809952..905a7db2a77 100644
> --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
> +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> @@ -105,35 +105,28 @@
>  
>  /*
>   * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
> - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
> - * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4.
> + * from SPI Flash, later SoCs are using pins PC0,PC1,PC2,PC3.
> + * Newer SoCs are all over the place.
>   */
>  static void spi0_pinmux_setup(unsigned int pin_function)
>  {
> -	/* All chips use PC2. And all chips use PC0, except R528/T113 */
> -	if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528))
> -		sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
> -
> -	sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
> +	const u16 spi0_pc_pins[4] = {
> +#if IS_ENABLED(CONFIG_MACH_SUN8I_R528)
> +		SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5)
> +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H616)
> +		SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4)
> +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H6)
> +		SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(5)
> +#elif IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN5I) || \

Are you sure about CONFIG_MACH_SUN5I? It seems to me that it should fall to PC3 pin.
Also A13 datasheet confirms it.

Best regards,
Jernej

> +      IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40)
> +		SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(23)
> +#else
> +		SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(3)
> +#endif
> +	};
>  
> -	/* All chips except H6/H616/R528/T113 use PC1. */
> -	if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) &&
> -	    !IS_ENABLED(CONFIG_MACH_SUN8I_R528))
> -		sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
> -
> -	if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) ||
> -	    IS_ENABLED(CONFIG_MACH_SUN8I_R528))
> -		sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
> -	if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
> -	    IS_ENABLED(CONFIG_MACH_SUN8I_R528))
> -		sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function);
> -
> -	/* Older generations use PC23 for CS, newer ones use PC3. */
> -	if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
> -	    IS_ENABLED(CONFIG_MACH_SUN8I_R40))
> -		sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
> -	else
> -		sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
> +	for (int i = 0; i < 4; i++)
> +		sunxi_gpio_set_cfgpin(spi0_pc_pins[i], pin_function);
>  }
>  
>  static bool is_sun6i_gen_spi(void)
> 

Re: [PATCH 2/5] sunxi: spl: spi: Clean up SPI0 pinmux setting

[Andre Przywara]

On Tue, 12 May 2026 19:37:06 +0200
Jernej Škrabec <jernej.skrabec@gmail.com> wrote:

> Dne ponedeljek, 11. maj 2026 ob 23:37:10 Srednjeevropski poletni čas je Andre Przywara napisal(a):
> > The function to set the pinmux for the Port C SPI0 pins was looking more
> > like a logic puzzle from a magazine than something that readers could
> > understand and extend.
> > 
> > Replace the convoluted pinmux setup, grouped by pin, with a simple array
> > of the four pins involved, and just initialise this array at build time,
> > based on the selected SoC.
> > 
> > This makes it easy to see which pins are needed, and even easier to extend.
> > 
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> >  arch/arm/mach-sunxi/spl_spi_sunxi.c | 43 ++++++++++++-----------------
> >  1 file changed, 18 insertions(+), 25 deletions(-)
> > 
> > diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > index 5f72e809952..905a7db2a77 100644
> > --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > @@ -105,35 +105,28 @@
> >  
> >  /*
> >   * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
> > - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
> > - * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4.
> > + * from SPI Flash, later SoCs are using pins PC0,PC1,PC2,PC3.
> > + * Newer SoCs are all over the place.
> >   */
> >  static void spi0_pinmux_setup(unsigned int pin_function)
> >  {
> > -	/* All chips use PC2. And all chips use PC0, except R528/T113 */
> > -	if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528))
> > -		sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
> > -
> > -	sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
> > +	const u16 spi0_pc_pins[4] = {
> > +#if IS_ENABLED(CONFIG_MACH_SUN8I_R528)
> > +		SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5)
> > +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H616)
> > +		SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4)
> > +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H6)
> > +		SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(5)
> > +#elif IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN5I) || \  
> 
> Are you sure about CONFIG_MACH_SUN5I? It seems to me that it should fall to PC3 pin.
> Also A13 datasheet confirms it.

Yes, you are right, good catch, will fix that!

Thanks for having a look!

Cheers,
Andre

> 
> Best regards,
> Jernej
> 
> > +      IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40)
> > +		SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(23)
> > +#else
> > +		SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(3)
> > +#endif
> > +	};
> >  
> > -	/* All chips except H6/H616/R528/T113 use PC1. */
> > -	if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) &&
> > -	    !IS_ENABLED(CONFIG_MACH_SUN8I_R528))
> > -		sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
> > -
> > -	if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) ||
> > -	    IS_ENABLED(CONFIG_MACH_SUN8I_R528))
> > -		sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
> > -	if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
> > -	    IS_ENABLED(CONFIG_MACH_SUN8I_R528))
> > -		sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function);
> > -
> > -	/* Older generations use PC23 for CS, newer ones use PC3. */
> > -	if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
> > -	    IS_ENABLED(CONFIG_MACH_SUN8I_R40))
> > -		sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
> > -	else
> > -		sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
> > +	for (int i = 0; i < 4; i++)
> > +		sunxi_gpio_set_cfgpin(spi0_pc_pins[i], pin_function);
> >  }
> >  
> >  static bool is_sun6i_gen_spi(void)
> >   
> 
> 
> 
> 

[PATCH 3/5] sunxi: spl: spi: Add support for Allwinner A523

[Andre Przywara]

The SPI IP in the Allwinner A523 is mostly compatible to the later
generation used in other Allwinner SoCs, at least as far as the SPL
driver is concerned.

Just add the pinmux configuration for SPI0 on PortC, as used by the
BROM. This enables SPI (NOR) boot on A523/A527/T527 boards.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/mach-sunxi/spl_spi_sunxi.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 905a7db2a77..25878026891 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -113,6 +113,8 @@ static void spi0_pinmux_setup(unsigned int pin_function)
 	const u16 spi0_pc_pins[4] = {
 #if IS_ENABLED(CONFIG_MACH_SUN8I_R528)
 		SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5)
+#elif IS_ENABLED(CONFIG_MACH_SUN55I_A523)
+		SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(12)
 #elif IS_ENABLED(CONFIG_MACH_SUN50I_H616)
 		SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4)
 #elif IS_ENABLED(CONFIG_MACH_SUN50I_H6)
@@ -250,7 +252,8 @@ static void spi0_init(void)
 	unsigned int pin_function = SUNXI_GPC_SPI0;
 
 	if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
-	    IS_ENABLED(CONFIG_SUN50I_GEN_H6))
+	    IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
+	    IS_ENABLED(CONFIG_MACH_SUN55I_A523))
 		pin_function = SUN50I_GPC_SPI0;
 	else if (IS_ENABLED(CONFIG_MACH_SUNIV) ||
 		 IS_ENABLED(CONFIG_MACH_SUN8I_R528))
-- 
2.46.4

Re: [PATCH 3/5] sunxi: spl: spi: Add support for Allwinner A523

[Jernej Škrabec]

Dne ponedeljek, 11. maj 2026 ob 23:37:11 Srednjeevropski poletni čas je Andre Przywara napisal(a):
> The SPI IP in the Allwinner A523 is mostly compatible to the later
> generation used in other Allwinner SoCs, at least as far as the SPL
> driver is concerned.
> 
> Just add the pinmux configuration for SPI0 on PortC, as used by the
> BROM. This enables SPI (NOR) boot on A523/A527/T527 boards.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

[PATCH 4/5] sunxi: configs: Radxa Cubie A5E: enable SPI

[Andre Przywara]

The Radxa Cubie A5E ships with SPI NOR flash, so enable the SPI and
flash drivers, also the SPL version, for SPI booting.

Sync the defconfig file with the version from savedefconfig on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 configs/radxa-cubie-a5e_defconfig | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/configs/radxa-cubie-a5e_defconfig b/configs/radxa-cubie-a5e_defconfig
index 84bc4e3d4a9..2a66d0e0866 100644
--- a/configs/radxa-cubie-a5e_defconfig
+++ b/configs/radxa-cubie-a5e_defconfig
@@ -15,6 +15,7 @@ CONFIG_DRAM_SUNXI_TPR12=0x3533302f
 CONFIG_MACH_SUN55I_A523=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_R_I2C_ENABLE=y
+CONFIG_SPL_SPI_SUNXI=y
 CONFIG_SPL_SUNXI_LED_STATUS=y
 CONFIG_SPL_SUNXI_LED_STATUS_GPIO=356
 # CONFIG_SPL_SUNXI_LED_STATUS_ACTIVE_HIGH is not set
@@ -25,11 +26,14 @@ CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_PHY_REALTEK=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SUN8I_EMAC=y
+CONFIG_PHY_REALTEK=y
 CONFIG_REGULATOR_AXP=y
 CONFIG_AXP717_POWER=y
 CONFIG_AXP_DCDC2_VOLT=920
 CONFIG_AXP_DCDC3_VOLT=1100
+CONFIG_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
-- 
2.46.4

Re: [PATCH 4/5] sunxi: configs: Radxa Cubie A5E: enable SPI

[Jernej Škrabec]

Dne ponedeljek, 11. maj 2026 ob 23:37:12 Srednjeevropski poletni čas je Andre Przywara napisal(a):
> The Radxa Cubie A5E ships with SPI NOR flash, so enable the SPI and
> flash drivers, also the SPL version, for SPI booting.
> 
> Sync the defconfig file with the version from savedefconfig on the way.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

[PATCH 5/5] sunxi: configs: OrangePi 4A: enable SPI

[Andre Przywara]

The OrangePi 4A board ships with SPI NOR flash, so enable the SPI and
flash drivers, also the SPL version, for SPI booting.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 configs/orangepi_4a_defconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/configs/orangepi_4a_defconfig b/configs/orangepi_4a_defconfig
index 6a44dd97959..2d36757ba11 100644
--- a/configs/orangepi_4a_defconfig
+++ b/configs/orangepi_4a_defconfig
@@ -16,6 +16,7 @@ CONFIG_DRAM_SUNXI_TPR12=0x3a373233
 CONFIG_MACH_SUN55I_A523=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_R_I2C_ENABLE=y
+CONFIG_SPL_SPI_SUNXI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
@@ -23,10 +24,13 @@ CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH_XMC=y
 CONFIG_REGULATOR_AXP=y
 CONFIG_AXP717_POWER=y
 CONFIG_AXP_I2C_ADDRESS=0x35
 CONFIG_AXP_DCDC2_VOLT=920
 CONFIG_AXP_DCDC3_VOLT=1160
+CONFIG_SPI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
-- 
2.46.4

Re: [PATCH 5/5] sunxi: configs: OrangePi 4A: enable SPI

[Jernej Škrabec]

Dne ponedeljek, 11. maj 2026 ob 23:37:13 Srednjeevropski poletni čas je Andre Przywara napisal(a):
> The OrangePi 4A board ships with SPI NOR flash, so enable the SPI and
> flash drivers, also the SPL version, for SPI booting.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej