[PATCH] clocksource: vf_pit_timer: use complement for sched_clock reading

[PATCH] clocksource: vf_pit_timer: use complement for sched_clock reading

[Stefan Agner]

Vybrids PIT register is monitonic decreasing. However, sched_clock
reading needs to be monitonic increasing. Use bitwise not to get
the complement of the clock register. This fixes the clock going
backward. Also, the clock now starts at 0 since we load the
register with the maximum value at start.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clocksource/vf_pit_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
index 02821b0..a918bc4 100644
--- a/drivers/clocksource/vf_pit_timer.c
+++ b/drivers/clocksource/vf_pit_timer.c
@@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void)
 
 static u64 pit_read_sched_clock(void)
 {
-	return __raw_readl(clksrc_base + PITCVAL);
+	return ~__raw_readl(clksrc_base + PITCVAL);
 }
 
 static int __init pit_clocksource_init(unsigned long rate)
-- 
1.9.0

[PATCH] clocksource: vf_pit_timer: use complement for sched_clock reading

[Stefan Agner]

Vybrids PIT register is monitonic decreasing. However, sched_clock
reading needs to be monitonic increasing. Use bitwise not to get
the complement of the clock register. This fixes the clock going
backward. Also, the clock now starts at 0 since we load the
register with the maximum value at start.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clocksource/vf_pit_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
index 02821b0..a918bc4 100644
--- a/drivers/clocksource/vf_pit_timer.c
+++ b/drivers/clocksource/vf_pit_timer.c
@@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void)
 
 static u64 pit_read_sched_clock(void)
 {
-	return __raw_readl(clksrc_base + PITCVAL);
+	return ~__raw_readl(clksrc_base + PITCVAL);
 }
 
 static int __init pit_clocksource_init(unsigned long rate)
-- 
1.9.0

[PATCH] clocksource: vf_pit_timer: use complement for sched_clock reading

[Shawn Guo]

On Wed, Mar 05, 2014 at 11:11:08PM +0100, Stefan Agner wrote:
> Vybrids PIT register is monitonic decreasing. However, sched_clock
> reading needs to be monitonic increasing. Use bitwise not to get
> the complement of the clock register. This fixes the clock going
> backward. Also, the clock now starts at 0 since we load the
> register with the maximum value at start.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>

Looks correct to me, so

Acked-by: Shawn Guo <shawn.guo@linaro.org>

But I also copied the driver author Jingchang to see if he has any
comment.

Shawn

> ---
>  drivers/clocksource/vf_pit_timer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
> index 02821b0..a918bc4 100644
> --- a/drivers/clocksource/vf_pit_timer.c
> +++ b/drivers/clocksource/vf_pit_timer.c
> @@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void)
>  
>  static u64 pit_read_sched_clock(void)
>  {
> -	return __raw_readl(clksrc_base + PITCVAL);
> +	return ~__raw_readl(clksrc_base + PITCVAL);
>  }
>  
>  static int __init pit_clocksource_init(unsigned long rate)
> -- 
> 1.9.0
> 

Re: [PATCH] clocksource: vf_pit_timer: use complement for sched_clock reading

[Shawn Guo]

On Wed, Mar 05, 2014 at 11:11:08PM +0100, Stefan Agner wrote:
> Vybrids PIT register is monitonic decreasing. However, sched_clock
> reading needs to be monitonic increasing. Use bitwise not to get
> the complement of the clock register. This fixes the clock going
> backward. Also, the clock now starts at 0 since we load the
> register with the maximum value at start.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>

Looks correct to me, so

Acked-by: Shawn Guo <shawn.guo@linaro.org>

But I also copied the driver author Jingchang to see if he has any
comment.

Shawn

> ---
>  drivers/clocksource/vf_pit_timer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
> index 02821b0..a918bc4 100644
> --- a/drivers/clocksource/vf_pit_timer.c
> +++ b/drivers/clocksource/vf_pit_timer.c
> @@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void)
>  
>  static u64 pit_read_sched_clock(void)
>  {
> -	return __raw_readl(clksrc_base + PITCVAL);
> +	return ~__raw_readl(clksrc_base + PITCVAL);
>  }
>  
>  static int __init pit_clocksource_init(unsigned long rate)
> -- 
> 1.9.0
> 

[PATCH] clocksource: vf_pit_timer: use complement for sched_clock reading

[Jingchang Lu]

> -----Original Message-----
> From: Shawn Guo [mailto:shawn.guo at linaro.org]
> Sent: Thursday, March 06, 2014 9:46 AM
> To: Stefan Agner
> Cc: daniel.lezcano at linaro.org; tglx at linutronix.de; linux at arm.linux.org.uk;
> linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org; Lu
> Jingchang-B35083
> Subject: Re: [PATCH] clocksource: vf_pit_timer: use complement for
> sched_clock reading
> 
> On Wed, Mar 05, 2014 at 11:11:08PM +0100, Stefan Agner wrote:
> > Vybrids PIT register is monitonic decreasing. However, sched_clock
> > reading needs to be monitonic increasing. Use bitwise not to get the
> > complement of the clock register. This fixes the clock going backward.
> > Also, the clock now starts at 0 since we load the register with the
> > maximum value at start.
> >
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
> Looks correct to me, so
> 
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
> 
> But I also copied the driver author Jingchang to see if he has any
> comment.
> 
> Shawn
> 
The fix is correct, thanks.

Best Regards,
Jingchang

> > ---
> >  drivers/clocksource/vf_pit_timer.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clocksource/vf_pit_timer.c
> > b/drivers/clocksource/vf_pit_timer.c
> > index 02821b0..a918bc4 100644
> > --- a/drivers/clocksource/vf_pit_timer.c
> > +++ b/drivers/clocksource/vf_pit_timer.c
> > @@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void)
> >
> >  static u64 pit_read_sched_clock(void)  {
> > -	return __raw_readl(clksrc_base + PITCVAL);
> > +	return ~__raw_readl(clksrc_base + PITCVAL);
> >  }
> >
> >  static int __init pit_clocksource_init(unsigned long rate)
> > --
> > 1.9.0
> >

RE: [PATCH] clocksource: vf_pit_timer: use complement for sched_clock reading

[Jingchang Lu]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1867 bytes --]



> -----Original Message-----
> From: Shawn Guo [mailto:shawn.guo@linaro.org]
> Sent: Thursday, March 06, 2014 9:46 AM
> To: Stefan Agner
> Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux@arm.linux.org.uk;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Lu
> Jingchang-B35083
> Subject: Re: [PATCH] clocksource: vf_pit_timer: use complement for
> sched_clock reading
> 
> On Wed, Mar 05, 2014 at 11:11:08PM +0100, Stefan Agner wrote:
> > Vybrids PIT register is monitonic decreasing. However, sched_clock
> > reading needs to be monitonic increasing. Use bitwise not to get the
> > complement of the clock register. This fixes the clock going backward.
> > Also, the clock now starts at 0 since we load the register with the
> > maximum value at start.
> >
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> 
> Looks correct to me, so
> 
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
> 
> But I also copied the driver author Jingchang to see if he has any
> comment.
> 
> Shawn
> 
The fix is correct, thanks.

Best Regards,
Jingchang

> > ---
> >  drivers/clocksource/vf_pit_timer.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clocksource/vf_pit_timer.c
> > b/drivers/clocksource/vf_pit_timer.c
> > index 02821b0..a918bc4 100644
> > --- a/drivers/clocksource/vf_pit_timer.c
> > +++ b/drivers/clocksource/vf_pit_timer.c
> > @@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void)
> >
> >  static u64 pit_read_sched_clock(void)  {
> > -	return __raw_readl(clksrc_base + PITCVAL);
> > +	return ~__raw_readl(clksrc_base + PITCVAL);
> >  }
> >
> >  static int __init pit_clocksource_init(unsigned long rate)
> > --
> > 1.9.0
> >

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[tip:timers/urgent] clocksource: vf_pit_timer: use complement for sched_clock reading

[tip-bot for Stefan Agner]

Commit-ID:  224aa3ed45c8735ae02bb2ecca002409fa6aa772
Gitweb:     http://git.kernel.org/tip/224aa3ed45c8735ae02bb2ecca002409fa6aa772
Author:     Stefan Agner <stefan@agner.ch>
AuthorDate: Wed, 5 Mar 2014 23:11:08 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Thu, 6 Mar 2014 11:34:14 +0100

clocksource: vf_pit_timer: use complement for sched_clock reading

Vybrids PIT register is monitonic decreasing. However, sched_clock
reading needs to be monitonic increasing. Use bitwise not to get
the complement of the clock register. This fixes the clock going
backward. Also, the clock now starts at 0 since we load the
register with the maximum value at start.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Cc: daniel.lezcano@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Link: http://lkml.kernel.org/r/d25af915993aec1b486be653eb86f748ddef54fe.1394057313.git.stefan@agner.ch
Cc: stable@vger.kernel.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 drivers/clocksource/vf_pit_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c
index 02821b0..a918bc4 100644
--- a/drivers/clocksource/vf_pit_timer.c
+++ b/drivers/clocksource/vf_pit_timer.c
@@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(void)
 
 static u64 pit_read_sched_clock(void)
 {
-	return __raw_readl(clksrc_base + PITCVAL);
+	return ~__raw_readl(clksrc_base + PITCVAL);
 }
 
 static int __init pit_clocksource_init(unsigned long rate)