From: Mark Langsdorf <mark.langsdorf@amd.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@redhat.com,
akpm@linux-foundation.org, andreas.herrmann3@amd.com,
mark.langsdorf@amd.com, tglx@linutronix.de, mingo@elte.hu
Subject: [tip:x86/cpu] x86: cacheinfo: disable L3 ECC scrubbing when L3 cache index is disabled
Date: Fri, 10 Apr 2009 12:37:19 GMT [thread overview]
Message-ID: <tip-ba518bea2db21c72d44a6cbfd825b026ef9cdcb6@git.kernel.org> (raw)
In-Reply-To: <20090409132406.GK31527@alberich.amd.com>
Commit-ID: ba518bea2db21c72d44a6cbfd825b026ef9cdcb6
Gitweb: http://git.kernel.org/tip/ba518bea2db21c72d44a6cbfd825b026ef9cdcb6
Author: Mark Langsdorf <mark.langsdorf@amd.com>
AuthorDate: Thu, 9 Apr 2009 15:24:06 +0200
Committer: Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 10 Apr 2009 14:22:34 +0200
x86: cacheinfo: disable L3 ECC scrubbing when L3 cache index is disabled
(Use correct mask to zero out bits 24-28 by Andreas)
Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <20090409132406.GK31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index fc28291..d46a849 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -731,6 +731,7 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
int node = cpu_to_node(cpu);
struct pci_dev *dev = node_to_k8_nb_misc(node);
unsigned long val = 0;
+ unsigned int scrubber = 0;
if (!this_leaf->can_disable)
return -EINVAL;
@@ -745,6 +746,11 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
return -EINVAL;
val |= 0xc0000000;
+
+ pci_read_config_dword(dev, 0x58, &scrubber);
+ scrubber &= ~0x1f000000;
+ pci_write_config_dword(dev, 0x58, scrubber);
+
pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
wbinvd();
pci_write_config_dword(dev, 0x1BC + index * 4, val);
next prev parent reply other threads:[~2009-04-10 12:41 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-04-09 12:56 [PATCH 0/8] x86: cacheinfo: cache_disable fixes/cleanup Andreas Herrmann
2009-04-09 12:59 ` [PATCH 1/8] Revert "x86, cpu: intel_cacheinfo.c: use cpumask_first(to_cpumask())" Andreas Herrmann
2009-04-09 13:02 ` [PATCH 2/8] Revert "x86, cpu: conform L3 Cache Index Disable to Linux standards" Andreas Herrmann
2009-04-09 13:05 ` [PATCH 3/8] x86: cacheinfo: use L3 cache index disable feature only for CPUs that support it Andreas Herrmann
2009-04-10 12:36 ` [tip:x86/cpu] " Andreas Herrmann
2009-04-09 13:07 ` [PATCH 4/8] x86: cacheinfo: correct return value when cache_disable feature is not active Andreas Herrmann
2009-04-10 12:36 ` [tip:x86/cpu] " Andreas Herrmann
2009-04-09 13:16 ` [PATCH 5/8] x86: cacheinfo: use cached K8 NB_MISC devices instead of scanning for it Andreas Herrmann
2009-04-10 12:36 ` [tip:x86/cpu] " Andreas Herrmann
2009-04-09 13:18 ` [PATCH 6/8] x86: cacheinfo: replace sysfs interface for cache_disable feature Andreas Herrmann
2009-04-10 12:37 ` [tip:x86/cpu] " Mark Langsdorf
2009-04-13 4:52 ` Jaswinder Singh Rajput
2009-04-13 4:56 ` Jaswinder Singh Rajput
2009-04-14 11:58 ` Ingo Molnar
2009-04-14 12:48 ` Jaswinder Singh Rajput
2009-04-14 13:28 ` Ingo Molnar
2009-04-09 13:24 ` [PATCH 7/8] x86: cacheinfo: disable L3 ECC scrubbing when L3 cache index is disabled Andreas Herrmann
2009-04-10 12:37 ` Mark Langsdorf [this message]
2009-04-09 13:31 ` [PATCH 8/8] x86/docs: add description for cache_disable sysfs interface Andreas Herrmann
2009-04-10 12:37 ` [tip:x86/cpu] " Mark Langsdorf
2009-04-10 12:28 ` [PATCH 0/8] x86: cacheinfo: cache_disable fixes/cleanup Ingo Molnar
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