* [PATCH 0/3] perf_event: improvements to p6 PMU driver
@ 2012-10-19 21:28 Vince Weaver
2012-10-19 21:30 ` [PATCH 1/3] perf_event: fix p6 FP_ASSIST event constraint Vince Weaver
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Vince Weaver @ 2012-10-19 21:28 UTC (permalink / raw)
To: linux-kernel
Cc: Peter Zijlstra, Paul Mackerras, Ingo Molnar,
Arnaldo Carvalho de Melo, eranian, vincent.weaver
Hello
The following patches include some fixes for the p6 PMU driver.
I noticed these when working on the KNC driver which is roughly based
on the p6 driver.
patch1: Fixes a wrong event constraint
patch2: Expands the number of generic events supported by p6
patch3: Cleans up p6_pmu_enable_event() and p6_pmu_disable_event()
Changes around the 2.6.33 to 2.6.34 transition left some
confusing dead code around that was no longer necessary.
I've tested all of these on a Pentium II machine I brought out of
retirement.
Vince Weaver
vincent.weaver@maine.edu
--
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^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/3] perf_event: fix p6 FP_ASSIST event constraint 2012-10-19 21:28 [PATCH 0/3] perf_event: improvements to p6 PMU driver Vince Weaver @ 2012-10-19 21:30 ` Vince Weaver 2012-10-24 9:59 ` [tip:perf/urgent] perf/x86: Fix P6 " tip-bot for Vince Weaver 2012-10-19 21:31 ` [PATCH 2/3] perf_event: Update generic events on p6 PMU Vince Weaver 2012-10-19 21:33 ` [PATCH 3/3] perf_event: remove cpuc->enabled check Vince Weaver 2 siblings, 1 reply; 7+ messages in thread From: Vince Weaver @ 2012-10-19 21:30 UTC (permalink / raw) To: linux-kernel Cc: Peter Zijlstra, Paul Mackerras, Ingo Molnar, Arnaldo Carvalho de Melo, eranian According to Intel SDM Volume 3B, FP_ASSIST is limited to Counter 1 only, not Counter 0. Tested on a Pentium II. Signed-off-by: Vince Weaver <vincent.weaver@maine.edu> diff -ur linux-3.7-rc1.orig/arch/x86/kernel/cpu/perf_event_p6.c linux-3.7-rc1/arch/x86/kernel/cpu/perf_event_p6.c --- linux-3.7-rc1.orig/arch/x86/kernel/cpu/perf_event_p6.c 2012-10-14 17:41:04.000000000 -0400 +++ linux-3.7-rc1/arch/x86/kernel/cpu/perf_event_p6.c 2012-10-19 14:50:41.212241569 -0400 @@ -34,7 +34,7 @@ { INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */ INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ - INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */ + INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ ^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip:perf/urgent] perf/x86: Fix P6 FP_ASSIST event constraint 2012-10-19 21:30 ` [PATCH 1/3] perf_event: fix p6 FP_ASSIST event constraint Vince Weaver @ 2012-10-24 9:59 ` tip-bot for Vince Weaver 0 siblings, 0 replies; 7+ messages in thread From: tip-bot for Vince Weaver @ 2012-10-24 9:59 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hpa, mingo, vincent.weaver, a.p.zijlstra, tglx Commit-ID: 7991c9ca40d3127dd2ffa3a9c1e33f7d4005495a Gitweb: http://git.kernel.org/tip/7991c9ca40d3127dd2ffa3a9c1e33f7d4005495a Author: Vince Weaver <vincent.weaver@maine.edu> AuthorDate: Fri, 19 Oct 2012 17:30:01 -0400 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Wed, 24 Oct 2012 10:31:57 +0200 perf/x86: Fix P6 FP_ASSIST event constraint According to Intel SDM Volume 3B, FP_ASSIST is limited to Counter 1 only, not Counter 0. Tested on a Pentium II. Signed-off-by: Vince Weaver <vincent.weaver@maine.edu> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191728570.14552@vincent-weaver-1.um.maine.edu Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/kernel/cpu/perf_event_p6.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c index e4dd0f7..0ff5f7f 100644 --- a/arch/x86/kernel/cpu/perf_event_p6.c +++ b/arch/x86/kernel/cpu/perf_event_p6.c @@ -34,7 +34,7 @@ static struct event_constraint p6_event_constraints[] = { INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */ INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ - INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */ + INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] perf_event: Update generic events on p6 PMU 2012-10-19 21:28 [PATCH 0/3] perf_event: improvements to p6 PMU driver Vince Weaver 2012-10-19 21:30 ` [PATCH 1/3] perf_event: fix p6 FP_ASSIST event constraint Vince Weaver @ 2012-10-19 21:31 ` Vince Weaver 2012-10-24 10:00 ` [tip:perf/urgent] perf/x86: Update/fix generic events on P6 PMU tip-bot for Vince Weaver 2012-10-19 21:33 ` [PATCH 3/3] perf_event: remove cpuc->enabled check Vince Weaver 2 siblings, 1 reply; 7+ messages in thread From: Vince Weaver @ 2012-10-19 21:31 UTC (permalink / raw) To: linux-kernel Cc: Peter Zijlstra, Paul Mackerras, Ingo Molnar, Arnaldo Carvalho de Melo, eranian This patch updates the generic events on p6, including some new extended cache events. Values for these events were taken from the equivelant PAPI predefined events. Tested on a Pentium II. Signed-off-by: Vince Weaver <vincent.weaver@maine.edu> diff -ur linux-3.7-rc1.orig/arch/x86/kernel/cpu/perf_event_p6.c linux-3.7-rc1/arch/x86/kernel/cpu/perf_event_p6.c --- linux-3.7-rc1.orig/arch/x86/kernel/cpu/perf_event_p6.c 2012-10-14 17:41:04.000000000 -0400 +++ linux-3.7-rc1/arch/x86/kernel/cpu/perf_event_p6.c 2012-10-19 15:34:17.728239395 -0400 @@ -8,13 +8,106 @@ */ static const u64 p6_perfmon_event_map[] = { - [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, - [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, - [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, - [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, - [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, - [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, + [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, /* CPU_CLK_UNHALTED */ + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, /* INST_RETIRED */ + [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, /* L2_RQSTS:M:E:S:I */ + [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, /* L2_RQSTS:I */ + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, /* BR_INST_RETIRED */ + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, /* BR_MISS_PRED_RETIRED */ + [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, /* BUS_DRDY_CLOCKS */ + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2, /* RESOURCE_STALLS */ + +}; + +static __initconst u64 p6_hw_cache_event_ids + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = +{ + [ C(L1D) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */ + [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */ + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + [ C(L1I ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */ + [ C(RESULT_MISS) ] = 0x0f28, /* L2_IFETCH:M:E:S:I */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + [ C(LL ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0x0025, /* L2_M_LINES_INM */ + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + [ C(DTLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */ + [ C(RESULT_MISS) ] = 0, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + [ C(ITLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */ + [ C(RESULT_MISS) ] = 0x0085, /* ITLB_MISS */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, + [ C(BPU ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED */ + [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISS_PRED_RETIRED */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, }; static u64 p6_pmu_event_map(int hw_event) @@ -158,5 +251,9 @@ x86_pmu = p6_pmu; + memcpy(hw_cache_event_ids, p6_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); + + return 0; } ^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip:perf/urgent] perf/x86: Update/fix generic events on P6 PMU 2012-10-19 21:31 ` [PATCH 2/3] perf_event: Update generic events on p6 PMU Vince Weaver @ 2012-10-24 10:00 ` tip-bot for Vince Weaver 0 siblings, 0 replies; 7+ messages in thread From: tip-bot for Vince Weaver @ 2012-10-24 10:00 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hpa, mingo, vincent.weaver, a.p.zijlstra, tglx Commit-ID: e09df47885d767e418902067ce1885aafa3b27db Gitweb: http://git.kernel.org/tip/e09df47885d767e418902067ce1885aafa3b27db Author: Vince Weaver <vincent.weaver@maine.edu> AuthorDate: Fri, 19 Oct 2012 17:31:54 -0400 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Wed, 24 Oct 2012 10:31:58 +0200 perf/x86: Update/fix generic events on P6 PMU This patch updates the generic events on p6, including some new extended cache events. Values for these events were taken from the equivelant PAPI predefined events. Tested on a Pentium II. Signed-off-by: Vince Weaver <vincent.weaver@maine.edu> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191730080.14552@vincent-weaver-1.um.maine.edu Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/kernel/cpu/perf_event_p6.c | 111 ++++++++++++++++++++++++++++++++-- 1 files changed, 104 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c index 0ff5f7f..9582fcb 100644 --- a/arch/x86/kernel/cpu/perf_event_p6.c +++ b/arch/x86/kernel/cpu/perf_event_p6.c @@ -8,13 +8,106 @@ */ static const u64 p6_perfmon_event_map[] = { - [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, - [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, - [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, - [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, - [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, - [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, + [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, /* CPU_CLK_UNHALTED */ + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, /* INST_RETIRED */ + [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, /* L2_RQSTS:M:E:S:I */ + [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, /* L2_RQSTS:I */ + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, /* BR_INST_RETIRED */ + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, /* BR_MISS_PRED_RETIRED */ + [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, /* BUS_DRDY_CLOCKS */ + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2, /* RESOURCE_STALLS */ + +}; + +static __initconst u64 p6_hw_cache_event_ids + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = +{ + [ C(L1D) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */ + [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */ + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + [ C(L1I ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */ + [ C(RESULT_MISS) ] = 0x0f28, /* L2_IFETCH:M:E:S:I */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + [ C(LL ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0x0025, /* L2_M_LINES_INM */ + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + [ C(DTLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */ + [ C(RESULT_MISS) ] = 0, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0, + [ C(RESULT_MISS) ] = 0, + }, + }, + [ C(ITLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */ + [ C(RESULT_MISS) ] = 0x0085, /* ITLB_MISS */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, + [ C(BPU ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED */ + [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISS_PRED_RETIRED */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, }; static u64 p6_pmu_event_map(int hw_event) @@ -158,5 +251,9 @@ __init int p6_pmu_init(void) x86_pmu = p6_pmu; + memcpy(hw_cache_event_ids, p6_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); + + return 0; } ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] perf_event: remove cpuc->enabled check 2012-10-19 21:28 [PATCH 0/3] perf_event: improvements to p6 PMU driver Vince Weaver 2012-10-19 21:30 ` [PATCH 1/3] perf_event: fix p6 FP_ASSIST event constraint Vince Weaver 2012-10-19 21:31 ` [PATCH 2/3] perf_event: Update generic events on p6 PMU Vince Weaver @ 2012-10-19 21:33 ` Vince Weaver 2012-10-24 10:01 ` [tip:perf/urgent] perf/x86: Remove P6 " tip-bot for Vince Weaver 2 siblings, 1 reply; 7+ messages in thread From: Vince Weaver @ 2012-10-19 21:33 UTC (permalink / raw) To: linux-kernel Cc: Peter Zijlstra, Paul Mackerras, Ingo Molnar, Arnaldo Carvalho de Melo, eranian Between 2.6.33 and 2.6.34 the PMU code was made modular. The x86_pmu_enable() call was extended to disable cpuc->enabled and iterate the counters, enabling one at a time, before calling enable_all() at the end, followed by re-enabling cpuc->enabled. Since cpuc->enabled was set to 0, that change effectively caused the "val |= ARCH_PERFMON_EVENTSEL_ENABLE;" code in p6_pmu_enable_event() and p6_pmu_disable_event() to be dead code that was never called. This change removes this code (which was confusing) and adds some extra commentary to make it more clear what is going on. Signed-off-by: Vince Weaver <vincent.weaver@maine.edu> diff -ur linux-3.7-rc1.orig/arch/x86/kernel/cpu/perf_event_p6.c linux-3.7-rc1/arch/x86/kernel/cpu/perf_event_p6.c --- linux-3.7-rc1.orig/arch/x86/kernel/cpu/perf_event_p6.c 2012-10-14 17:41:04.000000000 -0400 +++ linux-3.7-rc1/arch/x86/kernel/cpu/perf_event_p6.c 2012-10-19 15:58:50.416238172 -0400 @@ -64,25 +64,25 @@ static inline void p6_pmu_disable_event(struct perf_event *event) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; u64 val = P6_NOP_EVENT; - if (cpuc->enabled) - val |= ARCH_PERFMON_EVENTSEL_ENABLE; - (void)wrmsrl_safe(hwc->config_base, val); } static void p6_pmu_enable_event(struct perf_event *event) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; u64 val; val = hwc->config; - if (cpuc->enabled) - val |= ARCH_PERFMON_EVENTSEL_ENABLE; + + /* + * p6 only has a global event enable, set on PerfEvtSel0 + * We "disable" events by programming P6_NOP_EVENT + * and we rely on p6_pmu_enable_all() being called + * to actually enable the events. + */ (void)wrmsrl_safe(hwc->config_base, val); } ^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip:perf/urgent] perf/x86: Remove P6 cpuc->enabled check 2012-10-19 21:33 ` [PATCH 3/3] perf_event: remove cpuc->enabled check Vince Weaver @ 2012-10-24 10:01 ` tip-bot for Vince Weaver 0 siblings, 0 replies; 7+ messages in thread From: tip-bot for Vince Weaver @ 2012-10-24 10:01 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hpa, mingo, vincent.weaver, a.p.zijlstra, tglx Commit-ID: 58e9eaf06f5476cb2192ec1d012674ce5e79dd21 Gitweb: http://git.kernel.org/tip/58e9eaf06f5476cb2192ec1d012674ce5e79dd21 Author: Vince Weaver <vincent.weaver@maine.edu> AuthorDate: Fri, 19 Oct 2012 17:33:38 -0400 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Wed, 24 Oct 2012 10:32:00 +0200 perf/x86: Remove P6 cpuc->enabled check Between 2.6.33 and 2.6.34 the PMU code was made modular. The x86_pmu_enable() call was extended to disable cpuc->enabled and iterate the counters, enabling one at a time, before calling enable_all() at the end, followed by re-enabling cpuc->enabled. Since cpuc->enabled was set to 0, that change effectively caused the "val |= ARCH_PERFMON_EVENTSEL_ENABLE;" code in p6_pmu_enable_event() and p6_pmu_disable_event() to be dead code that was never called. This change removes this code (which was confusing) and adds some extra commentary to make it more clear what is going on. Signed-off-by: Vince Weaver <vincent.weaver@maine.edu> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191732000.14552@vincent-weaver-1.um.maine.edu Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/kernel/cpu/perf_event_p6.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c index 9582fcb..7d0270b 100644 --- a/arch/x86/kernel/cpu/perf_event_p6.c +++ b/arch/x86/kernel/cpu/perf_event_p6.c @@ -157,25 +157,25 @@ static void p6_pmu_enable_all(int added) static inline void p6_pmu_disable_event(struct perf_event *event) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; u64 val = P6_NOP_EVENT; - if (cpuc->enabled) - val |= ARCH_PERFMON_EVENTSEL_ENABLE; - (void)wrmsrl_safe(hwc->config_base, val); } static void p6_pmu_enable_event(struct perf_event *event) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; u64 val; val = hwc->config; - if (cpuc->enabled) - val |= ARCH_PERFMON_EVENTSEL_ENABLE; + + /* + * p6 only has a global event enable, set on PerfEvtSel0 + * We "disable" events by programming P6_NOP_EVENT + * and we rely on p6_pmu_enable_all() being called + * to actually enable the events. + */ (void)wrmsrl_safe(hwc->config_base, val); } ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2012-10-24 10:02 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-10-19 21:28 [PATCH 0/3] perf_event: improvements to p6 PMU driver Vince Weaver 2012-10-19 21:30 ` [PATCH 1/3] perf_event: fix p6 FP_ASSIST event constraint Vince Weaver 2012-10-24 9:59 ` [tip:perf/urgent] perf/x86: Fix P6 " tip-bot for Vince Weaver 2012-10-19 21:31 ` [PATCH 2/3] perf_event: Update generic events on p6 PMU Vince Weaver 2012-10-24 10:00 ` [tip:perf/urgent] perf/x86: Update/fix generic events on P6 PMU tip-bot for Vince Weaver 2012-10-19 21:33 ` [PATCH 3/3] perf_event: remove cpuc->enabled check Vince Weaver 2012-10-24 10:01 ` [tip:perf/urgent] perf/x86: Remove P6 " tip-bot for Vince Weaver
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