RISC-V Floating Point Extension

RISC-V Floating Point Extension

[Derek Christ]

Hello,

I'm currently trying to run a RISC-V bare-metal kernel on QEMU that uses the 
floating point extension F.
It seems like this extension, besides D, is enabled automatically in QEMU. 
In fact, the floating point registers can be examined successfully using 
GDB.
However, when the first floating point instruction is reached in the program 
execution (in this case flw), an illegal instruction trap is raised. The 
kernel itself is compiled using these flags: -march=rv32imaf -mabi=ilp32f
Is there something I am missing? Perhaps, the FPU needs to be enabled in 
some way?

Thanks for your help!

Best
Derek

Re: RISC-V Floating Point Extension

[Palmer Dabbelt]

On Mon, 29 Apr 2024 07:02:59 PDT (-0700), dchrist@rptu.de wrote:
> Hello,
>
> I'm currently trying to run a RISC-V bare-metal kernel on QEMU that uses the
> floating point extension F.
> It seems like this extension, besides D, is enabled automatically in QEMU.
> In fact, the floating point registers can be examined successfully using
> GDB.
> However, when the first floating point instruction is reached in the program
> execution (in this case flw), an illegal instruction trap is raised. The
> kernel itself is compiled using these flags: -march=rv32imaf -mabi=ilp32f
> Is there something I am missing? Perhaps, the FPU needs to be enabled in
> some way?

There's dynamic enable bits for floating point in the various status 
registers, see mstatus.FS in the priv spec for the details.

> Thanks for your help!
>
> Best
> Derek

Re: RISC-V Floating Point Extension

[Derek Christ]

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Thanks, that was it!

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