From: Keith Packard <keithp@keithp.com>
To: meteor <meteor@ms1.url.com.tw>, intel-gfx@lists.freedesktop.org
Subject: Re: Garbage on screen when switching resolution after BIOS post
Date: Tue, 04 Oct 2011 08:38:33 -0700 [thread overview]
Message-ID: <yunobxwlqbq.fsf@aiko.keithp.com> (raw)
In-Reply-To: <CADsGByqLjX==6tG6+k33taUN8UJQcBUjkQee+Pja=DXW7THraQ@mail.gmail.com>
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On Tue, 4 Oct 2011 17:53:08 +0800, meteor <meteor@ms1.url.com.tw> wrote:
> Please refer to the VDD power monitoring image:
> http://imageshack.us/photo/my-images/827/auoi.jpg/
Nice picture. As Daniel mentioned, you'll want to try my eDP power
sequencing changes and see what they do.
I'm not sure they will though -- my understanding of the eDP spec is
that if we drop VDD, we must hold it low for the specified interval, but
I haven't found anything saying that we must lower VDD when disabling
and re-enabling the display.
Given that the VDD low interval is often quite long (500ms or more), I'd
prefer to avoid doing this when booting the operating system.
I wonder if the final solution will be to move the whole DP link
training and eDP power sequencing stuff to a separate thread to keep
that out of the sequential path of the mode setting code which is run
when the driver loads.
--
keith.packard@intel.com
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prev parent reply other threads:[~2011-10-04 15:38 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-04 9:53 Garbage on screen when switching resolution after BIOS post meteor
2011-10-04 11:08 ` Daniel Vetter
2011-10-04 15:38 ` Keith Packard [this message]
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