Multi Delta 1010 sync

Multi Delta 1010 sync

[John Rigg]

After some reverse engineering I've found out why I was having trouble
syncing my two Delta 1010s at high sample rates using the word clock inputs.

The Delta 1010 uses a 74HC4046 phase-locked loop (PLL) to lock onto the word
clock input signal. This is used in a feedback loop with a /256 counter to
produce a frequency that's multiplied by 256x at the output of the PLL
oscillator. With a 48kHz input this gives a PLL frequency of 12.288MHz.

According to the 74HC4046 data sheet, the maximum frequency it can
work at is 13MHz. In other words, even a 48kHz clock is close to the
specified limit, so forget about higher frequencies. (I didn't discover
this until after I'd built a 96kHz word clock :-(. )

The S/PDIF receiver OTOH uses its own internal PLL which works with 96kHz
sample rate. However,I couldn't sync reliably using the S/PDIF in/outs with
one card as master and the other as slave. At 96kHz jackd would die at random
times with a floating point exception, so often it was unusable.
At 48kHz this would still happen, but not often (every couple of hours).
I'm guessing that this is due to a phase difference between master and
slave clocks.

My conclusion is that the only way to sync these cards reliably
at all frequencies is to clock them both from an external S/PDIF device,
and to make sure both cards are receiving the clock signal directly from the
master device (ie. not going through the S/PDIF circuitry of the first card on
the way to the second card).

John


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Re: Multi Delta 1010 sync

[Doug McLain]

The only similarity between the 1010 and the 1010lt is the ice1712 chip 
itself.  The 1010LT doesnt use the 74HC4046, nor does it use the 
8404/8413 combo for spdif.  Until tonight, thats about as far as I would 
have been able to go with this conversation, but I finally hit paydirt 
with the spdif problems on the 1010lt. I posted a patch to bug 1806 
thats fixes spdif functionality, so that we 1010lt users can finally run 
2 cards together.  Now we can get some real world reports on 1010lt's 
running in tandem.  If the 96Khz issue exists for the 1010lt as well, it 
wont be a concern for me at all, since I consider anything over 48Khz a 
waste of space.  I did some testing tonight, and things are looking great!

John Rigg wrote:
> After some reverse engineering I've found out why I was having trouble
> syncing my two Delta 1010s at high sample rates using the word clock inputs.
> 
> The Delta 1010 uses a 74HC4046 phase-locked loop (PLL) to lock onto the word
> clock input signal. This is used in a feedback loop with a /256 counter to
> produce a frequency that's multiplied by 256x at the output of the PLL
> oscillator. With a 48kHz input this gives a PLL frequency of 12.288MHz.
> 
> According to the 74HC4046 data sheet, the maximum frequency it can
> work at is 13MHz. In other words, even a 48kHz clock is close to the
> specified limit, so forget about higher frequencies. (I didn't discover
> this until after I'd built a 96kHz word clock :-(. )
> 
> The S/PDIF receiver OTOH uses its own internal PLL which works with 96kHz
> sample rate. However,I couldn't sync reliably using the S/PDIF in/outs with
> one card as master and the other as slave. At 96kHz jackd would die at random
> times with a floating point exception, so often it was unusable.
> At 48kHz this would still happen, but not often (every couple of hours).
> I'm guessing that this is due to a phase difference between master and
> slave clocks.
> 
> My conclusion is that the only way to sync these cards reliably
> at all frequencies is to clock them both from an external S/PDIF device,
> and to make sure both cards are receiving the clock signal directly from the
> master device (ie. not going through the S/PDIF circuitry of the first card on
> the way to the second card).
> 
> John


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Re: Multi Delta 1010 sync

[John Rigg]

On Sun, Feb 05, 2006 at 04:15:25PM +0000, John Rigg wrote:
> The S/PDIF receiver OTOH uses its own internal PLL which works with 96kHz
> sample rate. However,I couldn't sync reliably using the S/PDIF in/outs with
> one card as master and the other as slave. At 96kHz jackd would die at random
> times with a floating point exception, so often it was unusable.
> At 48kHz this would still happen, but not often (every couple of hours).
> I'm guessing that this is due to a phase difference between master and
> slave clocks.

An update: the floating point exception was a divide-by-zero error
in jackd that only occurred sporadically.
The Delta 1010s sync perfectly well via the S/PDIF in/outs with one card
as master and the other as slave.

To summarize:
Word clock inputs work at 48kHz but not higher due to a hardware
limitation.
S/PDIF inputs can be used to sync up to 96kHz.

John


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Re: Multi Delta 1010 sync

[Doug McLain]

Yesterday I set the master 1010LT to 96000 Internal, and the slave card 
to SPDIF In (with an rca cable connecting SPDIF Out to SPDIF In), ran 
jack at 96Khz, and fired up xmms and ran an mp3 in repeat mode for the 
last 24 hours, with its outputs connected to all 16 outputs, and all 16 
inputs connected to my mixer, with no xruns.

Doug

John Rigg wrote:
> After some reverse engineering I've found out why I was having trouble
> syncing my two Delta 1010s at high sample rates using the word clock inputs.
> 
> The Delta 1010 uses a 74HC4046 phase-locked loop (PLL) to lock onto the word
> clock input signal. This is used in a feedback loop with a /256 counter to
> produce a frequency that's multiplied by 256x at the output of the PLL
> oscillator. With a 48kHz input this gives a PLL frequency of 12.288MHz.
> 
> According to the 74HC4046 data sheet, the maximum frequency it can
> work at is 13MHz. In other words, even a 48kHz clock is close to the
> specified limit, so forget about higher frequencies. (I didn't discover
> this until after I'd built a 96kHz word clock :-(. )
> 
> The S/PDIF receiver OTOH uses its own internal PLL which works with 96kHz
> sample rate. However,I couldn't sync reliably using the S/PDIF in/outs with
> one card as master and the other as slave. At 96kHz jackd would die at random
> times with a floating point exception, so often it was unusable.
> At 48kHz this would still happen, but not often (every couple of hours).
> I'm guessing that this is due to a phase difference between master and
> slave clocks.
> 
> My conclusion is that the only way to sync these cards reliably
> at all frequencies is to clock them both from an external S/PDIF device,
> and to make sure both cards are receiving the clock signal directly from the
> master device (ie. not going through the S/PDIF circuitry of the first card on
> the way to the second card).
> 
> John


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