Re: [RFC 6/7] ASoC: hda: Add support for SSP register settings

[Vinod Koul <vinod.koul@intel.com>]

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On Fri, Apr 24, 2015 at 06:55:32PM +0100, Mark Brown wrote:
> On Sun, Apr 19, 2015 at 02:27:32AM +0530, Vinod Koul wrote:
> 
> > +	req_bclk = fs * slots * s_fmt;
> 
> We have a helper for this.
will use
> 
> > +	dummy = 0;
> > +	/* Find the lowest bit clock possible for particular configuration */
> > +	do {
> > +		req_bclk = ((s_fmt * fs * slots) + (fs * dummy));
> > +		mod = HDA_SSP_MAX_FREQ_192 % req_bclk;
> > +		divisor = HDA_SSP_MAX_FREQ_192 / req_bclk;
> > +		if (!mod) {
> > +			found = 1;
> > +			break;
> > +		}
> > +		/* Dont add odd number of dummy bits, since I2S requires
> > +		 * dummy bit after each slot/channel
> > +		 */
> 
> It does?
For us unfortuntely yes. We send 24 bit audio to codec and clock divider
doesn't give us 48clocks per frame, so we have to add dummy clocks in each
slot and send 25 clocks per slot

> > +		dummy += 2;
> > +		if (dummy > (HDA_SSPSP2_FEP_MASK >> HDA_SSPSP2_FEP_SHIFT)) {
> > +			dev_err(ctx->dev, "Dummy bit greater than what SSP can support\n");
> > +			return -EINVAL;
> > +		}
> > +
> > +	} while (divisor > 0);
> 
> Aside from the limits this all looks like it could be generic?
sure will try to do that.

Thanks
-- 
~Vinod

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