From: Zidan Wang <zidan.wang@freescale.com>
To: ckeepax@opensource.wolfsonmicro.com
Cc: tiwai@suse.de, alsa-devel@alsa-project.org, broonie@kernel.org,
patches@opensource.wolfsonmicro.com
Subject: Re: [PATCH v3] ASoC: wm8960: update pll and clock setting function
Date: Tue, 4 Aug 2015 09:28:46 +0800 [thread overview]
Message-ID: <20150804012844.GA21306@shlinux2> (raw)
In-Reply-To: <ac311441efbc167953de3ab8706217c3c669f88d.1436776563.git.zidan.wang@freescale.com>
On Mon, Jul 13, 2015 at 04:41:00PM +0800, Zidan Wang wrote:
> Add sysclk auto mode. When it's sysclk auto mode, if the MCLK is
> available for clock configure, using MCLK to provide sysclk directly,
> otherwise, search a available pll out frequcncy and set pll.
>
> Configure clock in hw_params may cause problems when using bypass style
> paths without hw_params in machine driver getting called. So add configure
> clock to set_bias_level.
>
> Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
Hi ckeepax,
Is this patch ok for wm8960 codec driver?
Best Regards,
Zidan
next prev parent reply other threads:[~2015-08-04 2:39 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-13 8:41 [PATCH v3] ASoC: wm8960: update pll and clock setting function Zidan Wang
2015-08-04 1:28 ` Zidan Wang [this message]
2015-08-06 8:12 ` Charles Keepax
2015-08-10 8:32 ` Charles Keepax
2015-08-10 8:08 ` Zidan Wang
2015-08-10 13:47 ` Charles Keepax
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