* [PATCH] ASoC: wm8962: Wait for updated value of WM8962_CLOCKING1 register
@ 2022-11-07 6:38 Chancel Liu
2022-11-07 10:10 ` Charles Keepax
0 siblings, 1 reply; 2+ messages in thread
From: Chancel Liu @ 2022-11-07 6:38 UTC (permalink / raw)
To: lgirdwood, broonie, perex, tiwai, ckeepax, luca.ceresoli, ojeda,
cmo, u.kleine-koenig, xiaolei.wang, steve, chi.minghao, patches,
alsa-devel, linux-kernel
Cc: shengjiu.wang, Chancel Liu
DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
correct frequency of LRCLK and BCLK. Sometimes the read-only value
can't be updated timely after enabling SYSCLK. This results in wrong
calculation values. Delay is introduced here to wait for newest value
from register. The time of the delay should be at least 500~1000us
according to test.
Signed-off-by: Chancel Liu <chancel.liu@nxp.com>
---
sound/soc/codecs/wm8962.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index b4b4355c6728..563843565f68 100644
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -2503,6 +2503,14 @@ static void wm8962_configure_bclk(struct snd_soc_component *component)
snd_soc_component_update_bits(component, WM8962_CLOCKING2,
WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
+ /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
+ * correct frequency of LRCLK and BCLK. Sometimes the read-only value
+ * can't be updated timely after enabling SYSCLK. This results in wrong
+ * calculation values. Delay is introduced here to wait for newest
+ * value from register. The time of the delay should be at least
+ * 500~1000us according to test.
+ */
+ msleep(1);
dspclk = snd_soc_component_read(component, WM8962_CLOCKING1);
if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] ASoC: wm8962: Wait for updated value of WM8962_CLOCKING1 register
2022-11-07 6:38 [PATCH] ASoC: wm8962: Wait for updated value of WM8962_CLOCKING1 register Chancel Liu
@ 2022-11-07 10:10 ` Charles Keepax
0 siblings, 0 replies; 2+ messages in thread
From: Charles Keepax @ 2022-11-07 10:10 UTC (permalink / raw)
To: Chancel Liu
Cc: alsa-devel, xiaolei.wang, cmo, patches, shengjiu.wang, tiwai,
chi.minghao, lgirdwood, broonie, u.kleine-koenig, ojeda, steve,
luca.ceresoli, linux-kernel
On Mon, Nov 07, 2022 at 02:38:18PM +0800, Chancel Liu wrote:
> DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
> correct frequency of LRCLK and BCLK. Sometimes the read-only value
> can't be updated timely after enabling SYSCLK. This results in wrong
> calculation values. Delay is introduced here to wait for newest value
> from register. The time of the delay should be at least 500~1000us
> according to test.
>
> Signed-off-by: Chancel Liu <chancel.liu@nxp.com>
> ---
> sound/soc/codecs/wm8962.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
> index b4b4355c6728..563843565f68 100644
> --- a/sound/soc/codecs/wm8962.c
> +++ b/sound/soc/codecs/wm8962.c
> @@ -2503,6 +2503,14 @@ static void wm8962_configure_bclk(struct snd_soc_component *component)
> snd_soc_component_update_bits(component, WM8962_CLOCKING2,
> WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
>
> + /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
> + * correct frequency of LRCLK and BCLK. Sometimes the read-only value
> + * can't be updated timely after enabling SYSCLK. This results in wrong
> + * calculation values. Delay is introduced here to wait for newest
> + * value from register. The time of the delay should be at least
> + * 500~1000us according to test.
> + */
> + msleep(1);
This looks reasonable but for a 1ms delay we should really be
using usleep_range rather than msleep.
Thanks,
Charles
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