From: Xuebing Wang <xbing6@gmail.com>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: alsa-devel@alsa-project.org,
niranjan Patil <Niranjan.Patil@infocus.com>,
fabio Estevam <festevam@gmail.com>,
richard Jiang <Richard.Jiang@infocus.com>
Subject: Re: Freescale iMX6SL SSI (I2S master mode) Rising edge vs Falling edge
Date: Thu, 28 May 2015 15:15:22 +0800 [thread overview]
Message-ID: <5566C08A.6060804@gmail.com> (raw)
In-Reply-To: <20150528070943.GA3532@Asurada>
On 05/28/2015 03:09 PM, Nicolin Chen wrote:
> On Thu, May 28, 2015 at 03:02:31PM +0800, Xuebing Wang wrote:
>
>> According to iMX6SL reference manual, 'TSCKP = 1' means "Data clocked out on
>> *falling* edge of bit clock." (for I2S master mode), rather than "Data on
>> rising edge of bclk in the comments". This means this comment in the source
>> code is *partially* WRONG, am I correct?
> As you can see, it says "clock out on falling edge" which means
> for the receiver is still latching the data at the rising edge.
>
Nicolin,
Thank you very much. Got you now.
> Nicolin
>
--
-- Xuebing
prev parent reply other threads:[~2015-05-28 7:15 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-28 7:02 Freescale iMX6SL SSI (I2S master mode) Rising edge vs Falling edge Xuebing Wang
2015-05-28 7:09 ` Nicolin Chen
2015-05-28 7:15 ` Xuebing Wang [this message]
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