* Freescale iMX6SL SSI (I2S master mode) Rising edge vs Falling edge
@ 2015-05-28 7:02 Xuebing Wang
2015-05-28 7:09 ` Nicolin Chen
0 siblings, 1 reply; 3+ messages in thread
From: Xuebing Wang @ 2015-05-28 7:02 UTC (permalink / raw)
To: Nicolin Chen, alsa-devel; +Cc: niranjan Patil, fabio Estevam, richard Jiang
Nicolin and alsa-devel community:
Source code in fsl_ssi.c shows below in function fsl_ssi_set_dai_fmt():
-----------
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
... ...
/* Data on rising edge of bclk, frame low, 1clk before data */
strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP
| CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
break;
-----------
According to iMX6SL reference manual, 'TSCKP = 1' means "Data clocked
out on *falling* edge of bit clock." (for I2S master mode), rather than
"Data on rising edge of bclk in the comments". This means this comment
in the source code is *partially* WRONG, am I correct?
However, RSCKP is = 1 (for receiving), it means "Data latched on rising
edge of bit clock", which is correct.
Also, I am not sure why there is inconsistency in iMX6SL reference
manual (48.9 SSI Memory Map/Register Definition), that TSCKP = 1 (for
transmitting) is FALLING_EDGE, but RSCKP = 1 (for receiving) is RISING_EDGE.
Note: SSI (I2S master mode) works perfect on my hardware, I did not
observe anything wrong.
Thanks.
--
Xuebing
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Freescale iMX6SL SSI (I2S master mode) Rising edge vs Falling edge
2015-05-28 7:02 Freescale iMX6SL SSI (I2S master mode) Rising edge vs Falling edge Xuebing Wang
@ 2015-05-28 7:09 ` Nicolin Chen
2015-05-28 7:15 ` Xuebing Wang
0 siblings, 1 reply; 3+ messages in thread
From: Nicolin Chen @ 2015-05-28 7:09 UTC (permalink / raw)
To: Xuebing Wang; +Cc: alsa-devel, niranjan Patil, fabio Estevam, richard Jiang
On Thu, May 28, 2015 at 03:02:31PM +0800, Xuebing Wang wrote:
> According to iMX6SL reference manual, 'TSCKP = 1' means "Data clocked out on
> *falling* edge of bit clock." (for I2S master mode), rather than "Data on
> rising edge of bclk in the comments". This means this comment in the source
> code is *partially* WRONG, am I correct?
As you can see, it says "clock out on falling edge" which means
for the receiver is still latching the data at the rising edge.
Nicolin
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Freescale iMX6SL SSI (I2S master mode) Rising edge vs Falling edge
2015-05-28 7:09 ` Nicolin Chen
@ 2015-05-28 7:15 ` Xuebing Wang
0 siblings, 0 replies; 3+ messages in thread
From: Xuebing Wang @ 2015-05-28 7:15 UTC (permalink / raw)
To: Nicolin Chen; +Cc: alsa-devel, niranjan Patil, fabio Estevam, richard Jiang
On 05/28/2015 03:09 PM, Nicolin Chen wrote:
> On Thu, May 28, 2015 at 03:02:31PM +0800, Xuebing Wang wrote:
>
>> According to iMX6SL reference manual, 'TSCKP = 1' means "Data clocked out on
>> *falling* edge of bit clock." (for I2S master mode), rather than "Data on
>> rising edge of bclk in the comments". This means this comment in the source
>> code is *partially* WRONG, am I correct?
> As you can see, it says "clock out on falling edge" which means
> for the receiver is still latching the data at the rising edge.
>
Nicolin,
Thank you very much. Got you now.
> Nicolin
>
--
-- Xuebing
^ permalink raw reply [flat|nested] 3+ messages in thread
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