Alsa-Devel Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Cezary Rojewski <cezary.rojewski@intel.com>
To: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>,
	<alsa-devel@alsa-project.org>
Cc: upstream@semihalf.com, harshapriya.n@intel.com, rad@semihalf.com,
	tiwai@suse.com, pierre-louis.bossart@linux.intel.com,
	hdegoede@redhat.com, broonie@kernel.org,
	amadeuszx.slawinski@linux.intel.com, cujomalainey@chromium.org,
	lma@semihalf.com
Subject: Re: [PATCH v3 10/17] ASoC: Intel: avs: Add basefw runtime-parameter requests
Date: Fri, 4 Mar 2022 18:37:53 +0100	[thread overview]
Message-ID: <b6cfd47b-1ff7-a012-f663-b7bb649be2a5@intel.com> (raw)
In-Reply-To: <2bc36351e4c14bd4b3d55f26eec2cda1b77e7728.camel@linux.intel.com>

On 2022-03-04 5:31 PM, Ranjani Sridharan wrote:
> On Fri, 2022-03-04 at 15:57 +0100, Cezary Rojewski wrote:

...

>> +int avs_ipc_get_fw_config(struct avs_dev *adev, struct avs_fw_cfg
>> *cfg)
>> +{
>> +	struct avs_tlv *tlv;
>> +	size_t payload_size;
>> +	size_t offset = 0;
>> +	u8 *payload;
>> +	int ret;
>> +
>> +	ret = avs_ipc_get_large_config(adev, AVS_BASEFW_MOD_ID,
>> AVS_BASEFW_INST_ID,
>> +				       AVS_BASEFW_FIRMWARE_CONFIG,
>> NULL, 0,
>> +				       &payload, &payload_size);
>> +	if (ret)
>> +		return ret;
>> +
>> +	while (offset < payload_size) {
>> +		tlv = (struct avs_tlv *)(payload + offset);
>> +
>> +		switch (tlv->type) {
>> +		case AVS_FW_CFG_FW_VERSION:
>> +			memcpy(&cfg->fw_version, tlv->value,
>> +				sizeof(cfg->fw_version));
>> +			break;
>> +
>> +		case AVS_FW_CFG_MEMORY_RECLAIMED:
>> +			cfg->memory_reclaimed = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_SLOW_CLOCK_FREQ_HZ:
>> +			cfg->slow_clock_freq_hz = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_FAST_CLOCK_FREQ_HZ:
>> +			cfg->fast_clock_freq_hz = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_ALH_SUPPORT_LEVEL:
>> +			cfg->alh_support = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_IPC_DL_MAILBOX_BYTES:
>> +			cfg->ipc_dl_mailbox_bytes = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_IPC_UL_MAILBOX_BYTES:
>> +			cfg->ipc_ul_mailbox_bytes = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_TRACE_LOG_BYTES:
>> +			cfg->trace_log_bytes = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_MAX_PPL_COUNT:
>> +			cfg->max_ppl_count = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_MAX_ASTATE_COUNT:
>> +			cfg->max_astate_count = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_MAX_MODULE_PIN_COUNT:
>> +			cfg->max_module_pin_count = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_MODULES_COUNT:
>> +			cfg->modules_count = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_MAX_MOD_INST_COUNT:
>> +			cfg->max_mod_inst_count = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT:
>> +			cfg->max_ll_tasks_per_pri_count = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_LL_PRI_COUNT:
>> +			cfg->ll_pri_count = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_MAX_DP_TASKS_COUNT:
>> +			cfg->max_dp_tasks_count = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_MAX_LIBS_COUNT:
>> +			cfg->max_libs_count = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_XTAL_FREQ_HZ:
>> +			cfg->xtal_freq_hz = *tlv->value;
>> +			break;
>> +
>> +		case AVS_FW_CFG_POWER_GATING_POLICY:
>> +			cfg->power_gating_policy = *tlv->value;
>> +			break;
>> +
>> +		/* Known but not useful to us. */
>> +		case AVS_FW_CFG_DMA_BUFFER_CONFIG:
>> +		case AVS_FW_CFG_SCHEDULER_CONFIG:
>> +		case AVS_FW_CFG_CLOCKS_CONFIG:
>> +			break;
>> +
>> +		default:
>> +			dev_info(adev->dev, "Unrecognized fw param:
>> %d\n",
>> +				 tlv->type);
>> +			break;
>> +		}
>> +
>> +		offset += sizeof(*tlv) + tlv->length;
>> +	}
>> +
>> +	kfree(payload);
> I think it would be easier to understand this kfree if payload was also
> allocated in this function in stead of inside the get_large_config().


That's a good thinking. There was an internal conversation regarding 
this back in time when we have been implementing getters for the first 
time. There are no clear victors, there are drawbacks - as you do not 
know the size upfront, caller has to guess and then reallocate the 
buffer accordingly to retrieved payload size from the firmware. So, even 
if you allocate buffer here, chances are, it's not the same buffer when 
the avs_ipc_get_large_config() returns to the caller.

We have decided to reduce the code size by letting the single, common 
handler do the allocation and leave the other responsibilities to the 
caller.


Regards,
Czarek

  reply	other threads:[~2022-03-04 17:39 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-04 14:57 [PATCH v3 00/17] ASoC: Intel: AVS - Audio DSP for cAVS Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 01/17] ALSA: hda: Add helper macros for DSP capable devices Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 02/17] ASoC: Export DAI register and widget ctor and dctor functions Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 03/17] ASoC: Intel: Introduce AVS driver Cezary Rojewski
2022-03-04 15:51   ` Ranjani Sridharan
2022-03-04 16:43     ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 04/17] ASoC: Intel: avs: Inter process communication Cezary Rojewski
2022-03-04 16:09   ` Ranjani Sridharan
2022-03-04 17:11     ` Cezary Rojewski
2022-03-07 16:15       ` Ranjani Sridharan
2022-03-07 16:23         ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 05/17] ASoC: Intel: avs: Add code loading requests Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 06/17] ASoC: Intel: avs: Add pipeline management requests Cezary Rojewski
2022-03-04 16:13   ` Ranjani Sridharan
2022-03-04 17:15     ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 07/17] ASoC: Intel: avs: Add module " Cezary Rojewski
2022-03-04 16:21   ` Ranjani Sridharan
2022-03-04 17:21     ` Cezary Rojewski
2022-03-07 16:39       ` Ranjani Sridharan
2022-03-07 16:58         ` Cezary Rojewski
2022-03-07 17:05           ` Ranjani Sridharan
2022-03-07 17:27             ` Cezary Rojewski
2022-03-07 17:47               ` Pierre-Louis Bossart
2022-03-04 14:57 ` [PATCH v3 08/17] ASoC: Intel: avs: Add power " Cezary Rojewski
2022-03-04 16:24   ` Ranjani Sridharan
2022-03-04 17:30     ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 09/17] ASoC: Intel: avs: Add ROM requests Cezary Rojewski
2022-03-04 16:26   ` Ranjani Sridharan
2022-03-04 17:33     ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 10/17] ASoC: Intel: avs: Add basefw runtime-parameter requests Cezary Rojewski
2022-03-04 16:31   ` Ranjani Sridharan
2022-03-04 17:37     ` Cezary Rojewski [this message]
2022-03-07 16:41       ` Ranjani Sridharan
2022-03-07 17:02         ` Cezary Rojewski
2022-03-07 17:06           ` Ranjani Sridharan
2022-03-07 17:28             ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 11/17] ASoC: Intel: avs: Firmware resources management utilities Cezary Rojewski
2022-03-04 16:41   ` Ranjani Sridharan
2022-03-04 18:02     ` Cezary Rojewski
2022-03-07 16:46       ` Ranjani Sridharan
2022-03-07 17:13         ` Cezary Rojewski
2022-03-07 17:30           ` Ranjani Sridharan
2022-03-08 16:57             ` Cezary Rojewski
2022-03-08 17:22               ` Ranjani Sridharan
2022-03-08 18:07                 ` Cezary Rojewski
2022-03-08 18:26                   ` Ranjani Sridharan
2022-03-08 18:31                     ` Cezary Rojewski
2022-03-08 19:42                       ` Pierre-Louis Bossart
2022-03-09 17:23                         ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 12/17] ASoC: Intel: avs: Declare module configuration types Cezary Rojewski
2022-03-04 16:43   ` Ranjani Sridharan
2022-03-04 18:10     ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 13/17] ASoC: Intel: avs: Dynamic firmware resources management Cezary Rojewski
2022-03-04 16:47   ` Ranjani Sridharan
2022-03-04 18:15     ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 14/17] ASoC: Intel: avs: General code loading flow Cezary Rojewski
2022-03-04 16:54   ` Ranjani Sridharan
2022-03-04 18:29     ` Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 15/17] ASoC: Intel: avs: Implement CLDMA transfer Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 16/17] ASoC: Intel: avs: Code loading over CLDMA Cezary Rojewski
2022-03-04 14:57 ` [PATCH v3 17/17] ASoC: Intel: avs: Code loading over HDA Cezary Rojewski
2022-03-04 16:59   ` Ranjani Sridharan
2022-03-04 18:44     ` Cezary Rojewski
2022-03-04 18:56       ` Pierre-Louis Bossart
2022-03-07 14:31         ` Cezary Rojewski

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=b6cfd47b-1ff7-a012-f663-b7bb649be2a5@intel.com \
    --to=cezary.rojewski@intel.com \
    --cc=alsa-devel@alsa-project.org \
    --cc=amadeuszx.slawinski@linux.intel.com \
    --cc=broonie@kernel.org \
    --cc=cujomalainey@chromium.org \
    --cc=harshapriya.n@intel.com \
    --cc=hdegoede@redhat.com \
    --cc=lma@semihalf.com \
    --cc=pierre-louis.bossart@linux.intel.com \
    --cc=rad@semihalf.com \
    --cc=ranjani.sridharan@linux.intel.com \
    --cc=tiwai@suse.com \
    --cc=upstream@semihalf.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox