From: Jack Yu <jack.yu@realtek.com>
To: "broonie@kernel.org" <broonie@kernel.org>,
"lgirdwood@gmail.com" <lgirdwood@gmail.com>
Cc: "Oder Chiou" <oder_chiou@realtek.com>,
"Jack Yu" <jack.yu@realtek.com>,
"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
"lars@metafoo.de" <lars@metafoo.de>,
"kent_chen@realtek.com [陳建宏]" <kent_chen@realtek.com>,
陳昶志 <kenny_chen@realtek.com>,
"Derek [方德義]" <derek.fang@realtek.com>,
"Shuming [范書銘]" <shumingf@realtek.com>,
"Flove(HsinFu)" <flove@realtek.com>
Subject: [PATCH] ASoC: rt1015: modify calibration sequence for better performance
Date: Tue, 22 Dec 2020 03:15:24 +0000 [thread overview]
Message-ID: <ec66399502514edbb1de3cf9bff08b1d@realtek.com> (raw)
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New calibration sequence to fix power issue in idle state.
Signed-off-by: Jack Yu <jack.yu@realtek.com>
---
sound/soc/codecs/rt1015.c | 40 ++++++++++-----------------------------
1 file changed, 10 insertions(+), 30 deletions(-)
diff --git a/sound/soc/codecs/rt1015.c b/sound/soc/codecs/rt1015.c
index 32e6bcf763d1..5fdf7bbfd375 100644
--- a/sound/soc/codecs/rt1015.c
+++ b/sound/soc/codecs/rt1015.c
@@ -497,40 +497,20 @@ static void rt1015_calibrate(struct rt1015_priv *rt1015)
snd_soc_dapm_mutex_lock(&component->dapm);
regcache_cache_bypass(regmap, true);
- regmap_write(regmap, RT1015_PWR9, 0xAA60);
- regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0089);
- regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x008A);
- regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x008C);
- regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x008D);
- regmap_write(regmap, RT1015_PWR4, 0x80B2);
- regmap_write(regmap, RT1015_CLASSD_SEQ, 0x5797);
- regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2100);
- regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0100);
- regmap_write(regmap, RT1015_PWR5, 0x2175);
- regmap_write(regmap, RT1015_MIXER1, 0x005D);
- regmap_write(regmap, RT1015_CLSD_INTERNAL1, 0x00A1);
- regmap_write(regmap, RT1015_CLSD_INTERNAL2, 0x12F7);
- regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x1205);
- msleep(200);
- regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2000);
- regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0180);
- regmap_write(regmap, RT1015_CLSD_INTERNAL1, 0x00A1);
- regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x0A05);
- msleep(200);
+ regmap_write(regmap, RT1015_CLK_DET, 0x0000);
regmap_write(regmap, RT1015_PWR4, 0x00B2);
+ regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0009);
+ msleep(100);
+ regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000A);
+ msleep(100);
+ regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000C);
+ msleep(100);
regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2028);
regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140);
- regmap_write(regmap, RT1015_PWR5, 0x0175);
- regmap_write(regmap, RT1015_CLSD_INTERNAL1, 0x1721);
- regmap_write(regmap, RT1015_CLASSD_SEQ, 0x570E);
- regmap_write(regmap, RT1015_MIXER1, 0x203D);
- regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5A01);
- regmap_write(regmap, RT1015_CLSD_INTERNAL2, 0x12FF);
- regmap_write(regmap, RT1015_GAT_BOOST, 0x0eFE);
- regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x008E);
- regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0088);
+ regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000D);
+ msleep(300);
+ regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0008);
regmap_write(regmap, RT1015_SYS_RST1, 0x05F5);
- regmap_write(regmap, RT1015_SYS_RST2, 0x0b9a);
regcache_cache_bypass(regmap, false);
regcache_mark_dirty(regmap);
--
2.29.0
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next reply other threads:[~2020-12-22 3:16 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-22 3:15 Jack Yu [this message]
2021-01-01 13:50 ` [PATCH] ASoC: rt1015: modify calibration sequence for better performance Jack Yu
2021-01-04 11:49 ` Mark Brown
-- strict thread matches above, loose matches on Subject: below --
2021-01-04 3:01 jack.yu
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