Re: [PATCH v3 2/7] ALSA: hda - add new HDA registers

[Takashi Iwai <tiwai@suse.de>]

At Wed, 29 Apr 2015 01:24:25 +0530,
Vinod Koul wrote:
> 
> From: Jeeja KP <jeeja.kp@intel.com>
> 
> This patch adds new registers as per HD audio Spec like capability registers
> for processing pipe, software position based FIFO, Multiple Links and Global
> Time Synchronization.
> 
> Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
> ---
>  include/sound/hda_register.h |   87 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 87 insertions(+)
> 
> diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h
> index 4f6d3fce6ee6..dced67f5c35f 100644
> --- a/include/sound/hda_register.h
> +++ b/include/sound/hda_register.h
> @@ -28,6 +28,10 @@
>  #define AZX_REG_STATESTS		0x0e
>  #define AZX_REG_GSTS			0x10
>  #define   AZX_GSTS_FSTS		(1 << 1)   /* flush status */
> +#define AZX_REG_GCAP2			0x12
> +#define AZX_REG_LLCH			0x14
> +#define AZX_REG_OUTSTRMPAY		0x18
> +#define AZX_REG_INSTRMPAY		0x1A
>  #define AZX_REG_INTCTL			0x20
>  #define AZX_REG_INTSTS			0x24
>  #define AZX_REG_WALLCLK			0x30	/* 24Mhz source */
> @@ -81,6 +85,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
>  #define AZX_REG_SD_FIFOW		0x0e
>  #define AZX_REG_SD_FIFOSIZE		0x10
>  #define AZX_REG_SD_FORMAT		0x12
> +#define AZX_REG_SD_FIFOL		0x14
>  #define AZX_REG_SD_BDLPL		0x18
>  #define AZX_REG_SD_BDLPU		0x1c
>  
> @@ -134,6 +139,88 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
>  #define AZX_MAX_CORB_ENTRIES	256
>  #define AZX_MAX_RIRB_ENTRIES	256
>  
> +#define AZX_REG_CAP_HDR		0x0
> +#define CAP_HDR_VER_OFF		28
> +#define CAP_HDR_VER_MASK	(0xF << CAP_HDR_VER_OFF)
> +#define CAP_HDR_ID_OFF		16
> +#define CAP_HDR_ID_MASK		(0xFFF << CAP_HDR_ID_OFF)
> +#define CAP_HDR_NXT_PTR_MASK	0xFFFF

In general, it's safer to a unique prefix like AZX_ (although we
didn't apply the rule strictly to some defines).


Takashi