Re: Non-coherent memory mapped devices

Re: Non-coherent memory mapped devices

[Jaroslav Kysela]

On Tue, 18 Mar 2003, Laurent Canet wrote:

> Hi,
> 
> On the HPPA architecture, devices (including sound ones) are memory-mapped. 
> On particular machines, memory access to devices are not consistent,
> i.e. data wrote to memory could be cached by the CPU, thus inacessible
> to the device. 
> To avoid inconsistency in memory writes, there are arch-dep functions 
> that flush write buffers. They are defined in <asm/io.h> as
> dma_cache_inv(start,size), dma_cache_wback and dma_cache_wback_inv; and should be called after all DMA memory writes.
> 
> On architectures that don't have such cache issues (most ia32, ia64, alpha, mips, ppc, ...), they are just NOP.
> 
> I grepped out the whole alsa source tree and didn't find any occurences
> of dma_cache_* functions. Who should implement these calls, low level drivers or PCM middle layer ? 

This code belongs to both midlevel and lowlevel drivers. See 
snd_pcm_lib_*_transfer() routines in pcm_lib.c.

Also, we'll probably need to define these functions in our library, 
because we can access directly to DMA ring buffers there, too.

						Jaroslav

-----
Jaroslav Kysela <perex@suse.cz>
Linux Kernel Sound Maintainer
ALSA Project, SuSE Labs



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Non-coherent memory mapped devices

[Laurent Canet]

Hi,

On the HPPA architecture, devices (including sound ones) are memory-mapped. 
On particular machines, memory access to devices are not consistent,
i.e. data wrote to memory could be cached by the CPU, thus inacessible
to the device. 
To avoid inconsistency in memory writes, there are arch-dep functions 
that flush write buffers. They are defined in <asm/io.h> as
dma_cache_inv(start,size), dma_cache_wback and dma_cache_wback_inv; and should be called after all DMA memory writes.

On architectures that don't have such cache issues (most ia32, ia64, alpha, mips, ppc, ...), they are just NOP.

I grepped out the whole alsa source tree and didn't find any occurences
of dma_cache_* functions. Who should implement these calls, low level drivers or PCM middle layer ? 

Thanks for your answer


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Re: Non-coherent memory mapped devices

[Takashi Iwai]

Hi,

At Tue, 18 Mar 2003 20:48:08 +0100,
Laurent Canet wrote:
> 
> Hi,
> 
> On the HPPA architecture, devices (including sound ones) are memory-mapped. 
> On particular machines, memory access to devices are not consistent,
> i.e. data wrote to memory could be cached by the CPU, thus inacessible
> to the device. 

doesn't ioremap_nocache() suffice for such a case?


Takashi


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