[PATCH v2] drm/amdgpu: do not use amdgpu_bo_gpu_offset_no_check individually

[PATCH v2] drm/amdgpu: do not use amdgpu_bo_gpu_offset_no_check individually

[Saleemkhan Jamadar]

This should not be used indiviually, use amdgpu_bo_gpu_offset
with bo reserved.

v2 - pin bo so that offset returned won't change after unresv/unlock (Christian)

Signed-off-by: Saleemkhan Jamadar <saleemkhan083@gmail.com>
Suggested-by: Christian König <christian.koenig@amd.com>
---
 .../gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/mes_userqueue.c    | 21 ++++++++++++++++++-
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
index 3040437d99c2..bc7858567321 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
@@ -129,7 +129,7 @@ uint32_t amdgpu_doorbell_index_on_bar(struct amdgpu_device *adev,
 {
 	int db_bo_offset;
 
-	db_bo_offset = amdgpu_bo_gpu_offset_no_check(db_bo);
+	db_bo_offset = amdgpu_bo_gpu_offset(db_bo);
 
 	/* doorbell index is 32 bit but doorbell's size can be 32 bit
 	 * or 64 bit, so *db_size(in byte)/4 for alignment.
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
index b1ee9473d628..f0ad3edbdef2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
@@ -93,8 +93,27 @@ mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
 		return ret;
 	}
 
-	queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset_no_check(wptr_obj->obj);
+	ret = amdgpu_bo_reserve(wptr_obj->obj, true);
+	if (ret) {
+		DRM_ERROR("Failed to reserve wptr bo\n");
+		return ret;
+	}
+
+	ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT);
+	if (ret) {
+		drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n");
+		goto unresv_bo;
+	}
+
+	queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj);
+	amdgpu_bo_unreserve(wptr_obj->obj);
+
 	return 0;
+
+unresv_bo:
+	amdgpu_bo_unreserve(wptr_obj->obj);
+	return ret;
+
 }
 
 static int convert_to_mes_priority(int priority)
-- 
2.43.0

Re: [PATCH v2] drm/amdgpu: do not use amdgpu_bo_gpu_offset_no_check individually

[Christian König]

On 11/8/25 20:02, Saleemkhan Jamadar wrote:
> This should not be used indiviually, use amdgpu_bo_gpu_offset
> with bo reserved.
> 
> v2 - pin bo so that offset returned won't change after unresv/unlock (Christian)

Each pin must have a matching unpin or otherwise you run into warnings on destruction.

Regards,
Christian.

> 
> Signed-off-by: Saleemkhan Jamadar <saleemkhan083@gmail.com>
> Suggested-by: Christian König <christian.koenig@amd.com>
> ---
>  .../gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c  |  2 +-
>  drivers/gpu/drm/amd/amdgpu/mes_userqueue.c    | 21 ++++++++++++++++++-
>  2 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
> index 3040437d99c2..bc7858567321 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
> @@ -129,7 +129,7 @@ uint32_t amdgpu_doorbell_index_on_bar(struct amdgpu_device *adev,
>  {
>  	int db_bo_offset;
>  
> -	db_bo_offset = amdgpu_bo_gpu_offset_no_check(db_bo);
> +	db_bo_offset = amdgpu_bo_gpu_offset(db_bo);
>  
>  	/* doorbell index is 32 bit but doorbell's size can be 32 bit
>  	 * or 64 bit, so *db_size(in byte)/4 for alignment.
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
> index b1ee9473d628..f0ad3edbdef2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
> @@ -93,8 +93,27 @@ mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
>  		return ret;
>  	}
>  
> -	queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset_no_check(wptr_obj->obj);
> +	ret = amdgpu_bo_reserve(wptr_obj->obj, true);
> +	if (ret) {
> +		DRM_ERROR("Failed to reserve wptr bo\n");
> +		return ret;
> +	}
> +
> +	ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT);
> +	if (ret) {
> +		drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n");
> +		goto unresv_bo;
> +	}
> +
> +	queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj);
> +	amdgpu_bo_unreserve(wptr_obj->obj);
> +
>  	return 0;
> +
> +unresv_bo:
> +	amdgpu_bo_unreserve(wptr_obj->obj);
> +	return ret;
> +
>  }
>  
>  static int convert_to_mes_priority(int priority)