[PATCH 07/14] drm/amd/ras: add check safety watermark func for pmfw eeprom

[PATCH 07/14] drm/amd/ras: add check safety watermark func for pmfw eeprom

[Gangliang Xie]

add check safety watermark func for pmfw eeprom

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c  |  3 ++
 drivers/gpu/drm/amd/ras/rascore/ras_core.c    |  3 ++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 30 +++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  1 +
 4 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
index 923bddd0af3a..36c264ab889c 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
@@ -570,6 +570,9 @@ bool amdgpu_ras_mgr_check_eeprom_safety_watermark(struct amdgpu_device *adev)
 	if (!amdgpu_ras_mgr_is_ready(adev))
 		return false;
 
+	if (ras_fw_eeprom_supported(ras_mgr->ras_core))
+		return ras_fw_eeprom_check_safety_watermark(ras_mgr->ras_core);
+
 	return ras_eeprom_check_safety_watermark(ras_mgr->ras_core);
 }
 
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
index 91c883f16ae5..1f2ce3749d43 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
@@ -561,6 +561,9 @@ bool ras_core_is_ready(struct ras_core_context *ras_core)
 
 bool ras_core_check_safety_watermark(struct ras_core_context *ras_core)
 {
+	if (ras_fw_eeprom_supported(ras_core))
+		return ras_fw_eeprom_check_safety_watermark(ras_core);
+
 	return ras_eeprom_check_safety_watermark(ras_core);
 }
 
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index 31bb423b4eb7..66934f61bcf9 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -190,3 +190,33 @@ int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core)
 
 	return res;
 }
+
+bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core)
+{
+	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+	bool ret = false;
+	int bad_page_count;
+
+	if (!control->record_threshold_config)
+		return false;
+
+	bad_page_count = ras_umc_get_badpage_count(ras_core);
+
+	if (bad_page_count > control->record_threshold_count)
+		RAS_DEV_WARN(ras_core->dev, "RAS records:%d exceed threshold:%d",
+			bad_page_count, control->record_threshold_count);
+
+	if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) ||
+		(control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) {
+		RAS_DEV_WARN(ras_core->dev,
+			"Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n");
+		ret = false;
+	} else {
+		ras_core->is_rma = true;
+		RAS_DEV_WARN(ras_core->dev,
+			"Please consider adjusting the customized threshold.\n");
+		ret = true;
+	}
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index 8ff2d554c3ba..09632f1121f0 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -67,5 +67,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
 int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
 				   uint32_t *result);
 int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
+bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core);
 
 #endif
-- 
2.34.1

[PATCH 01/14] drm/amd/pm: add pmfw eeprom messages into uniras interface

[Gangliang Xie]

add pmfw eeprom related messages into smu_v13_0_6_ras_send_msg

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 57f4069bc827..0fcd6a1c0e92 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -3499,12 +3499,22 @@ static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_ty
 {
 	int ret;
 
+	if (amdgpu_sriov_vf(adev))
+		return -EOPNOTSUPP;
+
 	switch (msg) {
 	case SMU_MSG_QueryValidMcaCount:
 	case SMU_MSG_QueryValidMcaCeCount:
 	case SMU_MSG_McaBankDumpDW:
 	case SMU_MSG_McaBankCeDumpDW:
 	case SMU_MSG_ClearMcaOnRead:
+	case SMU_MSG_GetRASTableVersion:
+	case SMU_MSG_GetBadPageCount:
+	case SMU_MSG_GetBadPageMcaAddr:
+	case SMU_MSG_SetTimestamp:
+	case SMU_MSG_GetTimestamp:
+	case SMU_MSG_GetBadPageIpid:
+	case SMU_MSG_EraseRasTable:
 		ret = smu_cmn_send_smc_msg_with_param(smu, msg, param, read_arg);
 		break;
 	default:
-- 
2.34.1

[PATCH 02/14] drm/amd/pm: add feature query interface for uniras

[Gangliang Xie]

add amdgpu_smu_ras_feature_is_enabled to query one feature
is supported or not

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 12 ++++++++++++
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  2 ++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index a15670e561b5..142f8351a7cd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -624,6 +624,18 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms
 	return ret;
 }
 
+int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev,
+						enum smu_feature_mask mask)
+{
+	struct smu_context *smu = adev->powerplay.pp_handle;
+	int ret = 0;
+
+	if (smu->ppt_funcs && smu->ppt_funcs->feature_is_enabled)
+		ret = smu->ppt_funcs->feature_is_enabled(smu, mask);
+
+	return ret;
+}
+
 static int smu_sys_get_pp_table(void *handle,
 				char **table)
 {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 4d5dfd936ee2..ba8c85f7c90c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1843,6 +1843,8 @@ void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev);
 
 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg,
 			    uint32_t param, uint32_t *readarg);
+int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev,
+						enum smu_feature_mask mask);
 #endif
 
 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id);
-- 
2.34.1

[PATCH 03/14] drm/amd/ras: add pmfw eeprom smu interfaces

[Gangliang Xie]

add smu interfaces and its data structures for
pmfw eeprom in uniras

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 .../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c    | 46 +++++++++++++++++++
 drivers/gpu/drm/amd/ras/rascore/ras.h         | 18 ++++++++
 2 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
index 79a51b1603ac..03922aa03417 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
@@ -28,6 +28,16 @@
 #define RAS_MP1_MSG_QueryValidMcaCeCount  0x3A
 #define RAS_MP1_MSG_McaBankCeDumpDW       0x3B
 
+static enum smu_message_type pmfw_eeprom_msgs[] = {
+	SMU_MSG_GetRASTableVersion,
+	SMU_MSG_GetBadPageCount,
+	SMU_MSG_SetTimestamp,
+	SMU_MSG_GetTimestamp,
+	SMU_MSG_GetBadPageIpid,
+	SMU_MSG_EraseRasTable,
+	SMU_MSG_GetBadPageMcaAddr,
+};
+
 static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core,
 					  u32 msg, u32 *count)
 {
@@ -87,8 +97,44 @@ static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core,
 	return ret;
 }
 
+static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core,
+				enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
+	int ret = 0;
+
+	if (down_read_trylock(&adev->reset_domain->sem)) {
+		ret = amdgpu_smu_ras_send_msg(adev,
+			pmfw_eeprom_msgs[index], param, read_arg);
+		up_read(&adev->reset_domain->sem);
+	} else {
+		ret = -RAS_CORE_GPU_IN_MODE1_RESET;
+	}
+
+	return ret;
+}
+
+static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core,
+					     uint64_t *enabled_mask)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
+	int ret = 0;
+
+	if (down_read_trylock(&adev->reset_domain->sem)) {
+		if (amdgpu_smu_ras_feature_is_enabled(adev, SMU_FEATURE_HROM_EN_BIT))
+			*enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM;
+		up_read(&adev->reset_domain->sem);
+	} else {
+		ret = -RAS_CORE_GPU_IN_MODE1_RESET;
+	}
+
+	return ret;
+}
+
 const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = {
 	.mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count,
 	.mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank,
+	.mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg,
+	.mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask,
 };
 
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
index 3396b2e0949d..2db838c444f1 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
@@ -49,6 +49,10 @@
 #define GPU_RESET_CAUSE_FATAL   (RAS_CORE_RESET_GPU | 0x0002)
 #define GPU_RESET_CAUSE_RMA     (RAS_CORE_RESET_GPU | 0x0004)
 
+enum ras_core_fw_feature_flags {
+	RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0),
+};
+
 enum ras_block_id {
 	RAS_BLOCK_ID__UMC = 0,
 	RAS_BLOCK_ID__SDMA,
@@ -127,6 +131,16 @@ enum ras_gpu_status {
 	RAS_GPU_STATUS__IS_VF = 0x8,
 };
 
+enum ras_fw_eeprom_cmd {
+	RAS_SMU_GetRASTableVersion = 0,
+	RAS_SMU_GetBadPageCount,
+	RAS_SMU_SetTimestamp,
+	RAS_SMU_GetTimestamp,
+	RAS_SMU_GetBadPageIpid,
+	RAS_SMU_EraseRasTable,
+	RAS_SMU_GetBadPageMcaAddr,
+};
+
 struct ras_core_context;
 struct ras_bank_ecc;
 struct ras_umc;
@@ -141,6 +155,10 @@ struct ras_mp1_sys_func {
 			u32 msg, u32 *count);
 	int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core,
 			u32 msg, u32 idx, u32 reg_idx, u64 *val);
+	int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core,
+			enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg);
+	int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core,
+			uint64_t *enabled_mask);
 };
 
 struct ras_eeprom_sys_func {
-- 
2.34.1

[PATCH 04/14] drm/amd/ras: add uniras smu feature flag init func

[Gangliang Xie]

add flag to indicate if pmfw eeprom is supported or
not, and initialize it

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 drivers/gpu/drm/amd/ras/rascore/Makefile      |  3 +-
 drivers/gpu/drm/amd/ras/rascore/ras.h         |  3 ++
 drivers/gpu/drm/amd/ras/rascore/ras_core.c    |  2 +
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 38 +++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   | 29 ++++++++++++++
 5 files changed, 74 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
 create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h

diff --git a/drivers/gpu/drm/amd/ras/rascore/Makefile b/drivers/gpu/drm/amd/ras/rascore/Makefile
index e826a1f86424..06b265ec1cde 100644
--- a/drivers/gpu/drm/amd/ras/rascore/Makefile
+++ b/drivers/gpu/drm/amd/ras/rascore/Makefile
@@ -36,7 +36,8 @@ RAS_CORE_FILES = ras_core.o \
 			ras_log_ring.o \
 			ras_cper.o \
 			ras_psp.o \
-			ras_psp_v13_0.o
+			ras_psp_v13_0.o \
+			ras_eeprom_fw.o
 
 
 RAS_CORE = $(addprefix $(AMD_GPU_RAS_PATH)/rascore/,$(RAS_CORE_FILES))
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
index 2db838c444f1..6e223eff522c 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
@@ -36,6 +36,7 @@
 #include "ras_mp1.h"
 #include "ras_psp.h"
 #include "ras_log_ring.h"
+#include "ras_eeprom_fw.h"
 
 #define RAS_HW_ERR		"[Hardware Error]: "
 
@@ -335,6 +336,8 @@ struct ras_core_context {
 	spinlock_t seqno_lock;
 
 	bool ras_core_enabled;
+
+	u64 ras_fw_features;
 };
 
 struct ras_core_context *ras_core_create(struct ras_core_config *init_config);
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
index 01122b55c98a..91c883f16ae5 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
@@ -382,6 +382,8 @@ int ras_core_hw_init(struct ras_core_context *ras_core)
 	if (ret)
 		goto init_err5;
 
+	ras_fw_init_feature_flags(ras_core);
+
 	ret = ras_eeprom_hw_init(ras_core);
 	if (ret)
 		goto init_err6;
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
new file mode 100644
index 000000000000..e94c368c3159
--- /dev/null
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "ras.h"
+
+void ras_fw_init_feature_flags(struct ras_core_context *ras_core)
+{
+	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
+	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
+	uint64_t flags = 0ULL;
+
+	if (!sys_func || !sys_func->mp1_get_ras_enabled_mask)
+		return;
+
+	if (!sys_func->mp1_get_ras_enabled_mask(ras_core, &flags))
+		ras_core->ras_fw_features = flags;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
new file mode 100644
index 000000000000..b41665467368
--- /dev/null
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __RAS_EEPROM_FW_H__
+#define __RAS_EEPROM_FW_H__
+
+void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
+
+#endif
-- 
2.34.1

[PATCH 05/14] drm/amd/ras: add wrapper funcs for pmfw eeprom

[Gangliang Xie]

add wrapper funcs for pmfw eeprom interface to make them
easier to be called

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 125 ++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  16 +++
 2 files changed, 141 insertions(+)

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index e94c368c3159..f880fc49477d 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -36,3 +36,128 @@ void ras_fw_init_feature_flags(struct ras_core_context *ras_core)
 	if (!sys_func->mp1_get_ras_enabled_mask(ras_core, &flags))
 		ras_core->ras_fw_features = flags;
 }
+
+bool ras_fw_eeprom_supported(struct ras_core_context *ras_core)
+{
+	return !!(ras_core->ras_fw_features & RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM);
+}
+
+int ras_fw_get_table_version(struct ras_core_context *ras_core,
+				     uint32_t *table_version)
+{
+	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
+	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
+
+	return sys_func->mp1_send_eeprom_msg(ras_core,
+				RAS_SMU_GetRASTableVersion, 0, table_version);
+}
+
+int ras_fw_get_badpage_count(struct ras_core_context *ras_core,
+				     uint32_t *count, uint32_t timeout)
+{
+	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
+	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
+	uint64_t end, now;
+	int ret = 0;
+
+	now = (uint64_t)ktime_to_ms(ktime_get());
+	end = now + timeout;
+
+	do {
+		ret = sys_func->mp1_send_eeprom_msg(ras_core,
+			RAS_SMU_GetBadPageCount, 0, count);
+		/* eeprom is not ready */
+		if (ret != -EBUSY)
+			return ret;
+
+		mdelay(10);
+		now = (uint64_t)ktime_to_ms(ktime_get());
+	} while (now < end);
+
+	RAS_DEV_ERR(ras_core->dev,
+			"smu get bad page count timeout!\n");
+	return ret;
+}
+
+int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core,
+					uint16_t index, uint64_t *mca_addr)
+{
+	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
+	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
+	uint32_t temp_arg, temp_addr_lo, temp_addr_high;
+	int ret;
+
+	temp_arg = index | (1 << 16);
+	ret = sys_func->mp1_send_eeprom_msg(ras_core,
+			RAS_SMU_GetBadPageMcaAddr, temp_arg, &temp_addr_lo);
+	if (ret)
+		return ret;
+
+	temp_arg = index | (2 << 16);
+	ret = sys_func->mp1_send_eeprom_msg(ras_core,
+			RAS_SMU_GetBadPageMcaAddr, temp_arg, &temp_addr_high);
+
+	if (!ret)
+		*mca_addr = (uint64_t)temp_addr_high << 32 | temp_addr_lo;
+
+	return ret;
+}
+
+int ras_fw_set_timestamp(struct ras_core_context *ras_core,
+				 uint64_t timestamp)
+{
+	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
+	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
+
+	return sys_func->mp1_send_eeprom_msg(ras_core,
+			RAS_SMU_SetTimestamp, (uint32_t)timestamp, 0);
+}
+
+int ras_fw_get_timestamp(struct ras_core_context *ras_core,
+				 uint16_t index, uint64_t *timestamp)
+{
+	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
+	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
+	uint32_t temp = 0;
+	int ret;
+
+	ret = sys_func->mp1_send_eeprom_msg(ras_core,
+			RAS_SMU_GetTimestamp, index, &temp);
+	if (!ret)
+		*timestamp = temp;
+
+	return ret;
+}
+
+int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
+				    uint16_t index, uint64_t *ipid)
+{
+	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
+	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
+	uint32_t temp_arg, temp_ipid_lo, temp_ipid_high;
+	int ret;
+
+	temp_arg = index | (1 << 16);
+	ret = sys_func->mp1_send_eeprom_msg(ras_core,
+			RAS_SMU_GetBadPageIpid, temp_arg, &temp_ipid_lo);
+	if (ret)
+		return ret;
+
+	temp_arg = index | (2 << 16);
+	ret = sys_func->mp1_send_eeprom_msg(ras_core,
+			RAS_SMU_GetBadPageIpid, temp_arg, &temp_ipid_high);
+	if (!ret)
+		*ipid = (uint64_t)temp_ipid_high << 32 | temp_ipid_lo;
+
+	return ret;
+}
+
+int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
+				   uint32_t *result)
+{
+	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
+	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
+
+	return sys_func->mp1_send_eeprom_msg(ras_core,
+			RAS_SMU_EraseRasTable, 0, result);
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index b41665467368..46f45e82a3f3 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -24,6 +24,22 @@
 #ifndef __RAS_EEPROM_FW_H__
 #define __RAS_EEPROM_FW_H__
 
+
 void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
+bool ras_fw_eeprom_supported(struct ras_core_context *ras_core);
+int ras_fw_get_table_version(struct ras_core_context *ras_core,
+				     uint32_t *table_version);
+int ras_fw_get_badpage_count(struct ras_core_context *ras_core,
+				     uint32_t *count, uint32_t timeout);
+int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core,
+					uint16_t index, uint64_t *mca_addr);
+int ras_fw_set_timestamp(struct ras_core_context *ras_core,
+				 uint64_t timestamp);
+int ras_fw_get_timestamp(struct ras_core_context *ras_core,
+				 uint16_t index, uint64_t *timestamp);
+int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
+				    uint16_t index, uint64_t *ipid);
+int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
+				   uint32_t *result);
 
 #endif
-- 
2.34.1

[PATCH 06/14] drm/amd/ras: Add table reset func for pmfw eeprom

[Gangliang Xie]

add table reset func for pmfw eeprom, add smu eeprom control
structure

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 drivers/gpu/drm/amd/ras/rascore/ras.h         |  1 +
 drivers/gpu/drm/amd/ras/rascore/ras_cmd.c     |  9 ++++--
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 29 +++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   | 26 +++++++++++++++++
 4 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
index 6e223eff522c..ae10d853c565 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
@@ -313,6 +313,7 @@ struct ras_core_context {
 
 	bool ras_eeprom_supported;
 	struct ras_eeprom_control ras_eeprom;
+	struct ras_fw_eeprom_control ras_fw_eeprom;
 
 	struct ras_psp ras_psp;
 	struct ras_umc ras_umc;
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
index 94e6d7420d94..4f89810d85a1 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
@@ -146,8 +146,13 @@ static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core,
 	if (cmd->input_size != sizeof(struct ras_cmd_dev_handle))
 		return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
 
-	if (ras_eeprom_reset_table(ras_core))
-		return RAS_CMD__ERROR_GENERIC;
+	if (ras_fw_eeprom_supported(ras_core)) {
+		if (ras_fw_eeprom_reset_table(ras_core))
+			return RAS_CMD__ERROR_GENERIC;
+	} else {
+		if (ras_eeprom_reset_table(ras_core))
+			return RAS_CMD__ERROR_GENERIC;
+	}
 
 	if (ras_umc_clean_badpage_data(ras_core))
 		return RAS_CMD__ERROR_GENERIC;
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index f880fc49477d..ae63e7394829 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -161,3 +161,32 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
 	return sys_func->mp1_send_eeprom_msg(ras_core,
 			RAS_SMU_EraseRasTable, 0, result);
 }
+
+int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core)
+{
+	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+	u32 erase_res = 0;
+	int res;
+
+	mutex_lock(&control->ras_tbl_mutex);
+
+	res = ras_fw_erase_ras_table(ras_core, &erase_res);
+	if (res || erase_res) {
+		RAS_DEV_WARN(ras_core->dev, "RAS EEPROM reset failed, res:%d result:%d",
+									res, erase_res);
+		if (!res)
+			res = -EIO;
+	}
+
+	control->ras_num_recs = 0;
+	control->bad_channel_bitmap = 0;
+	ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM,
+		&control->ras_num_recs);
+	ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP,
+		&control->bad_channel_bitmap);
+	control->update_channel_flag = false;
+
+	mutex_unlock(&control->ras_tbl_mutex);
+
+	return res;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index 46f45e82a3f3..a1003db3c33b 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -24,6 +24,31 @@
 #ifndef __RAS_EEPROM_FW_H__
 #define __RAS_EEPROM_FW_H__
 
+struct ras_fw_eeprom_control {
+	uint32_t version;
+	/* record threshold */
+	int record_threshold_config;
+	uint32_t record_threshold_count;
+	bool update_channel_flag;
+
+	/* Number of records in the table.
+	 */
+	u32 ras_num_recs;
+
+	/* Maximum possible number of records
+	 * we could store, i.e. the maximum capacity
+	 * of the table.
+	 */
+	u32 ras_max_record_count;
+
+	/* Protect table access via this mutex.
+	 */
+	struct mutex ras_tbl_mutex;
+
+	/* Record channel info which occurred bad pages
+	 */
+	u32 bad_channel_bitmap;
+};
 
 void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
 bool ras_fw_eeprom_supported(struct ras_core_context *ras_core);
@@ -41,5 +66,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
 				    uint16_t index, uint64_t *ipid);
 int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
 				   uint32_t *result);
+int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
 
 #endif
-- 
2.34.1

[PATCH 07/14] drm/amd/ras: add check safety watermark func for pmfw eeprom

[Gangliang Xie]

add check safety watermark func for pmfw eeprom

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c  |  3 ++
 drivers/gpu/drm/amd/ras/rascore/ras_core.c    |  3 ++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 30 +++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  1 +
 4 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
index 923bddd0af3a..36c264ab889c 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
@@ -570,6 +570,9 @@ bool amdgpu_ras_mgr_check_eeprom_safety_watermark(struct amdgpu_device *adev)
 	if (!amdgpu_ras_mgr_is_ready(adev))
 		return false;
 
+	if (ras_fw_eeprom_supported(ras_mgr->ras_core))
+		return ras_fw_eeprom_check_safety_watermark(ras_mgr->ras_core);
+
 	return ras_eeprom_check_safety_watermark(ras_mgr->ras_core);
 }
 
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
index 91c883f16ae5..1f2ce3749d43 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
@@ -561,6 +561,9 @@ bool ras_core_is_ready(struct ras_core_context *ras_core)
 
 bool ras_core_check_safety_watermark(struct ras_core_context *ras_core)
 {
+	if (ras_fw_eeprom_supported(ras_core))
+		return ras_fw_eeprom_check_safety_watermark(ras_core);
+
 	return ras_eeprom_check_safety_watermark(ras_core);
 }
 
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index ae63e7394829..34a4161251b3 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -190,3 +190,33 @@ int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core)
 
 	return res;
 }
+
+bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core)
+{
+	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+	bool ret = false;
+	int bad_page_count;
+
+	if (!control->record_threshold_config)
+		return false;
+
+	bad_page_count = ras_umc_get_badpage_count(ras_core);
+
+	if (bad_page_count > control->record_threshold_count)
+		RAS_DEV_WARN(ras_core->dev, "RAS records:%d exceed threshold:%d",
+			bad_page_count, control->record_threshold_count);
+
+	if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) ||
+		(control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) {
+		RAS_DEV_WARN(ras_core->dev,
+			"Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n");
+		ret = false;
+	} else {
+		ras_core->is_rma = true;
+		RAS_DEV_WARN(ras_core->dev,
+			"Please consider adjusting the customized threshold.\n");
+		ret = true;
+	}
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index a1003db3c33b..b0d3eade4377 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -67,5 +67,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
 int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
 				   uint32_t *result);
 int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
+bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core);
 
 #endif
-- 
2.34.1

[PATCH 08/14] drm/amd/ras: add append func for pmfw eeprom

[Gangliang Xie]

add append func for pmfw eeprom

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 39 +++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  2 +
 drivers/gpu/drm/amd/ras/rascore/ras_umc.c     | 10 +++--
 3 files changed, 48 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index 34a4161251b3..580dd7b09d00 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -220,3 +220,42 @@ bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core)
 
 	return ret;
 }
+
+int ras_fw_eeprom_append(struct ras_core_context *ras_core,
+			   struct eeprom_umc_record *record, const u32 num)
+{
+	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+	int threshold_config = control->record_threshold_config;
+	int i, bad_page_count;
+
+	mutex_lock(&control->ras_tbl_mutex);
+
+	for (i = 0; i < num; i++) {
+		/* update bad channel bitmap */
+		if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
+			!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
+			control->bad_channel_bitmap |= 1 << record[i].mem_channel;
+			control->update_channel_flag = true;
+		}
+	}
+	control->ras_num_recs += num;
+
+	bad_page_count = ras_umc_get_badpage_count(ras_core);
+
+	if (threshold_config != 0 &&
+		bad_page_count > control->record_threshold_count) {
+		RAS_DEV_WARN(ras_core->dev,
+			"Saved bad pages %d reaches threshold value %d\n",
+			bad_page_count, control->record_threshold_count);
+
+		if ((threshold_config != WARN_NONSTOP_OVER_THRESHOLD) &&
+			(threshold_config != NONSTOP_OVER_THRESHOLD))
+			ras_core->is_rma = true;
+
+		/* ignore the -ENOTSUPP return value */
+		ras_core_event_notify(ras_core, RAS_EVENT_ID__DEVICE_RMA, NULL);
+	}
+
+	mutex_unlock(&control->ras_tbl_mutex);
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index b0d3eade4377..b94d3c9703e3 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -68,5 +68,7 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
 				   uint32_t *result);
 int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
 bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core);
+int ras_fw_eeprom_append(struct ras_core_context *ras_core,
+			   struct eeprom_umc_record *record, const u32 num);
 
 #endif
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
index 4dae64c424a2..fd427fd59ecf 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
@@ -479,9 +479,13 @@ static int ras_umc_save_bad_pages(struct ras_core_context *ras_core)
 	save_count = data->count - eeprom_record_num;
 	/* only new entries are saved */
 	if (save_count > 0) {
-		if (ras_eeprom_append(ras_core,
-					   &data->bps[eeprom_record_num],
-					   save_count)) {
+		if (ras_fw_eeprom_supported(ras_core))
+			ret = ras_fw_eeprom_append(ras_core, &data->bps[eeprom_record_num],
+					save_count);
+		else
+			ret = ras_eeprom_append(ras_core, &data->bps[eeprom_record_num],
+					save_count);
+		if (ret) {
 			RAS_DEV_ERR(ras_core->dev, "Failed to save EEPROM table data!");
 			ret = -EIO;
 			goto exit;
-- 
2.34.1

[PATCH 09/14] drm/amd/ras: make MCA IPID parse global

[Gangliang Xie]

From: Tao Zhou <tao.zhou1@amd.com>

add a new IPID parse interface for umc, so we can
implement it for each ASIC, and so we can call it
in other blocks

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 drivers/gpu/drm/amd/ras/rascore/ras_umc.h       |  2 ++
 drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c | 14 ++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h
index 7d9e779d8c4c..795fa351258e 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h
@@ -108,6 +108,8 @@ struct ras_umc_ip_func {
 			struct umc_bank_addr bank_addr, uint64_t *soc_pa);
 	int (*soc_pa_to_bank)(struct ras_core_context *ras_core,
 			uint64_t soc_pa, struct umc_bank_addr *bank_addr);
+	void (*mca_ipid_parse)(struct ras_core_context *ras_core, uint64_t ipid,
+			uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid);
 };
 
 struct eeprom_store_record {
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
index 5d9a11c17a86..e2792b239bea 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
@@ -501,11 +501,25 @@ static int umc_12_0_bank_to_soc_pa(struct ras_core_context *ras_core,
 	return 0;
 }
 
+static void umc_v12_0_mca_ipid_parse(struct ras_core_context *ras_core, uint64_t ipid,
+		uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid)
+{
+	if (did)
+		*did = ACA_IPID_2_DIE_ID(ipid);
+	if (ch)
+		*ch = ACA_IPID_2_UMC_CH(ipid);
+	if (umc_inst)
+		*umc_inst = ACA_IPID_2_UMC_INST(ipid);
+	if (sid)
+		*sid = ACA_IPID_2_SOCKET_ID(ipid);
+}
+
 const struct ras_umc_ip_func ras_umc_func_v12_0 = {
 	.bank_to_eeprom_record = umc_v12_0_bank_to_eeprom_record,
 	.eeprom_record_to_nps_record = umc_v12_0_eeprom_record_to_nps_record,
 	.eeprom_record_to_nps_pages = umc_v12_0_eeprom_record_to_nps_pages,
 	.bank_to_soc_pa = umc_12_0_bank_to_soc_pa,
 	.soc_pa_to_bank = umc_12_0_soc_pa_to_bank,
+	.mca_ipid_parse = umc_v12_0_mca_ipid_parse,
 };
 
-- 
2.34.1

[PATCH 10/14] drm/amd/ras: add read func for pmfw eeprom

[Gangliang Xie]

add read func for pmfw eeprom, and adapt address converting
for bad pages loaded from pmfw eeprom

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 drivers/gpu/drm/amd/ras/rascore/ras.h         |  1 +
 drivers/gpu/drm/amd/ras/rascore/ras_core.c    |  5 +-
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 70 +++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  5 ++
 drivers/gpu/drm/amd/ras/rascore/ras_umc.c     | 27 +++++--
 .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.c   |  2 +-
 6 files changed, 101 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
index ae10d853c565..05c7923e8f0f 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
@@ -241,6 +241,7 @@ struct ras_bank_ecc {
 	uint64_t status;
 	uint64_t ipid;
 	uint64_t addr;
+	uint64_t ts;
 };
 
 struct ras_bank_ecc_node {
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
index 1f2ce3749d43..fe188a5304d9 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
@@ -239,7 +239,10 @@ static int ras_core_eeprom_recovery(struct ras_core_context *ras_core)
 	int count;
 	int ret;
 
-	count = ras_eeprom_get_record_count(ras_core);
+	if (ras_fw_eeprom_supported(ras_core))
+		count = ras_fw_eeprom_get_record_count(ras_core);
+	else
+		count = ras_eeprom_get_record_count(ras_core);
 	if (!count)
 		return 0;
 
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index 580dd7b09d00..79494ad16ee5 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -259,3 +259,73 @@ int ras_fw_eeprom_append(struct ras_core_context *ras_core,
 	mutex_unlock(&control->ras_tbl_mutex);
 	return 0;
 }
+
+int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
+			 struct eeprom_umc_record *record_umc,
+			 struct ras_bank_ecc *ras_ecc,
+			 u32 rec_idx, const u32 num)
+{
+	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+	int i, ret, end_idx;
+	u64 mca, ipid, ts;
+
+	if (!ras_core->ras_umc.ip_func ||
+	    !ras_core->ras_umc.ip_func->mca_ipid_parse)
+		return -EOPNOTSUPP;
+
+	mutex_lock(&control->ras_tbl_mutex);
+
+	end_idx = rec_idx + num;
+	for (i = rec_idx; i < end_idx; i++) {
+		ret = ras_fw_get_badpage_mca_addr(ras_core, i, &mca);
+		if (ret)
+			goto out;
+
+		ret = ras_fw_get_badpage_ipid(ras_core, i, &ipid);
+		if (ret)
+			goto out;
+
+		ret = ras_fw_get_timestamp(ras_core, i, &ts);
+		if (ret)
+			goto out;
+
+		if (record_umc) {
+			record_umc[i - rec_idx].address = mca;
+			/* retired_page (pa) is unused now */
+			record_umc[i - rec_idx].retired_row_pfn = 0x1ULL;
+			record_umc[i - rec_idx].ts = ts;
+			record_umc[i - rec_idx].err_type = RAS_EEPROM_ERR_NON_RECOVERABLE;
+
+			ras_core->ras_umc.ip_func->mca_ipid_parse(ras_core, ipid,
+				(uint32_t *)&(record_umc[i - rec_idx].cu),
+				(uint32_t *)&(record_umc[i - rec_idx].mem_channel),
+				(uint32_t *)&(record_umc[i - rec_idx].mcumc_id), NULL);
+
+			/* update bad channel bitmap */
+			if ((record_umc[i - rec_idx].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
+				!(control->bad_channel_bitmap & (1 << record_umc[i - rec_idx].mem_channel))) {
+				control->bad_channel_bitmap |= 1 << record_umc[i - rec_idx].mem_channel;
+				control->update_channel_flag = true;
+			}
+		}
+
+		if (ras_ecc) {
+			ras_ecc[i - rec_idx].addr = mca;
+			ras_ecc[i - rec_idx].ipid = ipid;
+			ras_ecc[i - rec_idx].ts = ts;
+		}
+
+	}
+
+out:
+	mutex_unlock(&control->ras_tbl_mutex);
+	return ret;
+}
+
+uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core)
+{
+	if (!ras_core)
+		return 0;
+
+	return ras_core->ras_fw_eeprom.ras_num_recs;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index b94d3c9703e3..353977a2371e 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -70,5 +70,10 @@ int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
 bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core);
 int ras_fw_eeprom_append(struct ras_core_context *ras_core,
 			   struct eeprom_umc_record *record, const u32 num);
+int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
+			 struct eeprom_umc_record *record_umc,
+			 struct ras_bank_ecc *ras_ecc,
+			 u32 rec_idx, const u32 num);
+uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core);
 
 #endif
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
index fd427fd59ecf..eb5bb6df18f5 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
@@ -436,17 +436,27 @@ int ras_umc_load_bad_pages(struct ras_core_context *ras_core)
 	uint32_t ras_num_recs;
 	int ret;
 
-	ras_num_recs = ras_eeprom_get_record_count(ras_core);
-	/* no bad page record, skip eeprom access */
-	if (!ras_num_recs ||
-	    ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE)
-		return 0;
+	if (ras_fw_eeprom_supported(ras_core)) {
+		ras_num_recs = ras_fw_eeprom_get_record_count(ras_core);
+		/* no bad page record, skip eeprom access */
+		if (!ras_num_recs ||
+		    ras_core->ras_fw_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE)
+			return 0;
+	} else {
+		ras_num_recs = ras_eeprom_get_record_count(ras_core);
+		if (!ras_num_recs ||
+		    ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE)
+			return 0;
+	}
 
 	bps = kcalloc(ras_num_recs, sizeof(*bps), GFP_KERNEL);
 	if (!bps)
 		return -ENOMEM;
 
-	ret = ras_eeprom_read(ras_core, bps, ras_num_recs);
+	if (ras_fw_eeprom_supported(ras_core))
+		ret = ras_fw_eeprom_read_idx(ras_core, bps, 0, 0, ras_num_recs);
+	else
+		ret = ras_eeprom_read(ras_core, bps, ras_num_recs);
 	if (ret) {
 		RAS_DEV_ERR(ras_core->dev, "Failed to load EEPROM table records!");
 	} else {
@@ -474,7 +484,10 @@ static int ras_umc_save_bad_pages(struct ras_core_context *ras_core)
 	if (!data->bps)
 		return 0;
 
-	eeprom_record_num = ras_eeprom_get_record_count(ras_core);
+	if (ras_fw_eeprom_supported(ras_core))
+		eeprom_record_num = ras_fw_eeprom_get_record_count(ras_core);
+	else
+		eeprom_record_num = ras_eeprom_get_record_count(ras_core);
 	mutex_lock(&ras_umc->umc_lock);
 	save_count = data->count - eeprom_record_num;
 	/* only new entries are saved */
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
index e2792b239bea..53dc59e4de0c 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
@@ -413,7 +413,7 @@ static int umc_v12_0_eeprom_record_to_nps_record(struct ras_core_context *ras_co
 	uint64_t pa = 0;
 	int ret = 0;
 
-	if (nps == EEPROM_RECORD_UMC_NPS_MODE(record)) {
+	if (nps == EEPROM_RECORD_UMC_NPS_MODE(record) && !ras_fw_eeprom_supported(ras_core)) {
 		record->cur_nps_retired_row_pfn = EEPROM_RECORD_UMC_ADDR_PFN(record);
 	} else {
 		ret = convert_eeprom_record_to_nps_addr(ras_core,
-- 
2.34.1

[PATCH 11/14] drm/amd/ras: adapt page retirement process for pmfw eeprom

[Gangliang Xie]

read bad page data from pmfw eeprom when retirement
is triggered, use timestamp read from eeprom

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 drivers/gpu/drm/amd/ras/rascore/ras_aca.c     | 31 +++++++++-----
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 40 +++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  2 +
 .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.c   |  3 ++
 4 files changed, 66 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
index e433c70d2989..67a35409ff0e 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c
@@ -234,16 +234,27 @@ static int aca_log_bad_bank(struct ras_core_context *ras_core,
 	    bank_ecc->de_count) {
 		struct ras_bank_ecc  ras_ecc = {0};
 
-		ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core);
-		ras_ecc.addr = bank_ecc->bank_info.addr;
-		ras_ecc.ipid = bank_ecc->bank_info.ipid;
-		ras_ecc.status = bank_ecc->bank_info.status;
-		ras_ecc.seq_no = bank->seq_no;
-
-		if (ras_core_gpu_in_reset(ras_core))
-			ras_umc_log_bad_bank_pending(ras_core, &ras_ecc);
-		else
-			ras_umc_log_bad_bank(ras_core, &ras_ecc);
+		if (ras_fw_eeprom_supported(ras_core)) {
+			ret = ras_fw_eeprom_update_record(ras_core, &ras_ecc);
+			if (!ret) {
+				ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core);
+				ras_ecc.status = bank_ecc->bank_info.status;
+				ras_ecc.seq_no = bank->seq_no;
+			}
+		} else {
+			ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core);
+			ras_ecc.addr = bank_ecc->bank_info.addr;
+			ras_ecc.ipid = bank_ecc->bank_info.ipid;
+			ras_ecc.status = bank_ecc->bank_info.status;
+			ras_ecc.seq_no = bank->seq_no;
+		}
+
+		if (!ret) {
+			if (ras_core_gpu_in_reset(ras_core))
+				ras_umc_log_bad_bank_pending(ras_core, &ras_ecc);
+			else
+				ras_umc_log_bad_bank(ras_core, &ras_ecc);
+		}
 	}
 
 	aca_report_ecc_info(ras_core,
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index 79494ad16ee5..4a1b966d22fa 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -24,6 +24,8 @@
 
 #include "ras.h"
 
+#define RAS_SMU_MESSAGE_TIMEOUT_MS 1000 /* 1s */
+
 void ras_fw_init_feature_flags(struct ras_core_context *ras_core)
 {
 	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
@@ -329,3 +331,41 @@ uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core)
 
 	return ras_core->ras_fw_eeprom.ras_num_recs;
 }
+
+int ras_fw_eeprom_update_record(struct ras_core_context *ras_core,
+				struct ras_bank_ecc *ras_ecc)
+{
+	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+	int ret, retry = 20;
+	u32 recs_num_new = control->ras_num_recs;
+
+	do {
+		/* 1000ms timeout is long enough, smu_get_badpage_count won't
+		 * return -EBUSY before timeout.
+		 */
+		ret = ras_fw_get_badpage_count(ras_core,
+			&recs_num_new, RAS_SMU_MESSAGE_TIMEOUT_MS);
+		if (!ret &&
+		    (recs_num_new == control->ras_num_recs)) {
+			/* record number update in PMFW needs some time,
+			 * smu_get_badpage_count may return immediately without
+			 * count update, sleep for a while and retry again.
+			 */
+			msleep(50);
+			retry--;
+		} else {
+			break;
+		}
+	} while (retry);
+
+	if (ret)
+		return ret;
+
+	if (recs_num_new > control->ras_num_recs)
+		ret = ras_fw_eeprom_read_idx(ras_core, 0,
+					ras_ecc, control->ras_num_recs, 1);
+	else
+		ret = -EINVAL;
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index 353977a2371e..18d6548e2151 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -75,5 +75,7 @@ int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
 			 struct ras_bank_ecc *ras_ecc,
 			 u32 rec_idx, const u32 num);
 uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core);
+int ras_fw_eeprom_update_record(struct ras_core_context *ras_core,
+				struct ras_bank_ecc *ras_ecc);
 
 #endif
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
index 53dc59e4de0c..b809a2f21d73 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
@@ -373,6 +373,9 @@ static int umc_v12_0_bank_to_eeprom_record(struct ras_core_context *ras_core,
 		ACA_ADDR_2_ERR_ADDR(bank->addr), ACA_IPID_2_UMC_INST(bank->ipid),
 		&nps_addr, bank->nps, record);
 
+	if (ras_fw_eeprom_supported(ras_core) && bank->ts)
+		record->ts = bank->ts;
+
 	lookup_bad_pages_in_a_row(ras_core, record,
 		bank->nps, NULL, 0, bank->seq_no, true);
 
-- 
2.34.1

[PATCH 12/14] drm/amd/ras: add initialization func for pmfw eeprom

[Gangliang Xie]

add initialization func for pmfw eeprom

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 drivers/gpu/drm/amd/ras/rascore/ras_core.c    | 15 +++-
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 84 +++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  2 +
 3 files changed, 98 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
index fe188a5304d9..1eba279a020b 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
@@ -387,7 +387,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core)
 
 	ras_fw_init_feature_flags(ras_core);
 
-	ret = ras_eeprom_hw_init(ras_core);
+	if (ras_fw_eeprom_supported(ras_core))
+		ret = ras_fw_eeprom_hw_init(ras_core);
+	else
+		ret = ras_eeprom_hw_init(ras_core);
 	if (ret)
 		goto init_err6;
 
@@ -411,7 +414,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core)
 	return 0;
 
 init_err7:
-	ras_eeprom_hw_fini(ras_core);
+	if (ras_fw_eeprom_supported(ras_core))
+		ras_fw_eeprom_hw_fini(ras_core);
+	else
+		ras_eeprom_hw_fini(ras_core);
 init_err6:
 	ras_gfx_hw_fini(ras_core);
 init_err5:
@@ -432,7 +438,10 @@ int ras_core_hw_fini(struct ras_core_context *ras_core)
 	ras_core->is_initialized = false;
 
 	ras_process_fini(ras_core);
-	ras_eeprom_hw_fini(ras_core);
+	if (ras_fw_eeprom_supported(ras_core))
+		ras_fw_eeprom_hw_fini(ras_core);
+	else
+		ras_eeprom_hw_fini(ras_core);
 	ras_gfx_hw_fini(ras_core);
 	ras_nbio_hw_fini(ras_core);
 	ras_umc_hw_fini(ras_core);
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index 4a1b966d22fa..4362b8a0f3c4 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -369,3 +369,87 @@ int ras_fw_eeprom_update_record(struct ras_core_context *ras_core,
 
 	return ret;
 }
+
+static int __check_ras_fw_table_status(struct ras_core_context *ras_core)
+{
+	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+	uint64_t local_time;
+	int res;
+
+	mutex_init(&control->ras_tbl_mutex);
+
+	res = ras_fw_get_table_version(ras_core, &(control->version));
+	if (res)
+		return res;
+
+	res = ras_fw_get_badpage_count(ras_core, &(control->ras_num_recs), 100);
+	if (res)
+		return res;
+
+	local_time = (uint64_t)ktime_get_real_seconds();
+	res = ras_fw_set_timestamp(ras_core, local_time);
+	if (res)
+		return res;
+
+	control->ras_max_record_count = 4000;
+
+
+	if (control->ras_num_recs > control->ras_max_record_count) {
+		RAS_DEV_ERR(ras_core->dev,
+			"RAS header invalid, records in header: %u max allowed :%u",
+			control->ras_num_recs, control->ras_max_record_count);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core)
+{
+	struct ras_fw_eeprom_control *control;
+	struct ras_eeprom_config *eeprom_cfg;
+	struct ras_mp1 *mp1;
+	const struct ras_mp1_sys_func *sys_func;
+
+	if (!ras_core)
+		return -EINVAL;
+
+	mp1 = &ras_core->ras_mp1;
+	sys_func = mp1->sys_func;
+
+	if (!sys_func || !sys_func->mp1_send_eeprom_msg)
+		return -EINVAL;
+
+	ras_core->is_rma = false;
+
+	control = &ras_core->ras_fw_eeprom;
+
+	memset(control, 0, sizeof(*control));
+
+	eeprom_cfg = &ras_core->config->eeprom_cfg;
+	control->record_threshold_config =
+		eeprom_cfg->eeprom_record_threshold_config;
+
+	control->record_threshold_count = 4000;
+	if (eeprom_cfg->eeprom_record_threshold_count <
+		control->record_threshold_count)
+		control->record_threshold_count =
+			eeprom_cfg->eeprom_record_threshold_count;
+
+	control->update_channel_flag = false;
+
+	return __check_ras_fw_table_status(ras_core);
+}
+
+int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core)
+{
+	struct ras_fw_eeprom_control *control;
+
+	if (!ras_core)
+		return -EINVAL;
+
+	control = &ras_core->ras_fw_eeprom;
+	mutex_destroy(&control->ras_tbl_mutex);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index 18d6548e2151..cb92e6a63cf5 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -77,5 +77,7 @@ int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
 uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core);
 int ras_fw_eeprom_update_record(struct ras_core_context *ras_core,
 				struct ras_bank_ecc *ras_ecc);
+int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core);
+int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core);
 
 #endif
-- 
2.34.1

[PATCH 13/14] drm/amd/ras: add check func for pmfw eeprom

[Gangliang Xie]

add check func for pmfw eeprom

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c  |  3 +-
 drivers/gpu/drm/amd/ras/rascore/ras.h         |  7 +++
 drivers/gpu/drm/amd/ras/rascore/ras_core.c    |  5 +-
 drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h  |  7 ---
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 51 +++++++++++++++++++
 .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  3 ++
 6 files changed, 67 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c
index 45ed8c3b5563..7d728e523604 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c
@@ -137,7 +137,8 @@ static int amdgpu_ras_sys_event_notifier(struct ras_core_context *ras_core,
 		break;
 	case RAS_EVENT_ID__DEVICE_RMA:
 		ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_RMA, NULL, NULL);
-		ret = amdgpu_dpm_send_rma_reason(ras_core->dev);
+		if (!ras_fw_eeprom_supported(ras_core))
+			ret = amdgpu_dpm_send_rma_reason(ras_core->dev);
 		break;
 	case RAS_EVENT_ID__RESET_GPU:
 		ret = amdgpu_ras_mgr_reset_gpu(ras_core->dev, *(uint32_t *)data);
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
index 05c7923e8f0f..c2a56138b2dd 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
@@ -50,6 +50,13 @@
 #define GPU_RESET_CAUSE_FATAL   (RAS_CORE_RESET_GPU | 0x0002)
 #define GPU_RESET_CAUSE_RMA     (RAS_CORE_RESET_GPU | 0x0004)
 
+enum ras_gpu_health_status {
+	RAS_GPU_HEALTH_NONE = 0,
+	RAS_GPU_HEALTH_USABLE = 1,
+	RAS_GPU_RETIRED__ECC_REACH_THRESHOLD = 2,
+	RAS_GPU_IN_BAD_STATUS = 3,
+};
+
 enum ras_core_fw_feature_flags {
 	RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0),
 };
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
index 1eba279a020b..a4e2ad6a159f 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
@@ -401,7 +401,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core)
 		goto init_err6;
 	}
 
-	ret = ras_eeprom_check_storage_status(ras_core);
+	if (ras_fw_eeprom_supported(ras_core))
+		ret = ras_fw_eeprom_check_storage_status(ras_core);
+	else
+		ret = ras_eeprom_check_storage_status(ras_core);
 	if (ret)
 		goto init_err6;
 
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h
index 2abe566c18b6..f2c001ef64e1 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h
@@ -57,13 +57,6 @@ do { \
 	(RECORD)->retired_row_pfn = tmp; \
 } while (0)
 
-enum ras_gpu_health_status {
-	RAS_GPU_HEALTH_NONE = 0,
-	RAS_GPU_HEALTH_USABLE = 1,
-	RAS_GPU_RETIRED__ECC_REACH_THRESHOLD = 2,
-	RAS_GPU_IN_BAD_STATUS = 3,
-};
-
 enum ras_eeprom_err_type {
 	RAS_EEPROM_ERR_NA,
 	RAS_EEPROM_ERR_RECOVERABLE,
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index 4362b8a0f3c4..70bbf1334c4f 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -453,3 +453,54 @@ int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core)
 
 	return 0;
 }
+
+int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core)
+{
+	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+	int bad_page_count;
+
+	bad_page_count = ras_umc_get_badpage_count(ras_core);
+
+	if ((control->record_threshold_count < bad_page_count) &&
+	    (control->record_threshold_config != 0)) {
+		RAS_DEV_ERR(ras_core->dev, "RAS records:%d exceed threshold:%d",
+				bad_page_count, control->record_threshold_count);
+		if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) ||
+			(control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) {
+			RAS_DEV_WARN(ras_core->dev,
+			"Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n");
+		} else {
+			ras_core->is_rma = true;
+			RAS_DEV_ERR(ras_core->dev,
+			"User defined threshold is set, runtime service will be halt when threshold is reached\n");
+		}
+		return 0;
+	}
+
+	RAS_DEV_INFO(ras_core->dev,
+			"Found existing EEPROM table with %d records\n",
+			bad_page_count);
+	/* Warn if we are at 90% of the threshold or above
+	 */
+	if (10 * bad_page_count >= 9 * control->record_threshold_count)
+		RAS_DEV_WARN(ras_core->dev,
+			"RAS records:%u exceeds 90%% of threshold:%d\n",
+			bad_page_count,
+			control->record_threshold_count);
+
+	return 0;
+}
+
+enum ras_gpu_health_status
+	ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core)
+{
+	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
+
+	if (!control->record_threshold_config)
+		return RAS_GPU_HEALTH_NONE;
+
+	if (ras_core->is_rma)
+		return RAS_GPU_RETIRED__ECC_REACH_THRESHOLD;
+
+	return RAS_GPU_HEALTH_USABLE;
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index cb92e6a63cf5..75d8b95c6923 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -79,5 +79,8 @@ int ras_fw_eeprom_update_record(struct ras_core_context *ras_core,
 				struct ras_bank_ecc *ras_ecc);
 int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core);
 int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core);
+int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core);
+enum ras_gpu_health_status
+	ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core);
 
 #endif
-- 
2.34.1

[PATCH 14/14] drm/amd/ras: adapt syc info func for pmfw eeprom

[Gangliang Xie]

adapt sync info func for pmfw eeprom

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 drivers/gpu/drm/amd/ras/rascore/ras_core.c      |  5 ++++-
 drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c | 14 ++++++++++++++
 drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h |  1 +
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
index a4e2ad6a159f..6a39e5499c5d 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
@@ -256,7 +256,10 @@ static int ras_core_eeprom_recovery(struct ras_core_context *ras_core)
 		return ret;
 	}
 
-	ras_eeprom_sync_info(ras_core);
+	if (ras_fw_eeprom_supported(ras_core))
+		ras_fw_eeprom_sync_info(ras_core);
+	else
+		ras_eeprom_sync_info(ras_core);
 
 	return ret;
 }
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
index 70bbf1334c4f..29001e606d1b 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
@@ -504,3 +504,17 @@ enum ras_gpu_health_status
 
 	return RAS_GPU_HEALTH_USABLE;
 }
+
+void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core)
+{
+	struct ras_fw_eeprom_control *control;
+
+	if (!ras_core)
+		return;
+
+	control = &ras_core->ras_fw_eeprom;
+	ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM,
+		&control->ras_num_recs);
+	ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP,
+		&control->bad_channel_bitmap);
+}
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
index 75d8b95c6923..762345be075c 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
@@ -82,5 +82,6 @@ int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core);
 int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core);
 enum ras_gpu_health_status
 	ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core);
+void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core);
 
 #endif
-- 
2.34.1

RE: [PATCH 03/14] drm/amd/ras: add pmfw eeprom smu interfaces

[Wang, Yang(Kevin)]

[AMD Official Use Only - AMD Internal Distribution Only]

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gangliang Xie
Sent: Friday, January 30, 2026 10:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Chai, Thomas <YiPeng.Chai@amd.com>; Wang, Yang(Kevin) <KevinYang.Wang@amd.com>; Xie, Patrick <Gangliang.Xie@amd.com>
Subject: [PATCH 03/14] drm/amd/ras: add pmfw eeprom smu interfaces

add smu interfaces and its data structures for pmfw eeprom in uniras

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 .../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c    | 46 +++++++++++++++++++
 drivers/gpu/drm/amd/ras/rascore/ras.h         | 18 ++++++++
 2 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
index 79a51b1603ac..03922aa03417 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
@@ -28,6 +28,16 @@
 #define RAS_MP1_MSG_QueryValidMcaCeCount  0x3A
 #define RAS_MP1_MSG_McaBankCeDumpDW       0x3B

+static enum smu_message_type pmfw_eeprom_msgs[] = {
+       SMU_MSG_GetRASTableVersion,
+       SMU_MSG_GetBadPageCount,
+       SMU_MSG_SetTimestamp,
+       SMU_MSG_GetTimestamp,
+       SMU_MSG_GetBadPageIpid,
+       SMU_MSG_EraseRasTable,
+       SMU_MSG_GetBadPageMcaAddr,
+};

[kevin]:
It is better add 'const' type for this array, with that fixed the patch 1-3 is
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
+
 static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core,
                                          u32 msg, u32 *count)
 {
@@ -87,8 +97,44 @@ static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core,
        return ret;
 }

+static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core,
+                               enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg) {
+       struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
+       int ret = 0;
+
+       if (down_read_trylock(&adev->reset_domain->sem)) {
+               ret = amdgpu_smu_ras_send_msg(adev,
+                       pmfw_eeprom_msgs[index], param, read_arg);
+               up_read(&adev->reset_domain->sem);
+       } else {
+               ret = -RAS_CORE_GPU_IN_MODE1_RESET;
+       }
+
+       return ret;
+}
+
+static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core,
+                                            uint64_t *enabled_mask)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
+       int ret = 0;
+
+       if (down_read_trylock(&adev->reset_domain->sem)) {
+               if (amdgpu_smu_ras_feature_is_enabled(adev, SMU_FEATURE_HROM_EN_BIT))
+                       *enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM;
+               up_read(&adev->reset_domain->sem);
+       } else {
+               ret = -RAS_CORE_GPU_IN_MODE1_RESET;
+       }
+
+       return ret;
+}
+
 const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = {
        .mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count,
        .mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank,
+       .mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg,
+       .mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask,
 };

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
index 3396b2e0949d..2db838c444f1 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
@@ -49,6 +49,10 @@
 #define GPU_RESET_CAUSE_FATAL   (RAS_CORE_RESET_GPU | 0x0002)
 #define GPU_RESET_CAUSE_RMA     (RAS_CORE_RESET_GPU | 0x0004)

+enum ras_core_fw_feature_flags {
+       RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), };
+
 enum ras_block_id {
        RAS_BLOCK_ID__UMC = 0,
        RAS_BLOCK_ID__SDMA,
@@ -127,6 +131,16 @@ enum ras_gpu_status {
        RAS_GPU_STATUS__IS_VF = 0x8,
 };

+enum ras_fw_eeprom_cmd {
+       RAS_SMU_GetRASTableVersion = 0,
+       RAS_SMU_GetBadPageCount,
+       RAS_SMU_SetTimestamp,
+       RAS_SMU_GetTimestamp,
+       RAS_SMU_GetBadPageIpid,
+       RAS_SMU_EraseRasTable,
+       RAS_SMU_GetBadPageMcaAddr,
+};
+
 struct ras_core_context;
 struct ras_bank_ecc;
 struct ras_umc;
@@ -141,6 +155,10 @@ struct ras_mp1_sys_func {
                        u32 msg, u32 *count);
        int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core,
                        u32 msg, u32 idx, u32 reg_idx, u64 *val);
+       int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core,
+                       enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg);
+       int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core,
+                       uint64_t *enabled_mask);
 };

 struct ras_eeprom_sys_func {
--
2.34.1

RE: [PATCH 03/14] drm/amd/ras: add pmfw eeprom smu interfaces

[Xie, Patrick]

[AMD Official Use Only - AMD Internal Distribution Only]

Thank you, Kevin
Will add const to the array

-----Original Message-----
From: Wang, Yang(Kevin) <KevinYang.Wang@amd.com>
Sent: Friday, January 30, 2026 11:02 AM
To: Xie, Patrick <Gangliang.Xie@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Chai, Thomas <YiPeng.Chai@amd.com>; Xie, Patrick <Gangliang.Xie@amd.com>
Subject: RE: [PATCH 03/14] drm/amd/ras: add pmfw eeprom smu interfaces

[AMD Official Use Only - AMD Internal Distribution Only]

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gangliang Xie
Sent: Friday, January 30, 2026 10:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Chai, Thomas <YiPeng.Chai@amd.com>; Wang, Yang(Kevin) <KevinYang.Wang@amd.com>; Xie, Patrick <Gangliang.Xie@amd.com>
Subject: [PATCH 03/14] drm/amd/ras: add pmfw eeprom smu interfaces

add smu interfaces and its data structures for pmfw eeprom in uniras

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
---
 .../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c    | 46 +++++++++++++++++++
 drivers/gpu/drm/amd/ras/rascore/ras.h         | 18 ++++++++
 2 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
index 79a51b1603ac..03922aa03417 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
@@ -28,6 +28,16 @@
 #define RAS_MP1_MSG_QueryValidMcaCeCount  0x3A
 #define RAS_MP1_MSG_McaBankCeDumpDW       0x3B

+static enum smu_message_type pmfw_eeprom_msgs[] = {
+       SMU_MSG_GetRASTableVersion,
+       SMU_MSG_GetBadPageCount,
+       SMU_MSG_SetTimestamp,
+       SMU_MSG_GetTimestamp,
+       SMU_MSG_GetBadPageIpid,
+       SMU_MSG_EraseRasTable,
+       SMU_MSG_GetBadPageMcaAddr,
+};

[kevin]:
It is better add 'const' type for this array, with that fixed the patch 1-3 is
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
+
 static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core,
                                          u32 msg, u32 *count)  { @@ -87,8 +97,44 @@ static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core,
        return ret;
 }

+static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core,
+                               enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg) {
+       struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
+       int ret = 0;
+
+       if (down_read_trylock(&adev->reset_domain->sem)) {
+               ret = amdgpu_smu_ras_send_msg(adev,
+                       pmfw_eeprom_msgs[index], param, read_arg);
+               up_read(&adev->reset_domain->sem);
+       } else {
+               ret = -RAS_CORE_GPU_IN_MODE1_RESET;
+       }
+
+       return ret;
+}
+
+static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core,
+                                            uint64_t *enabled_mask) {
+       struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
+       int ret = 0;
+
+       if (down_read_trylock(&adev->reset_domain->sem)) {
+               if (amdgpu_smu_ras_feature_is_enabled(adev, SMU_FEATURE_HROM_EN_BIT))
+                       *enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM;
+               up_read(&adev->reset_domain->sem);
+       } else {
+               ret = -RAS_CORE_GPU_IN_MODE1_RESET;
+       }
+
+       return ret;
+}
+
 const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = {
        .mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count,
        .mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank,
+       .mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg,
+       .mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask,
 };

diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
index 3396b2e0949d..2db838c444f1 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
@@ -49,6 +49,10 @@
 #define GPU_RESET_CAUSE_FATAL   (RAS_CORE_RESET_GPU | 0x0002)
 #define GPU_RESET_CAUSE_RMA     (RAS_CORE_RESET_GPU | 0x0004)

+enum ras_core_fw_feature_flags {
+       RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), };
+
 enum ras_block_id {
        RAS_BLOCK_ID__UMC = 0,
        RAS_BLOCK_ID__SDMA,
@@ -127,6 +131,16 @@ enum ras_gpu_status {
        RAS_GPU_STATUS__IS_VF = 0x8,
 };

+enum ras_fw_eeprom_cmd {
+       RAS_SMU_GetRASTableVersion = 0,
+       RAS_SMU_GetBadPageCount,
+       RAS_SMU_SetTimestamp,
+       RAS_SMU_GetTimestamp,
+       RAS_SMU_GetBadPageIpid,
+       RAS_SMU_EraseRasTable,
+       RAS_SMU_GetBadPageMcaAddr,
+};
+
 struct ras_core_context;
 struct ras_bank_ecc;
 struct ras_umc;
@@ -141,6 +155,10 @@ struct ras_mp1_sys_func {
                        u32 msg, u32 *count);
        int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core,
                        u32 msg, u32 idx, u32 reg_idx, u64 *val);
+       int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core,
+                       enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg);
+       int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core,
+                       uint64_t *enabled_mask);
 };

 struct ras_eeprom_sys_func {
--
2.34.1

Re: [PATCH 03/14] drm/amd/ras: add pmfw eeprom smu interfaces

[Lazar, Lijo]

On 30-Jan-26 7:59 AM, Gangliang Xie wrote:
> add smu interfaces and its data structures for
> pmfw eeprom in uniras
> 
> Signed-off-by: Gangliang Xie <ganglxie@amd.com>
> ---
>   .../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c    | 46 +++++++++++++++++++
>   drivers/gpu/drm/amd/ras/rascore/ras.h         | 18 ++++++++
>   2 files changed, 64 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
> index 79a51b1603ac..03922aa03417 100644
> --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
> +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
> @@ -28,6 +28,16 @@
>   #define RAS_MP1_MSG_QueryValidMcaCeCount  0x3A
>   #define RAS_MP1_MSG_McaBankCeDumpDW       0x3B
>   
> +static enum smu_message_type pmfw_eeprom_msgs[] = {
> +	SMU_MSG_GetRASTableVersion,
> +	SMU_MSG_GetBadPageCount,
> +	SMU_MSG_SetTimestamp,
> +	SMU_MSG_GetTimestamp,
> +	SMU_MSG_GetBadPageIpid,
> +	SMU_MSG_EraseRasTable,
> +	SMU_MSG_GetBadPageMcaAddr,
> +};
> +

You may consider designated index initialization to be explicit.

[RAS_SMU_GetRASTableVersion] = SMU_MSG_GetRASTableVersion

Thanks,
Lijo

>   static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core,
>   					  u32 msg, u32 *count)
>   {
> @@ -87,8 +97,44 @@ static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core,
>   	return ret;
>   }
>   
> +static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core,
> +				enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg)
> +{
> +	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
> +	int ret = 0;
> +
> +	if (down_read_trylock(&adev->reset_domain->sem)) {
> +		ret = amdgpu_smu_ras_send_msg(adev,
> +			pmfw_eeprom_msgs[index], param, read_arg);
> +		up_read(&adev->reset_domain->sem);
> +	} else {
> +		ret = -RAS_CORE_GPU_IN_MODE1_RESET;
> +	}
> +
> +	return ret;
> +}
> +
> +static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core,
> +					     uint64_t *enabled_mask)
> +{
> +	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
> +	int ret = 0;
> +
> +	if (down_read_trylock(&adev->reset_domain->sem)) {
> +		if (amdgpu_smu_ras_feature_is_enabled(adev, SMU_FEATURE_HROM_EN_BIT))
> +			*enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM;
> +		up_read(&adev->reset_domain->sem);
> +	} else {
> +		ret = -RAS_CORE_GPU_IN_MODE1_RESET;
> +	}
> +
> +	return ret;
> +}
> +
>   const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = {
>   	.mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count,
>   	.mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank,
> +	.mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg,
> +	.mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask,
>   };
>   
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
> index 3396b2e0949d..2db838c444f1 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
> @@ -49,6 +49,10 @@
>   #define GPU_RESET_CAUSE_FATAL   (RAS_CORE_RESET_GPU | 0x0002)
>   #define GPU_RESET_CAUSE_RMA     (RAS_CORE_RESET_GPU | 0x0004)
>   
> +enum ras_core_fw_feature_flags {
> +	RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0),
> +};
> +
>   enum ras_block_id {
>   	RAS_BLOCK_ID__UMC = 0,
>   	RAS_BLOCK_ID__SDMA,
> @@ -127,6 +131,16 @@ enum ras_gpu_status {
>   	RAS_GPU_STATUS__IS_VF = 0x8,
>   };
>   
> +enum ras_fw_eeprom_cmd {
> +	RAS_SMU_GetRASTableVersion = 0,
> +	RAS_SMU_GetBadPageCount,
> +	RAS_SMU_SetTimestamp,
> +	RAS_SMU_GetTimestamp,
> +	RAS_SMU_GetBadPageIpid,
> +	RAS_SMU_EraseRasTable,
> +	RAS_SMU_GetBadPageMcaAddr,
> +};
> +
>   struct ras_core_context;
>   struct ras_bank_ecc;
>   struct ras_umc;
> @@ -141,6 +155,10 @@ struct ras_mp1_sys_func {
>   			u32 msg, u32 *count);
>   	int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core,
>   			u32 msg, u32 idx, u32 reg_idx, u64 *val);
> +	int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core,
> +			enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg);
> +	int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core,
> +			uint64_t *enabled_mask);
>   };
>   
>   struct ras_eeprom_sys_func {

Re: [PATCH 05/14] drm/amd/ras: add wrapper funcs for pmfw eeprom

[Lazar, Lijo]

On 30-Jan-26 7:59 AM, Gangliang Xie wrote:
> add wrapper funcs for pmfw eeprom interface to make them
> easier to be called
> 
> Signed-off-by: Gangliang Xie <ganglxie@amd.com>
> ---
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 125 ++++++++++++++++++
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  16 +++
>   2 files changed, 141 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> index e94c368c3159..f880fc49477d 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c

If all FW interactions are kept here, ras_eeprom_fw may be a misnomer. 
Just use ras_fw/ras_mp_fw or similar.

Thanks,
Lijo

> @@ -36,3 +36,128 @@ void ras_fw_init_feature_flags(struct ras_core_context *ras_core)
>   	if (!sys_func->mp1_get_ras_enabled_mask(ras_core, &flags))
>   		ras_core->ras_fw_features = flags;
>   }
> +
> +bool ras_fw_eeprom_supported(struct ras_core_context *ras_core)
> +{
> +	return !!(ras_core->ras_fw_features & RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM);
> +}
> +
> +int ras_fw_get_table_version(struct ras_core_context *ras_core,
> +				     uint32_t *table_version)
> +{
> +	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
> +	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
> +
> +	return sys_func->mp1_send_eeprom_msg(ras_core,
> +				RAS_SMU_GetRASTableVersion, 0, table_version);
> +}
> +
> +int ras_fw_get_badpage_count(struct ras_core_context *ras_core,
> +				     uint32_t *count, uint32_t timeout)
> +{
> +	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
> +	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
> +	uint64_t end, now;
> +	int ret = 0;
> +
> +	now = (uint64_t)ktime_to_ms(ktime_get());
> +	end = now + timeout;
> +
> +	do {
> +		ret = sys_func->mp1_send_eeprom_msg(ras_core,
> +			RAS_SMU_GetBadPageCount, 0, count);
> +		/* eeprom is not ready */
> +		if (ret != -EBUSY)
> +			return ret;
> +
> +		mdelay(10);
> +		now = (uint64_t)ktime_to_ms(ktime_get());
> +	} while (now < end);
> +
> +	RAS_DEV_ERR(ras_core->dev,
> +			"smu get bad page count timeout!\n");
> +	return ret;
> +}
> +
> +int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core,
> +					uint16_t index, uint64_t *mca_addr)
> +{
> +	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
> +	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
> +	uint32_t temp_arg, temp_addr_lo, temp_addr_high;
> +	int ret;
> +
> +	temp_arg = index | (1 << 16);
> +	ret = sys_func->mp1_send_eeprom_msg(ras_core,
> +			RAS_SMU_GetBadPageMcaAddr, temp_arg, &temp_addr_lo);
> +	if (ret)
> +		return ret;
> +
> +	temp_arg = index | (2 << 16);
> +	ret = sys_func->mp1_send_eeprom_msg(ras_core,
> +			RAS_SMU_GetBadPageMcaAddr, temp_arg, &temp_addr_high);
> +
> +	if (!ret)
> +		*mca_addr = (uint64_t)temp_addr_high << 32 | temp_addr_lo;
> +
> +	return ret;
> +}
> +
> +int ras_fw_set_timestamp(struct ras_core_context *ras_core,
> +				 uint64_t timestamp)
> +{
> +	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
> +	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
> +
> +	return sys_func->mp1_send_eeprom_msg(ras_core,
> +			RAS_SMU_SetTimestamp, (uint32_t)timestamp, 0);
> +}
> +
> +int ras_fw_get_timestamp(struct ras_core_context *ras_core,
> +				 uint16_t index, uint64_t *timestamp)
> +{
> +	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
> +	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
> +	uint32_t temp = 0;
> +	int ret;
> +
> +	ret = sys_func->mp1_send_eeprom_msg(ras_core,
> +			RAS_SMU_GetTimestamp, index, &temp);
> +	if (!ret)
> +		*timestamp = temp;
> +
> +	return ret;
> +}
> +
> +int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
> +				    uint16_t index, uint64_t *ipid)
> +{
> +	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
> +	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
> +	uint32_t temp_arg, temp_ipid_lo, temp_ipid_high;
> +	int ret;
> +
> +	temp_arg = index | (1 << 16);
> +	ret = sys_func->mp1_send_eeprom_msg(ras_core,
> +			RAS_SMU_GetBadPageIpid, temp_arg, &temp_ipid_lo);
> +	if (ret)
> +		return ret;
> +
> +	temp_arg = index | (2 << 16);
> +	ret = sys_func->mp1_send_eeprom_msg(ras_core,
> +			RAS_SMU_GetBadPageIpid, temp_arg, &temp_ipid_high);
> +	if (!ret)
> +		*ipid = (uint64_t)temp_ipid_high << 32 | temp_ipid_lo;
> +
> +	return ret;
> +}
> +
> +int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
> +				   uint32_t *result)
> +{
> +	struct ras_mp1 *mp1 = &ras_core->ras_mp1;
> +	const struct ras_mp1_sys_func *sys_func = mp1->sys_func;
> +
> +	return sys_func->mp1_send_eeprom_msg(ras_core,
> +			RAS_SMU_EraseRasTable, 0, result);
> +}
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> index b41665467368..46f45e82a3f3 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> @@ -24,6 +24,22 @@
>   #ifndef __RAS_EEPROM_FW_H__
>   #define __RAS_EEPROM_FW_H__
>   
> +
>   void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
> +bool ras_fw_eeprom_supported(struct ras_core_context *ras_core);
> +int ras_fw_get_table_version(struct ras_core_context *ras_core,
> +				     uint32_t *table_version);
> +int ras_fw_get_badpage_count(struct ras_core_context *ras_core,
> +				     uint32_t *count, uint32_t timeout);
> +int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core,
> +					uint16_t index, uint64_t *mca_addr);
> +int ras_fw_set_timestamp(struct ras_core_context *ras_core,
> +				 uint64_t timestamp);
> +int ras_fw_get_timestamp(struct ras_core_context *ras_core,
> +				 uint16_t index, uint64_t *timestamp);
> +int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
> +				    uint16_t index, uint64_t *ipid);
> +int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
> +				   uint32_t *result);
>   
>   #endif

Re: [PATCH 06/14] drm/amd/ras: Add table reset func for pmfw eeprom

[Lazar, Lijo]

On 30-Jan-26 7:59 AM, Gangliang Xie wrote:
> add table reset func for pmfw eeprom, add smu eeprom control
> structure
> 
> Signed-off-by: Gangliang Xie <ganglxie@amd.com>
> ---
>   drivers/gpu/drm/amd/ras/rascore/ras.h         |  1 +
>   drivers/gpu/drm/amd/ras/rascore/ras_cmd.c     |  9 ++++--
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 29 +++++++++++++++++++
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   | 26 +++++++++++++++++
>   4 files changed, 63 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
> index 6e223eff522c..ae10d853c565 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
> @@ -313,6 +313,7 @@ struct ras_core_context {
>   
>   	bool ras_eeprom_supported;
>   	struct ras_eeprom_control ras_eeprom;
> +	struct ras_fw_eeprom_control ras_fw_eeprom;
>   
>   	struct ras_psp ras_psp;
>   	struct ras_umc ras_umc;
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
> index 94e6d7420d94..4f89810d85a1 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
> @@ -146,8 +146,13 @@ static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core,
>   	if (cmd->input_size != sizeof(struct ras_cmd_dev_handle))
>   		return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
>   
> -	if (ras_eeprom_reset_table(ras_core))
> -		return RAS_CMD__ERROR_GENERIC;
> +	if (ras_fw_eeprom_supported(ras_core)) {
> +		if (ras_fw_eeprom_reset_table(ras_core))
> +			return RAS_CMD__ERROR_GENERIC;
> +	} else {
> +		if (ras_eeprom_reset_table(ras_core))
> +			return RAS_CMD__ERROR_GENERIC;
> +	}
>   
>   	if (ras_umc_clean_badpage_data(ras_core))
>   		return RAS_CMD__ERROR_GENERIC;
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> index f880fc49477d..ae63e7394829 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> @@ -161,3 +161,32 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
>   	return sys_func->mp1_send_eeprom_msg(ras_core,
>   			RAS_SMU_EraseRasTable, 0, result);
>   }
> +
> +int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core)
> +{
> +	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
> +	u32 erase_res = 0;
> +	int res;
> +
> +	mutex_lock(&control->ras_tbl_mutex);
> +
> +	res = ras_fw_erase_ras_table(ras_core, &erase_res);

Except this call, everything else looks like a common logic. For ex: 
num_recs, bitmap etc. looks like common for eeprom as a whole and not 
specific to fw eeprom.

Thanks,
Lijo

> +	if (res || erase_res) {
> +		RAS_DEV_WARN(ras_core->dev, "RAS EEPROM reset failed, res:%d result:%d",
> +									res, erase_res);
> +		if (!res)
> +			res = -EIO;
> +	}
> +
> +	control->ras_num_recs = 0;
> +	control->bad_channel_bitmap = 0;
> +	ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM,
> +		&control->ras_num_recs);
> +	ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP,
> +		&control->bad_channel_bitmap);
> +	control->update_channel_flag = false;
> +
> +	mutex_unlock(&control->ras_tbl_mutex);
> +
> +	return res;
> +}
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> index 46f45e82a3f3..a1003db3c33b 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> @@ -24,6 +24,31 @@
>   #ifndef __RAS_EEPROM_FW_H__
>   #define __RAS_EEPROM_FW_H__
>   
> +struct ras_fw_eeprom_control {
> +	uint32_t version;
> +	/* record threshold */
> +	int record_threshold_config;
> +	uint32_t record_threshold_count;
> +	bool update_channel_flag;
> +
> +	/* Number of records in the table.
> +	 */
> +	u32 ras_num_recs;
> +
> +	/* Maximum possible number of records
> +	 * we could store, i.e. the maximum capacity
> +	 * of the table.
> +	 */
> +	u32 ras_max_record_count;
> +
> +	/* Protect table access via this mutex.
> +	 */
> +	struct mutex ras_tbl_mutex;
> +
> +	/* Record channel info which occurred bad pages
> +	 */
> +	u32 bad_channel_bitmap;
> +};
>   
>   void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
>   bool ras_fw_eeprom_supported(struct ras_core_context *ras_core);
> @@ -41,5 +66,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
>   				    uint16_t index, uint64_t *ipid);
>   int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
>   				   uint32_t *result);
> +int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
>   
>   #endif

Re: [PATCH 07/14] drm/amd/ras: add check safety watermark func for pmfw eeprom

[Lazar, Lijo]

On 30-Jan-26 7:59 AM, Gangliang Xie wrote:
> add check safety watermark func for pmfw eeprom
> 
> Signed-off-by: Gangliang Xie <ganglxie@amd.com>
> ---
>   .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c  |  3 ++
>   drivers/gpu/drm/amd/ras/rascore/ras_core.c    |  3 ++
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 30 +++++++++++++++++++
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  1 +
>   4 files changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> index 923bddd0af3a..36c264ab889c 100644
> --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
> @@ -570,6 +570,9 @@ bool amdgpu_ras_mgr_check_eeprom_safety_watermark(struct amdgpu_device *adev)
>   	if (!amdgpu_ras_mgr_is_ready(adev))
>   		return false;
>   
> +	if (ras_fw_eeprom_supported(ras_mgr->ras_core))
> +		return ras_fw_eeprom_check_safety_watermark(ras_mgr->ras_core);
> +
>   	return ras_eeprom_check_safety_watermark(ras_mgr->ras_core);
>   }
>   
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> index 91c883f16ae5..1f2ce3749d43 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> @@ -561,6 +561,9 @@ bool ras_core_is_ready(struct ras_core_context *ras_core)
>   
>   bool ras_core_check_safety_watermark(struct ras_core_context *ras_core)
>   {
> +	if (ras_fw_eeprom_supported(ras_core))
> +		return ras_fw_eeprom_check_safety_watermark(ras_core);
> +
>   	return ras_eeprom_check_safety_watermark(ras_core);
>   }
>   
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> index ae63e7394829..34a4161251b3 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> @@ -190,3 +190,33 @@ int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core)
>   
>   	return res;
>   }
> +
> +bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core)
> +{

Again looks like duplicate logic. ras_eeprom can carry the threshold 
config regardless of the access type. There is nothing in here specific 
to the way eeprom is accessed.

Thanks,
Lijo

> +	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
> +	bool ret = false;
> +	int bad_page_count;
> +
> +	if (!control->record_threshold_config)
> +		return false;
> +
> +	bad_page_count = ras_umc_get_badpage_count(ras_core);
> +
> +	if (bad_page_count > control->record_threshold_count)
> +		RAS_DEV_WARN(ras_core->dev, "RAS records:%d exceed threshold:%d",
> +			bad_page_count, control->record_threshold_count);
> +
> +	if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) ||
> +		(control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) {
> +		RAS_DEV_WARN(ras_core->dev,
> +			"Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n");
> +		ret = false;
> +	} else {
> +		ras_core->is_rma = true;
> +		RAS_DEV_WARN(ras_core->dev,
> +			"Please consider adjusting the customized threshold.\n");
> +		ret = true;
> +	}
> +
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> index a1003db3c33b..b0d3eade4377 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> @@ -67,5 +67,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
>   int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
>   				   uint32_t *result);
>   int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
> +bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core);
>   
>   #endif

Re: [PATCH 08/14] drm/amd/ras: add append func for pmfw eeprom

[Lazar, Lijo]

On 30-Jan-26 7:59 AM, Gangliang Xie wrote:
> add append func for pmfw eeprom
> 
> Signed-off-by: Gangliang Xie <ganglxie@amd.com>
> ---
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 39 +++++++++++++++++++
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  2 +
>   drivers/gpu/drm/amd/ras/rascore/ras_umc.c     | 10 +++--
>   3 files changed, 48 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> index 34a4161251b3..580dd7b09d00 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> @@ -220,3 +220,42 @@ bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core)
>   
>   	return ret;
>   }
> +
> +int ras_fw_eeprom_append(struct ras_core_context *ras_core,
> +			   struct eeprom_umc_record *record, const u32 num)
> +{
> +	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
> +	int threshold_config = control->record_threshold_config;
> +	int i, bad_page_count;
> +
> +	mutex_lock(&control->ras_tbl_mutex);
> +

Same comment as in earlier patches. All seems to be duplicated just 
because a mutex is added to specific access control. Instead, all of 
that can be kept in common eeprom and only access mechanism can be 
separated.

Thanks,
Lijo

> +	for (i = 0; i < num; i++) {
> +		/* update bad channel bitmap */
> +		if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
> +			!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
> +			control->bad_channel_bitmap |= 1 << record[i].mem_channel;
> +			control->update_channel_flag = true;
> +		}
> +	}
> +	control->ras_num_recs += num;
> +
> +	bad_page_count = ras_umc_get_badpage_count(ras_core);
> +
> +	if (threshold_config != 0 &&
> +		bad_page_count > control->record_threshold_count) {
> +		RAS_DEV_WARN(ras_core->dev,
> +			"Saved bad pages %d reaches threshold value %d\n",
> +			bad_page_count, control->record_threshold_count);
> +
> +		if ((threshold_config != WARN_NONSTOP_OVER_THRESHOLD) &&
> +			(threshold_config != NONSTOP_OVER_THRESHOLD))
> +			ras_core->is_rma = true;
> +
> +		/* ignore the -ENOTSUPP return value */
> +		ras_core_event_notify(ras_core, RAS_EVENT_ID__DEVICE_RMA, NULL);
> +	}
> +
> +	mutex_unlock(&control->ras_tbl_mutex);
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> index b0d3eade4377..b94d3c9703e3 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> @@ -68,5 +68,7 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
>   				   uint32_t *result);
>   int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
>   bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core);
> +int ras_fw_eeprom_append(struct ras_core_context *ras_core,
> +			   struct eeprom_umc_record *record, const u32 num);
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
> index 4dae64c424a2..fd427fd59ecf 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
> @@ -479,9 +479,13 @@ static int ras_umc_save_bad_pages(struct ras_core_context *ras_core)
>   	save_count = data->count - eeprom_record_num;
>   	/* only new entries are saved */
>   	if (save_count > 0) {
> -		if (ras_eeprom_append(ras_core,
> -					   &data->bps[eeprom_record_num],
> -					   save_count)) {
> +		if (ras_fw_eeprom_supported(ras_core))
> +			ret = ras_fw_eeprom_append(ras_core, &data->bps[eeprom_record_num],
> +					save_count);
> +		else
> +			ret = ras_eeprom_append(ras_core, &data->bps[eeprom_record_num],
> +					save_count);
> +		if (ret) {
>   			RAS_DEV_ERR(ras_core->dev, "Failed to save EEPROM table data!");
>   			ret = -EIO;
>   			goto exit;

Re: [PATCH 10/14] drm/amd/ras: add read func for pmfw eeprom

[Lazar, Lijo]

On 30-Jan-26 7:59 AM, Gangliang Xie wrote:
> add read func for pmfw eeprom, and adapt address converting
> for bad pages loaded from pmfw eeprom
> 
> Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
> Signed-off-by: Gangliang Xie <ganglxie@amd.com>
> ---
>   drivers/gpu/drm/amd/ras/rascore/ras.h         |  1 +
>   drivers/gpu/drm/amd/ras/rascore/ras_core.c    |  5 +-
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 70 +++++++++++++++++++
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   |  5 ++
>   drivers/gpu/drm/amd/ras/rascore/ras_umc.c     | 27 +++++--
>   .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.c   |  2 +-
>   6 files changed, 101 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h
> index ae10d853c565..05c7923e8f0f 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
> @@ -241,6 +241,7 @@ struct ras_bank_ecc {
>   	uint64_t status;
>   	uint64_t ipid;
>   	uint64_t addr;
> +	uint64_t ts;
>   };
>   
>   struct ras_bank_ecc_node {
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> index 1f2ce3749d43..fe188a5304d9 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c
> @@ -239,7 +239,10 @@ static int ras_core_eeprom_recovery(struct ras_core_context *ras_core)
>   	int count;
>   	int ret;
>   
> -	count = ras_eeprom_get_record_count(ras_core);
> +	if (ras_fw_eeprom_supported(ras_core))
> +		count = ras_fw_eeprom_get_record_count(ras_core);

As mentioned in earlier patches, suggestion is to keep just

ras_eeprom_get_record_count.

With ras_eeprom, you may decide the access mechanism and fork to 
different paths. That looks cleaner and all common variables can be kept 
inside ras_eeprom itself.


> +	else
> +		count = ras_eeprom_get_record_count(ras_core);
>   	if (!count)
>   		return 0;
>   
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> index 580dd7b09d00..79494ad16ee5 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> @@ -259,3 +259,73 @@ int ras_fw_eeprom_append(struct ras_core_context *ras_core,
>   	mutex_unlock(&control->ras_tbl_mutex);
>   	return 0;
>   }
> +
> +int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
> +			 struct eeprom_umc_record *record_umc,
> +			 struct ras_bank_ecc *ras_ecc,
> +			 u32 rec_idx, const u32 num)
> +{
> +	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
> +	int i, ret, end_idx;
> +	u64 mca, ipid, ts;
> +
> +	if (!ras_core->ras_umc.ip_func ||
> +	    !ras_core->ras_umc.ip_func->mca_ipid_parse)
> +		return -EOPNOTSUPP;
> +
> +	mutex_lock(&control->ras_tbl_mutex);
> +
> +	end_idx = rec_idx + num;
> +	for (i = rec_idx; i < end_idx; i++) {
> +		ret = ras_fw_get_badpage_mca_addr(ras_core, i, &mca);
> +		if (ret)
> +			goto out;
> +
> +		ret = ras_fw_get_badpage_ipid(ras_core, i, &ipid);
> +		if (ret)
> +			goto out;
> +
> +		ret = ras_fw_get_timestamp(ras_core, i, &ts);
> +		if (ret)
> +			goto out;
> +
> +		if (record_umc) {
> +			record_umc[i - rec_idx].address = mca;
> +			/* retired_page (pa) is unused now */
> +			record_umc[i - rec_idx].retired_row_pfn = 0x1ULL;
> +			record_umc[i - rec_idx].ts = ts;
> +			record_umc[i - rec_idx].err_type = RAS_EEPROM_ERR_NON_RECOVERABLE;
> +
> +			ras_core->ras_umc.ip_func->mca_ipid_parse(ras_core, ipid,
> +				(uint32_t *)&(record_umc[i - rec_idx].cu),
> +				(uint32_t *)&(record_umc[i - rec_idx].mem_channel),
> +				(uint32_t *)&(record_umc[i - rec_idx].mcumc_id), NULL);
> +
> +			/* update bad channel bitmap */
> +			if ((record_umc[i - rec_idx].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
> +				!(control->bad_channel_bitmap & (1 << record_umc[i - rec_idx].mem_channel))) {
> +				control->bad_channel_bitmap |= 1 << record_umc[i - rec_idx].mem_channel;
> +				control->update_channel_flag = true;
> +			}
> +		}
> +
> +		if (ras_ecc) {
> +			ras_ecc[i - rec_idx].addr = mca;
> +			ras_ecc[i - rec_idx].ipid = ipid;
> +			ras_ecc[i - rec_idx].ts = ts;
> +		}
> +
> +	}
> +
> +out:
> +	mutex_unlock(&control->ras_tbl_mutex);
> +	return ret;
> +}
> +
> +uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core)
> +{
> +	if (!ras_core)
> +		return 0;
> +
> +	return ras_core->ras_fw_eeprom.ras_num_recs;
> +}
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> index b94d3c9703e3..353977a2371e 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> @@ -70,5 +70,10 @@ int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
>   bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core);
>   int ras_fw_eeprom_append(struct ras_core_context *ras_core,
>   			   struct eeprom_umc_record *record, const u32 num);
> +int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core,
> +			 struct eeprom_umc_record *record_umc,
> +			 struct ras_bank_ecc *ras_ecc,
> +			 u32 rec_idx, const u32 num);
> +uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core);
>   
>   #endif
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
> index fd427fd59ecf..eb5bb6df18f5 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c
> @@ -436,17 +436,27 @@ int ras_umc_load_bad_pages(struct ras_core_context *ras_core)
>   	uint32_t ras_num_recs;
>   	int ret;
>   
> -	ras_num_recs = ras_eeprom_get_record_count(ras_core);
> -	/* no bad page record, skip eeprom access */
> -	if (!ras_num_recs ||
> -	    ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE)
> -		return 0;
> +	if (ras_fw_eeprom_supported(ras_core)) {
> +		ras_num_recs = ras_fw_eeprom_get_record_count(ras_core);
> +		/* no bad page record, skip eeprom access */
> +		if (!ras_num_recs ||
> +		    ras_core->ras_fw_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE)
> +			return 0;
> +	} else {
> +		ras_num_recs = ras_eeprom_get_record_count(ras_core);
> +		if (!ras_num_recs ||
> +		    ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE)

This is an example where common variables/logic get repeated.

Thanks,
Lijo

> +			return 0;
> +	}
>   
>   	bps = kcalloc(ras_num_recs, sizeof(*bps), GFP_KERNEL);
>   	if (!bps)
>   		return -ENOMEM;
>   
> -	ret = ras_eeprom_read(ras_core, bps, ras_num_recs);
> +	if (ras_fw_eeprom_supported(ras_core))
> +		ret = ras_fw_eeprom_read_idx(ras_core, bps, 0, 0, ras_num_recs);
> +	else
> +		ret = ras_eeprom_read(ras_core, bps, ras_num_recs);
>   	if (ret) {
>   		RAS_DEV_ERR(ras_core->dev, "Failed to load EEPROM table records!");
>   	} else {
> @@ -474,7 +484,10 @@ static int ras_umc_save_bad_pages(struct ras_core_context *ras_core)
>   	if (!data->bps)
>   		return 0;
>   
> -	eeprom_record_num = ras_eeprom_get_record_count(ras_core);
> +	if (ras_fw_eeprom_supported(ras_core))
> +		eeprom_record_num = ras_fw_eeprom_get_record_count(ras_core);
> +	else
> +		eeprom_record_num = ras_eeprom_get_record_count(ras_core);
>   	mutex_lock(&ras_umc->umc_lock);
>   	save_count = data->count - eeprom_record_num;
>   	/* only new entries are saved */
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
> index e2792b239bea..53dc59e4de0c 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c
> @@ -413,7 +413,7 @@ static int umc_v12_0_eeprom_record_to_nps_record(struct ras_core_context *ras_co
>   	uint64_t pa = 0;
>   	int ret = 0;
>   
> -	if (nps == EEPROM_RECORD_UMC_NPS_MODE(record)) {
> +	if (nps == EEPROM_RECORD_UMC_NPS_MODE(record) && !ras_fw_eeprom_supported(ras_core)) {
>   		record->cur_nps_retired_row_pfn = EEPROM_RECORD_UMC_ADDR_PFN(record);
>   	} else {
>   		ret = convert_eeprom_record_to_nps_addr(ras_core,

RE: [PATCH 03/14] drm/amd/ras: add pmfw eeprom smu interfaces

[Xie, Patrick]

[AMD Official Use Only - AMD Internal Distribution Only]

Thanks, will take this advice

-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Friday, January 30, 2026 1:42 PM
To: Xie, Patrick <Gangliang.Xie@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Chai, Thomas <YiPeng.Chai@amd.com>; Wang, Yang(Kevin) <KevinYang.Wang@amd.com>
Subject: Re: [PATCH 03/14] drm/amd/ras: add pmfw eeprom smu interfaces



On 30-Jan-26 7:59 AM, Gangliang Xie wrote:
> add smu interfaces and its data structures for pmfw eeprom in uniras
>
> Signed-off-by: Gangliang Xie <ganglxie@amd.com>
> ---
>   .../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c    | 46 +++++++++++++++++++
>   drivers/gpu/drm/amd/ras/rascore/ras.h         | 18 ++++++++
>   2 files changed, 64 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
> b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
> index 79a51b1603ac..03922aa03417 100644
> --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
> +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c
> @@ -28,6 +28,16 @@
>   #define RAS_MP1_MSG_QueryValidMcaCeCount  0x3A
>   #define RAS_MP1_MSG_McaBankCeDumpDW       0x3B
>
> +static enum smu_message_type pmfw_eeprom_msgs[] = {
> +     SMU_MSG_GetRASTableVersion,
> +     SMU_MSG_GetBadPageCount,
> +     SMU_MSG_SetTimestamp,
> +     SMU_MSG_GetTimestamp,
> +     SMU_MSG_GetBadPageIpid,
> +     SMU_MSG_EraseRasTable,
> +     SMU_MSG_GetBadPageMcaAddr,
> +};
> +

You may consider designated index initialization to be explicit.

[RAS_SMU_GetRASTableVersion] = SMU_MSG_GetRASTableVersion

Thanks,
Lijo

>   static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core,
>                                         u32 msg, u32 *count)
>   {
> @@ -87,8 +97,44 @@ static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core,
>       return ret;
>   }
>
> +static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core,
> +                             enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg)
> +{
> +     struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
> +     int ret = 0;
> +
> +     if (down_read_trylock(&adev->reset_domain->sem)) {
> +             ret = amdgpu_smu_ras_send_msg(adev,
> +                     pmfw_eeprom_msgs[index], param, read_arg);
> +             up_read(&adev->reset_domain->sem);
> +     } else {
> +             ret = -RAS_CORE_GPU_IN_MODE1_RESET;
> +     }
> +
> +     return ret;
> +}
> +
> +static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core,
> +                                          uint64_t *enabled_mask)
> +{
> +     struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
> +     int ret = 0;
> +
> +     if (down_read_trylock(&adev->reset_domain->sem)) {
> +             if (amdgpu_smu_ras_feature_is_enabled(adev, SMU_FEATURE_HROM_EN_BIT))
> +                     *enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM;
> +             up_read(&adev->reset_domain->sem);
> +     } else {
> +             ret = -RAS_CORE_GPU_IN_MODE1_RESET;
> +     }
> +
> +     return ret;
> +}
> +
>   const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = {
>       .mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count,
>       .mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank,
> +     .mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg,
> +     .mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask,
>   };
>
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h
> b/drivers/gpu/drm/amd/ras/rascore/ras.h
> index 3396b2e0949d..2db838c444f1 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
> @@ -49,6 +49,10 @@
>   #define GPU_RESET_CAUSE_FATAL   (RAS_CORE_RESET_GPU | 0x0002)
>   #define GPU_RESET_CAUSE_RMA     (RAS_CORE_RESET_GPU | 0x0004)
>
> +enum ras_core_fw_feature_flags {
> +     RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), };
> +
>   enum ras_block_id {
>       RAS_BLOCK_ID__UMC = 0,
>       RAS_BLOCK_ID__SDMA,
> @@ -127,6 +131,16 @@ enum ras_gpu_status {
>       RAS_GPU_STATUS__IS_VF = 0x8,
>   };
>
> +enum ras_fw_eeprom_cmd {
> +     RAS_SMU_GetRASTableVersion = 0,
> +     RAS_SMU_GetBadPageCount,
> +     RAS_SMU_SetTimestamp,
> +     RAS_SMU_GetTimestamp,
> +     RAS_SMU_GetBadPageIpid,
> +     RAS_SMU_EraseRasTable,
> +     RAS_SMU_GetBadPageMcaAddr,
> +};
> +
>   struct ras_core_context;
>   struct ras_bank_ecc;
>   struct ras_umc;
> @@ -141,6 +155,10 @@ struct ras_mp1_sys_func {
>                       u32 msg, u32 *count);
>       int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core,
>                       u32 msg, u32 idx, u32 reg_idx, u64 *val);
> +     int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core,
> +                     enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg);
> +     int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core,
> +                     uint64_t *enabled_mask);
>   };
>
>   struct ras_eeprom_sys_func {

RE: [PATCH 06/14] drm/amd/ras: Add table reset func for pmfw eeprom

[Xie, Patrick]

[AMD Official Use Only - AMD Internal Distribution Only]

Hi, Lijo
        Currently the feature is being developed, to avoid affecting functions already in driver, we separate it from the other code, and it is disabled by default, will replace the original code when it is ready. Thank you.

-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Friday, January 30, 2026 1:49 PM
To: Xie, Patrick <Gangliang.Xie@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Chai, Thomas <YiPeng.Chai@amd.com>; Wang, Yang(Kevin) <KevinYang.Wang@amd.com>
Subject: Re: [PATCH 06/14] drm/amd/ras: Add table reset func for pmfw eeprom



On 30-Jan-26 7:59 AM, Gangliang Xie wrote:
> add table reset func for pmfw eeprom, add smu eeprom control structure
>
> Signed-off-by: Gangliang Xie <ganglxie@amd.com>
> ---
>   drivers/gpu/drm/amd/ras/rascore/ras.h         |  1 +
>   drivers/gpu/drm/amd/ras/rascore/ras_cmd.c     |  9 ++++--
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.c   | 29 +++++++++++++++++++
>   .../gpu/drm/amd/ras/rascore/ras_eeprom_fw.h   | 26 +++++++++++++++++
>   4 files changed, 63 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h
> b/drivers/gpu/drm/amd/ras/rascore/ras.h
> index 6e223eff522c..ae10d853c565 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h
> @@ -313,6 +313,7 @@ struct ras_core_context {
>
>       bool ras_eeprom_supported;
>       struct ras_eeprom_control ras_eeprom;
> +     struct ras_fw_eeprom_control ras_fw_eeprom;
>
>       struct ras_psp ras_psp;
>       struct ras_umc ras_umc;
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
> b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
> index 94e6d7420d94..4f89810d85a1 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c
> @@ -146,8 +146,13 @@ static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core,
>       if (cmd->input_size != sizeof(struct ras_cmd_dev_handle))
>               return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
>
> -     if (ras_eeprom_reset_table(ras_core))
> -             return RAS_CMD__ERROR_GENERIC;
> +     if (ras_fw_eeprom_supported(ras_core)) {
> +             if (ras_fw_eeprom_reset_table(ras_core))
> +                     return RAS_CMD__ERROR_GENERIC;
> +     } else {
> +             if (ras_eeprom_reset_table(ras_core))
> +                     return RAS_CMD__ERROR_GENERIC;
> +     }
>
>       if (ras_umc_clean_badpage_data(ras_core))
>               return RAS_CMD__ERROR_GENERIC;
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> index f880fc49477d..ae63e7394829 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
> @@ -161,3 +161,32 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
>       return sys_func->mp1_send_eeprom_msg(ras_core,
>                       RAS_SMU_EraseRasTable, 0, result);
>   }
> +
> +int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core) {
> +     struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;
> +     u32 erase_res = 0;
> +     int res;
> +
> +     mutex_lock(&control->ras_tbl_mutex);
> +
> +     res = ras_fw_erase_ras_table(ras_core, &erase_res);

Except this call, everything else looks like a common logic. For ex:
num_recs, bitmap etc. looks like common for eeprom as a whole and not specific to fw eeprom.

Thanks,
Lijo

> +     if (res || erase_res) {
> +             RAS_DEV_WARN(ras_core->dev, "RAS EEPROM reset failed, res:%d result:%d",
> +                                                                     res, erase_res);
> +             if (!res)
> +                     res = -EIO;
> +     }
> +
> +     control->ras_num_recs = 0;
> +     control->bad_channel_bitmap = 0;
> +     ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM,
> +             &control->ras_num_recs);
> +     ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP,
> +             &control->bad_channel_bitmap);
> +     control->update_channel_flag = false;
> +
> +     mutex_unlock(&control->ras_tbl_mutex);
> +
> +     return res;
> +}
> diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> index 46f45e82a3f3..a1003db3c33b 100644
> --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
> @@ -24,6 +24,31 @@
>   #ifndef __RAS_EEPROM_FW_H__
>   #define __RAS_EEPROM_FW_H__
>
> +struct ras_fw_eeprom_control {
> +     uint32_t version;
> +     /* record threshold */
> +     int record_threshold_config;
> +     uint32_t record_threshold_count;
> +     bool update_channel_flag;
> +
> +     /* Number of records in the table.
> +      */
> +     u32 ras_num_recs;
> +
> +     /* Maximum possible number of records
> +      * we could store, i.e. the maximum capacity
> +      * of the table.
> +      */
> +     u32 ras_max_record_count;
> +
> +     /* Protect table access via this mutex.
> +      */
> +     struct mutex ras_tbl_mutex;
> +
> +     /* Record channel info which occurred bad pages
> +      */
> +     u32 bad_channel_bitmap;
> +};
>
>   void ras_fw_init_feature_flags(struct ras_core_context *ras_core);
>   bool ras_fw_eeprom_supported(struct ras_core_context *ras_core); @@
> -41,5 +66,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core,
>                                   uint16_t index, uint64_t *ipid);
>   int ras_fw_erase_ras_table(struct ras_core_context *ras_core,
>                                  uint32_t *result);
> +int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);
>
>   #endif