* [PATCH v2 0/3] Expand amdgpu documentation
@ 2022-08-11 15:48 Rodrigo Siqueira
2022-08-11 15:48 ` [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs Rodrigo Siqueira
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Rodrigo Siqueira @ 2022-08-11 15:48 UTC (permalink / raw)
To: amd-gfx
This patchset introduces some new AMDGPU documentation. You will find:
1. A CSV table that maps which component version is part of some ASIC
families. This can be useful to narrow down bugs;
2. Some explanation about AMD Display Pipeline;
3. An explanation of Multiple Plane Overlay, which can be useful for
userspace applications.
Since we have some diagrams, I recommend applying these patches and
building the documentation to have a better experience.
In this new version, I just rebased this patchset with the latest code
from amd-staging-drm-next, and I also changed patch 2.
Thanks
Siqueira
Rodrigo Siqueira (3):
Documentation/gpu: Add info table for ASICs
Documentation/gpu: Add an explanation about the DCN pipeline
Documentation/gpu: Add Multiplane Overlay doc
.../gpu/amdgpu/apu-asic-info-table.csv | 8 +
.../gpu/amdgpu/dgpu-asic-info-table.csv | 24 +
.../gpu/amdgpu/display/dcn-overview.rst | 59 +
Documentation/gpu/amdgpu/display/index.rst | 1 +
.../gpu/amdgpu/display/mpo-cursor.svg | 435 +++++++
.../gpu/amdgpu/display/mpo-overview.rst | 242 ++++
.../multi-display-hdcp-mpo-less-pipe-ex.svg | 220 ++++
.../amdgpu/display/multi-display-hdcp-mpo.svg | 171 +++
.../amdgpu/display/pipeline_4k_no_split.svg | 958 +++++++++++++++
.../gpu/amdgpu/display/pipeline_4k_split.svg | 1062 +++++++++++++++++
.../single-display-mpo-multi-video.svg | 339 ++++++
.../gpu/amdgpu/display/single-display-mpo.svg | 266 +++++
Documentation/gpu/amdgpu/driver-misc.rst | 17 +
13 files changed, 3802 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/apu-asic-info-table.csv
create mode 100644 Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
create mode 100644 Documentation/gpu/amdgpu/display/mpo-cursor.svg
create mode 100644 Documentation/gpu/amdgpu/display/mpo-overview.rst
create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svg
create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo.svg
create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg
create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo-multi-video.svg
create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo.svg
--
2.35.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs
2022-08-11 15:48 [PATCH v2 0/3] Expand amdgpu documentation Rodrigo Siqueira
@ 2022-08-11 15:48 ` Rodrigo Siqueira
2022-08-11 16:02 ` Russell, Kent
2022-08-11 15:48 ` [PATCH v2 2/3] Documentation/gpu: Add an explanation about the DCN pipeline Rodrigo Siqueira
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Rodrigo Siqueira @ 2022-08-11 15:48 UTC (permalink / raw)
To: amd-gfx
Cc: Pierre-Eric Pelloux-Prayer, Mark Yacoub, Pekka Paalanen,
Michel Dänzer, Alex Hung, Harry Wentland, Leo Li, Hersen Wu,
Kent Russell, Simon Ser, Sean Paul, Bhawanpreet Lakha,
Nicholas Kazlauskas, Pierre-Loup
Amdgpu driver is used in an extensive range of devices, and each ASIC
has some specific configuration. As a result of this variety, sometimes
it is hard to identify the correct block that might cause the issue.
This commit expands the amdgpu kernel-doc to alleviate this issue by
introducing one ASIC table that describes dGPU and another one that
shares the APU info.
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Cc: Kent Russell <Kent.Russell@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../gpu/amdgpu/apu-asic-info-table.csv | 8 +++++++
.../gpu/amdgpu/dgpu-asic-info-table.csv | 24 +++++++++++++++++++
Documentation/gpu/amdgpu/driver-misc.rst | 17 +++++++++++++
3 files changed, 49 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/apu-asic-info-table.csv
create mode 100644 Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
new file mode 100644
index 000000000000..98c6988e424e
--- /dev/null
+++ b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
@@ -0,0 +1,8 @@
+Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version
+Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3
+Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
+Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
+Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
+SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
+Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
+Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
diff --git a/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
new file mode 100644
index 000000000000..84617aa35dab
--- /dev/null
+++ b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
@@ -0,0 +1,24 @@
+Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version
+AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --, 6, --, --
+AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --
+AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1
+AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1
+AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
+AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3
+AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
+Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
+Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
+Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
+Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0
+AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD 7.2.0, 4.2.0
+MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
+MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
+AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
+AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2
+AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0
+AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2
+AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
+AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
diff --git a/Documentation/gpu/amdgpu/driver-misc.rst b/Documentation/gpu/amdgpu/driver-misc.rst
index e3d6b2fa2493..1800543d45f7 100644
--- a/Documentation/gpu/amdgpu/driver-misc.rst
+++ b/Documentation/gpu/amdgpu/driver-misc.rst
@@ -32,6 +32,23 @@ unique_id
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
:doc: unique_id
+Accelerated Processing Units (APU) Info
+---------------------------------------
+
+.. csv-table::
+ :header-rows: 1
+ :widths: 3, 2, 2, 1, 1, 1
+ :file: ./apu-asic-info-table.csv
+
+Discrete GPU Info
+-----------------
+
+.. csv-table::
+ :header-rows: 1
+ :widths: 3, 2, 2, 1, 1, 1
+ :file: ./dgpu-asic-info-table.csv
+
+
GPU Memory Usage Information
============================
--
2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] Documentation/gpu: Add an explanation about the DCN pipeline
2022-08-11 15:48 [PATCH v2 0/3] Expand amdgpu documentation Rodrigo Siqueira
2022-08-11 15:48 ` [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs Rodrigo Siqueira
@ 2022-08-11 15:48 ` Rodrigo Siqueira
2022-08-11 15:48 ` [PATCH v2 3/3] Documentation/gpu: Add Multiplane Overlay doc Rodrigo Siqueira
2022-08-30 19:52 ` [PATCH v2 0/3] Expand amdgpu documentation Harry Wentland
3 siblings, 0 replies; 8+ messages in thread
From: Rodrigo Siqueira @ 2022-08-11 15:48 UTC (permalink / raw)
To: amd-gfx
Cc: Pierre-Eric Pelloux-Prayer, Mark Yacoub, Pekka Paalanen,
Michel Dänzer, Alex Hung, Harry Wentland, Leo Li, Hersen Wu,
Simon Ser, Sean Paul, Bhawanpreet Lakha, Nicholas Kazlauskas,
Pierre-Loup
In the DCN code, we constantly talk about hardware pipeline, pipeline,
or even just pipes, which is a concept that is not obvious to everyone.
For this reason, this commit expands the DCN overview explanation by
adding a new section that describes what a pipeline is from the DCN
perspective.
Changes since V1:
- Rewrite the first paragraph that describes AMD hardware pipeline.
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../gpu/amdgpu/display/dcn-overview.rst | 59 +
.../amdgpu/display/pipeline_4k_no_split.svg | 958 +++++++++++++++
.../gpu/amdgpu/display/pipeline_4k_split.svg | 1062 +++++++++++++++++
3 files changed, 2079 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg
diff --git a/Documentation/gpu/amdgpu/display/dcn-overview.rst b/Documentation/gpu/amdgpu/display/dcn-overview.rst
index f98624d7828e..9fea6500448b 100644
--- a/Documentation/gpu/amdgpu/display/dcn-overview.rst
+++ b/Documentation/gpu/amdgpu/display/dcn-overview.rst
@@ -124,6 +124,65 @@ depth format), bit-depth reduction/dithering would kick in. In OPP, we would
also apply a regamma function to introduce the gamma removed earlier back.
Eventually, we output data in integer format at DIO.
+AMD Hardware Pipeline
+---------------------
+
+When discussing graphics on Linux, the **pipeline** term can sometimes be
+overloaded with multiple meanings, so it is important to define what we mean
+when we say **pipeline**. In the DCN driver, we use the term **hardware
+pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
+sequence of DCN blocks instantiated to address some specific configuration. DC
+core treats DCN blocks as individual resources, meaning we can build a pipeline
+by taking resources for all individual hardware blocks to compose one pipeline.
+In actuality, we can't connect an arbitrary block from one pipe to a block from
+another pipe; they are routed linearly, except for DSC, which can be
+arbitrarily assigned as needed. We have this pipeline concept for trying to
+optimize bandwidth utilization.
+
+.. kernel-figure:: pipeline_4k_no_split.svg
+
+Additionally, let's take a look at parts of the DTN log (see
+'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
+this log can help us to see part of this pipeline behavior in real-time::
+
+ HUBP: format addr_hi width height ...
+ [ 0]: 8h 81h 3840 2160
+ [ 1]: 0h 0h 0 0
+ [ 2]: 0h 0h 0 0
+ [ 3]: 0h 0h 0 0
+ [ 4]: 0h 0h 0 0
+ ...
+ MPCC: OPP DPP ...
+ [ 0]: 0h 0h ...
+
+The first thing to notice from the diagram and DTN log it is the fact that we
+have different clock domains for each part of the DCN blocks. In this example,
+we have just a single **pipeline** where the data flows from DCHUB to DIO, as
+we intuitively expect. Nonetheless, DCN is flexible, as mentioned before, and
+we can split this single pipe differently, as described in the below diagram:
+
+.. kernel-figure:: pipeline_4k_split.svg
+
+Now, if we inspect the DTN log again we can see some interesting changes::
+
+ HUBP: format addr_hi width height ...
+ [ 0]: 8h 81h 1920 2160 ...
+ ...
+ [ 4]: 0h 0h 0 0 ...
+ [ 5]: 8h 81h 1920 2160 ...
+ ...
+ MPCC: OPP DPP ...
+ [ 0]: 0h 0h ...
+ [ 5]: 0h 5h ...
+
+From the above example, we now split the display pipeline into two vertical
+parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
+clock frequency in the DPP part. This is not only useful for saving power but
+also to better handle the required throughput. The idea to keep in mind here is
+that the pipe configuration can vary a lot according to the display
+configuration, and it is the DML's responsibility to set up all required
+configuration parameters for multiple scenarios supported by our hardware.
+
Global Sync
-----------
diff --git a/Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg b/Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
new file mode 100644
index 000000000000..5fa289d99fcd
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
@@ -0,0 +1,958 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!-- Created with Inkscape (http://www.inkscape.org/) -->
+
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+ xmlns:dc="http://purl.org/dc/elements/1.1/"
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+ xmlns:svg="http://www.w3.org/2000/svg"
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] Documentation/gpu: Add Multiplane Overlay doc
2022-08-11 15:48 [PATCH v2 0/3] Expand amdgpu documentation Rodrigo Siqueira
2022-08-11 15:48 ` [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs Rodrigo Siqueira
2022-08-11 15:48 ` [PATCH v2 2/3] Documentation/gpu: Add an explanation about the DCN pipeline Rodrigo Siqueira
@ 2022-08-11 15:48 ` Rodrigo Siqueira
2022-08-30 19:52 ` [PATCH v2 0/3] Expand amdgpu documentation Harry Wentland
3 siblings, 0 replies; 8+ messages in thread
From: Rodrigo Siqueira @ 2022-08-11 15:48 UTC (permalink / raw)
To: amd-gfx
Cc: Pierre-Eric Pelloux-Prayer, Mark Yacoub, Pekka Paalanen,
Michel Dänzer, Alex Hung, Harry Wentland, Leo Li, Hersen Wu,
Simon Ser, Sean Paul, Bhawanpreet Lakha, Nicholas Kazlauskas,
Pierre-Loup
Multiple plane overlay is a feature supported by AMD hardware, but it
has specific details that deserve proper documentation. This commit
introduces a documentation that describes some of the features,
limitations, and use cases for this feature. Part of this documentation
came from some discussion in the public upstream [1][2].
[1]. https://lore.kernel.org/amd-gfx/3qY-QeukF_Q_MJeIXAuBjO4szbS4jRtqkTifXnbnN3bp88SxVodFQRpah3mIIVJq24DUkF6g0rOGdCmSqTvVxx9LCGEItmzLw8uWU44jtXE=@emersion.fr/
[2]. https://lore.kernel.org/amd-gfx/864e45d0-c14b-3b12-0f5b-9d26a9cb41bd@amd.com/
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: Simon Ser <contact@emersion.fr>
Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Pierre-Loup <pgriffais@valvesoftware.com>
Cc: Michel Dänzer <michel.daenzer@mailbox.org>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
Documentation/gpu/amdgpu/display/index.rst | 1 +
.../gpu/amdgpu/display/mpo-cursor.svg | 435 ++++++++++++++++++
.../gpu/amdgpu/display/mpo-overview.rst | 242 ++++++++++
.../multi-display-hdcp-mpo-less-pipe-ex.svg | 220 +++++++++
.../amdgpu/display/multi-display-hdcp-mpo.svg | 171 +++++++
.../single-display-mpo-multi-video.svg | 339 ++++++++++++++
.../gpu/amdgpu/display/single-display-mpo.svg | 266 +++++++++++
7 files changed, 1674 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/display/mpo-cursor.svg
create mode 100644 Documentation/gpu/amdgpu/display/mpo-overview.rst
create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svg
create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo.svg
create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo-multi-video.svg
create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo.svg
diff --git a/Documentation/gpu/amdgpu/display/index.rst b/Documentation/gpu/amdgpu/display/index.rst
index c1fb2fb3c710..f8a4f53d70d8 100644
--- a/Documentation/gpu/amdgpu/display/index.rst
+++ b/Documentation/gpu/amdgpu/display/index.rst
@@ -28,4 +28,5 @@ table of content:
display-manager.rst
dc-debug.rst
dcn-overview.rst
+ mpo-overview.rst
dc-glossary.rst
diff --git a/Documentation/gpu/amdgpu/display/mpo-cursor.svg b/Documentation/gpu/amdgpu/display/mpo-cursor.svg
new file mode 100644
index 000000000000..9d9de76847c3
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diff --git a/Documentation/gpu/amdgpu/display/mpo-overview.rst b/Documentation/gpu/amdgpu/display/mpo-overview.rst
new file mode 100644
index 000000000000..0499aa92d08d
--- /dev/null
+++ b/Documentation/gpu/amdgpu/display/mpo-overview.rst
@@ -0,0 +1,242 @@
+========================
+Multiplane Overlay (MPO)
+========================
+
+.. note:: You will get more from this page if you have already read the
+ 'Documentation/gpu/amdgpu/display/dcn-overview.rst'.
+
+
+Multiplane Overlay (MPO) allows for multiple framebuffers to be composited via
+fixed-function hardware in the display controller rather than using graphics or
+compute shaders for composition. This can yield some power savings if it means
+the graphics/compute pipelines can be put into low-power states. In summary,
+MPO can bring the following benefits:
+
+* Decreased GPU and CPU workload - no composition shaders needed, no extra
+ buffer copy needed, GPU can remain idle.
+* Plane independent page flips - No need to be tied to global compositor
+ page-flip present rate, reduced latency, independent timing.
+
+.. note:: Keep in mind that MPO is all about power-saving; if you want to learn
+ more about power-save in the display context, check the link:
+ `Power <https://gitlab.freedesktop.org/pq/color-and-hdr/-/blob/main/doc/power.rst>`__.
+
+Multiplane Overlay is only available using the DRM atomic model. The atomic
+model only uses a single userspace IOCTL for configuring the display hardware
+(modesetting, page-flipping, etc) - drmModeAtomicCommit. To query hardware
+resources and limitations userspace also calls into drmModeGetResources which
+reports back the number of planes, CRTCs, and connectors. There are three types
+of DRM planes that the driver can register and work with:
+
+* ``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a
+ CRTC, primary planes are the planes operated upon by CRTC modesetting and
+ flipping operations.
+* ``DRM_PLANE_TYPE_CURSOR``: Cursor planes represent a "cursor" plane for a
+ CRTC. Cursor planes are the planes operated upon by the cursor IOCTLs
+* ``DRM_PLANE_TYPE_OVERLAY``: Overlay planes represent all non-primary,
+ non-cursor planes. Some drivers refer to these types of planes as "sprites"
+ internally.
+
+To illustrate how it works, let's take a look at a device that exposes the
+following planes to userspace:
+
+* 4 Primary planes (1 per CRTC).
+* 4 Cursor planes (1 per CRTC).
+* 1 Overlay plane (shared among CRTCs).
+
+.. note:: Keep in mind that different ASICs might expose other numbers of
+ planes.
+
+For this hardware example, we have 4 pipes (if you don't know what AMD pipe
+means, look at 'Documentation/gpu/amdgpu/display/dcn-overview.rst', section
+"AMD Hardware Pipeline"). Typically most AMD devices operate in a pipe-split
+configuration for optimal single display output (e.g., 2 pipes per plane).
+
+A typical MPO configuration from userspace - 1 primary + 1 overlay on a single
+display - will see 4 pipes in use, 2 per plane.
+
+At least 1 pipe must be used per plane (primary and overlay), so for this
+hypothetical hardware that we are using as an example, we have an absolute
+limit of 4 planes across all CRTCs. Atomic commits will be rejected for display
+configurations using more than 4 planes. Again, it is important to stress that
+every DCN has different restrictions; here, we are just trying to provide the
+concept idea.
+
+Plane Restrictions
+==================
+
+AMDGPU imposes restrictions on the use of DRM planes in the driver.
+
+Atomic commits will be rejected for commits which do not follow these
+restrictions:
+
+* Overlay planes must be in ARGB8888 or XRGB8888 format
+* Planes cannot be placed outside of the CRTC destination rectangle
+* Planes cannot be downscaled more than 1/4x of their original size
+* Planes cannot be upscaled more than 16x of their original size
+
+Not every property is available on every plane:
+
+* Only primary planes have color-space and non-RGB format support
+* Only overlay planes have alpha blending support
+
+Cursor Restrictions
+===================
+
+Before we start to describe some restrictions around cursor and MPO, see the
+below image:
+
+.. kernel-figure:: mpo-cursor.svg
+
+The image on the left side represents how DRM expects the cursor and planes to
+be blended. However, AMD hardware handles cursors differently, as you can see
+on the right side; basically, our cursor cannot be drawn outside its associated
+plane as it is being treated as part of the plane. Another consequence of that
+is that cursors inherit the color and scale from the plane.
+
+As a result of the above behavior, do not use legacy API to set up the cursor
+plane when working with MPO; otherwise, you might encounter unexpected
+behavior.
+
+In short, AMD HW has no dedicated cursor planes. A cursor is attached to
+another plane and therefore inherits any scaling or color processing from its
+parent plane.
+
+Use Cases
+=========
+
+Picture-in-Picture (PIP) playback - Underlay strategy
+-----------------------------------------------------
+
+Video playback should be done using the "primary plane as underlay" MPO
+strategy. This is a 2 planes configuration:
+
+* 1 YUV DRM Primary Plane (e.g. NV12 Video)
+* 1 RGBA DRM Overlay Plane (e.g. ARGB8888 desktop). The compositor should
+ prepare the framebuffers for the planes as follows:
+ - The overlay plane contains general desktop UI, video player controls, and video subtitles
+ - Primary plane contains one or more videos
+
+.. note:: Keep in mind that we could extend this configuration to more planes,
+ but that is currently not supported by our driver yet (maybe if we have a
+ userspace request in the future, we can change that).
+
+See below a single-video example:
+
+.. kernel-figure:: single-display-mpo.svg
+
+.. note:: We could extend this behavior to more planes, but that is currently
+ not supported by our driver.
+
+The video buffer should be used directly for the primary plane. The video can
+be scaled and positioned for the desktop using the properties: CRTC_X, CRTC_Y,
+CRTC_W, and CRTC_H. The primary plane should also have the color encoding and
+color range properties set based on the source content:
+
+* ``COLOR_RANGE``, ``COLOR_ENCODING``
+
+The overlay plane should be the native size of the CRTC. The compositor must
+draw a transparent cutout for where the video should be placed on the desktop
+(i.e., set the alpha to zero). The primary plane video will be visible through
+the underlay. The overlay plane's buffer may remain static while the primary
+plane's framebuffer is used for standard double-buffered playback.
+
+The compositor should create a YUV buffer matching the native size of the CRTC.
+Each video buffer should be composited onto this YUV buffer for direct YUV
+scanout. The primary plane should have the color encoding and color range
+properties set based on the source content: ``COLOR_RANGE``,
+``COLOR_ENCODING``. However, be mindful that the source color space and
+encoding match for each video since it affect the entire plane.
+
+The overlay plane should be the native size of the CRTC. The compositor must
+draw a transparent cutout for where each video should be placed on the desktop
+(i.e., set the alpha to zero). The primary plane videos will be visible through
+the underlay. The overlay plane's buffer may remain static while compositing
+operations for video playback will be done on the video buffer.
+
+This kernel interface is validated using IGT GPU Tools. The following tests can
+be run to validate positioning, blending, scaling under a variety of sequences
+and interactions with operations such as DPMS and S3:
+
+- ``kms_plane@plane-panning-bottom-right-pipe-*-planes``
+- ``kms_plane@plane-panning-bottom-right-suspend-pipe-*-``
+- ``kms_plane@plane-panning-top-left-pipe-*-``
+- ``kms_plane@plane-position-covered-pipe-*-``
+- ``kms_plane@plane-position-hole-dpms-pipe-*-``
+- ``kms_plane@plane-position-hole-pipe-*-``
+- ``kms_plane_multiple@atomic-pipe-*-tiling-``
+- ``kms_plane_scaling@pipe-*-plane-scaling``
+- ``kms_plane_alpha_blend@pipe-*-alpha-basic``
+- ``kms_plane_alpha_blend@pipe-*-alpha-transparant-fb``
+- ``kms_plane_alpha_blend@pipe-*-alpha-opaque-fb``
+- ``kms_plane_alpha_blend@pipe-*-constant-alpha-min``
+- ``kms_plane_alpha_blend@pipe-*-constant-alpha-mid``
+- ``kms_plane_alpha_blend@pipe-*-constant-alpha-max``
+
+Multiple Display MPO
+--------------------
+
+AMDGPU supports display MPO when using multiple displays; however, this feature
+behavior heavily relies on the compositor implementation. Keep in mind that
+usespace can define different policies. For example, some OSes can use MPO to
+protect the plane that handles the video playback; notice that we don't have
+many limitations for a single display. Nonetheless, this manipulation can have
+many more restrictions for a multi-display scenario. The below example shows a
+video playback in the middle of two displays, and it is up to the compositor to
+define a policy on how to handle it:
+
+.. kernel-figure:: multi-display-hdcp-mpo.svg
+
+Let's discuss some of the hardware limitations we have when dealing with
+multi-display with MPO.
+
+Limitations
+~~~~~~~~~~~
+
+For simplicity's sake, for discussing the hardware limitation, this
+documentation supposes an example where we have two displays and video playback
+that will be moved around different displays.
+
+* **Hardware limitations**
+
+From the DCN overview page, each display requires at least one pipe and each
+MPO plane needs another pipe. As a result, when the video is in the middle of
+the two displays, we need to use 2 pipes. See the example below where we avoid
+pipe split:
+
+- 1 display (1 pipe) + MPO (1 pipe), we will use two pipes
+- 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the
+ middle of both displays needs 2 pipes.
+- 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.
+
+If we use MPO with multiple displays, the userspace has to decide to enable
+multiple MPO by the price of limiting the number of external displays supported
+or disable it in favor of multiple displays; it is a policy decision. For
+example:
+
+* When ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO
+* When ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO
+
+Let's briefly explore how userspace can handle these two display configurations
+on an ASIC that only supports three pipes. We can have:
+
+.. kernel-figure:: multi-display-hdcp-mpo-less-pipe-ex.svg
+
+- Total pipes are 3
+- User lights up 2 displays (2 out of 3 pipes are used)
+- User launches video (1 pipe used for MPO)
+- Now, if the user moves the video in the middle of 2 displays, one part of the
+ video won't be MPO since we have used 3/3 pipes.
+
+* **Scaling limitation**
+
+MPO cannot handle scaling less than 0.25 and more than x16. For example:
+
+If 4k video (3840x2160) is playing in windowed mode, the physical size of the
+window cannot be smaller than (960x540).
+
+.. note:: These scaling limitations might vary from ASIC to ASIC.
+
+* **Size Limitation**
+
+The minimum MPO size is 12px.
diff --git a/Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svg b/Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svg
new file mode 100644
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2.35.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* RE: [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs
2022-08-11 15:48 ` [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs Rodrigo Siqueira
@ 2022-08-11 16:02 ` Russell, Kent
2022-08-11 19:45 ` Rodrigo Siqueira Jordao
0 siblings, 1 reply; 8+ messages in thread
From: Russell, Kent @ 2022-08-11 16:02 UTC (permalink / raw)
To: Siqueira, Rodrigo, amd-gfx@lists.freedesktop.org
Cc: Pelloux-Prayer, Pierre-Eric, Mark Yacoub, Pekka Paalanen,
Michel Dänzer, Hung, Alex, Wentland, Harry,
Li, Sun peng (Leo), Wu, Hersen, Simon Ser, Sean Paul,
Lakha, Bhawanpreet, Kazlauskas, Nicholas, Pierre-Loup
[AMD Official Use Only - General]
I noticed that you added DCE and VCE/UVD prefixes in the columns, but not GC or SDMA.
E.g.
CHIP DCE GC VCE SDMA
BONAIRE DCE 8 7 VCE 2 / UVD 4.2 1
For consistency, should we drop the DCE/VCE/UVD prefixes and add a separate UVD column, so it's just:
CHIP DCE GC VCE UVD SDMA
BONAIRE 8 7 VCE 2 4.2 1
? I know that from a compute perspective, I'd like to have the columns represent the fields, so there's less to parse through, but I am not a display guy so the DCE/VCE/UVD relationship is a mystery to me.
Also, for VG10 you have SDMA 4.0.0, but Polaris it's SDMA 3 . Again, just consistency with trailing decimals. I don't know if that's just because we didn't do point releases on SDMA <4 or whatnot, but it's something I observed.
I am not staunchly steadfast one way or another, I just wanted to hear rationale for it. Especially if we're maintaining it going forward, and for when someone inevitably starts parsing it via automated script and needs consistency. If you're confident in the format and can justify it, then that's sufficient for me.
Kent
> -----Original Message-----
> From: Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>
> Sent: Thursday, August 11, 2022 11:48 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wentland, Harry <Harry.Wentland@amd.com>; Kazlauskas, Nicholas
> <Nicholas.Kazlauskas@amd.com>; Lakha, Bhawanpreet
> <Bhawanpreet.Lakha@amd.com>; Wu, Hersen <hersenxs.wu@amd.com>;
> Hung, Alex <Alex.Hung@amd.com>; Pelloux-Prayer, Pierre-Eric <Pierre-
> eric.Pelloux-prayer@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>;
> Simon Ser <contact@emersion.fr>; Pekka Paalanen
> <pekka.paalanen@collabora.com>; Sean Paul <seanpaul@chromium.org>; Mark
> Yacoub <markyacoub@chromium.org>; Pierre-Loup
> <pgriffais@valvesoftware.com>; Michel Dänzer
> <michel.daenzer@mailbox.org>; Russell, Kent <Kent.Russell@amd.com>
> Subject: [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs
>
> Amdgpu driver is used in an extensive range of devices, and each ASIC
> has some specific configuration. As a result of this variety, sometimes
> it is hard to identify the correct block that might cause the issue.
> This commit expands the amdgpu kernel-doc to alleviate this issue by
> introducing one ASIC table that describes dGPU and another one that
> shares the APU info.
>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> Cc: Hersen Wu <hersenxs.wu@amd.com>
> Cc: Alex Hung <alex.hung@amd.com>
> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> Cc: Leo Li <sunpeng.li@amd.com>
> Cc: Simon Ser <contact@emersion.fr>
> Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Mark Yacoub <markyacoub@chromium.org>
> Cc: Pierre-Loup <pgriffais@valvesoftware.com>
> Cc: Michel Dänzer <michel.daenzer@mailbox.org>
> Cc: Kent Russell <Kent.Russell@amd.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> .../gpu/amdgpu/apu-asic-info-table.csv | 8 +++++++
> .../gpu/amdgpu/dgpu-asic-info-table.csv | 24 +++++++++++++++++++
> Documentation/gpu/amdgpu/driver-misc.rst | 17 +++++++++++++
> 3 files changed, 49 insertions(+)
> create mode 100644 Documentation/gpu/amdgpu/apu-asic-info-table.csv
> create mode 100644 Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
>
> diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> new file mode 100644
> index 000000000000..98c6988e424e
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> @@ -0,0 +1,8 @@
> +Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN
> version, SDMA version
> +Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3
> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
> RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
> +Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
> RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
> +SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
> +Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
> +Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
> diff --git a/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
> b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
> new file mode 100644
> index 000000000000..84617aa35dab
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
> @@ -0,0 +1,24 @@
> +Product Name, Code Reference, DCN/DCE version, GC version, VCN version,
> SDMA version
> +AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series,
> HAINAN, --, 6, --, --
> +AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
> +AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND,
> DCE 6, 6, VCE 1 / UVD 3, --
> +AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN,
> DCE 6, 6, VCE 1 / UVD 3, --
> +AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M)
> /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --
> +AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE
> 2 / UVD 4.2, 1
> +AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE
> 2 / UVD 4.2, 1
> +AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
> +AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA,
> DCE 10, 8, VCE 3 / UVD 5, 3
> +AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
> +Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100
> /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 /
> UVD 6.3, 3
> +Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11,
> DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
> +Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series,
> POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
> +Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG
> MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0
> +AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD
> 7.2.0, 4.2.0
> +MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
> +MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
> +AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN
> 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
> +AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14,
> DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2
> +AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0,
> 10.3.0, VCN 3.0.0, 5.2.0
> +AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0,
> 10.3.2, VCN 3.0.0, 5.2.2
> +AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH,
> DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
> +AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN
> 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
> diff --git a/Documentation/gpu/amdgpu/driver-misc.rst
> b/Documentation/gpu/amdgpu/driver-misc.rst
> index e3d6b2fa2493..1800543d45f7 100644
> --- a/Documentation/gpu/amdgpu/driver-misc.rst
> +++ b/Documentation/gpu/amdgpu/driver-misc.rst
> @@ -32,6 +32,23 @@ unique_id
> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> :doc: unique_id
>
> +Accelerated Processing Units (APU) Info
> +---------------------------------------
> +
> +.. csv-table::
> + :header-rows: 1
> + :widths: 3, 2, 2, 1, 1, 1
> + :file: ./apu-asic-info-table.csv
> +
> +Discrete GPU Info
> +-----------------
> +
> +.. csv-table::
> + :header-rows: 1
> + :widths: 3, 2, 2, 1, 1, 1
> + :file: ./dgpu-asic-info-table.csv
> +
> +
> GPU Memory Usage Information
> ============================
>
> --
> 2.35.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs
2022-08-11 16:02 ` Russell, Kent
@ 2022-08-11 19:45 ` Rodrigo Siqueira Jordao
2022-08-16 13:06 ` Alex Deucher
0 siblings, 1 reply; 8+ messages in thread
From: Rodrigo Siqueira Jordao @ 2022-08-11 19:45 UTC (permalink / raw)
To: Russell, Kent, amd-gfx@lists.freedesktop.org, Deucher, Alexander
Cc: Pelloux-Prayer, Pierre-Eric, Mark Yacoub, Pekka Paalanen,
Michel Dänzer, Hung, Alex, Wentland, Harry,
Li, Sun peng (Leo), Wu, Hersen, Simon Ser, Sean Paul,
Lakha, Bhawanpreet, Kazlauskas, Nicholas, Pierre-Loup
Hi Kent,
First of all, thanks for your feedback.
See my comments inline.
On 2022-08-11 12:02, Russell, Kent wrote:
> [AMD Official Use Only - General]
>
> I noticed that you added DCE and VCE/UVD prefixes in the columns, but not GC or SDMA.
> E.g.
> CHIP DCE GC VCE SDMA
> BONAIRE DCE 8 7 VCE 2 / UVD 4.2 1
>
Are you referencing when I added it in some specific lines? If so, I
added it because we may have a different architecture for the same area.
For example, DCE is our old display architecture, and we replaced it
with DCN. That's why I added DCE/DCN in the label, and in the ASIC
description, I specify if it is a DCE or DCN.
> For consistency, should we drop the DCE/VCE/UVD prefixes and add a separate UVD column, so it's just:
Iirc UVD is the previous version of VCE; in that case, I think they
should be grouped. Or is UVD a different component?
> CHIP DCE GC VCE UVD SDMA
> BONAIRE 8 7 VCE 2 4.2 1
> ? I know that from a compute perspective, I'd like to have the columns represent the fields, so there's less to parse through, but I am not a display guy so the DCE/VCE/UVD relationship is a mystery to me.
>
> Also, for VG10 you have SDMA 4.0.0, but Polaris it's SDMA 3 . Again, just consistency with trailing decimals. I don't know if that's just because we didn't do point releases on SDMA <4 or whatnot, but it's something I observed.
I also don't know if we have a good reason for not using the decimal
part, but I can add it to all components if it makes sense. Maybe Alex know?
Thanks
Siqueira
>
> I am not staunchly steadfast one way or another, I just wanted to hear rationale for it. Especially if we're maintaining it going forward, and for when someone inevitably starts parsing it via automated script and needs consistency. If you're confident in the format and can justify it, then that's sufficient for me.
>
> Kent
>
>> -----Original Message-----
>> From: Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>
>> Sent: Thursday, August 11, 2022 11:48 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Wentland, Harry <Harry.Wentland@amd.com>; Kazlauskas, Nicholas
>> <Nicholas.Kazlauskas@amd.com>; Lakha, Bhawanpreet
>> <Bhawanpreet.Lakha@amd.com>; Wu, Hersen <hersenxs.wu@amd.com>;
>> Hung, Alex <Alex.Hung@amd.com>; Pelloux-Prayer, Pierre-Eric <Pierre-
>> eric.Pelloux-prayer@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>;
>> Simon Ser <contact@emersion.fr>; Pekka Paalanen
>> <pekka.paalanen@collabora.com>; Sean Paul <seanpaul@chromium.org>; Mark
>> Yacoub <markyacoub@chromium.org>; Pierre-Loup
>> <pgriffais@valvesoftware.com>; Michel Dänzer
>> <michel.daenzer@mailbox.org>; Russell, Kent <Kent.Russell@amd.com>
>> Subject: [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs
>>
>> Amdgpu driver is used in an extensive range of devices, and each ASIC
>> has some specific configuration. As a result of this variety, sometimes
>> it is hard to identify the correct block that might cause the issue.
>> This commit expands the amdgpu kernel-doc to alleviate this issue by
>> introducing one ASIC table that describes dGPU and another one that
>> shares the APU info.
>>
>> Cc: Harry Wentland <harry.wentland@amd.com>
>> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
>> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
>> Cc: Hersen Wu <hersenxs.wu@amd.com>
>> Cc: Alex Hung <alex.hung@amd.com>
>> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>> Cc: Leo Li <sunpeng.li@amd.com>
>> Cc: Simon Ser <contact@emersion.fr>
>> Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
>> Cc: Sean Paul <seanpaul@chromium.org>
>> Cc: Mark Yacoub <markyacoub@chromium.org>
>> Cc: Pierre-Loup <pgriffais@valvesoftware.com>
>> Cc: Michel Dänzer <michel.daenzer@mailbox.org>
>> Cc: Kent Russell <Kent.Russell@amd.com>
>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>> ---
>> .../gpu/amdgpu/apu-asic-info-table.csv | 8 +++++++
>> .../gpu/amdgpu/dgpu-asic-info-table.csv | 24 +++++++++++++++++++
>> Documentation/gpu/amdgpu/driver-misc.rst | 17 +++++++++++++
>> 3 files changed, 49 insertions(+)
>> create mode 100644 Documentation/gpu/amdgpu/apu-asic-info-table.csv
>> create mode 100644 Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
>>
>> diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv
>> b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
>> new file mode 100644
>> index 000000000000..98c6988e424e
>> --- /dev/null
>> +++ b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
>> @@ -0,0 +1,8 @@
>> +Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN
>> version, SDMA version
>> +Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3
>> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
>> RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
>> +Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
>> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
>> RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
>> +SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
>> +Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
>> +Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
>> diff --git a/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
>> b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
>> new file mode 100644
>> index 000000000000..84617aa35dab
>> --- /dev/null
>> +++ b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
>> @@ -0,0 +1,24 @@
>> +Product Name, Code Reference, DCN/DCE version, GC version, VCN version,
>> SDMA version
>> +AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series,
>> HAINAN, --, 6, --, --
>> +AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
>> +AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND,
>> DCE 6, 6, VCE 1 / UVD 3, --
>> +AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN,
>> DCE 6, 6, VCE 1 / UVD 3, --
>> +AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M)
>> /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --
>> +AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE
>> 2 / UVD 4.2, 1
>> +AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE
>> 2 / UVD 4.2, 1
>> +AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
>> +AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA,
>> DCE 10, 8, VCE 3 / UVD 5, 3
>> +AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
>> +Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100
>> /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 /
>> UVD 6.3, 3
>> +Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11,
>> DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
>> +Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series,
>> POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
>> +Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG
>> MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0
>> +AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD
>> 7.2.0, 4.2.0
>> +MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
>> +MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
>> +AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN
>> 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
>> +AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14,
>> DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2
>> +AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0,
>> 10.3.0, VCN 3.0.0, 5.2.0
>> +AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0,
>> 10.3.2, VCN 3.0.0, 5.2.2
>> +AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH,
>> DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
>> +AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN
>> 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
>> diff --git a/Documentation/gpu/amdgpu/driver-misc.rst
>> b/Documentation/gpu/amdgpu/driver-misc.rst
>> index e3d6b2fa2493..1800543d45f7 100644
>> --- a/Documentation/gpu/amdgpu/driver-misc.rst
>> +++ b/Documentation/gpu/amdgpu/driver-misc.rst
>> @@ -32,6 +32,23 @@ unique_id
>> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
>> :doc: unique_id
>>
>> +Accelerated Processing Units (APU) Info
>> +---------------------------------------
>> +
>> +.. csv-table::
>> + :header-rows: 1
>> + :widths: 3, 2, 2, 1, 1, 1
>> + :file: ./apu-asic-info-table.csv
>> +
>> +Discrete GPU Info
>> +-----------------
>> +
>> +.. csv-table::
>> + :header-rows: 1
>> + :widths: 3, 2, 2, 1, 1, 1
>> + :file: ./dgpu-asic-info-table.csv
>> +
>> +
>> GPU Memory Usage Information
>> ============================
>>
>> --
>> 2.35.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs
2022-08-11 19:45 ` Rodrigo Siqueira Jordao
@ 2022-08-16 13:06 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2022-08-16 13:06 UTC (permalink / raw)
To: Rodrigo Siqueira Jordao
Cc: Pelloux-Prayer, Pierre-Eric, Pekka Paalanen, Michel Dänzer,
Hung, Alex, Mark Yacoub, amd-gfx@lists.freedesktop.org,
Lakha, Bhawanpreet, Li, Sun peng (Leo), Wu, Hersen, Russell, Kent,
Simon Ser, Deucher, Alexander, Sean Paul, Wentland, Harry,
Kazlauskas, Nicholas, Pierre-Loup
On Thu, Aug 11, 2022 at 3:45 PM Rodrigo Siqueira Jordao
<Rodrigo.Siqueira@amd.com> wrote:
>
> Hi Kent,
>
> First of all, thanks for your feedback.
> See my comments inline.
>
> On 2022-08-11 12:02, Russell, Kent wrote:
> > [AMD Official Use Only - General]
> >
> > I noticed that you added DCE and VCE/UVD prefixes in the columns, but not GC or SDMA.
> > E.g.
> > CHIP DCE GC VCE SDMA
> > BONAIRE DCE 8 7 VCE 2 / UVD 4.2 1
> >
>
> Are you referencing when I added it in some specific lines? If so, I
> added it because we may have a different architecture for the same area.
> For example, DCE is our old display architecture, and we replaced it
> with DCN. That's why I added DCE/DCN in the label, and in the ASIC
> description, I specify if it is a DCE or DCN.
>
> > For consistency, should we drop the DCE/VCE/UVD prefixes and add a separate UVD column, so it's just:
>
> Iirc UVD is the previous version of VCE; in that case, I think they
> should be grouped. Or is UVD a different component?
DCE was the old display IP and it was replaced with DCN. UVD/VCE
where the old video decode/encode IPs and they were replaced with VCN.
>
> > CHIP DCE GC VCE UVD SDMA
> > BONAIRE 8 7 VCE 2 4.2 1
> > ? I know that from a compute perspective, I'd like to have the columns represent the fields, so there's less to parse through, but I am not a display guy so the DCE/VCE/UVD relationship is a mystery to me.
> >
> > Also, for VG10 you have SDMA 4.0.0, but Polaris it's SDMA 3 . Again, just consistency with trailing decimals. I don't know if that's just because we didn't do point releases on SDMA <4 or whatnot, but it's something I observed.
>
> I also don't know if we have a good reason for not using the decimal
> part, but I can add it to all components if it makes sense. Maybe Alex know?
The old parts didn't really have well enumerated IP minor versions
like we do today. We could make up minor/rev numbers, but we don't
really have them in most cases. We could do something like 8.x or 7.x
if you think that is clearer.
Alex
>
> Thanks
> Siqueira
>
> >
> > I am not staunchly steadfast one way or another, I just wanted to hear rationale for it. Especially if we're maintaining it going forward, and for when someone inevitably starts parsing it via automated script and needs consistency. If you're confident in the format and can justify it, then that's sufficient for me.
> >
> > Kent
> >
> >> -----Original Message-----
> >> From: Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>
> >> Sent: Thursday, August 11, 2022 11:48 AM
> >> To: amd-gfx@lists.freedesktop.org
> >> Cc: Wentland, Harry <Harry.Wentland@amd.com>; Kazlauskas, Nicholas
> >> <Nicholas.Kazlauskas@amd.com>; Lakha, Bhawanpreet
> >> <Bhawanpreet.Lakha@amd.com>; Wu, Hersen <hersenxs.wu@amd.com>;
> >> Hung, Alex <Alex.Hung@amd.com>; Pelloux-Prayer, Pierre-Eric <Pierre-
> >> eric.Pelloux-prayer@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>;
> >> Simon Ser <contact@emersion.fr>; Pekka Paalanen
> >> <pekka.paalanen@collabora.com>; Sean Paul <seanpaul@chromium.org>; Mark
> >> Yacoub <markyacoub@chromium.org>; Pierre-Loup
> >> <pgriffais@valvesoftware.com>; Michel Dänzer
> >> <michel.daenzer@mailbox.org>; Russell, Kent <Kent.Russell@amd.com>
> >> Subject: [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs
> >>
> >> Amdgpu driver is used in an extensive range of devices, and each ASIC
> >> has some specific configuration. As a result of this variety, sometimes
> >> it is hard to identify the correct block that might cause the issue.
> >> This commit expands the amdgpu kernel-doc to alleviate this issue by
> >> introducing one ASIC table that describes dGPU and another one that
> >> shares the APU info.
> >>
> >> Cc: Harry Wentland <harry.wentland@amd.com>
> >> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> >> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> >> Cc: Hersen Wu <hersenxs.wu@amd.com>
> >> Cc: Alex Hung <alex.hung@amd.com>
> >> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> >> Cc: Leo Li <sunpeng.li@amd.com>
> >> Cc: Simon Ser <contact@emersion.fr>
> >> Cc: Pekka Paalanen <pekka.paalanen@collabora.com>
> >> Cc: Sean Paul <seanpaul@chromium.org>
> >> Cc: Mark Yacoub <markyacoub@chromium.org>
> >> Cc: Pierre-Loup <pgriffais@valvesoftware.com>
> >> Cc: Michel Dänzer <michel.daenzer@mailbox.org>
> >> Cc: Kent Russell <Kent.Russell@amd.com>
> >> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> >> ---
> >> .../gpu/amdgpu/apu-asic-info-table.csv | 8 +++++++
> >> .../gpu/amdgpu/dgpu-asic-info-table.csv | 24 +++++++++++++++++++
> >> Documentation/gpu/amdgpu/driver-misc.rst | 17 +++++++++++++
> >> 3 files changed, 49 insertions(+)
> >> create mode 100644 Documentation/gpu/amdgpu/apu-asic-info-table.csv
> >> create mode 100644 Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
> >>
> >> diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> >> b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> >> new file mode 100644
> >> index 000000000000..98c6988e424e
> >> --- /dev/null
> >> +++ b/Documentation/gpu/amdgpu/apu-asic-info-table.csv
> >> @@ -0,0 +1,8 @@
> >> +Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN
> >> version, SDMA version
> >> +Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3
> >> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
> >> RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
> >> +Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
> >> +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx,
> >> RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
> >> +SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
> >> +Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
> >> +Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
> >> diff --git a/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
> >> b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
> >> new file mode 100644
> >> index 000000000000..84617aa35dab
> >> --- /dev/null
> >> +++ b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
> >> @@ -0,0 +1,24 @@
> >> +Product Name, Code Reference, DCN/DCE version, GC version, VCN version,
> >> SDMA version
> >> +AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series,
> >> HAINAN, --, 6, --, --
> >> +AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
> >> +AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND,
> >> DCE 6, 6, VCE 1 / UVD 3, --
> >> +AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN,
> >> DCE 6, 6, VCE 1 / UVD 3, --
> >> +AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M)
> >> /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --
> >> +AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE
> >> 2 / UVD 4.2, 1
> >> +AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE
> >> 2 / UVD 4.2, 1
> >> +AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
> >> +AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA,
> >> DCE 10, 8, VCE 3 / UVD 5, 3
> >> +AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
> >> +Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100
> >> /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 /
> >> UVD 6.3, 3
> >> +Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11,
> >> DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
> >> +Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series,
> >> POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3
> >> +Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG
> >> MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0
> >> +AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD
> >> 7.2.0, 4.2.0
> >> +MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
> >> +MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
> >> +AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN
> >> 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
> >> +AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14,
> >> DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2
> >> +AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0,
> >> 10.3.0, VCN 3.0.0, 5.2.0
> >> +AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0,
> >> 10.3.2, VCN 3.0.0, 5.2.2
> >> +AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH,
> >> DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
> >> +AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN
> >> 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
> >> diff --git a/Documentation/gpu/amdgpu/driver-misc.rst
> >> b/Documentation/gpu/amdgpu/driver-misc.rst
> >> index e3d6b2fa2493..1800543d45f7 100644
> >> --- a/Documentation/gpu/amdgpu/driver-misc.rst
> >> +++ b/Documentation/gpu/amdgpu/driver-misc.rst
> >> @@ -32,6 +32,23 @@ unique_id
> >> .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> >> :doc: unique_id
> >>
> >> +Accelerated Processing Units (APU) Info
> >> +---------------------------------------
> >> +
> >> +.. csv-table::
> >> + :header-rows: 1
> >> + :widths: 3, 2, 2, 1, 1, 1
> >> + :file: ./apu-asic-info-table.csv
> >> +
> >> +Discrete GPU Info
> >> +-----------------
> >> +
> >> +.. csv-table::
> >> + :header-rows: 1
> >> + :widths: 3, 2, 2, 1, 1, 1
> >> + :file: ./dgpu-asic-info-table.csv
> >> +
> >> +
> >> GPU Memory Usage Information
> >> ============================
> >>
> >> --
> >> 2.35.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/3] Expand amdgpu documentation
2022-08-11 15:48 [PATCH v2 0/3] Expand amdgpu documentation Rodrigo Siqueira
` (2 preceding siblings ...)
2022-08-11 15:48 ` [PATCH v2 3/3] Documentation/gpu: Add Multiplane Overlay doc Rodrigo Siqueira
@ 2022-08-30 19:52 ` Harry Wentland
3 siblings, 0 replies; 8+ messages in thread
From: Harry Wentland @ 2022-08-30 19:52 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx
On 2022-08-11 11:48, Rodrigo Siqueira wrote:
> This patchset introduces some new AMDGPU documentation. You will find:
>
> 1. A CSV table that maps which component version is part of some ASIC
> families. This can be useful to narrow down bugs;
> 2. Some explanation about AMD Display Pipeline;
> 3. An explanation of Multiple Plane Overlay, which can be useful for
> userspace applications.
>
> Since we have some diagrams, I recommend applying these patches and
> building the documentation to have a better experience.
>
> In this new version, I just rebased this patchset with the latest code
> from amd-staging-drm-next, and I also changed patch 2.
>
> Thanks
> Siqueira
This set looks good to me and should hopefully help others when
digging into the AMD display driver.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
>
> Rodrigo Siqueira (3):
> Documentation/gpu: Add info table for ASICs
> Documentation/gpu: Add an explanation about the DCN pipeline
> Documentation/gpu: Add Multiplane Overlay doc
>
> .../gpu/amdgpu/apu-asic-info-table.csv | 8 +
> .../gpu/amdgpu/dgpu-asic-info-table.csv | 24 +
> .../gpu/amdgpu/display/dcn-overview.rst | 59 +
> Documentation/gpu/amdgpu/display/index.rst | 1 +
> .../gpu/amdgpu/display/mpo-cursor.svg | 435 +++++++
> .../gpu/amdgpu/display/mpo-overview.rst | 242 ++++
> .../multi-display-hdcp-mpo-less-pipe-ex.svg | 220 ++++
> .../amdgpu/display/multi-display-hdcp-mpo.svg | 171 +++
> .../amdgpu/display/pipeline_4k_no_split.svg | 958 +++++++++++++++
> .../gpu/amdgpu/display/pipeline_4k_split.svg | 1062 +++++++++++++++++
> .../single-display-mpo-multi-video.svg | 339 ++++++
> .../gpu/amdgpu/display/single-display-mpo.svg | 266 +++++
> Documentation/gpu/amdgpu/driver-misc.rst | 17 +
> 13 files changed, 3802 insertions(+)
> create mode 100644 Documentation/gpu/amdgpu/apu-asic-info-table.csv
> create mode 100644 Documentation/gpu/amdgpu/dgpu-asic-info-table.csv
> create mode 100644 Documentation/gpu/amdgpu/display/mpo-cursor.svg
> create mode 100644 Documentation/gpu/amdgpu/display/mpo-overview.rst
> create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo-less-pipe-ex.svg
> create mode 100644 Documentation/gpu/amdgpu/display/multi-display-hdcp-mpo.svg
> create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_no_split.svg
> create mode 100644 Documentation/gpu/amdgpu/display/pipeline_4k_split.svg
> create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo-multi-video.svg
> create mode 100644 Documentation/gpu/amdgpu/display/single-display-mpo.svg
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-08-30 19:52 UTC | newest]
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2022-08-11 15:48 [PATCH v2 0/3] Expand amdgpu documentation Rodrigo Siqueira
2022-08-11 15:48 ` [PATCH v2 1/3] Documentation/gpu: Add info table for ASICs Rodrigo Siqueira
2022-08-11 16:02 ` Russell, Kent
2022-08-11 19:45 ` Rodrigo Siqueira Jordao
2022-08-16 13:06 ` Alex Deucher
2022-08-11 15:48 ` [PATCH v2 2/3] Documentation/gpu: Add an explanation about the DCN pipeline Rodrigo Siqueira
2022-08-11 15:48 ` [PATCH v2 3/3] Documentation/gpu: Add Multiplane Overlay doc Rodrigo Siqueira
2022-08-30 19:52 ` [PATCH v2 0/3] Expand amdgpu documentation Harry Wentland
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