From: "Christian König" <ckoenig.leichtzumerken@gmail.com>
To: "Marek Olšák" <maraeo@gmail.com>,
"amd-gfx mailing list" <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 1/2] drm/amdgpu: return the PCIe gen and lanes from the INFO
Date: Mon, 2 Jan 2023 16:54:20 +0100 [thread overview]
Message-ID: <0931a762-c3a3-16c3-33a5-88e83fca4bcb@gmail.com> (raw)
In-Reply-To: <CAAxE2A720cJguG5b+0zbP=G4TxTjpqKBvOqDXXAP0LWHZEuj0A@mail.gmail.com>
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That stuff is already available as current_link_speed and
current_link_width in sysfs.
I'm a bit reluctant duplicating this information in the IOCTL interface.
Christian.
Am 30.12.22 um 23:07 schrieb Marek Olšák:
> For computing PCIe bandwidth in userspace and troubleshooting PCIe
> bandwidth issues.
>
> For example, my Navi21 has been limited to PCIe gen 1 and this is
> the first time I noticed it after 2 years.
>
> Note that this intentionally fills a hole and padding
> in drm_amdgpu_info_device.
>
> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
>
> The patch is attached.
>
> Marek
>
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next prev parent reply other threads:[~2023-01-02 15:54 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-30 22:07 [PATCH 1/2] drm/amdgpu: return the PCIe gen and lanes from the INFO Marek Olšák
2023-01-02 15:54 ` Christian König [this message]
2023-01-02 17:55 ` Marek Olšák
2023-01-03 8:31 ` Christian König
2023-01-03 22:41 ` Marek Olšák
2023-01-04 11:50 ` Lazar, Lijo
2023-01-04 14:13 ` Marek Olšák
2023-01-04 14:18 ` Lazar, Lijo
2023-01-04 15:10 ` Marek Olšák
2023-01-04 15:33 ` Lazar, Lijo
2023-01-04 20:17 ` Marek Olšák
2023-01-11 20:48 ` Alex Deucher
2023-01-11 20:50 ` Alex Deucher
2023-01-12 2:39 ` Marek Olšák
2023-01-12 11:46 ` Christian König
2023-01-12 11:50 ` Christian König
2023-01-12 16:43 ` Alex Deucher
2023-01-13 21:01 ` Marek Olšák
2023-01-13 21:20 ` Alex Deucher
2023-01-13 23:33 ` Marek Olšák
2023-01-13 23:38 ` Marek Olšák
2023-01-16 11:31 ` Christian König
2023-01-17 19:21 ` Alex Deucher
2023-01-04 14:15 ` Alex Deucher
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