[PATCH 1/4] drm/amd/powerplay: refine struct name for code style reason.

[PATCH 1/4] drm/amd/powerplay: refine struct name for code style reason.

[Rex Zhu]

Change-Id: I491a1de273f350a14576c45b2ec986365797dcc0
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h             | 4 ++--
 drivers/gpu/drm/amd/powerplay/inc/power_state.h       | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index 6c321b0..ccf7ebe 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -1523,7 +1523,7 @@ int get_number_of_vce_state_table_entries(
 
 int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
 							unsigned long i,
-							struct PP_VCEState *vce_state,
+							struct pp_vce_state *vce_state,
 							void **clock_info,
 							unsigned long *flag)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index aca94e0..25f4b42 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -36,7 +36,7 @@ struct pp_instance;
 struct pp_hwmgr;
 struct pp_hw_power_state;
 struct pp_power_state;
-struct PP_VCEState;
+struct pp_vce_state;
 struct phm_fan_speed_info;
 struct pp_atomctrl_voltage_table;
 
@@ -354,7 +354,7 @@ struct pp_table_func {
 	int (*pptable_get_vce_state_table_entry)(
 						struct pp_hwmgr *hwmgr,
 						unsigned long i,
-						struct PP_VCEState *vce_state,
+						struct pp_vce_state *vce_state,
 						void **clock_info,
 						unsigned long *flag);
 };
diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
index a3f0ce4..08b4b9f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/power_state.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
@@ -158,7 +158,7 @@ struct pp_power_state {
 
 
 /*Structure to hold a VCE state entry*/
-struct PP_VCEState {
+struct pp_vce_state {
 	uint32_t evclk;
 	uint32_t ecclk;
 	uint32_t sclk;
-- 
1.9.1

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[PATCH 2/4] drm/amd/powerplay: add vce state tables initialize for ppt v1.

[Rex Zhu]

Change-Id: Ib44bf1c7c1cb71ce619cc4589608e4c049f9db7e
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 .../amd/powerplay/hwmgr/tonga_processpptables.c    | 58 ++++++++++++++++++++++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          | 22 ++++++--
 2 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
index cfb647f..940487c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
@@ -1164,6 +1164,54 @@ static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
 	return result;
 }
 
+static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr)
+{
+	const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
+	const ATOM_Tonga_VCE_State_Table *vce_state_table =
+				(ATOM_Tonga_VCE_State_Table *)(((unsigned long)pp_table) + le16_to_cpu(pp_table->usVCEStateTableOffset));
+
+	if (vce_state_table == NULL)
+		return 0;
+
+	return vce_state_table->ucNumEntries;
+}
+
+
+static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i,
+		struct pp_vce_state *vce_state, void **clock_info, uint32_t *flag)
+{
+	const ATOM_Tonga_VCE_State_Record *vce_state_record;
+	const ATOM_Tonga_POWERPLAYTABLE *pptable = get_powerplay_table(hwmgr);
+	const ATOM_Tonga_VCE_State_Table *vce_state_table = (ATOM_Tonga_VCE_State_Table *)(((unsigned long)pptable)
+							  + le16_to_cpu(pptable->usVCEStateTableOffset));
+	const ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = (ATOM_Tonga_SCLK_Dependency_Table *)(((unsigned long)pptable)
+							  + le16_to_cpu(pptable->usSclkDependencyTableOffset));
+	const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = (ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long)pptable)
+							  + le16_to_cpu(pptable->usMclkDependencyTableOffset));
+	const ATOM_Tonga_MM_Dependency_Table *mm_dep_table = (ATOM_Tonga_MM_Dependency_Table *)(((unsigned long)pptable)
+							  + le16_to_cpu(pptable->usMMDependencyTableOffset));
+
+	PP_ASSERT_WITH_CODE((i <= vce_state_table->ucNumEntries),
+			 "Requested state entry ID is out of range!",
+			 return -EINVAL);
+
+	vce_state_record = (ATOM_Tonga_VCE_State_Record *)((char *)&vce_state_table->entries[1]
+				+ (sizeof(ATOM_Tonga_VCE_State_Record) * i));
+
+	*flag = vce_state_record->ucFlag;
+
+	vce_state->evclk = mm_dep_table->entries[vce_state_record->ucVCEClockIndex].ulEClk;
+	vce_state->ecclk = mm_dep_table->entries[vce_state_record->ucVCEClockIndex].ulEClk;
+	vce_state->sclk = sclk_dep_table->entries[vce_state_record->ucSCLKIndex].ulSclk;
+
+	if (vce_state_record->ucMCLKIndex >= mclk_dep_table->ucNumEntries)
+		vce_state->mclk = mclk_dep_table->entries[mclk_dep_table->ucNumEntries - 1].ulMclk;
+	else
+		vce_state->mclk = mclk_dep_table->entries[vce_state_record->ucMCLKIndex].ulMclk;
+
+	return 0;
+}
+
 /**
 * Create a Power State out of an entry in the PowerPlay table.
 * This function is called by the hardware back-end.
@@ -1181,6 +1229,8 @@ int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
 	const ATOM_Tonga_State_Array * state_arrays;
 	const ATOM_Tonga_State *state_entry;
 	const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
+	int i, j;
+	uint32_t flags = 0;
 
 	PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;);
 	power_state->classification.bios_index = entry_index;
@@ -1210,5 +1260,13 @@ int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
 			PP_StateClassificationFlag_Boot))
 		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
 
+	hwmgr->num_vce_state_tables = i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr);
+
+	if ((i != 0) && (i <= PP_MAX_VCE_LEVELS)) {
+		for (j = 0; j < i; j++)
+			ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL, &flags);
+	}
+
 	return result;
 }
+
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 25f4b42..1456565 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -31,16 +31,13 @@
 #include "hwmgr_ppt.h"
 #include "ppatomctrl.h"
 #include "hwmgr_ppt.h"
+#include "power_state.h"
 
 struct pp_instance;
 struct pp_hwmgr;
-struct pp_hw_power_state;
-struct pp_power_state;
-struct pp_vce_state;
 struct phm_fan_speed_info;
 struct pp_atomctrl_voltage_table;
 
-
 extern int amdgpu_powercontainment;
 extern int amdgpu_sclk_deep_sleep_en;
 
@@ -52,7 +49,6 @@ enum DISPLAY_GAP {
 };
 typedef enum DISPLAY_GAP DISPLAY_GAP;
 
-
 struct vi_dpm_level {
 	bool enabled;
 	uint32_t value;
@@ -573,6 +569,18 @@ struct phm_microcode_version_info {
 	uint32_t NB;
 };
 
+#define PP_MAX_VCE_LEVELS 6
+
+enum PP_VCE_LEVEL {
+	PP_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
+	PP_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
+	PP_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
+	PP_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
+	PP_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
+	PP_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
+};
+
+
 /**
  * The main hardware manager structure.
  */
@@ -586,6 +594,10 @@ struct pp_hwmgr {
 	uint32_t soft_pp_table_size;
 	void *hardcode_pp_table;
 	bool need_pp_table_upload;
+
+	struct pp_vce_state vce_states[PP_MAX_VCE_LEVELS];
+	uint32_t num_vce_state_tables;
+
 	enum amd_dpm_forced_level dpm_level;
 	bool block_hw_access;
 	struct phm_gfx_arbiter gfx_arbiter;
-- 
1.9.1

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[PATCH 3/4] drm/amd/powerplay: refine struct name for coding style reason.

[Rex Zhu]

delete useless member.

Change-Id: I03585fc3476f2954735f487c17dffa668287ad45
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/power_state.h | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
index 08b4b9f..9ceaed9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/power_state.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
@@ -171,30 +171,28 @@ enum PP_MMProfilingState {
 	PP_MMProfilingState_Stopped
 };
 
-struct PP_Clock_Engine_Request {
-	unsigned long clientType;
-	unsigned long ctxid;
+struct pp_clock_engine_request {
+	unsigned long client_type;
+	unsigned long ctx_id;
 	uint64_t  context_handle;
 	unsigned long sclk;
-	unsigned long sclkHardMin;
+	unsigned long sclk_hard_min;
 	unsigned long mclk;
 	unsigned long iclk;
 	unsigned long evclk;
 	unsigned long ecclk;
-	unsigned long ecclkHardMin;
+	unsigned long ecclk_hard_min;
 	unsigned long vclk;
 	unsigned long dclk;
-	unsigned long samclk;
-	unsigned long acpclk;
-	unsigned long sclkOverdrive;
-	unsigned long mclkOverdrive;
+	unsigned long sclk_over_drive;
+	unsigned long mclk_over_drive;
 	unsigned long sclk_threshold;
 	unsigned long flag;
 	unsigned long vclk_ceiling;
 	unsigned long dclk_ceiling;
 	unsigned long num_cus;
-	unsigned long pmflag;
-	enum PP_MMProfilingState MMProfilingState;
+	unsigned long pm_flag;
+	enum PP_MMProfilingState mm_profiling_state;
 };
 
 #endif
-- 
1.9.1

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[PATCH 4/4] drm/amd/powerplay: read power state table from vbios and can't be changed. so allocate memory for request ps and current ps.

[Rex Zhu]

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |  2 +-
 drivers/gpu/drm/amd/powerplay/eventmgr/psm.c  |  5 +++--
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   | 15 +++++++++++++--
 3 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 2de34a5..a4b0f41 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -538,7 +538,7 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input,
 		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 		break;
 	case AMD_PP_EVENT_READJUST_POWER_STATE:
-		pp_handle->hwmgr->current_ps = pp_handle->hwmgr->boot_ps;
+		memcpy(pp_handle->hwmgr->current_ps, pp_handle->hwmgr->boot_ps, pp_handle->hwmgr->ps_size);
 		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 		break;
 	default:
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
index a46225c..1d1875a 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
@@ -70,11 +70,12 @@ int psm_set_states(struct pp_eventmgr *eventmgr, unsigned long *state_id)
 	int i;
 
 	table_entries = hwmgr->num_ps;
+
 	state = hwmgr->ps;
 
 	for (i = 0; i < table_entries; i++) {
 		if (state->id == *state_id) {
-			hwmgr->request_ps = state;
+			memcpy(hwmgr->request_ps, state, hwmgr->ps_size);
 			return 0;
 		}
 		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
@@ -106,7 +107,7 @@ int psm_adjust_power_state_dynamic(struct pp_eventmgr *eventmgr, bool skip)
 	if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
 		phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
 		phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
-		hwmgr->current_ps = requested;
+		memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size);
 	}
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 50d465d..9794f10 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -128,6 +128,8 @@ int hwmgr_fini(struct pp_hwmgr *hwmgr)
 	kfree(hwmgr->set_temperature_range.function_list);
 
 	kfree(hwmgr->ps);
+	kfree(hwmgr->current_ps);
+	kfree(hwmgr->request_ps);
 	kfree(hwmgr);
 	return 0;
 }
@@ -152,10 +154,17 @@ int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
 					  sizeof(struct pp_power_state);
 
 	hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
-
 	if (hwmgr->ps == NULL)
 		return -ENOMEM;
 
+	hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
+	if (hwmgr->request_ps == NULL)
+		return -ENOMEM;
+
+	hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
+	if (hwmgr->current_ps == NULL)
+		return -ENOMEM;
+
 	state = hwmgr->ps;
 
 	for (i = 0; i < table_entries; i++) {
@@ -163,7 +172,8 @@ int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
 
 		if (state->classification.flags & PP_StateClassificationFlag_Boot) {
 			hwmgr->boot_ps = state;
-			hwmgr->current_ps = hwmgr->request_ps = state;
+			memcpy(hwmgr->current_ps, state, size);
+			memcpy(hwmgr->request_ps, state, size);
 		}
 
 		state->id = i + 1; /* assigned unique num for every power state id */
@@ -173,6 +183,7 @@ int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
 		state = (struct pp_power_state *)((unsigned long)state + size);
 	}
 
+
 	return 0;
 }
 
-- 
1.9.1

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RE: [PATCH 4/4] drm/amd/powerplay: read power state table from vbios and can't be changed. so allocate memory for request ps and current ps.

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, August 31, 2016 5:06 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 4/4] drm/amd/powerplay: read power state table from
> vbios and can't be changed. so allocate memory for request ps and current
> ps.

The subject line is way too long.  Make it shorter and include a description in the commit log.  With that fixed, this series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> 
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c |  2 +-
>  drivers/gpu/drm/amd/powerplay/eventmgr/psm.c  |  5 +++--
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   | 15 +++++++++++++--
>  3 files changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 2de34a5..a4b0f41 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -538,7 +538,7 @@ int pp_dpm_dispatch_tasks(void *handle, enum
> amd_pp_event event_id, void *input,
>  		ret = pem_handle_event(pp_handle->eventmgr, event_id,
> &data);
>  		break;
>  	case AMD_PP_EVENT_READJUST_POWER_STATE:
> -		pp_handle->hwmgr->current_ps = pp_handle->hwmgr-
> >boot_ps;
> +		memcpy(pp_handle->hwmgr->current_ps, pp_handle-
> >hwmgr->boot_ps, pp_handle->hwmgr->ps_size);
>  		ret = pem_handle_event(pp_handle->eventmgr, event_id,
> &data);
>  		break;
>  	default:
> diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
> b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
> index a46225c..1d1875a 100644
> --- a/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
> +++ b/drivers/gpu/drm/amd/powerplay/eventmgr/psm.c
> @@ -70,11 +70,12 @@ int psm_set_states(struct pp_eventmgr *eventmgr,
> unsigned long *state_id)
>  	int i;
> 
>  	table_entries = hwmgr->num_ps;
> +
>  	state = hwmgr->ps;
> 
>  	for (i = 0; i < table_entries; i++) {
>  		if (state->id == *state_id) {
> -			hwmgr->request_ps = state;
> +			memcpy(hwmgr->request_ps, state, hwmgr-
> >ps_size);
>  			return 0;
>  		}
>  		state = (struct pp_power_state *)((unsigned long)state +
> hwmgr->ps_size);
> @@ -106,7 +107,7 @@ int psm_adjust_power_state_dynamic(struct
> pp_eventmgr *eventmgr, bool skip)
>  	if (!equal ||
> phm_check_smc_update_required_for_display_configuration(hwmgr)) {
>  		phm_apply_state_adjust_rules(hwmgr, requested,
> pcurrent);
>  		phm_set_power_state(hwmgr, &pcurrent->hardware,
> &requested->hardware);
> -		hwmgr->current_ps = requested;
> +		memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr-
> >ps_size);
>  	}
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 50d465d..9794f10 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -128,6 +128,8 @@ int hwmgr_fini(struct pp_hwmgr *hwmgr)
>  	kfree(hwmgr->set_temperature_range.function_list);
> 
>  	kfree(hwmgr->ps);
> +	kfree(hwmgr->current_ps);
> +	kfree(hwmgr->request_ps);
>  	kfree(hwmgr);
>  	return 0;
>  }
> @@ -152,10 +154,17 @@ int hw_init_power_state_table(struct pp_hwmgr
> *hwmgr)
>  					  sizeof(struct pp_power_state);
> 
>  	hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
> -
>  	if (hwmgr->ps == NULL)
>  		return -ENOMEM;
> 
> +	hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
> +	if (hwmgr->request_ps == NULL)
> +		return -ENOMEM;
> +
> +	hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
> +	if (hwmgr->current_ps == NULL)
> +		return -ENOMEM;
> +
>  	state = hwmgr->ps;
> 
>  	for (i = 0; i < table_entries; i++) {
> @@ -163,7 +172,8 @@ int hw_init_power_state_table(struct pp_hwmgr
> *hwmgr)
> 
>  		if (state->classification.flags &
> PP_StateClassificationFlag_Boot) {
>  			hwmgr->boot_ps = state;
> -			hwmgr->current_ps = hwmgr->request_ps = state;
> +			memcpy(hwmgr->current_ps, state, size);
> +			memcpy(hwmgr->request_ps, state, size);
>  		}
> 
>  		state->id = i + 1; /* assigned unique num for every power
> state id */
> @@ -173,6 +183,7 @@ int hw_init_power_state_table(struct pp_hwmgr
> *hwmgr)
>  		state = (struct pp_power_state *)((unsigned long)state +
> size);
>  	}
> 
> +
>  	return 0;
>  }
> 
> --
> 1.9.1
> 
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