* [PATCH 1/9] drm/amd/powerplay: mark symbols static where possible on tonga/iceland.
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2016-09-09 13:37 ` Rex Zhu
2016-09-09 13:37 ` [PATCH 2/9] drm/amd/powerplay: add feature flags in hwmgr to enable/disable special features Rex Zhu
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Rex Zhu @ 2016-09-09 13:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c | 6 +++---
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 10 +++++-----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
index 8a7ada5..00e2e9a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
@@ -781,7 +781,7 @@ static int iceland_upload_firmware(struct pp_hwmgr *hwmgr)
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
+static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
{
iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
@@ -2606,7 +2606,7 @@ static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
* @param pInput the pointer to input data (PowerState)
* @return always 0
*/
-int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
+static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
{
int result;
iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
@@ -4629,7 +4629,7 @@ static int iceland_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
return 0;
}
-int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
+static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
{
iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index eb5fa9e..989e497 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -233,7 +233,7 @@ uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
return i-1;
}
-bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
+static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
{
/*
* We return the status of Voltage Control instead of checking SCLK/MCLK DPM
@@ -338,7 +338,7 @@ void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
}
-int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
+static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
@@ -775,7 +775,7 @@ int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
-int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
+static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
@@ -2898,7 +2898,7 @@ int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr,
* @param pInput the pointer to input data (PowerState)
* @return always 0
*/
-int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
+static int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
{
int result;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
@@ -3993,7 +3993,7 @@ int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
return 0;
}
-int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
+static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
{
int result;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 2/9] drm/amd/powerplay: add feature flags in hwmgr to enable/disable special features.
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2016-09-09 13:37 ` [PATCH 1/9] drm/amd/powerplay: mark symbols static where possible on tonga/iceland Rex Zhu
@ 2016-09-09 13:37 ` Rex Zhu
2016-09-09 13:37 ` [PATCH 3/9] drm/amd/powerplay: add module parameter for mask pp feature Rex Zhu
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Rex Zhu @ 2016-09-09 13:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I8d3a8cbcac10d65d0d7b724dfb6eb6fbaedcfda9
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 1456565..a4d490a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -70,6 +70,19 @@ enum PP_Result {
#define PCIE_PERF_REQ_GEN2 3
#define PCIE_PERF_REQ_GEN3 4
+enum PP_FEATURE_MASK {
+ PP_SCLK_DPM_MASK = 0x1,
+ PP_MCLK_DPM_MASK = 0x2,
+ PP_PCIE_DPM_MASK = 0x4,
+ PP_SCLK_DEEP_SLEEP_MASK = 0x8,
+ PP_POWER_CONTAINMENT_MASK = 0x10,
+ PP_UVD_HANDSHAKE_MASK = 0x20,
+ PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
+ PP_VBI_TIME_SUPPORT_MASK = 0x80,
+ PP_ULV_MASK = 0x100,
+ PP_ENABLE_GFX_CG_THRU_SMU = 0x200
+};
+
enum PHM_BackEnd_Magic {
PHM_Dummy_Magic = 0xAA5555AA,
PHM_RV770_Magic = 0xDCBAABCD,
@@ -635,6 +648,7 @@ struct pp_hwmgr {
struct pp_power_state *boot_ps;
struct pp_power_state *uvd_ps;
struct amd_pp_display_configuration display_config;
+ uint32_t feature_mask;
};
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 3/9] drm/amd/powerplay: add module parameter for mask pp feature
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2016-09-09 13:37 ` [PATCH 1/9] drm/amd/powerplay: mark symbols static where possible on tonga/iceland Rex Zhu
2016-09-09 13:37 ` [PATCH 2/9] drm/amd/powerplay: add feature flags in hwmgr to enable/disable special features Rex Zhu
@ 2016-09-09 13:37 ` Rex Zhu
2016-09-09 13:37 ` [PATCH 4/9] drm/amd/powerplay: initialize platform caps in hwmgr_init Rex Zhu
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Rex Zhu @ 2016-09-09 13:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I0fad3f4f96a57b41a5c47293e412fca40c741738
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9d39fa8..ce2414a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -96,6 +96,7 @@ extern unsigned amdgpu_cg_mask;
extern unsigned amdgpu_pg_mask;
extern int amdgpu_sclk_deep_sleep_en;
extern char *amdgpu_virtual_display;
+extern unsigned amdgpu_pp_feature_mask;
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 00b71ce..0c1d3c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -94,6 +94,7 @@ unsigned amdgpu_pcie_lane_cap = 0;
unsigned amdgpu_cg_mask = 0xffffffff;
unsigned amdgpu_pg_mask = 0xffffffff;
char *amdgpu_virtual_display = NULL;
+unsigned amdgpu_pp_feature_mask = 0xffffffff;
MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -179,6 +180,9 @@ module_param_named(powerplay, amdgpu_powerplay, int, 0444);
MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)");
module_param_named(powercontainment, amdgpu_powercontainment, int, 0444);
+
+MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
+module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444);
#endif
MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)");
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 4/9] drm/amd/powerplay: initialize platform caps in hwmgr_init.
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2016-09-09 13:37 ` [PATCH 3/9] drm/amd/powerplay: add module parameter for mask pp feature Rex Zhu
@ 2016-09-09 13:37 ` Rex Zhu
2016-09-09 13:37 ` [PATCH 5/9] drm/amd/powerplay: add common functiones for visiting pp table Rex Zhu
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Rex Zhu @ 2016-09-09 13:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
.../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 34 -------
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 109 ++++++++++++++++-----
.../gpu/drm/amd/powerplay/inc/hardwaremanager.h | 1 -
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
4 files changed, 87 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 789f98a..14f8c1f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -24,8 +24,6 @@
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "power_state.h"
-#include "pp_acpi.h"
-#include "amd_acpi.h"
#include "pp_debug.h"
#define PHM_FUNC_CHECK(hw) \
@@ -34,38 +32,6 @@
return -EINVAL; \
} while (0)
-void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
-{
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
- phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
-
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
-
- phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
- phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
-
- if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
- acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
- phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
-}
-
bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
{
return hwmgr->block_hw_access;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 9794f10..1aacda7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -32,6 +32,8 @@
#include "pp_debug.h"
#include "ppatomctrl.h"
#include "ppsmc.h"
+#include "pp_acpi.h"
+#include "amd_acpi.h"
#define VOLTAGE_SCALE 4
@@ -41,24 +43,8 @@ extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int iceland_hwmgr_init(struct pp_hwmgr *hwmgr);
-static int hwmgr_set_features_platform_caps(struct pp_hwmgr *hwmgr)
-{
- if (amdgpu_sclk_deep_sleep_en)
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkDeepSleep);
- else
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkDeepSleep);
-
- if (amdgpu_powercontainment)
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment);
- else
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment);
-
- return 0;
-}
+static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
+static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
{
@@ -79,7 +65,8 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
hwmgr->power_source = PP_PowerSource_AC;
- hwmgr_set_features_platform_caps(hwmgr);
+ hwmgr_init_default_caps(hwmgr);
+ hwmgr_set_user_specify_caps(hwmgr);
switch (hwmgr->chip_family) {
case AMDGPU_FAMILY_CZ:
@@ -108,8 +95,6 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
return -EINVAL;
}
- phm_init_dynamic_caps(hwmgr);
-
return 0;
}
@@ -217,8 +202,6 @@ int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
}
-
-
/**
* Returns once the part of the register indicated by the mask has
* reached the given value.The indirect space is described by giving
@@ -613,3 +596,83 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
printk(KERN_ERR "DAL requested level can not"
" found a available voltage in VDDC DPM Table \n");
}
+
+void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
+{
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
+
+ if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
+ acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_DynamicPatchPowerState);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_TablelessHardwareInterface);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_EnableSMU7ThermalManagement);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_DynamicPowerManagement);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UnTabledHardwareInterface);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SMC);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_DynamicUVDState);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_FanSpeedInTableIsRPM);
+
+ return;
+}
+
+int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
+{
+ if (amdgpu_sclk_deep_sleep_en)
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkDeepSleep);
+ else
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkDeepSleep);
+
+ if (amdgpu_powercontainment)
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_PowerContainment);
+ else
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_PowerContainment);
+
+ hwmgr->feature_mask = amdgpu_pp_feature_mask;
+
+ return 0;
+}
+
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 962cb53..d449583 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -341,7 +341,6 @@ extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
-extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr);
extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index a4d490a..2a060f6 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -40,6 +40,7 @@ struct pp_atomctrl_voltage_table;
extern int amdgpu_powercontainment;
extern int amdgpu_sclk_deep_sleep_en;
+extern unsigned amdgpu_pp_feature_mask;
enum DISPLAY_GAP {
DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
--
1.9.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 5/9] drm/amd/powerplay: add common functiones for visiting pp table.
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2016-09-09 13:37 ` [PATCH 4/9] drm/amd/powerplay: initialize platform caps in hwmgr_init Rex Zhu
@ 2016-09-09 13:37 ` Rex Zhu
2016-09-09 13:37 ` [PATCH 6/9] drm/amd/powerplay: wrap get evv voltage of fiji and polaris Rex Zhu
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Rex Zhu @ 2016-09-09 13:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 57 +++++++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 8 +++-
2 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 1aacda7..7f39ce6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -443,6 +443,27 @@ uint8_t phm_get_voltage_index(
return i - 1;
}
+uint8_t phm_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
+ uint32_t voltage)
+{
+ uint8_t count = (uint8_t) (voltage_table->count);
+ uint8_t i = 0;
+
+ PP_ASSERT_WITH_CODE((NULL != voltage_table),
+ "Voltage Table empty.", return 0;);
+ PP_ASSERT_WITH_CODE((0 != count),
+ "Voltage Table empty.", return 0;);
+
+ for (i = 0; i < count; i++) {
+ /* find first voltage bigger than requested */
+ if (voltage_table->entries[i].value >= voltage)
+ return i;
+ }
+
+ /* voltage is bigger than max voltage in the table */
+ return i - 1;
+}
+
uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci)
{
uint32_t i;
@@ -676,3 +697,39 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
return 0;
}
+int phm_add_voltage(struct pp_hwmgr *hwmgr,
+ phm_ppt_v1_voltage_lookup_table *look_up_table,
+ phm_ppt_v1_voltage_lookup_record *record)
+{
+ uint32_t i;
+
+ PP_ASSERT_WITH_CODE((NULL != look_up_table),
+ "Lookup Table empty.", return -EINVAL);
+ PP_ASSERT_WITH_CODE((0 != look_up_table->count),
+ "Lookup Table empty.", return -EINVAL);
+
+ i = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX);
+ PP_ASSERT_WITH_CODE((i >= look_up_table->count),
+ "Lookup Table is full.", return -EINVAL);
+
+ /* This is to avoid entering duplicate calculated records. */
+ for (i = 0; i < look_up_table->count; i++) {
+ if (look_up_table->entries[i].us_vdd == record->us_vdd) {
+ if (look_up_table->entries[i].us_calculated == 1)
+ return 0;
+ break;
+ }
+ }
+
+ look_up_table->entries[i].us_calculated = 1;
+ look_up_table->entries[i].us_vdd = record->us_vdd;
+ look_up_table->entries[i].us_cac_low = record->us_cac_low;
+ look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
+ look_up_table->entries[i].us_cac_high = record->us_cac_high;
+ /* Only increment the count when we're appending, not replacing duplicate entry. */
+ if (i == look_up_table->count)
+ look_up_table->count++;
+
+ return 0;
+}
+
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 2a060f6..c4772d7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -685,6 +685,8 @@ extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, st
extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
+extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
+ uint32_t voltage);
extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
@@ -695,6 +697,10 @@ extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
+extern int phm_add_voltage(struct pp_hwmgr *hwmgr,
+ phm_ppt_v1_voltage_lookup_table *look_up_table,
+ phm_ppt_v1_voltage_lookup_record *record);
+
#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
@@ -709,8 +715,6 @@ extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
PHM_FIELD_SHIFT(reg, field))
-
-
/* Operations on named fields. */
#define PHM_READ_FIELD(device, reg, field) \
--
1.9.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6/9] drm/amd/powerplay: wrap get evv voltage of fiji and polaris
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2016-09-09 13:37 ` [PATCH 5/9] drm/amd/powerplay: add common functiones for visiting pp table Rex Zhu
@ 2016-09-09 13:37 ` Rex Zhu
2016-09-09 13:37 ` [PATCH 7/9] drm/amd/powerplay: move smu related variable definitions to smumgr Rex Zhu
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Rex Zhu @ 2016-09-09 13:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 17 +++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 7f39ce6..f1b1c34 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -733,3 +733,20 @@ int phm_add_voltage(struct pp_hwmgr *hwmgr,
return 0;
}
+int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+ uint32_t sclk, uint16_t id, uint16_t *voltage)
+{
+ uint32_t vol;
+ int ret = 0;
+
+ if (hwmgr->chip_id < CHIP_POLARIS10) {
+ atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
+ if (*voltage >= 2000 || *voltage == 0)
+ *voltage = 1150;
+ } else {
+ ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
+ *voltage = (uint16_t)vol/100;
+ }
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index c4772d7..08b288f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -701,6 +701,9 @@ extern int phm_add_voltage(struct pp_hwmgr *hwmgr,
phm_ppt_v1_voltage_lookup_table *look_up_table,
phm_ppt_v1_voltage_lookup_record *record);
+extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+ uint32_t sclk, uint16_t id, uint16_t *voltage);
+
#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
--
1.9.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 7/9] drm/amd/powerplay: move smu related variable definitions to smumgr.
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2016-09-09 13:37 ` [PATCH 6/9] drm/amd/powerplay: wrap get evv voltage of fiji and polaris Rex Zhu
@ 2016-09-09 13:37 ` Rex Zhu
2016-09-09 13:37 ` [PATCH 8/9] drm/amd/powerplay: delete const flag of hwmgr_funcs for overload Rex Zhu
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Rex Zhu @ 2016-09-09 13:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: Ia64aee14b196bef708aded00cc257c7eafcfbcb9
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
.../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h | 5 +----
.../drm/amd/powerplay/hwmgr/polaris10_powertune.h | 13 -------------
.../gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h | 20 ++++++++++++++++++++
3 files changed, 21 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
index dabbb5d..56d4329 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
@@ -30,6 +30,7 @@
#include "ppatomctrl.h"
#include "polaris10_ppsmc.h"
#include "polaris10_powertune.h"
+#include "polaris10_smumgr.h"
#define POLARIS10_MAX_HARDWARE_POWERLEVELS 2
@@ -165,10 +166,6 @@ struct polaris10_pcie_perf_range {
uint16_t max;
uint16_t min;
};
-struct polaris10_range_table {
- uint32_t trans_lower_frequency; /* in 10khz */
- uint32_t trans_upper_frequency;
-};
struct polaris10_hwmgr {
struct polaris10_dpm_table dpm_table;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
index bc78e28..329119d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h
@@ -66,19 +66,6 @@ struct polaris10_pt_config_reg {
enum polaris10_pt_config_reg_type type;
};
-struct polaris10_pt_defaults {
- uint8_t SviLoadLineEn;
- uint8_t SviLoadLineVddC;
- uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
- uint8_t TDC_MAWt;
- uint8_t TdcWaterfallCtl;
- uint8_t DTEAmbientTempBase;
-
- uint32_t DisplayCac;
- uint32_t BAPM_TEMP_GRADIENT;
- uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
- uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
-};
void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
index e5377ae..7c2445f 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h
@@ -26,12 +26,27 @@
#include <polaris10_ppsmc.h>
#include <pp_endian.h>
+#include "smu74.h"
struct polaris10_avfs {
enum AVFS_BTC_STATUS avfs_btc_status;
uint32_t avfs_btc_param;
};
+struct polaris10_pt_defaults {
+ uint8_t SviLoadLineEn;
+ uint8_t SviLoadLineVddC;
+ uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
+ uint8_t TDC_MAWt;
+ uint8_t TdcWaterfallCtl;
+ uint8_t DTEAmbientTempBase;
+
+ uint32_t DisplayCac;
+ uint32_t BAPM_TEMP_GRADIENT;
+ uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
+ uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
+};
+
struct polaris10_buffer_entry {
uint32_t data_size;
uint32_t mc_addr_low;
@@ -40,6 +55,11 @@ struct polaris10_buffer_entry {
unsigned long handle;
};
+struct polaris10_range_table {
+ uint32_t trans_lower_frequency; /* in 10khz */
+ uint32_t trans_upper_frequency;
+};
+
struct polaris10_smumgr {
uint8_t *header;
uint8_t *mec_image;
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 8/9] drm/amd/powerplay: delete const flag of hwmgr_funcs for overload.
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2016-09-09 13:37 ` [PATCH 7/9] drm/amd/powerplay: move smu related variable definitions to smumgr Rex Zhu
@ 2016-09-09 13:37 ` Rex Zhu
2016-09-09 13:37 ` [PATCH 9/9] drm/amd/powerplay: delete dupicated function and definition Rex Zhu
2016-09-09 14:23 ` [PATCH 0/9] misc patches related to powerplay Christian König
9 siblings, 0 replies; 14+ messages in thread
From: Rex Zhu @ 2016-09-09 13:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I832464f3de9cbacd2e0f6b6a22d2d7d9980be418
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 5ecef17..f4b7a45 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1857,7 +1857,7 @@ static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_c
return 0;
}
-static const struct pp_hwmgr_func cz_hwmgr_funcs = {
+static struct pp_hwmgr_func cz_hwmgr_funcs = {
.backend_init = cz_hwmgr_backend_init,
.backend_fini = cz_hwmgr_backend_fini,
.asic_setup = NULL,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index e93492b..b5d3b3e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -5541,7 +5541,7 @@ static int fiji_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
return 0;
}
-static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
+static struct pp_hwmgr_func fiji_hwmgr_funcs = {
.backend_init = &fiji_hwmgr_backend_init,
.backend_fini = &fiji_hwmgr_backend_fini,
.asic_setup = &fiji_setup_asic_task,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
index 00e2e9a..be29ff4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
@@ -5627,7 +5627,7 @@ static int iceland_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
return 0;
}
-static const struct pp_hwmgr_func iceland_hwmgr_funcs = {
+static struct pp_hwmgr_func iceland_hwmgr_funcs = {
.backend_init = &iceland_hwmgr_backend_init,
.backend_fini = &iceland_hwmgr_backend_fini,
.asic_setup = &iceland_setup_asic_task,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 3979adf..f7e0626 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -5232,7 +5232,7 @@ static int polaris10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
return 0;
}
-static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
+static struct pp_hwmgr_func polaris10_hwmgr_funcs = {
.backend_init = &polaris10_hwmgr_backend_init,
.backend_fini = &polaris10_hwmgr_backend_fini,
.asic_setup = &polaris10_setup_asic_task,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 989e497..a7d1028 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -6325,7 +6325,7 @@ static int tonga_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
return 0;
}
-static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
+static struct pp_hwmgr_func tonga_hwmgr_funcs = {
.backend_init = &tonga_hwmgr_backend_init,
.backend_fini = &tonga_hwmgr_backend_fini,
.asic_setup = &tonga_setup_asic_task,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 08b288f..09c6e7e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -633,7 +633,7 @@ struct pp_hwmgr {
struct phm_runtime_table_header display_configuration_changed;
struct phm_runtime_table_header start_thermal_controller;
struct phm_runtime_table_header set_temperature_range;
- const struct pp_hwmgr_func *hwmgr_func;
+ struct pp_hwmgr_func *hwmgr_func;
const struct pp_table_func *pptable_func;
struct pp_power_state *ps;
enum pp_power_source power_source;
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 9/9] drm/amd/powerplay: delete dupicated function and definition.
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2016-09-09 13:37 ` [PATCH 8/9] drm/amd/powerplay: delete const flag of hwmgr_funcs for overload Rex Zhu
@ 2016-09-09 13:37 ` Rex Zhu
2016-09-09 14:23 ` [PATCH 0/9] misc patches related to powerplay Christian König
9 siblings, 0 replies; 14+ messages in thread
From: Rex Zhu @ 2016-09-09 13:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I9a03c3aac811259e32edbf7c20ef3eeca69d0252
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +++++--
drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c | 8 --------
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 5 -----
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 9 ---------
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 4 ++++
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 1 -
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 1 +
7 files changed, 10 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index f1b1c34..e64b6a2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -35,8 +35,6 @@
#include "pp_acpi.h"
#include "amd_acpi.h"
-#define VOLTAGE_SCALE 4
-
extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
@@ -46,6 +44,11 @@ extern int iceland_hwmgr_init(struct pp_hwmgr *hwmgr);
static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
+uint8_t convert_to_vid(uint16_t vddc)
+{
+ return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
+}
+
int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
{
struct pp_hwmgr *hwmgr;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
index be29ff4..3128228 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
@@ -1355,14 +1355,6 @@ static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
return 0;
}
-/**
- * Convert a voltage value in mv unit to VID number required by SMU firmware
- */
-static uint8_t convert_to_vid(uint16_t vddc)
-{
- return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
-}
-
int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
{
int i;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index f7e0626..8058aa6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -736,11 +736,6 @@ int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
return 0;
}
-uint8_t convert_to_vid(uint16_t vddc)
-{
- return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
-}
-
/**
* Mvdd table preparation for SMC.
*
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index a7d1028..0e1919d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -1319,15 +1319,6 @@ static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
}
/**
- * Convert a voltage value in mv unit to VID number required by SMU firmware
- */
-static uint8_t convert_to_vid(uint16_t vddc)
-{
- return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
-}
-
-
-/**
* Preparation of vddc and vddgfx CAC tables for SMC.
*
* @param hwmgr the address of the hardware manager
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 09c6e7e..0665c8c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -42,6 +42,10 @@ extern int amdgpu_powercontainment;
extern int amdgpu_sclk_deep_sleep_en;
extern unsigned amdgpu_pp_feature_mask;
+#define VOLTAGE_SCALE 4
+
+uint8_t convert_to_vid(uint16_t vddc);
+
enum DISPLAY_GAP {
DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 704ff4c..8047ad2 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -40,7 +40,6 @@
#include "cgs_common.h"
#define POLARIS10_SMC_SIZE 0x20000
-#define VOLTAGE_SCALE 4
/* Microcode file is stored in this buffer */
#define BUFFER_SIZE 80000
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index 83d8f7e..bbeb786 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -29,6 +29,7 @@
#include "cgs_common.h"
#include "linux/delay.h"
+
int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
{
struct pp_smumgr *smumgr;
--
1.9.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 0/9] misc patches related to powerplay
[not found] ` <1473428259-580-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2016-09-09 13:37 ` [PATCH 9/9] drm/amd/powerplay: delete dupicated function and definition Rex Zhu
@ 2016-09-09 14:23 ` Christian König
[not found] ` <ead74fd5-6d6f-ba4e-d0a1-fea21e7296dd-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
9 siblings, 1 reply; 14+ messages in thread
From: Christian König @ 2016-09-09 14:23 UTC (permalink / raw)
To: Rex Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Patch #1-#7 and #9 are Acked-by: Christian König <christian.koenig@amd.com>.
Patch #8: That looks fishy, usually we don't want to override static
functions tables.
So what is the specific use case here?
Regards,
Christian.
Am 09.09.2016 um 15:37 schrieb Rex Zhu:
> Rex Zhu (9):
> drm/amd/powerplay: mark symbols static where possible on tonga.
> drm/amd/powerplay: add feature flags in hwmgr to enable/disable
> special features.
> drm/amd/powerplay: add module parameter for mask pp feature
> drm/amd/powerplay: initialize platform caps in hwmgr_init.
> drm/amd/powerplay: add common functiones for visiting pp table.
> drm/amd/powerplay: wrap get evv voltage of fiji and polaris
> drm/amd/powerplay: move smu related variable definitions to smumgr.
> drm/amd/powerplay: delete const flag of hwmgr_funcs for overload.
> drm/amd/powerplay: delete dupicated function and definition.
>
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +
> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 2 +-
> .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 34 ----
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 186 ++++++++++++++++++---
> .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c | 10 +-
> .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 7 +-
> .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h | 5 +-
> .../drm/amd/powerplay/hwmgr/polaris10_powertune.h | 13 --
> drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 21 +--
> .../gpu/drm/amd/powerplay/inc/hardwaremanager.h | 1 -
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 32 +++-
> .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 1 -
> .../drm/amd/powerplay/smumgr/polaris10_smumgr.h | 20 +++
> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 1 +
> 16 files changed, 229 insertions(+), 111 deletions(-)
>
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^ permalink raw reply [flat|nested] 14+ messages in thread