[PATCH 1/2] drm/amdgpu: no need to ungate uvd/vce clock when fini.

[PATCH 1/2] drm/amdgpu: no need to ungate uvd/vce clock when fini.

[Rex Zhu]

Change-Id: Ia7f9c32d72f87deaf25d4cccbf6fa4cb85562d97
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index dbfe471..25ad736 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1471,20 +1471,26 @@ static int amdgpu_fini(struct amdgpu_device *adev)
 			amdgpu_wb_fini(adev);
 			amdgpu_vram_scratch_fini(adev);
 		}
-		/* ungate blocks before hw fini so that we can shutdown the blocks safely */
-		r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
-									     AMD_CG_STATE_UNGATE);
-		if (r) {
-			DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
-				  adev->ip_blocks[i].version->funcs->name, r);
-			return r;
+
+		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
+			adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
+			/* ungate blocks before hw fini so that we can shutdown the blocks safely */
+			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
+										     AMD_CG_STATE_UNGATE);
+			if (r) {
+				DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
+					  adev->ip_blocks[i].version->funcs->name, r);
+				return r;
+			}
 		}
+
 		r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
 		/* XXX handle errors */
 		if (r) {
 			DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
 				  adev->ip_blocks[i].version->funcs->name, r);
 		}
+
 		adev->ip_blocks[i].status.hw = false;
 	}
 
-- 
1.9.1

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[PATCH 2/2] drm/amd/powerplay: disable cg pg task when pp uninitialize.

[Rex Zhu]

fix bug on uvd pg enabled, when reboot vm in pass through case,
we need to notify smu power up uvd/vce if they were power down.
otherwise, the vbios post will fail.

Change-Id: I5df801ab0f6105be550fbbbd98dbf8329357784a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c   |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 13 +++++++++++++
 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   |  1 +
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
index b6f45fd..ec36c0e 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
@@ -154,7 +154,7 @@ int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_
 
 int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
 {
-	/* TODO */
+	phm_disable_clock_power_gatings(eventmgr->hwmgr);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 0723758..c355a0f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -209,6 +209,19 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
+{
+	PHM_FUNC_CHECK(hwmgr);
+
+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+		PHM_PlatformCaps_TablelessHardwareInterface)) {
+		if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
+			return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
+	}
+	return 0;
+}
+
+
 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
 {
 	PHM_FUNC_CHECK(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index d449583..2612997 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -334,6 +334,7 @@ struct phm_clocks {
 	uint32_t clock[MAX_NUM_CLOCKS];
 };
 
+extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
 extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
-- 
1.9.1

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RE: [PATCH 2/2] drm/amd/powerplay: disable cg pg task when pp uninitialize.

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, November 29, 2016 6:24 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 2/2] drm/amd/powerplay: disable cg pg task when pp
> uninitialize.
> 
> fix bug on uvd pg enabled, when reboot vm in pass through case,
> we need to notify smu power up uvd/vce if they were power down.
> otherwise, the vbios post will fail.
> 
> Change-Id: I5df801ab0f6105be550fbbbd98dbf8329357784a
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

For the series:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c   |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 13
> +++++++++++++
>  drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   |  1 +
>  3 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
> b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
> index b6f45fd..ec36c0e 100644
> --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
> +++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
> @@ -154,7 +154,7 @@ int pem_task_powerdown_vce_tasks(struct
> pp_eventmgr *eventmgr, struct pem_event_
> 
>  int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr
> *eventmgr, struct pem_event_data *event_data)
>  {
> -	/* TODO */
> +	phm_disable_clock_power_gatings(eventmgr->hwmgr);
>  	return 0;
>  }
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index 0723758..c355a0f 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -209,6 +209,19 @@ int phm_enable_clock_power_gatings(struct
> pp_hwmgr *hwmgr)
>  	return 0;
>  }
> 
> +int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
> +{
> +	PHM_FUNC_CHECK(hwmgr);
> +
> +	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> +		PHM_PlatformCaps_TablelessHardwareInterface)) {
> +		if (NULL != hwmgr->hwmgr_func-
> >disable_clock_power_gating)
> +			return hwmgr->hwmgr_func-
> >disable_clock_power_gating(hwmgr);
> +	}
> +	return 0;
> +}
> +
> +
>  int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
>  {
>  	PHM_FUNC_CHECK(hwmgr);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> index d449583..2612997 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> @@ -334,6 +334,7 @@ struct phm_clocks {
>  	uint32_t clock[MAX_NUM_CLOCKS];
>  };
> 
> +extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
>  extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
>  extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
>  extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
> --
> 1.9.1
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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