* [PATCH 1/2] drm/amd/powerplay: refine code in cz_smumgr.c
@ 2016-12-23 9:50 Rex Zhu
[not found] ` <1482486601-4681-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Rex Zhu @ 2016-12-23 9:50 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
cz_smu_init will be called in sw_init.
so it should not touch other blocks's
firmware as they were not ready.
Change-Id: I3af8cce2059aaacfc260e24a41b1af46a0aeb18b
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 135 ++++++++++++-----------
1 file changed, 70 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 5a44485..3ea437c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -141,41 +141,6 @@ static int cz_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
return cz_send_msg_to_smc(smumgr, msg);
}
-static int cz_request_smu_load_fw(struct pp_smumgr *smumgr)
-{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend);
- uint32_t smc_address;
-
- if (!smumgr->reload_fw) {
- printk(KERN_INFO "[ powerplay ] skip reloading...\n");
- return 0;
- }
-
- smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
- offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
-
- cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4);
-
- cz_send_msg_to_smc_with_parameter(smumgr,
- PPSMC_MSG_DriverDramAddrHi,
- cz_smu->toc_buffer.mc_addr_high);
-
- cz_send_msg_to_smc_with_parameter(smumgr,
- PPSMC_MSG_DriverDramAddrLo,
- cz_smu->toc_buffer.mc_addr_low);
-
- cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs);
-
- cz_send_msg_to_smc_with_parameter(smumgr,
- PPSMC_MSG_ExecuteJob,
- cz_smu->toc_entry_aram);
- cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
- cz_smu->toc_entry_power_profiling_index);
-
- return cz_send_msg_to_smc_with_parameter(smumgr,
- PPSMC_MSG_ExecuteJob,
- cz_smu->toc_entry_initialize_index);
-}
static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
uint32_t firmware)
@@ -250,34 +215,6 @@ static int cz_load_mec_firmware(struct pp_smumgr *smumgr)
return 0;
}
-static int cz_start_smu(struct pp_smumgr *smumgr)
-{
- int ret = 0;
- uint32_t fw_to_check = UCODE_ID_RLC_G_MASK |
- UCODE_ID_SDMA0_MASK |
- UCODE_ID_SDMA1_MASK |
- UCODE_ID_CP_CE_MASK |
- UCODE_ID_CP_ME_MASK |
- UCODE_ID_CP_PFP_MASK |
- UCODE_ID_CP_MEC_JT1_MASK |
- UCODE_ID_CP_MEC_JT2_MASK;
-
- if (smumgr->chip_id == CHIP_STONEY)
- fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
-
- ret = cz_request_smu_load_fw(smumgr);
- if (ret)
- printk(KERN_ERR "[ powerplay] SMU firmware load failed\n");
-
- cz_check_fw_load_finish(smumgr, fw_to_check);
-
- ret = cz_load_mec_firmware(smumgr);
- if (ret)
- printk(KERN_ERR "[ powerplay ] Mec Firmware load failed\n");
-
- return ret;
-}
-
static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
enum cz_scratch_entry firmware_enum)
{
@@ -729,6 +666,76 @@ static int cz_upload_pptable_settings(struct pp_smumgr *smumgr)
return 0;
}
+static int cz_request_smu_load_fw(struct pp_smumgr *smumgr)
+{
+ struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend);
+ uint32_t smc_address;
+
+ if (!smumgr->reload_fw) {
+ printk(KERN_INFO "[ powerplay ] skip reloading...\n");
+ return 0;
+ }
+
+ cz_smu_populate_firmware_entries(smumgr);
+
+ cz_smu_construct_toc(smumgr);
+
+ smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
+ offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
+
+ cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4);
+
+ cz_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_DriverDramAddrHi,
+ cz_smu->toc_buffer.mc_addr_high);
+
+ cz_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_DriverDramAddrLo,
+ cz_smu->toc_buffer.mc_addr_low);
+
+ cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs);
+
+ cz_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_ExecuteJob,
+ cz_smu->toc_entry_aram);
+ cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
+ cz_smu->toc_entry_power_profiling_index);
+
+ return cz_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_ExecuteJob,
+ cz_smu->toc_entry_initialize_index);
+}
+
+static int cz_start_smu(struct pp_smumgr *smumgr)
+{
+ int ret = 0;
+ uint32_t fw_to_check = 0;
+
+ fw_to_check = UCODE_ID_RLC_G_MASK |
+ UCODE_ID_SDMA0_MASK |
+ UCODE_ID_SDMA1_MASK |
+ UCODE_ID_CP_CE_MASK |
+ UCODE_ID_CP_ME_MASK |
+ UCODE_ID_CP_PFP_MASK |
+ UCODE_ID_CP_MEC_JT1_MASK |
+ UCODE_ID_CP_MEC_JT2_MASK;
+
+ if (smumgr->chip_id == CHIP_STONEY)
+ fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
+
+ ret = cz_request_smu_load_fw(smumgr);
+ if (ret)
+ printk(KERN_ERR "[ powerplay] SMU firmware load failed\n");
+
+ cz_check_fw_load_finish(smumgr, fw_to_check);
+
+ ret = cz_load_mec_firmware(smumgr);
+ if (ret)
+ printk(KERN_ERR "[ powerplay ] Mec Firmware load failed\n");
+
+ return ret;
+}
+
static int cz_smu_init(struct pp_smumgr *smumgr)
{
struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
@@ -769,7 +776,6 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
- cz_smu_populate_firmware_entries(smumgr);
if (0 != cz_smu_populate_single_scratch_entry(smumgr,
CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
@@ -808,7 +814,6 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
return -1;
}
- cz_smu_construct_toc(smumgr);
return 0;
}
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread[parent not found: <1482486601-4681-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>]
* [PATCH 2/2] drm/amd/powerplay: fix issue can't load another smu firmware. [not found] ` <1482486601-4681-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2016-12-23 9:50 ` Rex Zhu 2016-12-31 6:30 ` [PATCH 1/2] drm/amd/powerplay: refine code in cz_smumgr.c Alex Deucher 1 sibling, 0 replies; 3+ messages in thread From: Rex Zhu @ 2016-12-23 9:50 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu need to release failed smu firmware before load another firmware. Change-Id: Ifb9e0f63a5261dffef28ee1e0ce982d9c5b0344c Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> --- drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c index f38a687..49cd887 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c @@ -328,6 +328,7 @@ static int polaris10_start_smu(struct pp_smumgr *smumgr) /* If failed, try with different security Key. */ if (result != 0) { smu_data->smu7_data.security_hard_key ^= 1; + cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU); result = polaris10_start_smu_in_protection_mode(smumgr); } } -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] drm/amd/powerplay: refine code in cz_smumgr.c [not found] ` <1482486601-4681-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2016-12-23 9:50 ` [PATCH 2/2] drm/amd/powerplay: fix issue can't load another smu firmware Rex Zhu @ 2016-12-31 6:30 ` Alex Deucher 1 sibling, 0 replies; 3+ messages in thread From: Alex Deucher @ 2016-12-31 6:30 UTC (permalink / raw) To: Rex Zhu; +Cc: amd-gfx list On Fri, Dec 23, 2016 at 4:50 AM, Rex Zhu <Rex.Zhu@amd.com> wrote: > cz_smu_init will be called in sw_init. > so it should not touch other blocks's > firmware as they were not ready. > > Change-Id: I3af8cce2059aaacfc260e24a41b1af46a0aeb18b > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> > Reviewed-by: Huang Rui <ray.huang@amd.com> Series is: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 135 ++++++++++++----------- > 1 file changed, 70 insertions(+), 65 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c > index 5a44485..3ea437c 100644 > --- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c > +++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c > @@ -141,41 +141,6 @@ static int cz_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, > return cz_send_msg_to_smc(smumgr, msg); > } > > -static int cz_request_smu_load_fw(struct pp_smumgr *smumgr) > -{ > - struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend); > - uint32_t smc_address; > - > - if (!smumgr->reload_fw) { > - printk(KERN_INFO "[ powerplay ] skip reloading...\n"); > - return 0; > - } > - > - smc_address = SMU8_FIRMWARE_HEADER_LOCATION + > - offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); > - > - cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4); > - > - cz_send_msg_to_smc_with_parameter(smumgr, > - PPSMC_MSG_DriverDramAddrHi, > - cz_smu->toc_buffer.mc_addr_high); > - > - cz_send_msg_to_smc_with_parameter(smumgr, > - PPSMC_MSG_DriverDramAddrLo, > - cz_smu->toc_buffer.mc_addr_low); > - > - cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs); > - > - cz_send_msg_to_smc_with_parameter(smumgr, > - PPSMC_MSG_ExecuteJob, > - cz_smu->toc_entry_aram); > - cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, > - cz_smu->toc_entry_power_profiling_index); > - > - return cz_send_msg_to_smc_with_parameter(smumgr, > - PPSMC_MSG_ExecuteJob, > - cz_smu->toc_entry_initialize_index); > -} > > static int cz_check_fw_load_finish(struct pp_smumgr *smumgr, > uint32_t firmware) > @@ -250,34 +215,6 @@ static int cz_load_mec_firmware(struct pp_smumgr *smumgr) > return 0; > } > > -static int cz_start_smu(struct pp_smumgr *smumgr) > -{ > - int ret = 0; > - uint32_t fw_to_check = UCODE_ID_RLC_G_MASK | > - UCODE_ID_SDMA0_MASK | > - UCODE_ID_SDMA1_MASK | > - UCODE_ID_CP_CE_MASK | > - UCODE_ID_CP_ME_MASK | > - UCODE_ID_CP_PFP_MASK | > - UCODE_ID_CP_MEC_JT1_MASK | > - UCODE_ID_CP_MEC_JT2_MASK; > - > - if (smumgr->chip_id == CHIP_STONEY) > - fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK); > - > - ret = cz_request_smu_load_fw(smumgr); > - if (ret) > - printk(KERN_ERR "[ powerplay] SMU firmware load failed\n"); > - > - cz_check_fw_load_finish(smumgr, fw_to_check); > - > - ret = cz_load_mec_firmware(smumgr); > - if (ret) > - printk(KERN_ERR "[ powerplay ] Mec Firmware load failed\n"); > - > - return ret; > -} > - > static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr, > enum cz_scratch_entry firmware_enum) > { > @@ -729,6 +666,76 @@ static int cz_upload_pptable_settings(struct pp_smumgr *smumgr) > return 0; > } > > +static int cz_request_smu_load_fw(struct pp_smumgr *smumgr) > +{ > + struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend); > + uint32_t smc_address; > + > + if (!smumgr->reload_fw) { > + printk(KERN_INFO "[ powerplay ] skip reloading...\n"); > + return 0; > + } > + > + cz_smu_populate_firmware_entries(smumgr); > + > + cz_smu_construct_toc(smumgr); > + > + smc_address = SMU8_FIRMWARE_HEADER_LOCATION + > + offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus); > + > + cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4); > + > + cz_send_msg_to_smc_with_parameter(smumgr, > + PPSMC_MSG_DriverDramAddrHi, > + cz_smu->toc_buffer.mc_addr_high); > + > + cz_send_msg_to_smc_with_parameter(smumgr, > + PPSMC_MSG_DriverDramAddrLo, > + cz_smu->toc_buffer.mc_addr_low); > + > + cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs); > + > + cz_send_msg_to_smc_with_parameter(smumgr, > + PPSMC_MSG_ExecuteJob, > + cz_smu->toc_entry_aram); > + cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob, > + cz_smu->toc_entry_power_profiling_index); > + > + return cz_send_msg_to_smc_with_parameter(smumgr, > + PPSMC_MSG_ExecuteJob, > + cz_smu->toc_entry_initialize_index); > +} > + > +static int cz_start_smu(struct pp_smumgr *smumgr) > +{ > + int ret = 0; > + uint32_t fw_to_check = 0; > + > + fw_to_check = UCODE_ID_RLC_G_MASK | > + UCODE_ID_SDMA0_MASK | > + UCODE_ID_SDMA1_MASK | > + UCODE_ID_CP_CE_MASK | > + UCODE_ID_CP_ME_MASK | > + UCODE_ID_CP_PFP_MASK | > + UCODE_ID_CP_MEC_JT1_MASK | > + UCODE_ID_CP_MEC_JT2_MASK; > + > + if (smumgr->chip_id == CHIP_STONEY) > + fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK); > + > + ret = cz_request_smu_load_fw(smumgr); > + if (ret) > + printk(KERN_ERR "[ powerplay] SMU firmware load failed\n"); > + > + cz_check_fw_load_finish(smumgr, fw_to_check); > + > + ret = cz_load_mec_firmware(smumgr); > + if (ret) > + printk(KERN_ERR "[ powerplay ] Mec Firmware load failed\n"); > + > + return ret; > +} > + > static int cz_smu_init(struct pp_smumgr *smumgr) > { > struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend; > @@ -769,7 +776,6 @@ static int cz_smu_init(struct pp_smumgr *smumgr) > cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr); > cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr); > > - cz_smu_populate_firmware_entries(smumgr); > if (0 != cz_smu_populate_single_scratch_entry(smumgr, > CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, > UCODE_ID_RLC_SCRATCH_SIZE_BYTE, > @@ -808,7 +814,6 @@ static int cz_smu_init(struct pp_smumgr *smumgr) > printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n"); > return -1; > } > - cz_smu_construct_toc(smumgr); > > return 0; > } > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-12-23 9:50 [PATCH 1/2] drm/amd/powerplay: refine code in cz_smumgr.c Rex Zhu
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2016-12-23 9:50 ` [PATCH 2/2] drm/amd/powerplay: fix issue can't load another smu firmware Rex Zhu
2016-12-31 6:30 ` [PATCH 1/2] drm/amd/powerplay: refine code in cz_smumgr.c Alex Deucher
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