* [PART1 PATCH v5 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6
@ 2017-01-09 16:04 Huang Rui
[not found] ` <1483977889-16256-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Huang Rui @ 2017-01-09 16:04 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
Christian König, Tom StDenis
Cc: Huang Rui, Hawking Zhang, Rex Zhu, Ping Fu, David Mao
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
Changes from V4 -> V5:
- remove pm mutex from set clock gating function
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 33 +++++++++++++++++++++++++++++++--
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 33 +++++++++++++++++++++++++++++++--
3 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 530549b..31054c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1183,6 +1183,7 @@ struct amdgpu_uvd {
bool use_ctx_buf;
struct amd_sched_entity entity;
uint32_t srbm_soft_reset;
+ bool is_powergated;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 03a35d9..2b8d2b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -781,16 +781,44 @@ static int uvd_v5_0_set_powergating_state(void *handle,
* the smc and the hw blocks
*/
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int ret = 0;
if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
return 0;
if (state == AMD_PG_STATE_GATE) {
uvd_v5_0_stop(adev);
- return 0;
+ adev->uvd.is_powergated = true;
} else {
- return uvd_v5_0_start(adev);
+ ret = uvd_v5_0_start(adev);
+ if (ret)
+ goto out;
+ adev->uvd.is_powergated = false;
+ }
+
+out:
+ return ret;
+}
+
+static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int data;
+
+ mutex_lock(&adev->pm.mutex);
+
+ if (adev->uvd.is_powergated) {
+ DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
+ goto out;
}
+
+ /* AMD_CG_SUPPORT_UVD_MGCG */
+ data = RREG32(mmUVD_CGC_CTRL);
+ if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
+ *flags |= AMD_CG_SUPPORT_UVD_MGCG;
+
+out:
+ mutex_unlock(&adev->pm.mutex);
}
static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
@@ -808,6 +836,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
.soft_reset = uvd_v5_0_soft_reset,
.set_clockgating_state = uvd_v5_0_set_clockgating_state,
.set_powergating_state = uvd_v5_0_set_powergating_state,
+ .get_clockgating_state = uvd_v5_0_get_clockgating_state,
};
static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 8779d4b..f11d760 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -987,6 +987,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
* the smc and the hw blocks
*/
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int ret = 0;
if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
return 0;
@@ -995,10 +996,37 @@ static int uvd_v6_0_set_powergating_state(void *handle,
if (state == AMD_PG_STATE_GATE) {
uvd_v6_0_stop(adev);
- return 0;
+ adev->uvd.is_powergated = true;
} else {
- return uvd_v6_0_start(adev);
+ ret = uvd_v6_0_start(adev);
+ if (ret)
+ goto out;
+ adev->uvd.is_powergated = false;
+ }
+
+out:
+ return ret;
+}
+
+static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int data;
+
+ mutex_lock(&adev->pm.mutex);
+
+ if (adev->uvd.is_powergated) {
+ DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
+ goto out;
}
+
+ /* AMD_CG_SUPPORT_UVD_MGCG */
+ data = RREG32(mmUVD_CGC_CTRL);
+ if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
+ *flags |= AMD_CG_SUPPORT_UVD_MGCG;
+
+out:
+ mutex_unlock(&adev->pm.mutex);
}
static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
@@ -1019,6 +1047,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
.post_soft_reset = uvd_v6_0_post_soft_reset,
.set_clockgating_state = uvd_v6_0_set_clockgating_state,
.set_powergating_state = uvd_v6_0_set_powergating_state,
+ .get_clockgating_state = uvd_v6_0_get_clockgating_state,
};
static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread[parent not found: <1483977889-16256-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>]
* [PART1 PATCH v5 8/8] drm/amdgpu: add get clockgating_state method for vce v3 [not found] ` <1483977889-16256-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org> @ 2017-01-09 16:04 ` Huang Rui 2017-01-09 16:20 ` [PART1 PATCH v5 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6 Christian König 1 sibling, 0 replies; 3+ messages in thread From: Huang Rui @ 2017-01-09 16:04 UTC (permalink / raw) To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Christian König, Tom StDenis Cc: Huang Rui, Hawking Zhang, Rex Zhu, Ping Fu, David Mao Signed-off-by: Huang Rui <ray.huang@amd.com> --- Changes from V4 -> V5: - Remove pm mutex from set clock gating function. --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 40 +++++++++++++++++++++++++++++++---- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 31054c7..3c52b81 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1212,6 +1212,7 @@ struct amdgpu_vce { struct amd_sched_entity entity; uint32_t srbm_soft_reset; unsigned num_rings; + bool is_powergated; }; /* diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 35ff1c3..b248c57 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -770,15 +770,46 @@ static int vce_v3_0_set_powergating_state(void *handle, * the smc and the hw blocks */ struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret = 0; if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE)) return 0; - if (state == AMD_PG_STATE_GATE) + if (state == AMD_PG_STATE_GATE) { + adev->vce.is_powergated = true; /* XXX do we need a vce_v3_0_stop()? */ - return 0; - else - return vce_v3_0_start(adev); + } else { + ret = vce_v3_0_start(adev); + if (ret) + goto out; + adev->vce.is_powergated = false; + } + +out: + return ret; +} + +static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int data; + + mutex_lock(&adev->pm.mutex); + + if (adev->vce.is_powergated) { + DRM_INFO("Cannot get clockgating state when VCE is powergated.\n"); + goto out; + } + + WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); + + /* AMD_CG_SUPPORT_VCE_MGCG */ + data = RREG32(mmVCE_CLOCK_GATING_A); + if (data & (0x04 << 4)) + *flags |= AMD_CG_SUPPORT_VCE_MGCG; + +out: + mutex_unlock(&adev->pm.mutex); } static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring, @@ -832,6 +863,7 @@ static const struct amd_ip_funcs vce_v3_0_ip_funcs = { .post_soft_reset = vce_v3_0_post_soft_reset, .set_clockgating_state = vce_v3_0_set_clockgating_state, .set_powergating_state = vce_v3_0_set_powergating_state, + .get_clockgating_state = vce_v3_0_get_clockgating_state, }; static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { -- 2.7.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PART1 PATCH v5 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6 [not found] ` <1483977889-16256-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org> 2017-01-09 16:04 ` [PART1 PATCH v5 8/8] drm/amdgpu: add get clockgating_state method for vce v3 Huang Rui @ 2017-01-09 16:20 ` Christian König 1 sibling, 0 replies; 3+ messages in thread From: Christian König @ 2017-01-09 16:20 UTC (permalink / raw) To: Huang Rui, Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Christian König, Tom StDenis Cc: David Mao, Rex Zhu, Ping Fu, Hawking Zhang Am 09.01.2017 um 17:04 schrieb Huang Rui: > Signed-off-by: Huang Rui <ray.huang@amd.com> For this one and the VCE equivalent are Reviewed-by: Christian König <christian.koenig@amd.com>. Regards, Christian. > --- > > Changes from V4 -> V5: > - remove pm mutex from set clock gating function > > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + > drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 33 +++++++++++++++++++++++++++++++-- > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 33 +++++++++++++++++++++++++++++++-- > 3 files changed, 63 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 530549b..31054c7 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -1183,6 +1183,7 @@ struct amdgpu_uvd { > bool use_ctx_buf; > struct amd_sched_entity entity; > uint32_t srbm_soft_reset; > + bool is_powergated; > }; > > /* > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > index 03a35d9..2b8d2b2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > @@ -781,16 +781,44 @@ static int uvd_v5_0_set_powergating_state(void *handle, > * the smc and the hw blocks > */ > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + int ret = 0; > > if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) > return 0; > > if (state == AMD_PG_STATE_GATE) { > uvd_v5_0_stop(adev); > - return 0; > + adev->uvd.is_powergated = true; > } else { > - return uvd_v5_0_start(adev); > + ret = uvd_v5_0_start(adev); > + if (ret) > + goto out; > + adev->uvd.is_powergated = false; > + } > + > +out: > + return ret; > +} > + > +static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) > +{ > + struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + int data; > + > + mutex_lock(&adev->pm.mutex); > + > + if (adev->uvd.is_powergated) { > + DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); > + goto out; > } > + > + /* AMD_CG_SUPPORT_UVD_MGCG */ > + data = RREG32(mmUVD_CGC_CTRL); > + if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) > + *flags |= AMD_CG_SUPPORT_UVD_MGCG; > + > +out: > + mutex_unlock(&adev->pm.mutex); > } > > static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { > @@ -808,6 +836,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { > .soft_reset = uvd_v5_0_soft_reset, > .set_clockgating_state = uvd_v5_0_set_clockgating_state, > .set_powergating_state = uvd_v5_0_set_powergating_state, > + .get_clockgating_state = uvd_v5_0_get_clockgating_state, > }; > > static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index 8779d4b..f11d760 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -987,6 +987,7 @@ static int uvd_v6_0_set_powergating_state(void *handle, > * the smc and the hw blocks > */ > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + int ret = 0; > > if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) > return 0; > @@ -995,10 +996,37 @@ static int uvd_v6_0_set_powergating_state(void *handle, > > if (state == AMD_PG_STATE_GATE) { > uvd_v6_0_stop(adev); > - return 0; > + adev->uvd.is_powergated = true; > } else { > - return uvd_v6_0_start(adev); > + ret = uvd_v6_0_start(adev); > + if (ret) > + goto out; > + adev->uvd.is_powergated = false; > + } > + > +out: > + return ret; > +} > + > +static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags) > +{ > + struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + int data; > + > + mutex_lock(&adev->pm.mutex); > + > + if (adev->uvd.is_powergated) { > + DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); > + goto out; > } > + > + /* AMD_CG_SUPPORT_UVD_MGCG */ > + data = RREG32(mmUVD_CGC_CTRL); > + if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) > + *flags |= AMD_CG_SUPPORT_UVD_MGCG; > + > +out: > + mutex_unlock(&adev->pm.mutex); > } > > static const struct amd_ip_funcs uvd_v6_0_ip_funcs = { > @@ -1019,6 +1047,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = { > .post_soft_reset = uvd_v6_0_post_soft_reset, > .set_clockgating_state = uvd_v6_0_set_clockgating_state, > .set_powergating_state = uvd_v6_0_set_powergating_state, > + .get_clockgating_state = uvd_v6_0_get_clockgating_state, > }; > > static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-01-09 16:04 [PART1 PATCH v5 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6 Huang Rui
[not found] ` <1483977889-16256-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2017-01-09 16:04 ` [PART1 PATCH v5 8/8] drm/amdgpu: add get clockgating_state method for vce v3 Huang Rui
2017-01-09 16:20 ` [PART1 PATCH v5 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6 Christian König
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