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From: James Zhu <James.Zhu-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH 2/3] drm/amd/amdgpu: Replace uvd_v6_0_enc_support with uvd.num_enc_rings after uvd_v6_0_early_init
Date: Thu, 18 Jan 2018 10:49:52 -0500	[thread overview]
Message-ID: <1516290593-6955-2-git-send-email-James.Zhu@amd.com> (raw)
In-Reply-To: <1516290593-6955-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>

Signed-off-by: James Zhu <James.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 55 +++++++++++++++--------------------
 1 file changed, 23 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 612455d..319d4b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -402,17 +402,16 @@ static int uvd_v6_0_sw_init(void *handle)
 	if (r)
 		return r;
 
-	/* UVD ENC TRAP */
-	if (uvd_v6_0_enc_support(adev)) {
+	if (adev->uvd.num_enc_rings) {
+		struct drm_sched_rq *rq;
+
+		/* UVD ENC TRAP */
 		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 			r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
 			if (r)
 				return r;
 		}
-	}
 
-	if (uvd_v6_0_enc_support(adev)) {
-		struct drm_sched_rq *rq;
 		ring = &adev->uvd.ring_enc[0];
 		rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 		r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
@@ -433,14 +432,12 @@ static int uvd_v6_0_sw_init(void *handle)
 	if (r)
 		return r;
 
-	if (uvd_v6_0_enc_support(adev)) {
-		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-			ring = &adev->uvd.ring_enc[i];
-			sprintf(ring->name, "uvd_enc%d", i);
-			r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
-			if (r)
-				return r;
-		}
+	for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+		ring = &adev->uvd.ring_enc[i];
+		sprintf(ring->name, "uvd_enc%d", i);
+		r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+		if (r)
+			return r;
 	}
 
 	return r;
@@ -455,7 +452,7 @@ static int uvd_v6_0_sw_fini(void *handle)
 	if (r)
 		return r;
 
-	if (uvd_v6_0_enc_support(adev)) {
+	if (adev->uvd.num_enc_rings) {
 		drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
 
 		for (i = 0; i < adev->uvd.num_enc_rings; ++i)
@@ -517,21 +514,19 @@ static int uvd_v6_0_hw_init(void *handle)
 
 	amdgpu_ring_commit(ring);
 
-	if (uvd_v6_0_enc_support(adev)) {
-		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-			ring = &adev->uvd.ring_enc[i];
-			ring->ready = true;
-			r = amdgpu_ring_test_ring(ring);
-			if (r) {
-				ring->ready = false;
-				goto done;
-			}
+	for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+		ring = &adev->uvd.ring_enc[i];
+		ring->ready = true;
+		r = amdgpu_ring_test_ring(ring);
+		if (r) {
+			ring->ready = false;
+			goto done;
 		}
 	}
 
 done:
 	if (!r) {
-		if (uvd_v6_0_enc_support(adev))
+		if (adev->uvd.num_enc_rings)
 			DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 		else
 			DRM_INFO("UVD initialized successfully.\n");
@@ -852,7 +847,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
 
 	WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 
-	if (uvd_v6_0_enc_support(adev)) {
+	if (adev->uvd.num_enc_rings) {
 		ring = &adev->uvd.ring_enc[0];
 		WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 		WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
@@ -1254,13 +1249,13 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 		amdgpu_fence_process(&adev->uvd.ring);
 		break;
 	case 119:
-		if (likely(uvd_v6_0_enc_support(adev)))
+		if (likely(adev->uvd.num_enc_rings))
 			amdgpu_fence_process(&adev->uvd.ring_enc[0]);
 		else
 			int_handled = false;
 		break;
 	case 120:
-		if (likely(uvd_v6_0_enc_support(adev)))
+		if (likely(adev->uvd.num_enc_rings))
 			amdgpu_fence_process(&adev->uvd.ring_enc[1]);
 		else
 			int_handled = false;
@@ -1652,11 +1647,7 @@ static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
 
 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-	if (uvd_v6_0_enc_support(adev))
-		adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
-	else
-		adev->uvd.irq.num_types = 1;
-
+	adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
 	adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
 }
 
-- 
2.7.4

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  parent reply	other threads:[~2018-01-18 15:49 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-18 15:49 [PATCH 1/3] drm/amd/amdgpu: Move UVD TRAP after amdgpu_uvd_sw_init James Zhu
     [not found] ` <1516290593-6955-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 15:49   ` James Zhu [this message]
2018-01-18 15:49   ` [PATCH 3/3] drm/amd/amdgpu: Add Polaris version check James Zhu
     [not found]     ` <1516290593-6955-3-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-22 13:57       ` Leo Liu

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