* [PATCH 1/5] drm/amdgpu: split soc15ip header into ip and ip_offset header
@ 2018-01-22 12:15 Hawking Zhang
[not found] ` <1516623354-24912-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Hawking Zhang @ 2018-01-22 12:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang
ip base could be different per ASIC since from soc15. split soc15
header into common ip/hw_id header and asic specific ip offset header
Change-Id: I54e5856e1b99d4e313e61328c0fcd85cdd3b3267
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/include/soc15_hw_ip.h | 98 ++
drivers/gpu/drm/amd/include/vega10_ip_offset.h | 1265 ++++++++++++++++++++++++
2 files changed, 1363 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/soc15_hw_ip.h
create mode 100644 drivers/gpu/drm/amd/include/vega10_ip_offset.h
diff --git a/drivers/gpu/drm/amd/include/soc15_hw_ip.h b/drivers/gpu/drm/amd/include/soc15_hw_ip.h
new file mode 100644
index 0000000..f17e30c
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/soc15_hw_ip.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _soc15_hw_ip_HEADER
+#define _soc15_hw_ip_HEADER
+
+// HW ID
+#define MP1_HWID 1
+#define MP2_HWID 2
+#define THM_HWID 3
+#define SMUIO_HWID 4
+#define FUSE_HWID 5
+#define CLKA_HWID 6
+#define PWR_HWID 10
+#define GC_HWID 11
+#define UVD_HWID 12
+#define VCN_HWID UVD_HWID
+#define AUDIO_AZ_HWID 13
+#define ACP_HWID 14
+#define DCI_HWID 15
+#define DMU_HWID 271
+#define DCO_HWID 16
+#define DIO_HWID 272
+#define XDMA_HWID 17
+#define DCEAZ_HWID 18
+#define DAZ_HWID 274
+#define SDPMUX_HWID 19
+#define NTB_HWID 20
+#define IOHC_HWID 24
+#define L2IMU_HWID 28
+#define VCE_HWID 32
+#define MMHUB_HWID 34
+#define ATHUB_HWID 35
+#define DBGU_NBIO_HWID 36
+#define DFX_HWID 37
+#define DBGU0_HWID 38
+#define DBGU1_HWID 39
+#define OSSSYS_HWID 40
+#define HDP_HWID 41
+#define SDMA0_HWID 42
+#define SDMA1_HWID 43
+#define ISP_HWID 44
+#define DBGU_IO_HWID 45
+#define DF_HWID 46
+#define CLKB_HWID 47
+#define FCH_HWID 48
+#define DFX_DAP_HWID 49
+#define L1IMU_PCIE_HWID 50
+#define L1IMU_NBIF_HWID 51
+#define L1IMU_IOAGR_HWID 52
+#define L1IMU3_HWID 53
+#define L1IMU4_HWID 54
+#define L1IMU5_HWID 55
+#define L1IMU6_HWID 56
+#define L1IMU7_HWID 57
+#define L1IMU8_HWID 58
+#define L1IMU9_HWID 59
+#define L1IMU10_HWID 60
+#define L1IMU11_HWID 61
+#define L1IMU12_HWID 62
+#define L1IMU13_HWID 63
+#define L1IMU14_HWID 64
+#define L1IMU15_HWID 65
+#define WAFLC_HWID 66
+#define FCH_USB_PD_HWID 67
+#define PCIE_HWID 70
+#define PCS_HWID 80
+#define DDCL_HWID 89
+#define SST_HWID 90
+#define IOAGR_HWID 100
+#define NBIF_HWID 108
+#define IOAPIC_HWID 124
+#define SYSTEMHUB_HWID 128
+#define NTBCCP_HWID 144
+#define UMC_HWID 150
+#define SATA_HWID 168
+#define USB_HWID 170
+#define CCXSEC_HWID 176
+#define XGBE_HWID 216
+#define MP0_HWID 254
+#endif
diff --git a/drivers/gpu/drm/amd/include/vega10_ip_offset.h b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
new file mode 100644
index 0000000..4c78dba
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
@@ -0,0 +1,1265 @@
+/*
+ * Copyright (C) 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _vega10_ip_offset_HEADER
+#define _vega10_ip_offset_HEADER
+
+#define MAX_INSTANCE 5
+#define MAX_SEGMENT 5
+
+struct IP_BASE_INSTANCE
+{
+ unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
+static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
+static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
+ { { 0x00016E00, 0, 0, 0, 0 } },
+ { { 0x00017000, 0, 0, 0, 0 } },
+ { { 0x00017200, 0, 0, 0, 0 } },
+ { { 0x00017E00, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+
+
+#define NBIF_BASE__INST0_SEG0 0x00000000
+#define NBIF_BASE__INST0_SEG1 0x00000014
+#define NBIF_BASE__INST0_SEG2 0x00000D20
+#define NBIF_BASE__INST0_SEG3 0x00010400
+#define NBIF_BASE__INST0_SEG4 0
+
+#define NBIF_BASE__INST1_SEG0 0
+#define NBIF_BASE__INST1_SEG1 0
+#define NBIF_BASE__INST1_SEG2 0
+#define NBIF_BASE__INST1_SEG3 0
+#define NBIF_BASE__INST1_SEG4 0
+
+#define NBIF_BASE__INST2_SEG0 0
+#define NBIF_BASE__INST2_SEG1 0
+#define NBIF_BASE__INST2_SEG2 0
+#define NBIF_BASE__INST2_SEG3 0
+#define NBIF_BASE__INST2_SEG4 0
+
+#define NBIF_BASE__INST3_SEG0 0
+#define NBIF_BASE__INST3_SEG1 0
+#define NBIF_BASE__INST3_SEG2 0
+#define NBIF_BASE__INST3_SEG3 0
+#define NBIF_BASE__INST3_SEG4 0
+
+#define NBIF_BASE__INST4_SEG0 0
+#define NBIF_BASE__INST4_SEG1 0
+#define NBIF_BASE__INST4_SEG2 0
+#define NBIF_BASE__INST4_SEG3 0
+#define NBIF_BASE__INST4_SEG4 0
+
+#define NBIO_BASE__INST0_SEG0 0x00000000
+#define NBIO_BASE__INST0_SEG1 0x00000014
+#define NBIO_BASE__INST0_SEG2 0x00000D20
+#define NBIO_BASE__INST0_SEG3 0x00010400
+#define NBIO_BASE__INST0_SEG4 0
+
+#define NBIO_BASE__INST1_SEG0 0
+#define NBIO_BASE__INST1_SEG1 0
+#define NBIO_BASE__INST1_SEG2 0
+#define NBIO_BASE__INST1_SEG3 0
+#define NBIO_BASE__INST1_SEG4 0
+
+#define NBIO_BASE__INST2_SEG0 0
+#define NBIO_BASE__INST2_SEG1 0
+#define NBIO_BASE__INST2_SEG2 0
+#define NBIO_BASE__INST2_SEG3 0
+#define NBIO_BASE__INST2_SEG4 0
+
+#define NBIO_BASE__INST3_SEG0 0
+#define NBIO_BASE__INST3_SEG1 0
+#define NBIO_BASE__INST3_SEG2 0
+#define NBIO_BASE__INST3_SEG3 0
+#define NBIO_BASE__INST3_SEG4 0
+
+#define NBIO_BASE__INST4_SEG0 0
+#define NBIO_BASE__INST4_SEG1 0
+#define NBIO_BASE__INST4_SEG2 0
+#define NBIO_BASE__INST4_SEG3 0
+#define NBIO_BASE__INST4_SEG4 0
+
+#define DCE_BASE__INST0_SEG0 0x00000012
+#define DCE_BASE__INST0_SEG1 0x000000C0
+#define DCE_BASE__INST0_SEG2 0x000034C0
+#define DCE_BASE__INST0_SEG3 0
+#define DCE_BASE__INST0_SEG4 0
+
+#define DCE_BASE__INST1_SEG0 0
+#define DCE_BASE__INST1_SEG1 0
+#define DCE_BASE__INST1_SEG2 0
+#define DCE_BASE__INST1_SEG3 0
+#define DCE_BASE__INST1_SEG4 0
+
+#define DCE_BASE__INST2_SEG0 0
+#define DCE_BASE__INST2_SEG1 0
+#define DCE_BASE__INST2_SEG2 0
+#define DCE_BASE__INST2_SEG3 0
+#define DCE_BASE__INST2_SEG4 0
+
+#define DCE_BASE__INST3_SEG0 0
+#define DCE_BASE__INST3_SEG1 0
+#define DCE_BASE__INST3_SEG2 0
+#define DCE_BASE__INST3_SEG3 0
+#define DCE_BASE__INST3_SEG4 0
+
+#define DCE_BASE__INST4_SEG0 0
+#define DCE_BASE__INST4_SEG1 0
+#define DCE_BASE__INST4_SEG2 0
+#define DCE_BASE__INST4_SEG3 0
+#define DCE_BASE__INST4_SEG4 0
+
+#define DCN_BASE__INST0_SEG0 0x00000012
+#define DCN_BASE__INST0_SEG1 0x000000C0
+#define DCN_BASE__INST0_SEG2 0x000034C0
+#define DCN_BASE__INST0_SEG3 0
+#define DCN_BASE__INST0_SEG4 0
+
+#define DCN_BASE__INST1_SEG0 0
+#define DCN_BASE__INST1_SEG1 0
+#define DCN_BASE__INST1_SEG2 0
+#define DCN_BASE__INST1_SEG3 0
+#define DCN_BASE__INST1_SEG4 0
+
+#define DCN_BASE__INST2_SEG0 0
+#define DCN_BASE__INST2_SEG1 0
+#define DCN_BASE__INST2_SEG2 0
+#define DCN_BASE__INST2_SEG3 0
+#define DCN_BASE__INST2_SEG4 0
+
+#define DCN_BASE__INST3_SEG0 0
+#define DCN_BASE__INST3_SEG1 0
+#define DCN_BASE__INST3_SEG2 0
+#define DCN_BASE__INST3_SEG3 0
+#define DCN_BASE__INST3_SEG4 0
+
+#define DCN_BASE__INST4_SEG0 0
+#define DCN_BASE__INST4_SEG1 0
+#define DCN_BASE__INST4_SEG2 0
+#define DCN_BASE__INST4_SEG3 0
+#define DCN_BASE__INST4_SEG4 0
+
+#define MP0_BASE__INST0_SEG0 0x00016000
+#define MP0_BASE__INST0_SEG1 0
+#define MP0_BASE__INST0_SEG2 0
+#define MP0_BASE__INST0_SEG3 0
+#define MP0_BASE__INST0_SEG4 0
+
+#define MP0_BASE__INST1_SEG0 0
+#define MP0_BASE__INST1_SEG1 0
+#define MP0_BASE__INST1_SEG2 0
+#define MP0_BASE__INST1_SEG3 0
+#define MP0_BASE__INST1_SEG4 0
+
+#define MP0_BASE__INST2_SEG0 0
+#define MP0_BASE__INST2_SEG1 0
+#define MP0_BASE__INST2_SEG2 0
+#define MP0_BASE__INST2_SEG3 0
+#define MP0_BASE__INST2_SEG4 0
+
+#define MP0_BASE__INST3_SEG0 0
+#define MP0_BASE__INST3_SEG1 0
+#define MP0_BASE__INST3_SEG2 0
+#define MP0_BASE__INST3_SEG3 0
+#define MP0_BASE__INST3_SEG4 0
+
+#define MP0_BASE__INST4_SEG0 0
+#define MP0_BASE__INST4_SEG1 0
+#define MP0_BASE__INST4_SEG2 0
+#define MP0_BASE__INST4_SEG3 0
+#define MP0_BASE__INST4_SEG4 0
+
+#define MP1_BASE__INST0_SEG0 0x00016200
+#define MP1_BASE__INST0_SEG1 0
+#define MP1_BASE__INST0_SEG2 0
+#define MP1_BASE__INST0_SEG3 0
+#define MP1_BASE__INST0_SEG4 0
+
+#define MP1_BASE__INST1_SEG0 0
+#define MP1_BASE__INST1_SEG1 0
+#define MP1_BASE__INST1_SEG2 0
+#define MP1_BASE__INST1_SEG3 0
+#define MP1_BASE__INST1_SEG4 0
+
+#define MP1_BASE__INST2_SEG0 0
+#define MP1_BASE__INST2_SEG1 0
+#define MP1_BASE__INST2_SEG2 0
+#define MP1_BASE__INST2_SEG3 0
+#define MP1_BASE__INST2_SEG4 0
+
+#define MP1_BASE__INST3_SEG0 0
+#define MP1_BASE__INST3_SEG1 0
+#define MP1_BASE__INST3_SEG2 0
+#define MP1_BASE__INST3_SEG3 0
+#define MP1_BASE__INST3_SEG4 0
+
+#define MP1_BASE__INST4_SEG0 0
+#define MP1_BASE__INST4_SEG1 0
+#define MP1_BASE__INST4_SEG2 0
+#define MP1_BASE__INST4_SEG3 0
+#define MP1_BASE__INST4_SEG4 0
+
+#define MP2_BASE__INST0_SEG0 0x00016400
+#define MP2_BASE__INST0_SEG1 0
+#define MP2_BASE__INST0_SEG2 0
+#define MP2_BASE__INST0_SEG3 0
+#define MP2_BASE__INST0_SEG4 0
+
+#define MP2_BASE__INST1_SEG0 0
+#define MP2_BASE__INST1_SEG1 0
+#define MP2_BASE__INST1_SEG2 0
+#define MP2_BASE__INST1_SEG3 0
+#define MP2_BASE__INST1_SEG4 0
+
+#define MP2_BASE__INST2_SEG0 0
+#define MP2_BASE__INST2_SEG1 0
+#define MP2_BASE__INST2_SEG2 0
+#define MP2_BASE__INST2_SEG3 0
+#define MP2_BASE__INST2_SEG4 0
+
+#define MP2_BASE__INST3_SEG0 0
+#define MP2_BASE__INST3_SEG1 0
+#define MP2_BASE__INST3_SEG2 0
+#define MP2_BASE__INST3_SEG3 0
+#define MP2_BASE__INST3_SEG4 0
+
+#define MP2_BASE__INST4_SEG0 0
+#define MP2_BASE__INST4_SEG1 0
+#define MP2_BASE__INST4_SEG2 0
+#define MP2_BASE__INST4_SEG3 0
+#define MP2_BASE__INST4_SEG4 0
+
+#define DF_BASE__INST0_SEG0 0x00007000
+#define DF_BASE__INST0_SEG1 0
+#define DF_BASE__INST0_SEG2 0
+#define DF_BASE__INST0_SEG3 0
+#define DF_BASE__INST0_SEG4 0
+
+#define DF_BASE__INST1_SEG0 0
+#define DF_BASE__INST1_SEG1 0
+#define DF_BASE__INST1_SEG2 0
+#define DF_BASE__INST1_SEG3 0
+#define DF_BASE__INST1_SEG4 0
+
+#define DF_BASE__INST2_SEG0 0
+#define DF_BASE__INST2_SEG1 0
+#define DF_BASE__INST2_SEG2 0
+#define DF_BASE__INST2_SEG3 0
+#define DF_BASE__INST2_SEG4 0
+
+#define DF_BASE__INST3_SEG0 0
+#define DF_BASE__INST3_SEG1 0
+#define DF_BASE__INST3_SEG2 0
+#define DF_BASE__INST3_SEG3 0
+#define DF_BASE__INST3_SEG4 0
+
+#define DF_BASE__INST4_SEG0 0
+#define DF_BASE__INST4_SEG1 0
+#define DF_BASE__INST4_SEG2 0
+#define DF_BASE__INST4_SEG3 0
+#define DF_BASE__INST4_SEG4 0
+
+#define UVD_BASE__INST0_SEG0 0x00007800
+#define UVD_BASE__INST0_SEG1 0x00007E00
+#define UVD_BASE__INST0_SEG2 0
+#define UVD_BASE__INST0_SEG3 0
+#define UVD_BASE__INST0_SEG4 0
+
+#define UVD_BASE__INST1_SEG0 0
+#define UVD_BASE__INST1_SEG1 0
+#define UVD_BASE__INST1_SEG2 0
+#define UVD_BASE__INST1_SEG3 0
+#define UVD_BASE__INST1_SEG4 0
+
+#define UVD_BASE__INST2_SEG0 0
+#define UVD_BASE__INST2_SEG1 0
+#define UVD_BASE__INST2_SEG2 0
+#define UVD_BASE__INST2_SEG3 0
+#define UVD_BASE__INST2_SEG4 0
+
+#define UVD_BASE__INST3_SEG0 0
+#define UVD_BASE__INST3_SEG1 0
+#define UVD_BASE__INST3_SEG2 0
+#define UVD_BASE__INST3_SEG3 0
+#define UVD_BASE__INST3_SEG4 0
+
+#define UVD_BASE__INST4_SEG0 0
+#define UVD_BASE__INST4_SEG1 0
+#define UVD_BASE__INST4_SEG2 0
+#define UVD_BASE__INST4_SEG3 0
+#define UVD_BASE__INST4_SEG4 0
+
+#define VCN_BASE__INST0_SEG0 0x00007800
+#define VCN_BASE__INST0_SEG1 0x00007E00
+#define VCN_BASE__INST0_SEG2 0
+#define VCN_BASE__INST0_SEG3 0
+#define VCN_BASE__INST0_SEG4 0
+
+#define VCN_BASE__INST1_SEG0 0
+#define VCN_BASE__INST1_SEG1 0
+#define VCN_BASE__INST1_SEG2 0
+#define VCN_BASE__INST1_SEG3 0
+#define VCN_BASE__INST1_SEG4 0
+
+#define VCN_BASE__INST2_SEG0 0
+#define VCN_BASE__INST2_SEG1 0
+#define VCN_BASE__INST2_SEG2 0
+#define VCN_BASE__INST2_SEG3 0
+#define VCN_BASE__INST2_SEG4 0
+
+#define VCN_BASE__INST3_SEG0 0
+#define VCN_BASE__INST3_SEG1 0
+#define VCN_BASE__INST3_SEG2 0
+#define VCN_BASE__INST3_SEG3 0
+#define VCN_BASE__INST3_SEG4 0
+
+#define VCN_BASE__INST4_SEG0 0
+#define VCN_BASE__INST4_SEG1 0
+#define VCN_BASE__INST4_SEG2 0
+#define VCN_BASE__INST4_SEG3 0
+#define VCN_BASE__INST4_SEG4 0
+
+#define DBGU_BASE__INST0_SEG0 0x00000180
+#define DBGU_BASE__INST0_SEG1 0x000001A0
+#define DBGU_BASE__INST0_SEG2 0
+#define DBGU_BASE__INST0_SEG3 0
+#define DBGU_BASE__INST0_SEG4 0
+
+#define DBGU_BASE__INST1_SEG0 0
+#define DBGU_BASE__INST1_SEG1 0
+#define DBGU_BASE__INST1_SEG2 0
+#define DBGU_BASE__INST1_SEG3 0
+#define DBGU_BASE__INST1_SEG4 0
+
+#define DBGU_BASE__INST2_SEG0 0
+#define DBGU_BASE__INST2_SEG1 0
+#define DBGU_BASE__INST2_SEG2 0
+#define DBGU_BASE__INST2_SEG3 0
+#define DBGU_BASE__INST2_SEG4 0
+
+#define DBGU_BASE__INST3_SEG0 0
+#define DBGU_BASE__INST3_SEG1 0
+#define DBGU_BASE__INST3_SEG2 0
+#define DBGU_BASE__INST3_SEG3 0
+#define DBGU_BASE__INST3_SEG4 0
+
+#define DBGU_BASE__INST4_SEG0 0
+#define DBGU_BASE__INST4_SEG1 0
+#define DBGU_BASE__INST4_SEG2 0
+#define DBGU_BASE__INST4_SEG3 0
+#define DBGU_BASE__INST4_SEG4 0
+
+#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0
+#define DBGU_NBIO_BASE__INST0_SEG1 0
+#define DBGU_NBIO_BASE__INST0_SEG2 0
+#define DBGU_NBIO_BASE__INST0_SEG3 0
+#define DBGU_NBIO_BASE__INST0_SEG4 0
+
+#define DBGU_NBIO_BASE__INST1_SEG0 0
+#define DBGU_NBIO_BASE__INST1_SEG1 0
+#define DBGU_NBIO_BASE__INST1_SEG2 0
+#define DBGU_NBIO_BASE__INST1_SEG3 0
+#define DBGU_NBIO_BASE__INST1_SEG4 0
+
+#define DBGU_NBIO_BASE__INST2_SEG0 0
+#define DBGU_NBIO_BASE__INST2_SEG1 0
+#define DBGU_NBIO_BASE__INST2_SEG2 0
+#define DBGU_NBIO_BASE__INST2_SEG3 0
+#define DBGU_NBIO_BASE__INST2_SEG4 0
+
+#define DBGU_NBIO_BASE__INST3_SEG0 0
+#define DBGU_NBIO_BASE__INST3_SEG1 0
+#define DBGU_NBIO_BASE__INST3_SEG2 0
+#define DBGU_NBIO_BASE__INST3_SEG3 0
+#define DBGU_NBIO_BASE__INST3_SEG4 0
+
+#define DBGU_NBIO_BASE__INST4_SEG0 0
+#define DBGU_NBIO_BASE__INST4_SEG1 0
+#define DBGU_NBIO_BASE__INST4_SEG2 0
+#define DBGU_NBIO_BASE__INST4_SEG3 0
+#define DBGU_NBIO_BASE__INST4_SEG4 0
+
+#define DBGU_IO_BASE__INST0_SEG0 0x000001E0
+#define DBGU_IO_BASE__INST0_SEG1 0
+#define DBGU_IO_BASE__INST0_SEG2 0
+#define DBGU_IO_BASE__INST0_SEG3 0
+#define DBGU_IO_BASE__INST0_SEG4 0
+
+#define DBGU_IO_BASE__INST1_SEG0 0
+#define DBGU_IO_BASE__INST1_SEG1 0
+#define DBGU_IO_BASE__INST1_SEG2 0
+#define DBGU_IO_BASE__INST1_SEG3 0
+#define DBGU_IO_BASE__INST1_SEG4 0
+
+#define DBGU_IO_BASE__INST2_SEG0 0
+#define DBGU_IO_BASE__INST2_SEG1 0
+#define DBGU_IO_BASE__INST2_SEG2 0
+#define DBGU_IO_BASE__INST2_SEG3 0
+#define DBGU_IO_BASE__INST2_SEG4 0
+
+#define DBGU_IO_BASE__INST3_SEG0 0
+#define DBGU_IO_BASE__INST3_SEG1 0
+#define DBGU_IO_BASE__INST3_SEG2 0
+#define DBGU_IO_BASE__INST3_SEG3 0
+#define DBGU_IO_BASE__INST3_SEG4 0
+
+#define DBGU_IO_BASE__INST4_SEG0 0
+#define DBGU_IO_BASE__INST4_SEG1 0
+#define DBGU_IO_BASE__INST4_SEG2 0
+#define DBGU_IO_BASE__INST4_SEG3 0
+#define DBGU_IO_BASE__INST4_SEG4 0
+
+#define DFX_DAP_BASE__INST0_SEG0 0x000005A0
+#define DFX_DAP_BASE__INST0_SEG1 0
+#define DFX_DAP_BASE__INST0_SEG2 0
+#define DFX_DAP_BASE__INST0_SEG3 0
+#define DFX_DAP_BASE__INST0_SEG4 0
+
+#define DFX_DAP_BASE__INST1_SEG0 0
+#define DFX_DAP_BASE__INST1_SEG1 0
+#define DFX_DAP_BASE__INST1_SEG2 0
+#define DFX_DAP_BASE__INST1_SEG3 0
+#define DFX_DAP_BASE__INST1_SEG4 0
+
+#define DFX_DAP_BASE__INST2_SEG0 0
+#define DFX_DAP_BASE__INST2_SEG1 0
+#define DFX_DAP_BASE__INST2_SEG2 0
+#define DFX_DAP_BASE__INST2_SEG3 0
+#define DFX_DAP_BASE__INST2_SEG4 0
+
+#define DFX_DAP_BASE__INST3_SEG0 0
+#define DFX_DAP_BASE__INST3_SEG1 0
+#define DFX_DAP_BASE__INST3_SEG2 0
+#define DFX_DAP_BASE__INST3_SEG3 0
+#define DFX_DAP_BASE__INST3_SEG4 0
+
+#define DFX_DAP_BASE__INST4_SEG0 0
+#define DFX_DAP_BASE__INST4_SEG1 0
+#define DFX_DAP_BASE__INST4_SEG2 0
+#define DFX_DAP_BASE__INST4_SEG3 0
+#define DFX_DAP_BASE__INST4_SEG4 0
+
+#define DFX_BASE__INST0_SEG0 0x00000580
+#define DFX_BASE__INST0_SEG1 0
+#define DFX_BASE__INST0_SEG2 0
+#define DFX_BASE__INST0_SEG3 0
+#define DFX_BASE__INST0_SEG4 0
+
+#define DFX_BASE__INST1_SEG0 0
+#define DFX_BASE__INST1_SEG1 0
+#define DFX_BASE__INST1_SEG2 0
+#define DFX_BASE__INST1_SEG3 0
+#define DFX_BASE__INST1_SEG4 0
+
+#define DFX_BASE__INST2_SEG0 0
+#define DFX_BASE__INST2_SEG1 0
+#define DFX_BASE__INST2_SEG2 0
+#define DFX_BASE__INST2_SEG3 0
+#define DFX_BASE__INST2_SEG4 0
+
+#define DFX_BASE__INST3_SEG0 0
+#define DFX_BASE__INST3_SEG1 0
+#define DFX_BASE__INST3_SEG2 0
+#define DFX_BASE__INST3_SEG3 0
+#define DFX_BASE__INST3_SEG4 0
+
+#define DFX_BASE__INST4_SEG0 0
+#define DFX_BASE__INST4_SEG1 0
+#define DFX_BASE__INST4_SEG2 0
+#define DFX_BASE__INST4_SEG3 0
+#define DFX_BASE__INST4_SEG4 0
+
+#define ISP_BASE__INST0_SEG0 0x00018000
+#define ISP_BASE__INST0_SEG1 0
+#define ISP_BASE__INST0_SEG2 0
+#define ISP_BASE__INST0_SEG3 0
+#define ISP_BASE__INST0_SEG4 0
+
+#define ISP_BASE__INST1_SEG0 0
+#define ISP_BASE__INST1_SEG1 0
+#define ISP_BASE__INST1_SEG2 0
+#define ISP_BASE__INST1_SEG3 0
+#define ISP_BASE__INST1_SEG4 0
+
+#define ISP_BASE__INST2_SEG0 0
+#define ISP_BASE__INST2_SEG1 0
+#define ISP_BASE__INST2_SEG2 0
+#define ISP_BASE__INST2_SEG3 0
+#define ISP_BASE__INST2_SEG4 0
+
+#define ISP_BASE__INST3_SEG0 0
+#define ISP_BASE__INST3_SEG1 0
+#define ISP_BASE__INST3_SEG2 0
+#define ISP_BASE__INST3_SEG3 0
+#define ISP_BASE__INST3_SEG4 0
+
+#define ISP_BASE__INST4_SEG0 0
+#define ISP_BASE__INST4_SEG1 0
+#define ISP_BASE__INST4_SEG2 0
+#define ISP_BASE__INST4_SEG3 0
+#define ISP_BASE__INST4_SEG4 0
+
+#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0
+#define SYSTEMHUB_BASE__INST0_SEG1 0
+#define SYSTEMHUB_BASE__INST0_SEG2 0
+#define SYSTEMHUB_BASE__INST0_SEG3 0
+#define SYSTEMHUB_BASE__INST0_SEG4 0
+
+#define SYSTEMHUB_BASE__INST1_SEG0 0
+#define SYSTEMHUB_BASE__INST1_SEG1 0
+#define SYSTEMHUB_BASE__INST1_SEG2 0
+#define SYSTEMHUB_BASE__INST1_SEG3 0
+#define SYSTEMHUB_BASE__INST1_SEG4 0
+
+#define SYSTEMHUB_BASE__INST2_SEG0 0
+#define SYSTEMHUB_BASE__INST2_SEG1 0
+#define SYSTEMHUB_BASE__INST2_SEG2 0
+#define SYSTEMHUB_BASE__INST2_SEG3 0
+#define SYSTEMHUB_BASE__INST2_SEG4 0
+
+#define SYSTEMHUB_BASE__INST3_SEG0 0
+#define SYSTEMHUB_BASE__INST3_SEG1 0
+#define SYSTEMHUB_BASE__INST3_SEG2 0
+#define SYSTEMHUB_BASE__INST3_SEG3 0
+#define SYSTEMHUB_BASE__INST3_SEG4 0
+
+#define SYSTEMHUB_BASE__INST4_SEG0 0
+#define SYSTEMHUB_BASE__INST4_SEG1 0
+#define SYSTEMHUB_BASE__INST4_SEG2 0
+#define SYSTEMHUB_BASE__INST4_SEG3 0
+#define SYSTEMHUB_BASE__INST4_SEG4 0
+
+#define L2IMU_BASE__INST0_SEG0 0x00007DC0
+#define L2IMU_BASE__INST0_SEG1 0
+#define L2IMU_BASE__INST0_SEG2 0
+#define L2IMU_BASE__INST0_SEG3 0
+#define L2IMU_BASE__INST0_SEG4 0
+
+#define L2IMU_BASE__INST1_SEG0 0
+#define L2IMU_BASE__INST1_SEG1 0
+#define L2IMU_BASE__INST1_SEG2 0
+#define L2IMU_BASE__INST1_SEG3 0
+#define L2IMU_BASE__INST1_SEG4 0
+
+#define L2IMU_BASE__INST2_SEG0 0
+#define L2IMU_BASE__INST2_SEG1 0
+#define L2IMU_BASE__INST2_SEG2 0
+#define L2IMU_BASE__INST2_SEG3 0
+#define L2IMU_BASE__INST2_SEG4 0
+
+#define L2IMU_BASE__INST3_SEG0 0
+#define L2IMU_BASE__INST3_SEG1 0
+#define L2IMU_BASE__INST3_SEG2 0
+#define L2IMU_BASE__INST3_SEG3 0
+#define L2IMU_BASE__INST3_SEG4 0
+
+#define L2IMU_BASE__INST4_SEG0 0
+#define L2IMU_BASE__INST4_SEG1 0
+#define L2IMU_BASE__INST4_SEG2 0
+#define L2IMU_BASE__INST4_SEG3 0
+#define L2IMU_BASE__INST4_SEG4 0
+
+#define IOHC_BASE__INST0_SEG0 0x00010000
+#define IOHC_BASE__INST0_SEG1 0
+#define IOHC_BASE__INST0_SEG2 0
+#define IOHC_BASE__INST0_SEG3 0
+#define IOHC_BASE__INST0_SEG4 0
+
+#define IOHC_BASE__INST1_SEG0 0
+#define IOHC_BASE__INST1_SEG1 0
+#define IOHC_BASE__INST1_SEG2 0
+#define IOHC_BASE__INST1_SEG3 0
+#define IOHC_BASE__INST1_SEG4 0
+
+#define IOHC_BASE__INST2_SEG0 0
+#define IOHC_BASE__INST2_SEG1 0
+#define IOHC_BASE__INST2_SEG2 0
+#define IOHC_BASE__INST2_SEG3 0
+#define IOHC_BASE__INST2_SEG4 0
+
+#define IOHC_BASE__INST3_SEG0 0
+#define IOHC_BASE__INST3_SEG1 0
+#define IOHC_BASE__INST3_SEG2 0
+#define IOHC_BASE__INST3_SEG3 0
+#define IOHC_BASE__INST3_SEG4 0
+
+#define IOHC_BASE__INST4_SEG0 0
+#define IOHC_BASE__INST4_SEG1 0
+#define IOHC_BASE__INST4_SEG2 0
+#define IOHC_BASE__INST4_SEG3 0
+#define IOHC_BASE__INST4_SEG4 0
+
+#define ATHUB_BASE__INST0_SEG0 0x00000C20
+#define ATHUB_BASE__INST0_SEG1 0
+#define ATHUB_BASE__INST0_SEG2 0
+#define ATHUB_BASE__INST0_SEG3 0
+#define ATHUB_BASE__INST0_SEG4 0
+
+#define ATHUB_BASE__INST1_SEG0 0
+#define ATHUB_BASE__INST1_SEG1 0
+#define ATHUB_BASE__INST1_SEG2 0
+#define ATHUB_BASE__INST1_SEG3 0
+#define ATHUB_BASE__INST1_SEG4 0
+
+#define ATHUB_BASE__INST2_SEG0 0
+#define ATHUB_BASE__INST2_SEG1 0
+#define ATHUB_BASE__INST2_SEG2 0
+#define ATHUB_BASE__INST2_SEG3 0
+#define ATHUB_BASE__INST2_SEG4 0
+
+#define ATHUB_BASE__INST3_SEG0 0
+#define ATHUB_BASE__INST3_SEG1 0
+#define ATHUB_BASE__INST3_SEG2 0
+#define ATHUB_BASE__INST3_SEG3 0
+#define ATHUB_BASE__INST3_SEG4 0
+
+#define ATHUB_BASE__INST4_SEG0 0
+#define ATHUB_BASE__INST4_SEG1 0
+#define ATHUB_BASE__INST4_SEG2 0
+#define ATHUB_BASE__INST4_SEG3 0
+#define ATHUB_BASE__INST4_SEG4 0
+
+#define VCE_BASE__INST0_SEG0 0x00007E00
+#define VCE_BASE__INST0_SEG1 0x00048800
+#define VCE_BASE__INST0_SEG2 0
+#define VCE_BASE__INST0_SEG3 0
+#define VCE_BASE__INST0_SEG4 0
+
+#define VCE_BASE__INST1_SEG0 0
+#define VCE_BASE__INST1_SEG1 0
+#define VCE_BASE__INST1_SEG2 0
+#define VCE_BASE__INST1_SEG3 0
+#define VCE_BASE__INST1_SEG4 0
+
+#define VCE_BASE__INST2_SEG0 0
+#define VCE_BASE__INST2_SEG1 0
+#define VCE_BASE__INST2_SEG2 0
+#define VCE_BASE__INST2_SEG3 0
+#define VCE_BASE__INST2_SEG4 0
+
+#define VCE_BASE__INST3_SEG0 0
+#define VCE_BASE__INST3_SEG1 0
+#define VCE_BASE__INST3_SEG2 0
+#define VCE_BASE__INST3_SEG3 0
+#define VCE_BASE__INST3_SEG4 0
+
+#define VCE_BASE__INST4_SEG0 0
+#define VCE_BASE__INST4_SEG1 0
+#define VCE_BASE__INST4_SEG2 0
+#define VCE_BASE__INST4_SEG3 0
+#define VCE_BASE__INST4_SEG4 0
+
+#define GC_BASE__INST0_SEG0 0x00002000
+#define GC_BASE__INST0_SEG1 0x0000A000
+#define GC_BASE__INST0_SEG2 0
+#define GC_BASE__INST0_SEG3 0
+#define GC_BASE__INST0_SEG4 0
+
+#define GC_BASE__INST1_SEG0 0
+#define GC_BASE__INST1_SEG1 0
+#define GC_BASE__INST1_SEG2 0
+#define GC_BASE__INST1_SEG3 0
+#define GC_BASE__INST1_SEG4 0
+
+#define GC_BASE__INST2_SEG0 0
+#define GC_BASE__INST2_SEG1 0
+#define GC_BASE__INST2_SEG2 0
+#define GC_BASE__INST2_SEG3 0
+#define GC_BASE__INST2_SEG4 0
+
+#define GC_BASE__INST3_SEG0 0
+#define GC_BASE__INST3_SEG1 0
+#define GC_BASE__INST3_SEG2 0
+#define GC_BASE__INST3_SEG3 0
+#define GC_BASE__INST3_SEG4 0
+
+#define GC_BASE__INST4_SEG0 0
+#define GC_BASE__INST4_SEG1 0
+#define GC_BASE__INST4_SEG2 0
+#define GC_BASE__INST4_SEG3 0
+#define GC_BASE__INST4_SEG4 0
+
+#define MMHUB_BASE__INST0_SEG0 0x0001A000
+#define MMHUB_BASE__INST0_SEG1 0
+#define MMHUB_BASE__INST0_SEG2 0
+#define MMHUB_BASE__INST0_SEG3 0
+#define MMHUB_BASE__INST0_SEG4 0
+
+#define MMHUB_BASE__INST1_SEG0 0
+#define MMHUB_BASE__INST1_SEG1 0
+#define MMHUB_BASE__INST1_SEG2 0
+#define MMHUB_BASE__INST1_SEG3 0
+#define MMHUB_BASE__INST1_SEG4 0
+
+#define MMHUB_BASE__INST2_SEG0 0
+#define MMHUB_BASE__INST2_SEG1 0
+#define MMHUB_BASE__INST2_SEG2 0
+#define MMHUB_BASE__INST2_SEG3 0
+#define MMHUB_BASE__INST2_SEG4 0
+
+#define MMHUB_BASE__INST3_SEG0 0
+#define MMHUB_BASE__INST3_SEG1 0
+#define MMHUB_BASE__INST3_SEG2 0
+#define MMHUB_BASE__INST3_SEG3 0
+#define MMHUB_BASE__INST3_SEG4 0
+
+#define MMHUB_BASE__INST4_SEG0 0
+#define MMHUB_BASE__INST4_SEG1 0
+#define MMHUB_BASE__INST4_SEG2 0
+#define MMHUB_BASE__INST4_SEG3 0
+#define MMHUB_BASE__INST4_SEG4 0
+
+#define RSMU_BASE__INST0_SEG0 0x00012000
+#define RSMU_BASE__INST0_SEG1 0
+#define RSMU_BASE__INST0_SEG2 0
+#define RSMU_BASE__INST0_SEG3 0
+#define RSMU_BASE__INST0_SEG4 0
+
+#define RSMU_BASE__INST1_SEG0 0
+#define RSMU_BASE__INST1_SEG1 0
+#define RSMU_BASE__INST1_SEG2 0
+#define RSMU_BASE__INST1_SEG3 0
+#define RSMU_BASE__INST1_SEG4 0
+
+#define RSMU_BASE__INST2_SEG0 0
+#define RSMU_BASE__INST2_SEG1 0
+#define RSMU_BASE__INST2_SEG2 0
+#define RSMU_BASE__INST2_SEG3 0
+#define RSMU_BASE__INST2_SEG4 0
+
+#define RSMU_BASE__INST3_SEG0 0
+#define RSMU_BASE__INST3_SEG1 0
+#define RSMU_BASE__INST3_SEG2 0
+#define RSMU_BASE__INST3_SEG3 0
+#define RSMU_BASE__INST3_SEG4 0
+
+#define RSMU_BASE__INST4_SEG0 0
+#define RSMU_BASE__INST4_SEG1 0
+#define RSMU_BASE__INST4_SEG2 0
+#define RSMU_BASE__INST4_SEG3 0
+#define RSMU_BASE__INST4_SEG4 0
+
+#define HDP_BASE__INST0_SEG0 0x00000F20
+#define HDP_BASE__INST0_SEG1 0
+#define HDP_BASE__INST0_SEG2 0
+#define HDP_BASE__INST0_SEG3 0
+#define HDP_BASE__INST0_SEG4 0
+
+#define HDP_BASE__INST1_SEG0 0
+#define HDP_BASE__INST1_SEG1 0
+#define HDP_BASE__INST1_SEG2 0
+#define HDP_BASE__INST1_SEG3 0
+#define HDP_BASE__INST1_SEG4 0
+
+#define HDP_BASE__INST2_SEG0 0
+#define HDP_BASE__INST2_SEG1 0
+#define HDP_BASE__INST2_SEG2 0
+#define HDP_BASE__INST2_SEG3 0
+#define HDP_BASE__INST2_SEG4 0
+
+#define HDP_BASE__INST3_SEG0 0
+#define HDP_BASE__INST3_SEG1 0
+#define HDP_BASE__INST3_SEG2 0
+#define HDP_BASE__INST3_SEG3 0
+#define HDP_BASE__INST3_SEG4 0
+
+#define HDP_BASE__INST4_SEG0 0
+#define HDP_BASE__INST4_SEG1 0
+#define HDP_BASE__INST4_SEG2 0
+#define HDP_BASE__INST4_SEG3 0
+#define HDP_BASE__INST4_SEG4 0
+
+#define OSSSYS_BASE__INST0_SEG0 0x000010A0
+#define OSSSYS_BASE__INST0_SEG1 0
+#define OSSSYS_BASE__INST0_SEG2 0
+#define OSSSYS_BASE__INST0_SEG3 0
+#define OSSSYS_BASE__INST0_SEG4 0
+
+#define OSSSYS_BASE__INST1_SEG0 0
+#define OSSSYS_BASE__INST1_SEG1 0
+#define OSSSYS_BASE__INST1_SEG2 0
+#define OSSSYS_BASE__INST1_SEG3 0
+#define OSSSYS_BASE__INST1_SEG4 0
+
+#define OSSSYS_BASE__INST2_SEG0 0
+#define OSSSYS_BASE__INST2_SEG1 0
+#define OSSSYS_BASE__INST2_SEG2 0
+#define OSSSYS_BASE__INST2_SEG3 0
+#define OSSSYS_BASE__INST2_SEG4 0
+
+#define OSSSYS_BASE__INST3_SEG0 0
+#define OSSSYS_BASE__INST3_SEG1 0
+#define OSSSYS_BASE__INST3_SEG2 0
+#define OSSSYS_BASE__INST3_SEG3 0
+#define OSSSYS_BASE__INST3_SEG4 0
+
+#define OSSSYS_BASE__INST4_SEG0 0
+#define OSSSYS_BASE__INST4_SEG1 0
+#define OSSSYS_BASE__INST4_SEG2 0
+#define OSSSYS_BASE__INST4_SEG3 0
+#define OSSSYS_BASE__INST4_SEG4 0
+
+#define SDMA0_BASE__INST0_SEG0 0x00001260
+#define SDMA0_BASE__INST0_SEG1 0
+#define SDMA0_BASE__INST0_SEG2 0
+#define SDMA0_BASE__INST0_SEG3 0
+#define SDMA0_BASE__INST0_SEG4 0
+
+#define SDMA0_BASE__INST1_SEG0 0
+#define SDMA0_BASE__INST1_SEG1 0
+#define SDMA0_BASE__INST1_SEG2 0
+#define SDMA0_BASE__INST1_SEG3 0
+#define SDMA0_BASE__INST1_SEG4 0
+
+#define SDMA0_BASE__INST2_SEG0 0
+#define SDMA0_BASE__INST2_SEG1 0
+#define SDMA0_BASE__INST2_SEG2 0
+#define SDMA0_BASE__INST2_SEG3 0
+#define SDMA0_BASE__INST2_SEG4 0
+
+#define SDMA0_BASE__INST3_SEG0 0
+#define SDMA0_BASE__INST3_SEG1 0
+#define SDMA0_BASE__INST3_SEG2 0
+#define SDMA0_BASE__INST3_SEG3 0
+#define SDMA0_BASE__INST3_SEG4 0
+
+#define SDMA0_BASE__INST4_SEG0 0
+#define SDMA0_BASE__INST4_SEG1 0
+#define SDMA0_BASE__INST4_SEG2 0
+#define SDMA0_BASE__INST4_SEG3 0
+#define SDMA0_BASE__INST4_SEG4 0
+
+#define SDMA1_BASE__INST0_SEG0 0x00001460
+#define SDMA1_BASE__INST0_SEG1 0
+#define SDMA1_BASE__INST0_SEG2 0
+#define SDMA1_BASE__INST0_SEG3 0
+#define SDMA1_BASE__INST0_SEG4 0
+
+#define SDMA1_BASE__INST1_SEG0 0
+#define SDMA1_BASE__INST1_SEG1 0
+#define SDMA1_BASE__INST1_SEG2 0
+#define SDMA1_BASE__INST1_SEG3 0
+#define SDMA1_BASE__INST1_SEG4 0
+
+#define SDMA1_BASE__INST2_SEG0 0
+#define SDMA1_BASE__INST2_SEG1 0
+#define SDMA1_BASE__INST2_SEG2 0
+#define SDMA1_BASE__INST2_SEG3 0
+#define SDMA1_BASE__INST2_SEG4 0
+
+#define SDMA1_BASE__INST3_SEG0 0
+#define SDMA1_BASE__INST3_SEG1 0
+#define SDMA1_BASE__INST3_SEG2 0
+#define SDMA1_BASE__INST3_SEG3 0
+#define SDMA1_BASE__INST3_SEG4 0
+
+#define SDMA1_BASE__INST4_SEG0 0
+#define SDMA1_BASE__INST4_SEG1 0
+#define SDMA1_BASE__INST4_SEG2 0
+#define SDMA1_BASE__INST4_SEG3 0
+#define SDMA1_BASE__INST4_SEG4 0
+
+#define XDMA_BASE__INST0_SEG0 0x00003400
+#define XDMA_BASE__INST0_SEG1 0
+#define XDMA_BASE__INST0_SEG2 0
+#define XDMA_BASE__INST0_SEG3 0
+#define XDMA_BASE__INST0_SEG4 0
+
+#define XDMA_BASE__INST1_SEG0 0
+#define XDMA_BASE__INST1_SEG1 0
+#define XDMA_BASE__INST1_SEG2 0
+#define XDMA_BASE__INST1_SEG3 0
+#define XDMA_BASE__INST1_SEG4 0
+
+#define XDMA_BASE__INST2_SEG0 0
+#define XDMA_BASE__INST2_SEG1 0
+#define XDMA_BASE__INST2_SEG2 0
+#define XDMA_BASE__INST2_SEG3 0
+#define XDMA_BASE__INST2_SEG4 0
+
+#define XDMA_BASE__INST3_SEG0 0
+#define XDMA_BASE__INST3_SEG1 0
+#define XDMA_BASE__INST3_SEG2 0
+#define XDMA_BASE__INST3_SEG3 0
+#define XDMA_BASE__INST3_SEG4 0
+
+#define XDMA_BASE__INST4_SEG0 0
+#define XDMA_BASE__INST4_SEG1 0
+#define XDMA_BASE__INST4_SEG2 0
+#define XDMA_BASE__INST4_SEG3 0
+#define XDMA_BASE__INST4_SEG4 0
+
+#define UMC_BASE__INST0_SEG0 0x00014000
+#define UMC_BASE__INST0_SEG1 0
+#define UMC_BASE__INST0_SEG2 0
+#define UMC_BASE__INST0_SEG3 0
+#define UMC_BASE__INST0_SEG4 0
+
+#define UMC_BASE__INST1_SEG0 0
+#define UMC_BASE__INST1_SEG1 0
+#define UMC_BASE__INST1_SEG2 0
+#define UMC_BASE__INST1_SEG3 0
+#define UMC_BASE__INST1_SEG4 0
+
+#define UMC_BASE__INST2_SEG0 0
+#define UMC_BASE__INST2_SEG1 0
+#define UMC_BASE__INST2_SEG2 0
+#define UMC_BASE__INST2_SEG3 0
+#define UMC_BASE__INST2_SEG4 0
+
+#define UMC_BASE__INST3_SEG0 0
+#define UMC_BASE__INST3_SEG1 0
+#define UMC_BASE__INST3_SEG2 0
+#define UMC_BASE__INST3_SEG3 0
+#define UMC_BASE__INST3_SEG4 0
+
+#define UMC_BASE__INST4_SEG0 0
+#define UMC_BASE__INST4_SEG1 0
+#define UMC_BASE__INST4_SEG2 0
+#define UMC_BASE__INST4_SEG3 0
+#define UMC_BASE__INST4_SEG4 0
+
+#define THM_BASE__INST0_SEG0 0x00016600
+#define THM_BASE__INST0_SEG1 0
+#define THM_BASE__INST0_SEG2 0
+#define THM_BASE__INST0_SEG3 0
+#define THM_BASE__INST0_SEG4 0
+
+#define THM_BASE__INST1_SEG0 0
+#define THM_BASE__INST1_SEG1 0
+#define THM_BASE__INST1_SEG2 0
+#define THM_BASE__INST1_SEG3 0
+#define THM_BASE__INST1_SEG4 0
+
+#define THM_BASE__INST2_SEG0 0
+#define THM_BASE__INST2_SEG1 0
+#define THM_BASE__INST2_SEG2 0
+#define THM_BASE__INST2_SEG3 0
+#define THM_BASE__INST2_SEG4 0
+
+#define THM_BASE__INST3_SEG0 0
+#define THM_BASE__INST3_SEG1 0
+#define THM_BASE__INST3_SEG2 0
+#define THM_BASE__INST3_SEG3 0
+#define THM_BASE__INST3_SEG4 0
+
+#define THM_BASE__INST4_SEG0 0
+#define THM_BASE__INST4_SEG1 0
+#define THM_BASE__INST4_SEG2 0
+#define THM_BASE__INST4_SEG3 0
+#define THM_BASE__INST4_SEG4 0
+
+#define SMUIO_BASE__INST0_SEG0 0x00016800
+#define SMUIO_BASE__INST0_SEG1 0
+#define SMUIO_BASE__INST0_SEG2 0
+#define SMUIO_BASE__INST0_SEG3 0
+#define SMUIO_BASE__INST0_SEG4 0
+
+#define SMUIO_BASE__INST1_SEG0 0
+#define SMUIO_BASE__INST1_SEG1 0
+#define SMUIO_BASE__INST1_SEG2 0
+#define SMUIO_BASE__INST1_SEG3 0
+#define SMUIO_BASE__INST1_SEG4 0
+
+#define SMUIO_BASE__INST2_SEG0 0
+#define SMUIO_BASE__INST2_SEG1 0
+#define SMUIO_BASE__INST2_SEG2 0
+#define SMUIO_BASE__INST2_SEG3 0
+#define SMUIO_BASE__INST2_SEG4 0
+
+#define SMUIO_BASE__INST3_SEG0 0
+#define SMUIO_BASE__INST3_SEG1 0
+#define SMUIO_BASE__INST3_SEG2 0
+#define SMUIO_BASE__INST3_SEG3 0
+#define SMUIO_BASE__INST3_SEG4 0
+
+#define SMUIO_BASE__INST4_SEG0 0
+#define SMUIO_BASE__INST4_SEG1 0
+#define SMUIO_BASE__INST4_SEG2 0
+#define SMUIO_BASE__INST4_SEG3 0
+#define SMUIO_BASE__INST4_SEG4 0
+
+#define PWR_BASE__INST0_SEG0 0x00016A00
+#define PWR_BASE__INST0_SEG1 0
+#define PWR_BASE__INST0_SEG2 0
+#define PWR_BASE__INST0_SEG3 0
+#define PWR_BASE__INST0_SEG4 0
+
+#define PWR_BASE__INST1_SEG0 0
+#define PWR_BASE__INST1_SEG1 0
+#define PWR_BASE__INST1_SEG2 0
+#define PWR_BASE__INST1_SEG3 0
+#define PWR_BASE__INST1_SEG4 0
+
+#define PWR_BASE__INST2_SEG0 0
+#define PWR_BASE__INST2_SEG1 0
+#define PWR_BASE__INST2_SEG2 0
+#define PWR_BASE__INST2_SEG3 0
+#define PWR_BASE__INST2_SEG4 0
+
+#define PWR_BASE__INST3_SEG0 0
+#define PWR_BASE__INST3_SEG1 0
+#define PWR_BASE__INST3_SEG2 0
+#define PWR_BASE__INST3_SEG3 0
+#define PWR_BASE__INST3_SEG4 0
+
+#define PWR_BASE__INST4_SEG0 0
+#define PWR_BASE__INST4_SEG1 0
+#define PWR_BASE__INST4_SEG2 0
+#define PWR_BASE__INST4_SEG3 0
+#define PWR_BASE__INST4_SEG4 0
+
+#define CLK_BASE__INST0_SEG0 0x00016C00
+#define CLK_BASE__INST0_SEG1 0
+#define CLK_BASE__INST0_SEG2 0
+#define CLK_BASE__INST0_SEG3 0
+#define CLK_BASE__INST0_SEG4 0
+
+#define CLK_BASE__INST1_SEG0 0x00016E00
+#define CLK_BASE__INST1_SEG1 0
+#define CLK_BASE__INST1_SEG2 0
+#define CLK_BASE__INST1_SEG3 0
+#define CLK_BASE__INST1_SEG4 0
+
+#define CLK_BASE__INST2_SEG0 0x00017000
+#define CLK_BASE__INST2_SEG1 0
+#define CLK_BASE__INST2_SEG2 0
+#define CLK_BASE__INST2_SEG3 0
+#define CLK_BASE__INST2_SEG4 0
+
+#define CLK_BASE__INST3_SEG0 0x00017200
+#define CLK_BASE__INST3_SEG1 0
+#define CLK_BASE__INST3_SEG2 0
+#define CLK_BASE__INST3_SEG3 0
+#define CLK_BASE__INST3_SEG4 0
+
+#define CLK_BASE__INST4_SEG0 0x00017E00
+#define CLK_BASE__INST4_SEG1 0
+#define CLK_BASE__INST4_SEG2 0
+#define CLK_BASE__INST4_SEG3 0
+#define CLK_BASE__INST4_SEG4 0
+
+#define FUSE_BASE__INST0_SEG0 0x00017400
+#define FUSE_BASE__INST0_SEG1 0
+#define FUSE_BASE__INST0_SEG2 0
+#define FUSE_BASE__INST0_SEG3 0
+#define FUSE_BASE__INST0_SEG4 0
+
+#define FUSE_BASE__INST1_SEG0 0
+#define FUSE_BASE__INST1_SEG1 0
+#define FUSE_BASE__INST1_SEG2 0
+#define FUSE_BASE__INST1_SEG3 0
+#define FUSE_BASE__INST1_SEG4 0
+
+#define FUSE_BASE__INST2_SEG0 0
+#define FUSE_BASE__INST2_SEG1 0
+#define FUSE_BASE__INST2_SEG2 0
+#define FUSE_BASE__INST2_SEG3 0
+#define FUSE_BASE__INST2_SEG4 0
+
+#define FUSE_BASE__INST3_SEG0 0
+#define FUSE_BASE__INST3_SEG1 0
+#define FUSE_BASE__INST3_SEG2 0
+#define FUSE_BASE__INST3_SEG3 0
+#define FUSE_BASE__INST3_SEG4 0
+
+#define FUSE_BASE__INST4_SEG0 0
+#define FUSE_BASE__INST4_SEG1 0
+#define FUSE_BASE__INST4_SEG2 0
+#define FUSE_BASE__INST4_SEG3 0
+#define FUSE_BASE__INST4_SEG4 0
+#endif
+
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/5] drm/amdgpu: include new ip and ip offset headers
[not found] ` <1516623354-24912-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-22 12:15 ` Hawking Zhang
2018-01-22 12:15 ` [PATCH 3/5] drm/amd/pp: " Hawking Zhang
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Hawking Zhang @ 2018-01-22 12:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang
Change-Id: I4abff0cc4cd1ffcbc7a571d3eed9df12b3ff7b7c
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index b7bdd04..4c45db7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -24,7 +24,8 @@
#include "soc15.h"
#include "soc15_common.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
int vega10_reg_base_init(struct amdgpu_device *adev)
{
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/5] drm/amd/pp: include new ip and ip offset headers
[not found] ` <1516623354-24912-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
2018-01-22 12:15 ` [PATCH 2/5] drm/amdgpu: include new ip and ip offset headers Hawking Zhang
@ 2018-01-22 12:15 ` Hawking Zhang
2018-01-22 12:15 ` [PATCH 4/5] drm/amd/dc: include new ip and ip_offset headers Hawking Zhang
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Hawking Zhang @ 2018-01-22 12:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang
Change-Id: I9b3a56147dfc00830a0229bf59990bfe9e8a7e95
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
index 414e684..214f370 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
@@ -23,7 +23,8 @@
#ifndef PP_SOC15_H
#define PP_SOC15_H
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
inline static uint32_t soc15_get_register_offset(
uint32_t hw_id,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/5] drm/amd/dc: include new ip and ip_offset headers
[not found] ` <1516623354-24912-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
2018-01-22 12:15 ` [PATCH 2/5] drm/amdgpu: include new ip and ip offset headers Hawking Zhang
2018-01-22 12:15 ` [PATCH 3/5] drm/amd/pp: " Hawking Zhang
@ 2018-01-22 12:15 ` Hawking Zhang
2018-01-22 12:15 ` [PATCH 5/5] drm/amdgpu: retire soc15ip.h Hawking Zhang
2018-01-22 12:20 ` [PATCH 1/5] drm/amdgpu: split soc15ip header into ip and ip_offset header Christian König
4 siblings, 0 replies; 6+ messages in thread
From: Hawking Zhang @ 2018-01-22 12:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang
Change-Id: I886747dbfea9eec4f3f7f8af8ce99f04c2a8f1b7
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c | 3 ++-
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c | 3 ++-
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c | 3 ++-
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c | 3 ++-
drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c | 3 ++-
drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 3 ++-
drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c | 3 ++-
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c | 3 ++-
13 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ebcad30..ca4d425 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -61,7 +61,8 @@
#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
#include "soc15_common.h"
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
index 75d0297..e96ff86 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
@@ -33,7 +33,8 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
#include "reg_helper.h"
#define CTX \
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 5aab01d..a8725ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -56,7 +56,8 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
#include "nbio/nbio_6_1_offset.h"
#include "reg_helper.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 0aa60e5..7bee781 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -27,7 +27,8 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
#include "dc_types.h"
#include "dc_bios_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 4610d9c..66af05b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -50,7 +50,8 @@
#include "dcn10_hubp.h"
#include "dcn10_hubbub.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
index 0c2314e..ea3f888 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
@@ -36,7 +36,8 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
#define block HPD
#define reg_num 0
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
index a225b02..39ef5c7 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
@@ -35,7 +35,8 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
index 5235f69..32aa47a 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
@@ -36,7 +36,8 @@
#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
#define block HPD
#define reg_num 0
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
index 3478648..fecc8688 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
@@ -35,7 +35,8 @@
#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
index a401636..0e7b182 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
@@ -38,7 +38,8 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
index bed7cc3..e44a890 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
@@ -38,7 +38,8 @@
#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
index 66d5258..1ea7256 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
@@ -32,7 +32,8 @@
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
#include "ivsrcid/ivsrcid_vislands30.h"
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
index 7f7db66..e04ae49 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
@@ -31,7 +31,8 @@
#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
-#include "soc15ip.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
#include "irq_service_dcn10.h"
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/5] drm/amdgpu: retire soc15ip.h
[not found] ` <1516623354-24912-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-01-22 12:15 ` [PATCH 4/5] drm/amd/dc: include new ip and ip_offset headers Hawking Zhang
@ 2018-01-22 12:15 ` Hawking Zhang
2018-01-22 12:20 ` [PATCH 1/5] drm/amdgpu: split soc15ip header into ip and ip_offset header Christian König
4 siblings, 0 replies; 6+ messages in thread
From: Hawking Zhang @ 2018-01-22 12:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hawking Zhang
Change-Id: Ieaa45fa9cfcdb9dec68dd777d27daac675d94a00
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/include/soc15ip.h | 1343 ---------------------------------
1 file changed, 1343 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/include/soc15ip.h
diff --git a/drivers/gpu/drm/amd/include/soc15ip.h b/drivers/gpu/drm/amd/include/soc15ip.h
deleted file mode 100644
index 1767db6..0000000
--- a/drivers/gpu/drm/amd/include/soc15ip.h
+++ /dev/null
@@ -1,1343 +0,0 @@
-/*
- * Copyright (C) 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef _soc15ip_new_HEADER
-#define _soc15ip_new_HEADER
-
-// HW ID
-#define MP1_HWID 1
-#define MP2_HWID 2
-#define THM_HWID 3
-#define SMUIO_HWID 4
-#define FUSE_HWID 5
-#define CLKA_HWID 6
-#define PWR_HWID 10
-#define GC_HWID 11
-#define UVD_HWID 12
-#define VCN_HWID UVD_HWID
-#define AUDIO_AZ_HWID 13
-#define ACP_HWID 14
-#define DCI_HWID 15
-#define DMU_HWID 271
-#define DCO_HWID 16
-#define DIO_HWID 272
-#define XDMA_HWID 17
-#define DCEAZ_HWID 18
-#define DAZ_HWID 274
-#define SDPMUX_HWID 19
-#define NTB_HWID 20
-#define IOHC_HWID 24
-#define L2IMU_HWID 28
-#define VCE_HWID 32
-#define MMHUB_HWID 34
-#define ATHUB_HWID 35
-#define DBGU_NBIO_HWID 36
-#define DFX_HWID 37
-#define DBGU0_HWID 38
-#define DBGU1_HWID 39
-#define OSSSYS_HWID 40
-#define HDP_HWID 41
-#define SDMA0_HWID 42
-#define SDMA1_HWID 43
-#define ISP_HWID 44
-#define DBGU_IO_HWID 45
-#define DF_HWID 46
-#define CLKB_HWID 47
-#define FCH_HWID 48
-#define DFX_DAP_HWID 49
-#define L1IMU_PCIE_HWID 50
-#define L1IMU_NBIF_HWID 51
-#define L1IMU_IOAGR_HWID 52
-#define L1IMU3_HWID 53
-#define L1IMU4_HWID 54
-#define L1IMU5_HWID 55
-#define L1IMU6_HWID 56
-#define L1IMU7_HWID 57
-#define L1IMU8_HWID 58
-#define L1IMU9_HWID 59
-#define L1IMU10_HWID 60
-#define L1IMU11_HWID 61
-#define L1IMU12_HWID 62
-#define L1IMU13_HWID 63
-#define L1IMU14_HWID 64
-#define L1IMU15_HWID 65
-#define WAFLC_HWID 66
-#define FCH_USB_PD_HWID 67
-#define PCIE_HWID 70
-#define PCS_HWID 80
-#define DDCL_HWID 89
-#define SST_HWID 90
-#define IOAGR_HWID 100
-#define NBIF_HWID 108
-#define IOAPIC_HWID 124
-#define SYSTEMHUB_HWID 128
-#define NTBCCP_HWID 144
-#define UMC_HWID 150
-#define SATA_HWID 168
-#define USB_HWID 170
-#define CCXSEC_HWID 176
-#define XGBE_HWID 216
-#define MP0_HWID 254
-
-#define MAX_INSTANCE 5
-#define MAX_SEGMENT 5
-
-
-struct IP_BASE_INSTANCE
-{
- unsigned int segment[MAX_SEGMENT];
-};
-
-struct IP_BASE
-{
- struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
-};
-
-
-static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
-static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
-static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } }; // not exist
-static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } }; // not exist
-static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } }; // not exist
-static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } }; // not exist
-static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
-static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } }; // not exist
-static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } }; // not exist
-static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
- { { 0x00016E00, 0, 0, 0, 0 } },
- { { 0x00017000, 0, 0, 0, 0 } },
- { { 0x00017200, 0, 0, 0, 0 } },
- { { 0x00017E00, 0, 0, 0, 0 } } } };
-static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } },
- { { 0, 0, 0, 0, 0 } } } };
-
-
-#define NBIF_BASE__INST0_SEG0 0x00000000
-#define NBIF_BASE__INST0_SEG1 0x00000014
-#define NBIF_BASE__INST0_SEG2 0x00000D20
-#define NBIF_BASE__INST0_SEG3 0x00010400
-#define NBIF_BASE__INST0_SEG4 0
-
-#define NBIF_BASE__INST1_SEG0 0
-#define NBIF_BASE__INST1_SEG1 0
-#define NBIF_BASE__INST1_SEG2 0
-#define NBIF_BASE__INST1_SEG3 0
-#define NBIF_BASE__INST1_SEG4 0
-
-#define NBIF_BASE__INST2_SEG0 0
-#define NBIF_BASE__INST2_SEG1 0
-#define NBIF_BASE__INST2_SEG2 0
-#define NBIF_BASE__INST2_SEG3 0
-#define NBIF_BASE__INST2_SEG4 0
-
-#define NBIF_BASE__INST3_SEG0 0
-#define NBIF_BASE__INST3_SEG1 0
-#define NBIF_BASE__INST3_SEG2 0
-#define NBIF_BASE__INST3_SEG3 0
-#define NBIF_BASE__INST3_SEG4 0
-
-#define NBIF_BASE__INST4_SEG0 0
-#define NBIF_BASE__INST4_SEG1 0
-#define NBIF_BASE__INST4_SEG2 0
-#define NBIF_BASE__INST4_SEG3 0
-#define NBIF_BASE__INST4_SEG4 0
-
-#define NBIO_BASE__INST0_SEG0 0x00000000
-#define NBIO_BASE__INST0_SEG1 0x00000014
-#define NBIO_BASE__INST0_SEG2 0x00000D20
-#define NBIO_BASE__INST0_SEG3 0x00010400
-#define NBIO_BASE__INST0_SEG4 0
-
-#define NBIO_BASE__INST1_SEG0 0
-#define NBIO_BASE__INST1_SEG1 0
-#define NBIO_BASE__INST1_SEG2 0
-#define NBIO_BASE__INST1_SEG3 0
-#define NBIO_BASE__INST1_SEG4 0
-
-#define NBIO_BASE__INST2_SEG0 0
-#define NBIO_BASE__INST2_SEG1 0
-#define NBIO_BASE__INST2_SEG2 0
-#define NBIO_BASE__INST2_SEG3 0
-#define NBIO_BASE__INST2_SEG4 0
-
-#define NBIO_BASE__INST3_SEG0 0
-#define NBIO_BASE__INST3_SEG1 0
-#define NBIO_BASE__INST3_SEG2 0
-#define NBIO_BASE__INST3_SEG3 0
-#define NBIO_BASE__INST3_SEG4 0
-
-#define NBIO_BASE__INST4_SEG0 0
-#define NBIO_BASE__INST4_SEG1 0
-#define NBIO_BASE__INST4_SEG2 0
-#define NBIO_BASE__INST4_SEG3 0
-#define NBIO_BASE__INST4_SEG4 0
-
-#define DCE_BASE__INST0_SEG0 0x00000012
-#define DCE_BASE__INST0_SEG1 0x000000C0
-#define DCE_BASE__INST0_SEG2 0x000034C0
-#define DCE_BASE__INST0_SEG3 0
-#define DCE_BASE__INST0_SEG4 0
-
-#define DCE_BASE__INST1_SEG0 0
-#define DCE_BASE__INST1_SEG1 0
-#define DCE_BASE__INST1_SEG2 0
-#define DCE_BASE__INST1_SEG3 0
-#define DCE_BASE__INST1_SEG4 0
-
-#define DCE_BASE__INST2_SEG0 0
-#define DCE_BASE__INST2_SEG1 0
-#define DCE_BASE__INST2_SEG2 0
-#define DCE_BASE__INST2_SEG3 0
-#define DCE_BASE__INST2_SEG4 0
-
-#define DCE_BASE__INST3_SEG0 0
-#define DCE_BASE__INST3_SEG1 0
-#define DCE_BASE__INST3_SEG2 0
-#define DCE_BASE__INST3_SEG3 0
-#define DCE_BASE__INST3_SEG4 0
-
-#define DCE_BASE__INST4_SEG0 0
-#define DCE_BASE__INST4_SEG1 0
-#define DCE_BASE__INST4_SEG2 0
-#define DCE_BASE__INST4_SEG3 0
-#define DCE_BASE__INST4_SEG4 0
-
-#define DCN_BASE__INST0_SEG0 0x00000012
-#define DCN_BASE__INST0_SEG1 0x000000C0
-#define DCN_BASE__INST0_SEG2 0x000034C0
-#define DCN_BASE__INST0_SEG3 0
-#define DCN_BASE__INST0_SEG4 0
-
-#define DCN_BASE__INST1_SEG0 0
-#define DCN_BASE__INST1_SEG1 0
-#define DCN_BASE__INST1_SEG2 0
-#define DCN_BASE__INST1_SEG3 0
-#define DCN_BASE__INST1_SEG4 0
-
-#define DCN_BASE__INST2_SEG0 0
-#define DCN_BASE__INST2_SEG1 0
-#define DCN_BASE__INST2_SEG2 0
-#define DCN_BASE__INST2_SEG3 0
-#define DCN_BASE__INST2_SEG4 0
-
-#define DCN_BASE__INST3_SEG0 0
-#define DCN_BASE__INST3_SEG1 0
-#define DCN_BASE__INST3_SEG2 0
-#define DCN_BASE__INST3_SEG3 0
-#define DCN_BASE__INST3_SEG4 0
-
-#define DCN_BASE__INST4_SEG0 0
-#define DCN_BASE__INST4_SEG1 0
-#define DCN_BASE__INST4_SEG2 0
-#define DCN_BASE__INST4_SEG3 0
-#define DCN_BASE__INST4_SEG4 0
-
-#define MP0_BASE__INST0_SEG0 0x00016000
-#define MP0_BASE__INST0_SEG1 0
-#define MP0_BASE__INST0_SEG2 0
-#define MP0_BASE__INST0_SEG3 0
-#define MP0_BASE__INST0_SEG4 0
-
-#define MP0_BASE__INST1_SEG0 0
-#define MP0_BASE__INST1_SEG1 0
-#define MP0_BASE__INST1_SEG2 0
-#define MP0_BASE__INST1_SEG3 0
-#define MP0_BASE__INST1_SEG4 0
-
-#define MP0_BASE__INST2_SEG0 0
-#define MP0_BASE__INST2_SEG1 0
-#define MP0_BASE__INST2_SEG2 0
-#define MP0_BASE__INST2_SEG3 0
-#define MP0_BASE__INST2_SEG4 0
-
-#define MP0_BASE__INST3_SEG0 0
-#define MP0_BASE__INST3_SEG1 0
-#define MP0_BASE__INST3_SEG2 0
-#define MP0_BASE__INST3_SEG3 0
-#define MP0_BASE__INST3_SEG4 0
-
-#define MP0_BASE__INST4_SEG0 0
-#define MP0_BASE__INST4_SEG1 0
-#define MP0_BASE__INST4_SEG2 0
-#define MP0_BASE__INST4_SEG3 0
-#define MP0_BASE__INST4_SEG4 0
-
-#define MP1_BASE__INST0_SEG0 0x00016200
-#define MP1_BASE__INST0_SEG1 0
-#define MP1_BASE__INST0_SEG2 0
-#define MP1_BASE__INST0_SEG3 0
-#define MP1_BASE__INST0_SEG4 0
-
-#define MP1_BASE__INST1_SEG0 0
-#define MP1_BASE__INST1_SEG1 0
-#define MP1_BASE__INST1_SEG2 0
-#define MP1_BASE__INST1_SEG3 0
-#define MP1_BASE__INST1_SEG4 0
-
-#define MP1_BASE__INST2_SEG0 0
-#define MP1_BASE__INST2_SEG1 0
-#define MP1_BASE__INST2_SEG2 0
-#define MP1_BASE__INST2_SEG3 0
-#define MP1_BASE__INST2_SEG4 0
-
-#define MP1_BASE__INST3_SEG0 0
-#define MP1_BASE__INST3_SEG1 0
-#define MP1_BASE__INST3_SEG2 0
-#define MP1_BASE__INST3_SEG3 0
-#define MP1_BASE__INST3_SEG4 0
-
-#define MP1_BASE__INST4_SEG0 0
-#define MP1_BASE__INST4_SEG1 0
-#define MP1_BASE__INST4_SEG2 0
-#define MP1_BASE__INST4_SEG3 0
-#define MP1_BASE__INST4_SEG4 0
-
-#define MP2_BASE__INST0_SEG0 0x00016400
-#define MP2_BASE__INST0_SEG1 0
-#define MP2_BASE__INST0_SEG2 0
-#define MP2_BASE__INST0_SEG3 0
-#define MP2_BASE__INST0_SEG4 0
-
-#define MP2_BASE__INST1_SEG0 0
-#define MP2_BASE__INST1_SEG1 0
-#define MP2_BASE__INST1_SEG2 0
-#define MP2_BASE__INST1_SEG3 0
-#define MP2_BASE__INST1_SEG4 0
-
-#define MP2_BASE__INST2_SEG0 0
-#define MP2_BASE__INST2_SEG1 0
-#define MP2_BASE__INST2_SEG2 0
-#define MP2_BASE__INST2_SEG3 0
-#define MP2_BASE__INST2_SEG4 0
-
-#define MP2_BASE__INST3_SEG0 0
-#define MP2_BASE__INST3_SEG1 0
-#define MP2_BASE__INST3_SEG2 0
-#define MP2_BASE__INST3_SEG3 0
-#define MP2_BASE__INST3_SEG4 0
-
-#define MP2_BASE__INST4_SEG0 0
-#define MP2_BASE__INST4_SEG1 0
-#define MP2_BASE__INST4_SEG2 0
-#define MP2_BASE__INST4_SEG3 0
-#define MP2_BASE__INST4_SEG4 0
-
-#define DF_BASE__INST0_SEG0 0x00007000
-#define DF_BASE__INST0_SEG1 0
-#define DF_BASE__INST0_SEG2 0
-#define DF_BASE__INST0_SEG3 0
-#define DF_BASE__INST0_SEG4 0
-
-#define DF_BASE__INST1_SEG0 0
-#define DF_BASE__INST1_SEG1 0
-#define DF_BASE__INST1_SEG2 0
-#define DF_BASE__INST1_SEG3 0
-#define DF_BASE__INST1_SEG4 0
-
-#define DF_BASE__INST2_SEG0 0
-#define DF_BASE__INST2_SEG1 0
-#define DF_BASE__INST2_SEG2 0
-#define DF_BASE__INST2_SEG3 0
-#define DF_BASE__INST2_SEG4 0
-
-#define DF_BASE__INST3_SEG0 0
-#define DF_BASE__INST3_SEG1 0
-#define DF_BASE__INST3_SEG2 0
-#define DF_BASE__INST3_SEG3 0
-#define DF_BASE__INST3_SEG4 0
-
-#define DF_BASE__INST4_SEG0 0
-#define DF_BASE__INST4_SEG1 0
-#define DF_BASE__INST4_SEG2 0
-#define DF_BASE__INST4_SEG3 0
-#define DF_BASE__INST4_SEG4 0
-
-#define UVD_BASE__INST0_SEG0 0x00007800
-#define UVD_BASE__INST0_SEG1 0x00007E00
-#define UVD_BASE__INST0_SEG2 0
-#define UVD_BASE__INST0_SEG3 0
-#define UVD_BASE__INST0_SEG4 0
-
-#define UVD_BASE__INST1_SEG0 0
-#define UVD_BASE__INST1_SEG1 0
-#define UVD_BASE__INST1_SEG2 0
-#define UVD_BASE__INST1_SEG3 0
-#define UVD_BASE__INST1_SEG4 0
-
-#define UVD_BASE__INST2_SEG0 0
-#define UVD_BASE__INST2_SEG1 0
-#define UVD_BASE__INST2_SEG2 0
-#define UVD_BASE__INST2_SEG3 0
-#define UVD_BASE__INST2_SEG4 0
-
-#define UVD_BASE__INST3_SEG0 0
-#define UVD_BASE__INST3_SEG1 0
-#define UVD_BASE__INST3_SEG2 0
-#define UVD_BASE__INST3_SEG3 0
-#define UVD_BASE__INST3_SEG4 0
-
-#define UVD_BASE__INST4_SEG0 0
-#define UVD_BASE__INST4_SEG1 0
-#define UVD_BASE__INST4_SEG2 0
-#define UVD_BASE__INST4_SEG3 0
-#define UVD_BASE__INST4_SEG4 0
-
-#define VCN_BASE__INST0_SEG0 0x00007800
-#define VCN_BASE__INST0_SEG1 0x00007E00
-#define VCN_BASE__INST0_SEG2 0
-#define VCN_BASE__INST0_SEG3 0
-#define VCN_BASE__INST0_SEG4 0
-
-#define VCN_BASE__INST1_SEG0 0
-#define VCN_BASE__INST1_SEG1 0
-#define VCN_BASE__INST1_SEG2 0
-#define VCN_BASE__INST1_SEG3 0
-#define VCN_BASE__INST1_SEG4 0
-
-#define VCN_BASE__INST2_SEG0 0
-#define VCN_BASE__INST2_SEG1 0
-#define VCN_BASE__INST2_SEG2 0
-#define VCN_BASE__INST2_SEG3 0
-#define VCN_BASE__INST2_SEG4 0
-
-#define VCN_BASE__INST3_SEG0 0
-#define VCN_BASE__INST3_SEG1 0
-#define VCN_BASE__INST3_SEG2 0
-#define VCN_BASE__INST3_SEG3 0
-#define VCN_BASE__INST3_SEG4 0
-
-#define VCN_BASE__INST4_SEG0 0
-#define VCN_BASE__INST4_SEG1 0
-#define VCN_BASE__INST4_SEG2 0
-#define VCN_BASE__INST4_SEG3 0
-#define VCN_BASE__INST4_SEG4 0
-
-#define DBGU_BASE__INST0_SEG0 0x00000180
-#define DBGU_BASE__INST0_SEG1 0x000001A0
-#define DBGU_BASE__INST0_SEG2 0
-#define DBGU_BASE__INST0_SEG3 0
-#define DBGU_BASE__INST0_SEG4 0
-
-#define DBGU_BASE__INST1_SEG0 0
-#define DBGU_BASE__INST1_SEG1 0
-#define DBGU_BASE__INST1_SEG2 0
-#define DBGU_BASE__INST1_SEG3 0
-#define DBGU_BASE__INST1_SEG4 0
-
-#define DBGU_BASE__INST2_SEG0 0
-#define DBGU_BASE__INST2_SEG1 0
-#define DBGU_BASE__INST2_SEG2 0
-#define DBGU_BASE__INST2_SEG3 0
-#define DBGU_BASE__INST2_SEG4 0
-
-#define DBGU_BASE__INST3_SEG0 0
-#define DBGU_BASE__INST3_SEG1 0
-#define DBGU_BASE__INST3_SEG2 0
-#define DBGU_BASE__INST3_SEG3 0
-#define DBGU_BASE__INST3_SEG4 0
-
-#define DBGU_BASE__INST4_SEG0 0
-#define DBGU_BASE__INST4_SEG1 0
-#define DBGU_BASE__INST4_SEG2 0
-#define DBGU_BASE__INST4_SEG3 0
-#define DBGU_BASE__INST4_SEG4 0
-
-#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0
-#define DBGU_NBIO_BASE__INST0_SEG1 0
-#define DBGU_NBIO_BASE__INST0_SEG2 0
-#define DBGU_NBIO_BASE__INST0_SEG3 0
-#define DBGU_NBIO_BASE__INST0_SEG4 0
-
-#define DBGU_NBIO_BASE__INST1_SEG0 0
-#define DBGU_NBIO_BASE__INST1_SEG1 0
-#define DBGU_NBIO_BASE__INST1_SEG2 0
-#define DBGU_NBIO_BASE__INST1_SEG3 0
-#define DBGU_NBIO_BASE__INST1_SEG4 0
-
-#define DBGU_NBIO_BASE__INST2_SEG0 0
-#define DBGU_NBIO_BASE__INST2_SEG1 0
-#define DBGU_NBIO_BASE__INST2_SEG2 0
-#define DBGU_NBIO_BASE__INST2_SEG3 0
-#define DBGU_NBIO_BASE__INST2_SEG4 0
-
-#define DBGU_NBIO_BASE__INST3_SEG0 0
-#define DBGU_NBIO_BASE__INST3_SEG1 0
-#define DBGU_NBIO_BASE__INST3_SEG2 0
-#define DBGU_NBIO_BASE__INST3_SEG3 0
-#define DBGU_NBIO_BASE__INST3_SEG4 0
-
-#define DBGU_NBIO_BASE__INST4_SEG0 0
-#define DBGU_NBIO_BASE__INST4_SEG1 0
-#define DBGU_NBIO_BASE__INST4_SEG2 0
-#define DBGU_NBIO_BASE__INST4_SEG3 0
-#define DBGU_NBIO_BASE__INST4_SEG4 0
-
-#define DBGU_IO_BASE__INST0_SEG0 0x000001E0
-#define DBGU_IO_BASE__INST0_SEG1 0
-#define DBGU_IO_BASE__INST0_SEG2 0
-#define DBGU_IO_BASE__INST0_SEG3 0
-#define DBGU_IO_BASE__INST0_SEG4 0
-
-#define DBGU_IO_BASE__INST1_SEG0 0
-#define DBGU_IO_BASE__INST1_SEG1 0
-#define DBGU_IO_BASE__INST1_SEG2 0
-#define DBGU_IO_BASE__INST1_SEG3 0
-#define DBGU_IO_BASE__INST1_SEG4 0
-
-#define DBGU_IO_BASE__INST2_SEG0 0
-#define DBGU_IO_BASE__INST2_SEG1 0
-#define DBGU_IO_BASE__INST2_SEG2 0
-#define DBGU_IO_BASE__INST2_SEG3 0
-#define DBGU_IO_BASE__INST2_SEG4 0
-
-#define DBGU_IO_BASE__INST3_SEG0 0
-#define DBGU_IO_BASE__INST3_SEG1 0
-#define DBGU_IO_BASE__INST3_SEG2 0
-#define DBGU_IO_BASE__INST3_SEG3 0
-#define DBGU_IO_BASE__INST3_SEG4 0
-
-#define DBGU_IO_BASE__INST4_SEG0 0
-#define DBGU_IO_BASE__INST4_SEG1 0
-#define DBGU_IO_BASE__INST4_SEG2 0
-#define DBGU_IO_BASE__INST4_SEG3 0
-#define DBGU_IO_BASE__INST4_SEG4 0
-
-#define DFX_DAP_BASE__INST0_SEG0 0x000005A0
-#define DFX_DAP_BASE__INST0_SEG1 0
-#define DFX_DAP_BASE__INST0_SEG2 0
-#define DFX_DAP_BASE__INST0_SEG3 0
-#define DFX_DAP_BASE__INST0_SEG4 0
-
-#define DFX_DAP_BASE__INST1_SEG0 0
-#define DFX_DAP_BASE__INST1_SEG1 0
-#define DFX_DAP_BASE__INST1_SEG2 0
-#define DFX_DAP_BASE__INST1_SEG3 0
-#define DFX_DAP_BASE__INST1_SEG4 0
-
-#define DFX_DAP_BASE__INST2_SEG0 0
-#define DFX_DAP_BASE__INST2_SEG1 0
-#define DFX_DAP_BASE__INST2_SEG2 0
-#define DFX_DAP_BASE__INST2_SEG3 0
-#define DFX_DAP_BASE__INST2_SEG4 0
-
-#define DFX_DAP_BASE__INST3_SEG0 0
-#define DFX_DAP_BASE__INST3_SEG1 0
-#define DFX_DAP_BASE__INST3_SEG2 0
-#define DFX_DAP_BASE__INST3_SEG3 0
-#define DFX_DAP_BASE__INST3_SEG4 0
-
-#define DFX_DAP_BASE__INST4_SEG0 0
-#define DFX_DAP_BASE__INST4_SEG1 0
-#define DFX_DAP_BASE__INST4_SEG2 0
-#define DFX_DAP_BASE__INST4_SEG3 0
-#define DFX_DAP_BASE__INST4_SEG4 0
-
-#define DFX_BASE__INST0_SEG0 0x00000580
-#define DFX_BASE__INST0_SEG1 0
-#define DFX_BASE__INST0_SEG2 0
-#define DFX_BASE__INST0_SEG3 0
-#define DFX_BASE__INST0_SEG4 0
-
-#define DFX_BASE__INST1_SEG0 0
-#define DFX_BASE__INST1_SEG1 0
-#define DFX_BASE__INST1_SEG2 0
-#define DFX_BASE__INST1_SEG3 0
-#define DFX_BASE__INST1_SEG4 0
-
-#define DFX_BASE__INST2_SEG0 0
-#define DFX_BASE__INST2_SEG1 0
-#define DFX_BASE__INST2_SEG2 0
-#define DFX_BASE__INST2_SEG3 0
-#define DFX_BASE__INST2_SEG4 0
-
-#define DFX_BASE__INST3_SEG0 0
-#define DFX_BASE__INST3_SEG1 0
-#define DFX_BASE__INST3_SEG2 0
-#define DFX_BASE__INST3_SEG3 0
-#define DFX_BASE__INST3_SEG4 0
-
-#define DFX_BASE__INST4_SEG0 0
-#define DFX_BASE__INST4_SEG1 0
-#define DFX_BASE__INST4_SEG2 0
-#define DFX_BASE__INST4_SEG3 0
-#define DFX_BASE__INST4_SEG4 0
-
-#define ISP_BASE__INST0_SEG0 0x00018000
-#define ISP_BASE__INST0_SEG1 0
-#define ISP_BASE__INST0_SEG2 0
-#define ISP_BASE__INST0_SEG3 0
-#define ISP_BASE__INST0_SEG4 0
-
-#define ISP_BASE__INST1_SEG0 0
-#define ISP_BASE__INST1_SEG1 0
-#define ISP_BASE__INST1_SEG2 0
-#define ISP_BASE__INST1_SEG3 0
-#define ISP_BASE__INST1_SEG4 0
-
-#define ISP_BASE__INST2_SEG0 0
-#define ISP_BASE__INST2_SEG1 0
-#define ISP_BASE__INST2_SEG2 0
-#define ISP_BASE__INST2_SEG3 0
-#define ISP_BASE__INST2_SEG4 0
-
-#define ISP_BASE__INST3_SEG0 0
-#define ISP_BASE__INST3_SEG1 0
-#define ISP_BASE__INST3_SEG2 0
-#define ISP_BASE__INST3_SEG3 0
-#define ISP_BASE__INST3_SEG4 0
-
-#define ISP_BASE__INST4_SEG0 0
-#define ISP_BASE__INST4_SEG1 0
-#define ISP_BASE__INST4_SEG2 0
-#define ISP_BASE__INST4_SEG3 0
-#define ISP_BASE__INST4_SEG4 0
-
-#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0
-#define SYSTEMHUB_BASE__INST0_SEG1 0
-#define SYSTEMHUB_BASE__INST0_SEG2 0
-#define SYSTEMHUB_BASE__INST0_SEG3 0
-#define SYSTEMHUB_BASE__INST0_SEG4 0
-
-#define SYSTEMHUB_BASE__INST1_SEG0 0
-#define SYSTEMHUB_BASE__INST1_SEG1 0
-#define SYSTEMHUB_BASE__INST1_SEG2 0
-#define SYSTEMHUB_BASE__INST1_SEG3 0
-#define SYSTEMHUB_BASE__INST1_SEG4 0
-
-#define SYSTEMHUB_BASE__INST2_SEG0 0
-#define SYSTEMHUB_BASE__INST2_SEG1 0
-#define SYSTEMHUB_BASE__INST2_SEG2 0
-#define SYSTEMHUB_BASE__INST2_SEG3 0
-#define SYSTEMHUB_BASE__INST2_SEG4 0
-
-#define SYSTEMHUB_BASE__INST3_SEG0 0
-#define SYSTEMHUB_BASE__INST3_SEG1 0
-#define SYSTEMHUB_BASE__INST3_SEG2 0
-#define SYSTEMHUB_BASE__INST3_SEG3 0
-#define SYSTEMHUB_BASE__INST3_SEG4 0
-
-#define SYSTEMHUB_BASE__INST4_SEG0 0
-#define SYSTEMHUB_BASE__INST4_SEG1 0
-#define SYSTEMHUB_BASE__INST4_SEG2 0
-#define SYSTEMHUB_BASE__INST4_SEG3 0
-#define SYSTEMHUB_BASE__INST4_SEG4 0
-
-#define L2IMU_BASE__INST0_SEG0 0x00007DC0
-#define L2IMU_BASE__INST0_SEG1 0
-#define L2IMU_BASE__INST0_SEG2 0
-#define L2IMU_BASE__INST0_SEG3 0
-#define L2IMU_BASE__INST0_SEG4 0
-
-#define L2IMU_BASE__INST1_SEG0 0
-#define L2IMU_BASE__INST1_SEG1 0
-#define L2IMU_BASE__INST1_SEG2 0
-#define L2IMU_BASE__INST1_SEG3 0
-#define L2IMU_BASE__INST1_SEG4 0
-
-#define L2IMU_BASE__INST2_SEG0 0
-#define L2IMU_BASE__INST2_SEG1 0
-#define L2IMU_BASE__INST2_SEG2 0
-#define L2IMU_BASE__INST2_SEG3 0
-#define L2IMU_BASE__INST2_SEG4 0
-
-#define L2IMU_BASE__INST3_SEG0 0
-#define L2IMU_BASE__INST3_SEG1 0
-#define L2IMU_BASE__INST3_SEG2 0
-#define L2IMU_BASE__INST3_SEG3 0
-#define L2IMU_BASE__INST3_SEG4 0
-
-#define L2IMU_BASE__INST4_SEG0 0
-#define L2IMU_BASE__INST4_SEG1 0
-#define L2IMU_BASE__INST4_SEG2 0
-#define L2IMU_BASE__INST4_SEG3 0
-#define L2IMU_BASE__INST4_SEG4 0
-
-#define IOHC_BASE__INST0_SEG0 0x00010000
-#define IOHC_BASE__INST0_SEG1 0
-#define IOHC_BASE__INST0_SEG2 0
-#define IOHC_BASE__INST0_SEG3 0
-#define IOHC_BASE__INST0_SEG4 0
-
-#define IOHC_BASE__INST1_SEG0 0
-#define IOHC_BASE__INST1_SEG1 0
-#define IOHC_BASE__INST1_SEG2 0
-#define IOHC_BASE__INST1_SEG3 0
-#define IOHC_BASE__INST1_SEG4 0
-
-#define IOHC_BASE__INST2_SEG0 0
-#define IOHC_BASE__INST2_SEG1 0
-#define IOHC_BASE__INST2_SEG2 0
-#define IOHC_BASE__INST2_SEG3 0
-#define IOHC_BASE__INST2_SEG4 0
-
-#define IOHC_BASE__INST3_SEG0 0
-#define IOHC_BASE__INST3_SEG1 0
-#define IOHC_BASE__INST3_SEG2 0
-#define IOHC_BASE__INST3_SEG3 0
-#define IOHC_BASE__INST3_SEG4 0
-
-#define IOHC_BASE__INST4_SEG0 0
-#define IOHC_BASE__INST4_SEG1 0
-#define IOHC_BASE__INST4_SEG2 0
-#define IOHC_BASE__INST4_SEG3 0
-#define IOHC_BASE__INST4_SEG4 0
-
-#define ATHUB_BASE__INST0_SEG0 0x00000C20
-#define ATHUB_BASE__INST0_SEG1 0
-#define ATHUB_BASE__INST0_SEG2 0
-#define ATHUB_BASE__INST0_SEG3 0
-#define ATHUB_BASE__INST0_SEG4 0
-
-#define ATHUB_BASE__INST1_SEG0 0
-#define ATHUB_BASE__INST1_SEG1 0
-#define ATHUB_BASE__INST1_SEG2 0
-#define ATHUB_BASE__INST1_SEG3 0
-#define ATHUB_BASE__INST1_SEG4 0
-
-#define ATHUB_BASE__INST2_SEG0 0
-#define ATHUB_BASE__INST2_SEG1 0
-#define ATHUB_BASE__INST2_SEG2 0
-#define ATHUB_BASE__INST2_SEG3 0
-#define ATHUB_BASE__INST2_SEG4 0
-
-#define ATHUB_BASE__INST3_SEG0 0
-#define ATHUB_BASE__INST3_SEG1 0
-#define ATHUB_BASE__INST3_SEG2 0
-#define ATHUB_BASE__INST3_SEG3 0
-#define ATHUB_BASE__INST3_SEG4 0
-
-#define ATHUB_BASE__INST4_SEG0 0
-#define ATHUB_BASE__INST4_SEG1 0
-#define ATHUB_BASE__INST4_SEG2 0
-#define ATHUB_BASE__INST4_SEG3 0
-#define ATHUB_BASE__INST4_SEG4 0
-
-#define VCE_BASE__INST0_SEG0 0x00007E00
-#define VCE_BASE__INST0_SEG1 0x00048800
-#define VCE_BASE__INST0_SEG2 0
-#define VCE_BASE__INST0_SEG3 0
-#define VCE_BASE__INST0_SEG4 0
-
-#define VCE_BASE__INST1_SEG0 0
-#define VCE_BASE__INST1_SEG1 0
-#define VCE_BASE__INST1_SEG2 0
-#define VCE_BASE__INST1_SEG3 0
-#define VCE_BASE__INST1_SEG4 0
-
-#define VCE_BASE__INST2_SEG0 0
-#define VCE_BASE__INST2_SEG1 0
-#define VCE_BASE__INST2_SEG2 0
-#define VCE_BASE__INST2_SEG3 0
-#define VCE_BASE__INST2_SEG4 0
-
-#define VCE_BASE__INST3_SEG0 0
-#define VCE_BASE__INST3_SEG1 0
-#define VCE_BASE__INST3_SEG2 0
-#define VCE_BASE__INST3_SEG3 0
-#define VCE_BASE__INST3_SEG4 0
-
-#define VCE_BASE__INST4_SEG0 0
-#define VCE_BASE__INST4_SEG1 0
-#define VCE_BASE__INST4_SEG2 0
-#define VCE_BASE__INST4_SEG3 0
-#define VCE_BASE__INST4_SEG4 0
-
-#define GC_BASE__INST0_SEG0 0x00002000
-#define GC_BASE__INST0_SEG1 0x0000A000
-#define GC_BASE__INST0_SEG2 0
-#define GC_BASE__INST0_SEG3 0
-#define GC_BASE__INST0_SEG4 0
-
-#define GC_BASE__INST1_SEG0 0
-#define GC_BASE__INST1_SEG1 0
-#define GC_BASE__INST1_SEG2 0
-#define GC_BASE__INST1_SEG3 0
-#define GC_BASE__INST1_SEG4 0
-
-#define GC_BASE__INST2_SEG0 0
-#define GC_BASE__INST2_SEG1 0
-#define GC_BASE__INST2_SEG2 0
-#define GC_BASE__INST2_SEG3 0
-#define GC_BASE__INST2_SEG4 0
-
-#define GC_BASE__INST3_SEG0 0
-#define GC_BASE__INST3_SEG1 0
-#define GC_BASE__INST3_SEG2 0
-#define GC_BASE__INST3_SEG3 0
-#define GC_BASE__INST3_SEG4 0
-
-#define GC_BASE__INST4_SEG0 0
-#define GC_BASE__INST4_SEG1 0
-#define GC_BASE__INST4_SEG2 0
-#define GC_BASE__INST4_SEG3 0
-#define GC_BASE__INST4_SEG4 0
-
-#define MMHUB_BASE__INST0_SEG0 0x0001A000
-#define MMHUB_BASE__INST0_SEG1 0
-#define MMHUB_BASE__INST0_SEG2 0
-#define MMHUB_BASE__INST0_SEG3 0
-#define MMHUB_BASE__INST0_SEG4 0
-
-#define MMHUB_BASE__INST1_SEG0 0
-#define MMHUB_BASE__INST1_SEG1 0
-#define MMHUB_BASE__INST1_SEG2 0
-#define MMHUB_BASE__INST1_SEG3 0
-#define MMHUB_BASE__INST1_SEG4 0
-
-#define MMHUB_BASE__INST2_SEG0 0
-#define MMHUB_BASE__INST2_SEG1 0
-#define MMHUB_BASE__INST2_SEG2 0
-#define MMHUB_BASE__INST2_SEG3 0
-#define MMHUB_BASE__INST2_SEG4 0
-
-#define MMHUB_BASE__INST3_SEG0 0
-#define MMHUB_BASE__INST3_SEG1 0
-#define MMHUB_BASE__INST3_SEG2 0
-#define MMHUB_BASE__INST3_SEG3 0
-#define MMHUB_BASE__INST3_SEG4 0
-
-#define MMHUB_BASE__INST4_SEG0 0
-#define MMHUB_BASE__INST4_SEG1 0
-#define MMHUB_BASE__INST4_SEG2 0
-#define MMHUB_BASE__INST4_SEG3 0
-#define MMHUB_BASE__INST4_SEG4 0
-
-#define RSMU_BASE__INST0_SEG0 0x00012000
-#define RSMU_BASE__INST0_SEG1 0
-#define RSMU_BASE__INST0_SEG2 0
-#define RSMU_BASE__INST0_SEG3 0
-#define RSMU_BASE__INST0_SEG4 0
-
-#define RSMU_BASE__INST1_SEG0 0
-#define RSMU_BASE__INST1_SEG1 0
-#define RSMU_BASE__INST1_SEG2 0
-#define RSMU_BASE__INST1_SEG3 0
-#define RSMU_BASE__INST1_SEG4 0
-
-#define RSMU_BASE__INST2_SEG0 0
-#define RSMU_BASE__INST2_SEG1 0
-#define RSMU_BASE__INST2_SEG2 0
-#define RSMU_BASE__INST2_SEG3 0
-#define RSMU_BASE__INST2_SEG4 0
-
-#define RSMU_BASE__INST3_SEG0 0
-#define RSMU_BASE__INST3_SEG1 0
-#define RSMU_BASE__INST3_SEG2 0
-#define RSMU_BASE__INST3_SEG3 0
-#define RSMU_BASE__INST3_SEG4 0
-
-#define RSMU_BASE__INST4_SEG0 0
-#define RSMU_BASE__INST4_SEG1 0
-#define RSMU_BASE__INST4_SEG2 0
-#define RSMU_BASE__INST4_SEG3 0
-#define RSMU_BASE__INST4_SEG4 0
-
-#define HDP_BASE__INST0_SEG0 0x00000F20
-#define HDP_BASE__INST0_SEG1 0
-#define HDP_BASE__INST0_SEG2 0
-#define HDP_BASE__INST0_SEG3 0
-#define HDP_BASE__INST0_SEG4 0
-
-#define HDP_BASE__INST1_SEG0 0
-#define HDP_BASE__INST1_SEG1 0
-#define HDP_BASE__INST1_SEG2 0
-#define HDP_BASE__INST1_SEG3 0
-#define HDP_BASE__INST1_SEG4 0
-
-#define HDP_BASE__INST2_SEG0 0
-#define HDP_BASE__INST2_SEG1 0
-#define HDP_BASE__INST2_SEG2 0
-#define HDP_BASE__INST2_SEG3 0
-#define HDP_BASE__INST2_SEG4 0
-
-#define HDP_BASE__INST3_SEG0 0
-#define HDP_BASE__INST3_SEG1 0
-#define HDP_BASE__INST3_SEG2 0
-#define HDP_BASE__INST3_SEG3 0
-#define HDP_BASE__INST3_SEG4 0
-
-#define HDP_BASE__INST4_SEG0 0
-#define HDP_BASE__INST4_SEG1 0
-#define HDP_BASE__INST4_SEG2 0
-#define HDP_BASE__INST4_SEG3 0
-#define HDP_BASE__INST4_SEG4 0
-
-#define OSSSYS_BASE__INST0_SEG0 0x000010A0
-#define OSSSYS_BASE__INST0_SEG1 0
-#define OSSSYS_BASE__INST0_SEG2 0
-#define OSSSYS_BASE__INST0_SEG3 0
-#define OSSSYS_BASE__INST0_SEG4 0
-
-#define OSSSYS_BASE__INST1_SEG0 0
-#define OSSSYS_BASE__INST1_SEG1 0
-#define OSSSYS_BASE__INST1_SEG2 0
-#define OSSSYS_BASE__INST1_SEG3 0
-#define OSSSYS_BASE__INST1_SEG4 0
-
-#define OSSSYS_BASE__INST2_SEG0 0
-#define OSSSYS_BASE__INST2_SEG1 0
-#define OSSSYS_BASE__INST2_SEG2 0
-#define OSSSYS_BASE__INST2_SEG3 0
-#define OSSSYS_BASE__INST2_SEG4 0
-
-#define OSSSYS_BASE__INST3_SEG0 0
-#define OSSSYS_BASE__INST3_SEG1 0
-#define OSSSYS_BASE__INST3_SEG2 0
-#define OSSSYS_BASE__INST3_SEG3 0
-#define OSSSYS_BASE__INST3_SEG4 0
-
-#define OSSSYS_BASE__INST4_SEG0 0
-#define OSSSYS_BASE__INST4_SEG1 0
-#define OSSSYS_BASE__INST4_SEG2 0
-#define OSSSYS_BASE__INST4_SEG3 0
-#define OSSSYS_BASE__INST4_SEG4 0
-
-#define SDMA0_BASE__INST0_SEG0 0x00001260
-#define SDMA0_BASE__INST0_SEG1 0
-#define SDMA0_BASE__INST0_SEG2 0
-#define SDMA0_BASE__INST0_SEG3 0
-#define SDMA0_BASE__INST0_SEG4 0
-
-#define SDMA0_BASE__INST1_SEG0 0
-#define SDMA0_BASE__INST1_SEG1 0
-#define SDMA0_BASE__INST1_SEG2 0
-#define SDMA0_BASE__INST1_SEG3 0
-#define SDMA0_BASE__INST1_SEG4 0
-
-#define SDMA0_BASE__INST2_SEG0 0
-#define SDMA0_BASE__INST2_SEG1 0
-#define SDMA0_BASE__INST2_SEG2 0
-#define SDMA0_BASE__INST2_SEG3 0
-#define SDMA0_BASE__INST2_SEG4 0
-
-#define SDMA0_BASE__INST3_SEG0 0
-#define SDMA0_BASE__INST3_SEG1 0
-#define SDMA0_BASE__INST3_SEG2 0
-#define SDMA0_BASE__INST3_SEG3 0
-#define SDMA0_BASE__INST3_SEG4 0
-
-#define SDMA0_BASE__INST4_SEG0 0
-#define SDMA0_BASE__INST4_SEG1 0
-#define SDMA0_BASE__INST4_SEG2 0
-#define SDMA0_BASE__INST4_SEG3 0
-#define SDMA0_BASE__INST4_SEG4 0
-
-#define SDMA1_BASE__INST0_SEG0 0x00001460
-#define SDMA1_BASE__INST0_SEG1 0
-#define SDMA1_BASE__INST0_SEG2 0
-#define SDMA1_BASE__INST0_SEG3 0
-#define SDMA1_BASE__INST0_SEG4 0
-
-#define SDMA1_BASE__INST1_SEG0 0
-#define SDMA1_BASE__INST1_SEG1 0
-#define SDMA1_BASE__INST1_SEG2 0
-#define SDMA1_BASE__INST1_SEG3 0
-#define SDMA1_BASE__INST1_SEG4 0
-
-#define SDMA1_BASE__INST2_SEG0 0
-#define SDMA1_BASE__INST2_SEG1 0
-#define SDMA1_BASE__INST2_SEG2 0
-#define SDMA1_BASE__INST2_SEG3 0
-#define SDMA1_BASE__INST2_SEG4 0
-
-#define SDMA1_BASE__INST3_SEG0 0
-#define SDMA1_BASE__INST3_SEG1 0
-#define SDMA1_BASE__INST3_SEG2 0
-#define SDMA1_BASE__INST3_SEG3 0
-#define SDMA1_BASE__INST3_SEG4 0
-
-#define SDMA1_BASE__INST4_SEG0 0
-#define SDMA1_BASE__INST4_SEG1 0
-#define SDMA1_BASE__INST4_SEG2 0
-#define SDMA1_BASE__INST4_SEG3 0
-#define SDMA1_BASE__INST4_SEG4 0
-
-#define XDMA_BASE__INST0_SEG0 0x00003400
-#define XDMA_BASE__INST0_SEG1 0
-#define XDMA_BASE__INST0_SEG2 0
-#define XDMA_BASE__INST0_SEG3 0
-#define XDMA_BASE__INST0_SEG4 0
-
-#define XDMA_BASE__INST1_SEG0 0
-#define XDMA_BASE__INST1_SEG1 0
-#define XDMA_BASE__INST1_SEG2 0
-#define XDMA_BASE__INST1_SEG3 0
-#define XDMA_BASE__INST1_SEG4 0
-
-#define XDMA_BASE__INST2_SEG0 0
-#define XDMA_BASE__INST2_SEG1 0
-#define XDMA_BASE__INST2_SEG2 0
-#define XDMA_BASE__INST2_SEG3 0
-#define XDMA_BASE__INST2_SEG4 0
-
-#define XDMA_BASE__INST3_SEG0 0
-#define XDMA_BASE__INST3_SEG1 0
-#define XDMA_BASE__INST3_SEG2 0
-#define XDMA_BASE__INST3_SEG3 0
-#define XDMA_BASE__INST3_SEG4 0
-
-#define XDMA_BASE__INST4_SEG0 0
-#define XDMA_BASE__INST4_SEG1 0
-#define XDMA_BASE__INST4_SEG2 0
-#define XDMA_BASE__INST4_SEG3 0
-#define XDMA_BASE__INST4_SEG4 0
-
-#define UMC_BASE__INST0_SEG0 0x00014000
-#define UMC_BASE__INST0_SEG1 0
-#define UMC_BASE__INST0_SEG2 0
-#define UMC_BASE__INST0_SEG3 0
-#define UMC_BASE__INST0_SEG4 0
-
-#define UMC_BASE__INST1_SEG0 0
-#define UMC_BASE__INST1_SEG1 0
-#define UMC_BASE__INST1_SEG2 0
-#define UMC_BASE__INST1_SEG3 0
-#define UMC_BASE__INST1_SEG4 0
-
-#define UMC_BASE__INST2_SEG0 0
-#define UMC_BASE__INST2_SEG1 0
-#define UMC_BASE__INST2_SEG2 0
-#define UMC_BASE__INST2_SEG3 0
-#define UMC_BASE__INST2_SEG4 0
-
-#define UMC_BASE__INST3_SEG0 0
-#define UMC_BASE__INST3_SEG1 0
-#define UMC_BASE__INST3_SEG2 0
-#define UMC_BASE__INST3_SEG3 0
-#define UMC_BASE__INST3_SEG4 0
-
-#define UMC_BASE__INST4_SEG0 0
-#define UMC_BASE__INST4_SEG1 0
-#define UMC_BASE__INST4_SEG2 0
-#define UMC_BASE__INST4_SEG3 0
-#define UMC_BASE__INST4_SEG4 0
-
-#define THM_BASE__INST0_SEG0 0x00016600
-#define THM_BASE__INST0_SEG1 0
-#define THM_BASE__INST0_SEG2 0
-#define THM_BASE__INST0_SEG3 0
-#define THM_BASE__INST0_SEG4 0
-
-#define THM_BASE__INST1_SEG0 0
-#define THM_BASE__INST1_SEG1 0
-#define THM_BASE__INST1_SEG2 0
-#define THM_BASE__INST1_SEG3 0
-#define THM_BASE__INST1_SEG4 0
-
-#define THM_BASE__INST2_SEG0 0
-#define THM_BASE__INST2_SEG1 0
-#define THM_BASE__INST2_SEG2 0
-#define THM_BASE__INST2_SEG3 0
-#define THM_BASE__INST2_SEG4 0
-
-#define THM_BASE__INST3_SEG0 0
-#define THM_BASE__INST3_SEG1 0
-#define THM_BASE__INST3_SEG2 0
-#define THM_BASE__INST3_SEG3 0
-#define THM_BASE__INST3_SEG4 0
-
-#define THM_BASE__INST4_SEG0 0
-#define THM_BASE__INST4_SEG1 0
-#define THM_BASE__INST4_SEG2 0
-#define THM_BASE__INST4_SEG3 0
-#define THM_BASE__INST4_SEG4 0
-
-#define SMUIO_BASE__INST0_SEG0 0x00016800
-#define SMUIO_BASE__INST0_SEG1 0
-#define SMUIO_BASE__INST0_SEG2 0
-#define SMUIO_BASE__INST0_SEG3 0
-#define SMUIO_BASE__INST0_SEG4 0
-
-#define SMUIO_BASE__INST1_SEG0 0
-#define SMUIO_BASE__INST1_SEG1 0
-#define SMUIO_BASE__INST1_SEG2 0
-#define SMUIO_BASE__INST1_SEG3 0
-#define SMUIO_BASE__INST1_SEG4 0
-
-#define SMUIO_BASE__INST2_SEG0 0
-#define SMUIO_BASE__INST2_SEG1 0
-#define SMUIO_BASE__INST2_SEG2 0
-#define SMUIO_BASE__INST2_SEG3 0
-#define SMUIO_BASE__INST2_SEG4 0
-
-#define SMUIO_BASE__INST3_SEG0 0
-#define SMUIO_BASE__INST3_SEG1 0
-#define SMUIO_BASE__INST3_SEG2 0
-#define SMUIO_BASE__INST3_SEG3 0
-#define SMUIO_BASE__INST3_SEG4 0
-
-#define SMUIO_BASE__INST4_SEG0 0
-#define SMUIO_BASE__INST4_SEG1 0
-#define SMUIO_BASE__INST4_SEG2 0
-#define SMUIO_BASE__INST4_SEG3 0
-#define SMUIO_BASE__INST4_SEG4 0
-
-#define PWR_BASE__INST0_SEG0 0x00016A00
-#define PWR_BASE__INST0_SEG1 0
-#define PWR_BASE__INST0_SEG2 0
-#define PWR_BASE__INST0_SEG3 0
-#define PWR_BASE__INST0_SEG4 0
-
-#define PWR_BASE__INST1_SEG0 0
-#define PWR_BASE__INST1_SEG1 0
-#define PWR_BASE__INST1_SEG2 0
-#define PWR_BASE__INST1_SEG3 0
-#define PWR_BASE__INST1_SEG4 0
-
-#define PWR_BASE__INST2_SEG0 0
-#define PWR_BASE__INST2_SEG1 0
-#define PWR_BASE__INST2_SEG2 0
-#define PWR_BASE__INST2_SEG3 0
-#define PWR_BASE__INST2_SEG4 0
-
-#define PWR_BASE__INST3_SEG0 0
-#define PWR_BASE__INST3_SEG1 0
-#define PWR_BASE__INST3_SEG2 0
-#define PWR_BASE__INST3_SEG3 0
-#define PWR_BASE__INST3_SEG4 0
-
-#define PWR_BASE__INST4_SEG0 0
-#define PWR_BASE__INST4_SEG1 0
-#define PWR_BASE__INST4_SEG2 0
-#define PWR_BASE__INST4_SEG3 0
-#define PWR_BASE__INST4_SEG4 0
-
-#define CLK_BASE__INST0_SEG0 0x00016C00
-#define CLK_BASE__INST0_SEG1 0
-#define CLK_BASE__INST0_SEG2 0
-#define CLK_BASE__INST0_SEG3 0
-#define CLK_BASE__INST0_SEG4 0
-
-#define CLK_BASE__INST1_SEG0 0x00016E00
-#define CLK_BASE__INST1_SEG1 0
-#define CLK_BASE__INST1_SEG2 0
-#define CLK_BASE__INST1_SEG3 0
-#define CLK_BASE__INST1_SEG4 0
-
-#define CLK_BASE__INST2_SEG0 0x00017000
-#define CLK_BASE__INST2_SEG1 0
-#define CLK_BASE__INST2_SEG2 0
-#define CLK_BASE__INST2_SEG3 0
-#define CLK_BASE__INST2_SEG4 0
-
-#define CLK_BASE__INST3_SEG0 0x00017200
-#define CLK_BASE__INST3_SEG1 0
-#define CLK_BASE__INST3_SEG2 0
-#define CLK_BASE__INST3_SEG3 0
-#define CLK_BASE__INST3_SEG4 0
-
-#define CLK_BASE__INST4_SEG0 0x00017E00
-#define CLK_BASE__INST4_SEG1 0
-#define CLK_BASE__INST4_SEG2 0
-#define CLK_BASE__INST4_SEG3 0
-#define CLK_BASE__INST4_SEG4 0
-
-#define FUSE_BASE__INST0_SEG0 0x00017400
-#define FUSE_BASE__INST0_SEG1 0
-#define FUSE_BASE__INST0_SEG2 0
-#define FUSE_BASE__INST0_SEG3 0
-#define FUSE_BASE__INST0_SEG4 0
-
-#define FUSE_BASE__INST1_SEG0 0
-#define FUSE_BASE__INST1_SEG1 0
-#define FUSE_BASE__INST1_SEG2 0
-#define FUSE_BASE__INST1_SEG3 0
-#define FUSE_BASE__INST1_SEG4 0
-
-#define FUSE_BASE__INST2_SEG0 0
-#define FUSE_BASE__INST2_SEG1 0
-#define FUSE_BASE__INST2_SEG2 0
-#define FUSE_BASE__INST2_SEG3 0
-#define FUSE_BASE__INST2_SEG4 0
-
-#define FUSE_BASE__INST3_SEG0 0
-#define FUSE_BASE__INST3_SEG1 0
-#define FUSE_BASE__INST3_SEG2 0
-#define FUSE_BASE__INST3_SEG3 0
-#define FUSE_BASE__INST3_SEG4 0
-
-#define FUSE_BASE__INST4_SEG0 0
-#define FUSE_BASE__INST4_SEG1 0
-#define FUSE_BASE__INST4_SEG2 0
-#define FUSE_BASE__INST4_SEG3 0
-#define FUSE_BASE__INST4_SEG4 0
-
-
-#endif
-
--
2.7.4
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* Re: [PATCH 1/5] drm/amdgpu: split soc15ip header into ip and ip_offset header
[not found] ` <1516623354-24912-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2018-01-22 12:15 ` [PATCH 5/5] drm/amdgpu: retire soc15ip.h Hawking Zhang
@ 2018-01-22 12:20 ` Christian König
4 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2018-01-22 12:20 UTC (permalink / raw)
To: Hawking Zhang, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 22.01.2018 um 13:15 schrieb Hawking Zhang:
> ip base could be different per ASIC since from soc15. split soc15
> header into common ip/hw_id header and asic specific ip offset header
>
> Change-Id: I54e5856e1b99d4e313e61328c0fcd85cdd3b3267
> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/include/soc15_hw_ip.h | 98 ++
> drivers/gpu/drm/amd/include/vega10_ip_offset.h | 1265 ++++++++++++++++++++++++
> 2 files changed, 1363 insertions(+)
> create mode 100644 drivers/gpu/drm/amd/include/soc15_hw_ip.h
> create mode 100644 drivers/gpu/drm/amd/include/vega10_ip_offset.h
>
> diff --git a/drivers/gpu/drm/amd/include/soc15_hw_ip.h b/drivers/gpu/drm/amd/include/soc15_hw_ip.h
> new file mode 100644
> index 0000000..f17e30c
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/soc15_hw_ip.h
> @@ -0,0 +1,98 @@
> +/*
> + * Copyright (C) 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> + * in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
> + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + */
> +#ifndef _soc15_hw_ip_HEADER
> +#define _soc15_hw_ip_HEADER
> +
> +// HW ID
> +#define MP1_HWID 1
> +#define MP2_HWID 2
> +#define THM_HWID 3
> +#define SMUIO_HWID 4
> +#define FUSE_HWID 5
> +#define CLKA_HWID 6
> +#define PWR_HWID 10
> +#define GC_HWID 11
> +#define UVD_HWID 12
> +#define VCN_HWID UVD_HWID
> +#define AUDIO_AZ_HWID 13
> +#define ACP_HWID 14
> +#define DCI_HWID 15
> +#define DMU_HWID 271
> +#define DCO_HWID 16
> +#define DIO_HWID 272
> +#define XDMA_HWID 17
> +#define DCEAZ_HWID 18
> +#define DAZ_HWID 274
> +#define SDPMUX_HWID 19
> +#define NTB_HWID 20
> +#define IOHC_HWID 24
> +#define L2IMU_HWID 28
> +#define VCE_HWID 32
> +#define MMHUB_HWID 34
> +#define ATHUB_HWID 35
> +#define DBGU_NBIO_HWID 36
> +#define DFX_HWID 37
> +#define DBGU0_HWID 38
> +#define DBGU1_HWID 39
> +#define OSSSYS_HWID 40
> +#define HDP_HWID 41
> +#define SDMA0_HWID 42
> +#define SDMA1_HWID 43
> +#define ISP_HWID 44
> +#define DBGU_IO_HWID 45
> +#define DF_HWID 46
> +#define CLKB_HWID 47
> +#define FCH_HWID 48
> +#define DFX_DAP_HWID 49
> +#define L1IMU_PCIE_HWID 50
> +#define L1IMU_NBIF_HWID 51
> +#define L1IMU_IOAGR_HWID 52
> +#define L1IMU3_HWID 53
> +#define L1IMU4_HWID 54
> +#define L1IMU5_HWID 55
> +#define L1IMU6_HWID 56
> +#define L1IMU7_HWID 57
> +#define L1IMU8_HWID 58
> +#define L1IMU9_HWID 59
> +#define L1IMU10_HWID 60
> +#define L1IMU11_HWID 61
> +#define L1IMU12_HWID 62
> +#define L1IMU13_HWID 63
> +#define L1IMU14_HWID 64
> +#define L1IMU15_HWID 65
> +#define WAFLC_HWID 66
> +#define FCH_USB_PD_HWID 67
> +#define PCIE_HWID 70
> +#define PCS_HWID 80
> +#define DDCL_HWID 89
> +#define SST_HWID 90
> +#define IOAGR_HWID 100
> +#define NBIF_HWID 108
> +#define IOAPIC_HWID 124
> +#define SYSTEMHUB_HWID 128
> +#define NTBCCP_HWID 144
> +#define UMC_HWID 150
> +#define SATA_HWID 168
> +#define USB_HWID 170
> +#define CCXSEC_HWID 176
> +#define XGBE_HWID 216
> +#define MP0_HWID 254
> +#endif
> diff --git a/drivers/gpu/drm/amd/include/vega10_ip_offset.h b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
> new file mode 100644
> index 0000000..4c78dba
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/vega10_ip_offset.h
> @@ -0,0 +1,1265 @@
> +/*
> + * Copyright (C) 2018 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> + * in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
> + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + */
> +#ifndef _vega10_ip_offset_HEADER
> +#define _vega10_ip_offset_HEADER
> +
> +#define MAX_INSTANCE 5
> +#define MAX_SEGMENT 5
> +
> +struct IP_BASE_INSTANCE
> +{
> + unsigned int segment[MAX_SEGMENT];
> +};
> +
> +struct IP_BASE
> +{
> + struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
> +};
> +
> +
> +static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
> +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
> +static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
> +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
> + { { 0x00016E00, 0, 0, 0, 0 } },
> + { { 0x00017000, 0, 0, 0, 0 } },
> + { { 0x00017200, 0, 0, 0, 0 } },
> + { { 0x00017E00, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +
> +
> +#define NBIF_BASE__INST0_SEG0 0x00000000
> +#define NBIF_BASE__INST0_SEG1 0x00000014
> +#define NBIF_BASE__INST0_SEG2 0x00000D20
> +#define NBIF_BASE__INST0_SEG3 0x00010400
> +#define NBIF_BASE__INST0_SEG4 0
> +
> +#define NBIF_BASE__INST1_SEG0 0
> +#define NBIF_BASE__INST1_SEG1 0
> +#define NBIF_BASE__INST1_SEG2 0
> +#define NBIF_BASE__INST1_SEG3 0
> +#define NBIF_BASE__INST1_SEG4 0
> +
> +#define NBIF_BASE__INST2_SEG0 0
> +#define NBIF_BASE__INST2_SEG1 0
> +#define NBIF_BASE__INST2_SEG2 0
> +#define NBIF_BASE__INST2_SEG3 0
> +#define NBIF_BASE__INST2_SEG4 0
> +
> +#define NBIF_BASE__INST3_SEG0 0
> +#define NBIF_BASE__INST3_SEG1 0
> +#define NBIF_BASE__INST3_SEG2 0
> +#define NBIF_BASE__INST3_SEG3 0
> +#define NBIF_BASE__INST3_SEG4 0
> +
> +#define NBIF_BASE__INST4_SEG0 0
> +#define NBIF_BASE__INST4_SEG1 0
> +#define NBIF_BASE__INST4_SEG2 0
> +#define NBIF_BASE__INST4_SEG3 0
> +#define NBIF_BASE__INST4_SEG4 0
> +
> +#define NBIO_BASE__INST0_SEG0 0x00000000
> +#define NBIO_BASE__INST0_SEG1 0x00000014
> +#define NBIO_BASE__INST0_SEG2 0x00000D20
> +#define NBIO_BASE__INST0_SEG3 0x00010400
> +#define NBIO_BASE__INST0_SEG4 0
> +
> +#define NBIO_BASE__INST1_SEG0 0
> +#define NBIO_BASE__INST1_SEG1 0
> +#define NBIO_BASE__INST1_SEG2 0
> +#define NBIO_BASE__INST1_SEG3 0
> +#define NBIO_BASE__INST1_SEG4 0
> +
> +#define NBIO_BASE__INST2_SEG0 0
> +#define NBIO_BASE__INST2_SEG1 0
> +#define NBIO_BASE__INST2_SEG2 0
> +#define NBIO_BASE__INST2_SEG3 0
> +#define NBIO_BASE__INST2_SEG4 0
> +
> +#define NBIO_BASE__INST3_SEG0 0
> +#define NBIO_BASE__INST3_SEG1 0
> +#define NBIO_BASE__INST3_SEG2 0
> +#define NBIO_BASE__INST3_SEG3 0
> +#define NBIO_BASE__INST3_SEG4 0
> +
> +#define NBIO_BASE__INST4_SEG0 0
> +#define NBIO_BASE__INST4_SEG1 0
> +#define NBIO_BASE__INST4_SEG2 0
> +#define NBIO_BASE__INST4_SEG3 0
> +#define NBIO_BASE__INST4_SEG4 0
> +
> +#define DCE_BASE__INST0_SEG0 0x00000012
> +#define DCE_BASE__INST0_SEG1 0x000000C0
> +#define DCE_BASE__INST0_SEG2 0x000034C0
> +#define DCE_BASE__INST0_SEG3 0
> +#define DCE_BASE__INST0_SEG4 0
> +
> +#define DCE_BASE__INST1_SEG0 0
> +#define DCE_BASE__INST1_SEG1 0
> +#define DCE_BASE__INST1_SEG2 0
> +#define DCE_BASE__INST1_SEG3 0
> +#define DCE_BASE__INST1_SEG4 0
> +
> +#define DCE_BASE__INST2_SEG0 0
> +#define DCE_BASE__INST2_SEG1 0
> +#define DCE_BASE__INST2_SEG2 0
> +#define DCE_BASE__INST2_SEG3 0
> +#define DCE_BASE__INST2_SEG4 0
> +
> +#define DCE_BASE__INST3_SEG0 0
> +#define DCE_BASE__INST3_SEG1 0
> +#define DCE_BASE__INST3_SEG2 0
> +#define DCE_BASE__INST3_SEG3 0
> +#define DCE_BASE__INST3_SEG4 0
> +
> +#define DCE_BASE__INST4_SEG0 0
> +#define DCE_BASE__INST4_SEG1 0
> +#define DCE_BASE__INST4_SEG2 0
> +#define DCE_BASE__INST4_SEG3 0
> +#define DCE_BASE__INST4_SEG4 0
> +
> +#define DCN_BASE__INST0_SEG0 0x00000012
> +#define DCN_BASE__INST0_SEG1 0x000000C0
> +#define DCN_BASE__INST0_SEG2 0x000034C0
> +#define DCN_BASE__INST0_SEG3 0
> +#define DCN_BASE__INST0_SEG4 0
> +
> +#define DCN_BASE__INST1_SEG0 0
> +#define DCN_BASE__INST1_SEG1 0
> +#define DCN_BASE__INST1_SEG2 0
> +#define DCN_BASE__INST1_SEG3 0
> +#define DCN_BASE__INST1_SEG4 0
> +
> +#define DCN_BASE__INST2_SEG0 0
> +#define DCN_BASE__INST2_SEG1 0
> +#define DCN_BASE__INST2_SEG2 0
> +#define DCN_BASE__INST2_SEG3 0
> +#define DCN_BASE__INST2_SEG4 0
> +
> +#define DCN_BASE__INST3_SEG0 0
> +#define DCN_BASE__INST3_SEG1 0
> +#define DCN_BASE__INST3_SEG2 0
> +#define DCN_BASE__INST3_SEG3 0
> +#define DCN_BASE__INST3_SEG4 0
> +
> +#define DCN_BASE__INST4_SEG0 0
> +#define DCN_BASE__INST4_SEG1 0
> +#define DCN_BASE__INST4_SEG2 0
> +#define DCN_BASE__INST4_SEG3 0
> +#define DCN_BASE__INST4_SEG4 0
> +
> +#define MP0_BASE__INST0_SEG0 0x00016000
> +#define MP0_BASE__INST0_SEG1 0
> +#define MP0_BASE__INST0_SEG2 0
> +#define MP0_BASE__INST0_SEG3 0
> +#define MP0_BASE__INST0_SEG4 0
> +
> +#define MP0_BASE__INST1_SEG0 0
> +#define MP0_BASE__INST1_SEG1 0
> +#define MP0_BASE__INST1_SEG2 0
> +#define MP0_BASE__INST1_SEG3 0
> +#define MP0_BASE__INST1_SEG4 0
> +
> +#define MP0_BASE__INST2_SEG0 0
> +#define MP0_BASE__INST2_SEG1 0
> +#define MP0_BASE__INST2_SEG2 0
> +#define MP0_BASE__INST2_SEG3 0
> +#define MP0_BASE__INST2_SEG4 0
> +
> +#define MP0_BASE__INST3_SEG0 0
> +#define MP0_BASE__INST3_SEG1 0
> +#define MP0_BASE__INST3_SEG2 0
> +#define MP0_BASE__INST3_SEG3 0
> +#define MP0_BASE__INST3_SEG4 0
> +
> +#define MP0_BASE__INST4_SEG0 0
> +#define MP0_BASE__INST4_SEG1 0
> +#define MP0_BASE__INST4_SEG2 0
> +#define MP0_BASE__INST4_SEG3 0
> +#define MP0_BASE__INST4_SEG4 0
> +
> +#define MP1_BASE__INST0_SEG0 0x00016200
> +#define MP1_BASE__INST0_SEG1 0
> +#define MP1_BASE__INST0_SEG2 0
> +#define MP1_BASE__INST0_SEG3 0
> +#define MP1_BASE__INST0_SEG4 0
> +
> +#define MP1_BASE__INST1_SEG0 0
> +#define MP1_BASE__INST1_SEG1 0
> +#define MP1_BASE__INST1_SEG2 0
> +#define MP1_BASE__INST1_SEG3 0
> +#define MP1_BASE__INST1_SEG4 0
> +
> +#define MP1_BASE__INST2_SEG0 0
> +#define MP1_BASE__INST2_SEG1 0
> +#define MP1_BASE__INST2_SEG2 0
> +#define MP1_BASE__INST2_SEG3 0
> +#define MP1_BASE__INST2_SEG4 0
> +
> +#define MP1_BASE__INST3_SEG0 0
> +#define MP1_BASE__INST3_SEG1 0
> +#define MP1_BASE__INST3_SEG2 0
> +#define MP1_BASE__INST3_SEG3 0
> +#define MP1_BASE__INST3_SEG4 0
> +
> +#define MP1_BASE__INST4_SEG0 0
> +#define MP1_BASE__INST4_SEG1 0
> +#define MP1_BASE__INST4_SEG2 0
> +#define MP1_BASE__INST4_SEG3 0
> +#define MP1_BASE__INST4_SEG4 0
> +
> +#define MP2_BASE__INST0_SEG0 0x00016400
> +#define MP2_BASE__INST0_SEG1 0
> +#define MP2_BASE__INST0_SEG2 0
> +#define MP2_BASE__INST0_SEG3 0
> +#define MP2_BASE__INST0_SEG4 0
> +
> +#define MP2_BASE__INST1_SEG0 0
> +#define MP2_BASE__INST1_SEG1 0
> +#define MP2_BASE__INST1_SEG2 0
> +#define MP2_BASE__INST1_SEG3 0
> +#define MP2_BASE__INST1_SEG4 0
> +
> +#define MP2_BASE__INST2_SEG0 0
> +#define MP2_BASE__INST2_SEG1 0
> +#define MP2_BASE__INST2_SEG2 0
> +#define MP2_BASE__INST2_SEG3 0
> +#define MP2_BASE__INST2_SEG4 0
> +
> +#define MP2_BASE__INST3_SEG0 0
> +#define MP2_BASE__INST3_SEG1 0
> +#define MP2_BASE__INST3_SEG2 0
> +#define MP2_BASE__INST3_SEG3 0
> +#define MP2_BASE__INST3_SEG4 0
> +
> +#define MP2_BASE__INST4_SEG0 0
> +#define MP2_BASE__INST4_SEG1 0
> +#define MP2_BASE__INST4_SEG2 0
> +#define MP2_BASE__INST4_SEG3 0
> +#define MP2_BASE__INST4_SEG4 0
> +
> +#define DF_BASE__INST0_SEG0 0x00007000
> +#define DF_BASE__INST0_SEG1 0
> +#define DF_BASE__INST0_SEG2 0
> +#define DF_BASE__INST0_SEG3 0
> +#define DF_BASE__INST0_SEG4 0
> +
> +#define DF_BASE__INST1_SEG0 0
> +#define DF_BASE__INST1_SEG1 0
> +#define DF_BASE__INST1_SEG2 0
> +#define DF_BASE__INST1_SEG3 0
> +#define DF_BASE__INST1_SEG4 0
> +
> +#define DF_BASE__INST2_SEG0 0
> +#define DF_BASE__INST2_SEG1 0
> +#define DF_BASE__INST2_SEG2 0
> +#define DF_BASE__INST2_SEG3 0
> +#define DF_BASE__INST2_SEG4 0
> +
> +#define DF_BASE__INST3_SEG0 0
> +#define DF_BASE__INST3_SEG1 0
> +#define DF_BASE__INST3_SEG2 0
> +#define DF_BASE__INST3_SEG3 0
> +#define DF_BASE__INST3_SEG4 0
> +
> +#define DF_BASE__INST4_SEG0 0
> +#define DF_BASE__INST4_SEG1 0
> +#define DF_BASE__INST4_SEG2 0
> +#define DF_BASE__INST4_SEG3 0
> +#define DF_BASE__INST4_SEG4 0
> +
> +#define UVD_BASE__INST0_SEG0 0x00007800
> +#define UVD_BASE__INST0_SEG1 0x00007E00
> +#define UVD_BASE__INST0_SEG2 0
> +#define UVD_BASE__INST0_SEG3 0
> +#define UVD_BASE__INST0_SEG4 0
> +
> +#define UVD_BASE__INST1_SEG0 0
> +#define UVD_BASE__INST1_SEG1 0
> +#define UVD_BASE__INST1_SEG2 0
> +#define UVD_BASE__INST1_SEG3 0
> +#define UVD_BASE__INST1_SEG4 0
> +
> +#define UVD_BASE__INST2_SEG0 0
> +#define UVD_BASE__INST2_SEG1 0
> +#define UVD_BASE__INST2_SEG2 0
> +#define UVD_BASE__INST2_SEG3 0
> +#define UVD_BASE__INST2_SEG4 0
> +
> +#define UVD_BASE__INST3_SEG0 0
> +#define UVD_BASE__INST3_SEG1 0
> +#define UVD_BASE__INST3_SEG2 0
> +#define UVD_BASE__INST3_SEG3 0
> +#define UVD_BASE__INST3_SEG4 0
> +
> +#define UVD_BASE__INST4_SEG0 0
> +#define UVD_BASE__INST4_SEG1 0
> +#define UVD_BASE__INST4_SEG2 0
> +#define UVD_BASE__INST4_SEG3 0
> +#define UVD_BASE__INST4_SEG4 0
> +
> +#define VCN_BASE__INST0_SEG0 0x00007800
> +#define VCN_BASE__INST0_SEG1 0x00007E00
> +#define VCN_BASE__INST0_SEG2 0
> +#define VCN_BASE__INST0_SEG3 0
> +#define VCN_BASE__INST0_SEG4 0
> +
> +#define VCN_BASE__INST1_SEG0 0
> +#define VCN_BASE__INST1_SEG1 0
> +#define VCN_BASE__INST1_SEG2 0
> +#define VCN_BASE__INST1_SEG3 0
> +#define VCN_BASE__INST1_SEG4 0
> +
> +#define VCN_BASE__INST2_SEG0 0
> +#define VCN_BASE__INST2_SEG1 0
> +#define VCN_BASE__INST2_SEG2 0
> +#define VCN_BASE__INST2_SEG3 0
> +#define VCN_BASE__INST2_SEG4 0
> +
> +#define VCN_BASE__INST3_SEG0 0
> +#define VCN_BASE__INST3_SEG1 0
> +#define VCN_BASE__INST3_SEG2 0
> +#define VCN_BASE__INST3_SEG3 0
> +#define VCN_BASE__INST3_SEG4 0
> +
> +#define VCN_BASE__INST4_SEG0 0
> +#define VCN_BASE__INST4_SEG1 0
> +#define VCN_BASE__INST4_SEG2 0
> +#define VCN_BASE__INST4_SEG3 0
> +#define VCN_BASE__INST4_SEG4 0
> +
> +#define DBGU_BASE__INST0_SEG0 0x00000180
> +#define DBGU_BASE__INST0_SEG1 0x000001A0
> +#define DBGU_BASE__INST0_SEG2 0
> +#define DBGU_BASE__INST0_SEG3 0
> +#define DBGU_BASE__INST0_SEG4 0
> +
> +#define DBGU_BASE__INST1_SEG0 0
> +#define DBGU_BASE__INST1_SEG1 0
> +#define DBGU_BASE__INST1_SEG2 0
> +#define DBGU_BASE__INST1_SEG3 0
> +#define DBGU_BASE__INST1_SEG4 0
> +
> +#define DBGU_BASE__INST2_SEG0 0
> +#define DBGU_BASE__INST2_SEG1 0
> +#define DBGU_BASE__INST2_SEG2 0
> +#define DBGU_BASE__INST2_SEG3 0
> +#define DBGU_BASE__INST2_SEG4 0
> +
> +#define DBGU_BASE__INST3_SEG0 0
> +#define DBGU_BASE__INST3_SEG1 0
> +#define DBGU_BASE__INST3_SEG2 0
> +#define DBGU_BASE__INST3_SEG3 0
> +#define DBGU_BASE__INST3_SEG4 0
> +
> +#define DBGU_BASE__INST4_SEG0 0
> +#define DBGU_BASE__INST4_SEG1 0
> +#define DBGU_BASE__INST4_SEG2 0
> +#define DBGU_BASE__INST4_SEG3 0
> +#define DBGU_BASE__INST4_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0
> +#define DBGU_NBIO_BASE__INST0_SEG1 0
> +#define DBGU_NBIO_BASE__INST0_SEG2 0
> +#define DBGU_NBIO_BASE__INST0_SEG3 0
> +#define DBGU_NBIO_BASE__INST0_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST1_SEG0 0
> +#define DBGU_NBIO_BASE__INST1_SEG1 0
> +#define DBGU_NBIO_BASE__INST1_SEG2 0
> +#define DBGU_NBIO_BASE__INST1_SEG3 0
> +#define DBGU_NBIO_BASE__INST1_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST2_SEG0 0
> +#define DBGU_NBIO_BASE__INST2_SEG1 0
> +#define DBGU_NBIO_BASE__INST2_SEG2 0
> +#define DBGU_NBIO_BASE__INST2_SEG3 0
> +#define DBGU_NBIO_BASE__INST2_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST3_SEG0 0
> +#define DBGU_NBIO_BASE__INST3_SEG1 0
> +#define DBGU_NBIO_BASE__INST3_SEG2 0
> +#define DBGU_NBIO_BASE__INST3_SEG3 0
> +#define DBGU_NBIO_BASE__INST3_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST4_SEG0 0
> +#define DBGU_NBIO_BASE__INST4_SEG1 0
> +#define DBGU_NBIO_BASE__INST4_SEG2 0
> +#define DBGU_NBIO_BASE__INST4_SEG3 0
> +#define DBGU_NBIO_BASE__INST4_SEG4 0
> +
> +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0
> +#define DBGU_IO_BASE__INST0_SEG1 0
> +#define DBGU_IO_BASE__INST0_SEG2 0
> +#define DBGU_IO_BASE__INST0_SEG3 0
> +#define DBGU_IO_BASE__INST0_SEG4 0
> +
> +#define DBGU_IO_BASE__INST1_SEG0 0
> +#define DBGU_IO_BASE__INST1_SEG1 0
> +#define DBGU_IO_BASE__INST1_SEG2 0
> +#define DBGU_IO_BASE__INST1_SEG3 0
> +#define DBGU_IO_BASE__INST1_SEG4 0
> +
> +#define DBGU_IO_BASE__INST2_SEG0 0
> +#define DBGU_IO_BASE__INST2_SEG1 0
> +#define DBGU_IO_BASE__INST2_SEG2 0
> +#define DBGU_IO_BASE__INST2_SEG3 0
> +#define DBGU_IO_BASE__INST2_SEG4 0
> +
> +#define DBGU_IO_BASE__INST3_SEG0 0
> +#define DBGU_IO_BASE__INST3_SEG1 0
> +#define DBGU_IO_BASE__INST3_SEG2 0
> +#define DBGU_IO_BASE__INST3_SEG3 0
> +#define DBGU_IO_BASE__INST3_SEG4 0
> +
> +#define DBGU_IO_BASE__INST4_SEG0 0
> +#define DBGU_IO_BASE__INST4_SEG1 0
> +#define DBGU_IO_BASE__INST4_SEG2 0
> +#define DBGU_IO_BASE__INST4_SEG3 0
> +#define DBGU_IO_BASE__INST4_SEG4 0
> +
> +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0
> +#define DFX_DAP_BASE__INST0_SEG1 0
> +#define DFX_DAP_BASE__INST0_SEG2 0
> +#define DFX_DAP_BASE__INST0_SEG3 0
> +#define DFX_DAP_BASE__INST0_SEG4 0
> +
> +#define DFX_DAP_BASE__INST1_SEG0 0
> +#define DFX_DAP_BASE__INST1_SEG1 0
> +#define DFX_DAP_BASE__INST1_SEG2 0
> +#define DFX_DAP_BASE__INST1_SEG3 0
> +#define DFX_DAP_BASE__INST1_SEG4 0
> +
> +#define DFX_DAP_BASE__INST2_SEG0 0
> +#define DFX_DAP_BASE__INST2_SEG1 0
> +#define DFX_DAP_BASE__INST2_SEG2 0
> +#define DFX_DAP_BASE__INST2_SEG3 0
> +#define DFX_DAP_BASE__INST2_SEG4 0
> +
> +#define DFX_DAP_BASE__INST3_SEG0 0
> +#define DFX_DAP_BASE__INST3_SEG1 0
> +#define DFX_DAP_BASE__INST3_SEG2 0
> +#define DFX_DAP_BASE__INST3_SEG3 0
> +#define DFX_DAP_BASE__INST3_SEG4 0
> +
> +#define DFX_DAP_BASE__INST4_SEG0 0
> +#define DFX_DAP_BASE__INST4_SEG1 0
> +#define DFX_DAP_BASE__INST4_SEG2 0
> +#define DFX_DAP_BASE__INST4_SEG3 0
> +#define DFX_DAP_BASE__INST4_SEG4 0
> +
> +#define DFX_BASE__INST0_SEG0 0x00000580
> +#define DFX_BASE__INST0_SEG1 0
> +#define DFX_BASE__INST0_SEG2 0
> +#define DFX_BASE__INST0_SEG3 0
> +#define DFX_BASE__INST0_SEG4 0
> +
> +#define DFX_BASE__INST1_SEG0 0
> +#define DFX_BASE__INST1_SEG1 0
> +#define DFX_BASE__INST1_SEG2 0
> +#define DFX_BASE__INST1_SEG3 0
> +#define DFX_BASE__INST1_SEG4 0
> +
> +#define DFX_BASE__INST2_SEG0 0
> +#define DFX_BASE__INST2_SEG1 0
> +#define DFX_BASE__INST2_SEG2 0
> +#define DFX_BASE__INST2_SEG3 0
> +#define DFX_BASE__INST2_SEG4 0
> +
> +#define DFX_BASE__INST3_SEG0 0
> +#define DFX_BASE__INST3_SEG1 0
> +#define DFX_BASE__INST3_SEG2 0
> +#define DFX_BASE__INST3_SEG3 0
> +#define DFX_BASE__INST3_SEG4 0
> +
> +#define DFX_BASE__INST4_SEG0 0
> +#define DFX_BASE__INST4_SEG1 0
> +#define DFX_BASE__INST4_SEG2 0
> +#define DFX_BASE__INST4_SEG3 0
> +#define DFX_BASE__INST4_SEG4 0
> +
> +#define ISP_BASE__INST0_SEG0 0x00018000
> +#define ISP_BASE__INST0_SEG1 0
> +#define ISP_BASE__INST0_SEG2 0
> +#define ISP_BASE__INST0_SEG3 0
> +#define ISP_BASE__INST0_SEG4 0
> +
> +#define ISP_BASE__INST1_SEG0 0
> +#define ISP_BASE__INST1_SEG1 0
> +#define ISP_BASE__INST1_SEG2 0
> +#define ISP_BASE__INST1_SEG3 0
> +#define ISP_BASE__INST1_SEG4 0
> +
> +#define ISP_BASE__INST2_SEG0 0
> +#define ISP_BASE__INST2_SEG1 0
> +#define ISP_BASE__INST2_SEG2 0
> +#define ISP_BASE__INST2_SEG3 0
> +#define ISP_BASE__INST2_SEG4 0
> +
> +#define ISP_BASE__INST3_SEG0 0
> +#define ISP_BASE__INST3_SEG1 0
> +#define ISP_BASE__INST3_SEG2 0
> +#define ISP_BASE__INST3_SEG3 0
> +#define ISP_BASE__INST3_SEG4 0
> +
> +#define ISP_BASE__INST4_SEG0 0
> +#define ISP_BASE__INST4_SEG1 0
> +#define ISP_BASE__INST4_SEG2 0
> +#define ISP_BASE__INST4_SEG3 0
> +#define ISP_BASE__INST4_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0
> +#define SYSTEMHUB_BASE__INST0_SEG1 0
> +#define SYSTEMHUB_BASE__INST0_SEG2 0
> +#define SYSTEMHUB_BASE__INST0_SEG3 0
> +#define SYSTEMHUB_BASE__INST0_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST1_SEG0 0
> +#define SYSTEMHUB_BASE__INST1_SEG1 0
> +#define SYSTEMHUB_BASE__INST1_SEG2 0
> +#define SYSTEMHUB_BASE__INST1_SEG3 0
> +#define SYSTEMHUB_BASE__INST1_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST2_SEG0 0
> +#define SYSTEMHUB_BASE__INST2_SEG1 0
> +#define SYSTEMHUB_BASE__INST2_SEG2 0
> +#define SYSTEMHUB_BASE__INST2_SEG3 0
> +#define SYSTEMHUB_BASE__INST2_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST3_SEG0 0
> +#define SYSTEMHUB_BASE__INST3_SEG1 0
> +#define SYSTEMHUB_BASE__INST3_SEG2 0
> +#define SYSTEMHUB_BASE__INST3_SEG3 0
> +#define SYSTEMHUB_BASE__INST3_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST4_SEG0 0
> +#define SYSTEMHUB_BASE__INST4_SEG1 0
> +#define SYSTEMHUB_BASE__INST4_SEG2 0
> +#define SYSTEMHUB_BASE__INST4_SEG3 0
> +#define SYSTEMHUB_BASE__INST4_SEG4 0
> +
> +#define L2IMU_BASE__INST0_SEG0 0x00007DC0
> +#define L2IMU_BASE__INST0_SEG1 0
> +#define L2IMU_BASE__INST0_SEG2 0
> +#define L2IMU_BASE__INST0_SEG3 0
> +#define L2IMU_BASE__INST0_SEG4 0
> +
> +#define L2IMU_BASE__INST1_SEG0 0
> +#define L2IMU_BASE__INST1_SEG1 0
> +#define L2IMU_BASE__INST1_SEG2 0
> +#define L2IMU_BASE__INST1_SEG3 0
> +#define L2IMU_BASE__INST1_SEG4 0
> +
> +#define L2IMU_BASE__INST2_SEG0 0
> +#define L2IMU_BASE__INST2_SEG1 0
> +#define L2IMU_BASE__INST2_SEG2 0
> +#define L2IMU_BASE__INST2_SEG3 0
> +#define L2IMU_BASE__INST2_SEG4 0
> +
> +#define L2IMU_BASE__INST3_SEG0 0
> +#define L2IMU_BASE__INST3_SEG1 0
> +#define L2IMU_BASE__INST3_SEG2 0
> +#define L2IMU_BASE__INST3_SEG3 0
> +#define L2IMU_BASE__INST3_SEG4 0
> +
> +#define L2IMU_BASE__INST4_SEG0 0
> +#define L2IMU_BASE__INST4_SEG1 0
> +#define L2IMU_BASE__INST4_SEG2 0
> +#define L2IMU_BASE__INST4_SEG3 0
> +#define L2IMU_BASE__INST4_SEG4 0
> +
> +#define IOHC_BASE__INST0_SEG0 0x00010000
> +#define IOHC_BASE__INST0_SEG1 0
> +#define IOHC_BASE__INST0_SEG2 0
> +#define IOHC_BASE__INST0_SEG3 0
> +#define IOHC_BASE__INST0_SEG4 0
> +
> +#define IOHC_BASE__INST1_SEG0 0
> +#define IOHC_BASE__INST1_SEG1 0
> +#define IOHC_BASE__INST1_SEG2 0
> +#define IOHC_BASE__INST1_SEG3 0
> +#define IOHC_BASE__INST1_SEG4 0
> +
> +#define IOHC_BASE__INST2_SEG0 0
> +#define IOHC_BASE__INST2_SEG1 0
> +#define IOHC_BASE__INST2_SEG2 0
> +#define IOHC_BASE__INST2_SEG3 0
> +#define IOHC_BASE__INST2_SEG4 0
> +
> +#define IOHC_BASE__INST3_SEG0 0
> +#define IOHC_BASE__INST3_SEG1 0
> +#define IOHC_BASE__INST3_SEG2 0
> +#define IOHC_BASE__INST3_SEG3 0
> +#define IOHC_BASE__INST3_SEG4 0
> +
> +#define IOHC_BASE__INST4_SEG0 0
> +#define IOHC_BASE__INST4_SEG1 0
> +#define IOHC_BASE__INST4_SEG2 0
> +#define IOHC_BASE__INST4_SEG3 0
> +#define IOHC_BASE__INST4_SEG4 0
> +
> +#define ATHUB_BASE__INST0_SEG0 0x00000C20
> +#define ATHUB_BASE__INST0_SEG1 0
> +#define ATHUB_BASE__INST0_SEG2 0
> +#define ATHUB_BASE__INST0_SEG3 0
> +#define ATHUB_BASE__INST0_SEG4 0
> +
> +#define ATHUB_BASE__INST1_SEG0 0
> +#define ATHUB_BASE__INST1_SEG1 0
> +#define ATHUB_BASE__INST1_SEG2 0
> +#define ATHUB_BASE__INST1_SEG3 0
> +#define ATHUB_BASE__INST1_SEG4 0
> +
> +#define ATHUB_BASE__INST2_SEG0 0
> +#define ATHUB_BASE__INST2_SEG1 0
> +#define ATHUB_BASE__INST2_SEG2 0
> +#define ATHUB_BASE__INST2_SEG3 0
> +#define ATHUB_BASE__INST2_SEG4 0
> +
> +#define ATHUB_BASE__INST3_SEG0 0
> +#define ATHUB_BASE__INST3_SEG1 0
> +#define ATHUB_BASE__INST3_SEG2 0
> +#define ATHUB_BASE__INST3_SEG3 0
> +#define ATHUB_BASE__INST3_SEG4 0
> +
> +#define ATHUB_BASE__INST4_SEG0 0
> +#define ATHUB_BASE__INST4_SEG1 0
> +#define ATHUB_BASE__INST4_SEG2 0
> +#define ATHUB_BASE__INST4_SEG3 0
> +#define ATHUB_BASE__INST4_SEG4 0
> +
> +#define VCE_BASE__INST0_SEG0 0x00007E00
> +#define VCE_BASE__INST0_SEG1 0x00048800
> +#define VCE_BASE__INST0_SEG2 0
> +#define VCE_BASE__INST0_SEG3 0
> +#define VCE_BASE__INST0_SEG4 0
> +
> +#define VCE_BASE__INST1_SEG0 0
> +#define VCE_BASE__INST1_SEG1 0
> +#define VCE_BASE__INST1_SEG2 0
> +#define VCE_BASE__INST1_SEG3 0
> +#define VCE_BASE__INST1_SEG4 0
> +
> +#define VCE_BASE__INST2_SEG0 0
> +#define VCE_BASE__INST2_SEG1 0
> +#define VCE_BASE__INST2_SEG2 0
> +#define VCE_BASE__INST2_SEG3 0
> +#define VCE_BASE__INST2_SEG4 0
> +
> +#define VCE_BASE__INST3_SEG0 0
> +#define VCE_BASE__INST3_SEG1 0
> +#define VCE_BASE__INST3_SEG2 0
> +#define VCE_BASE__INST3_SEG3 0
> +#define VCE_BASE__INST3_SEG4 0
> +
> +#define VCE_BASE__INST4_SEG0 0
> +#define VCE_BASE__INST4_SEG1 0
> +#define VCE_BASE__INST4_SEG2 0
> +#define VCE_BASE__INST4_SEG3 0
> +#define VCE_BASE__INST4_SEG4 0
> +
> +#define GC_BASE__INST0_SEG0 0x00002000
> +#define GC_BASE__INST0_SEG1 0x0000A000
> +#define GC_BASE__INST0_SEG2 0
> +#define GC_BASE__INST0_SEG3 0
> +#define GC_BASE__INST0_SEG4 0
> +
> +#define GC_BASE__INST1_SEG0 0
> +#define GC_BASE__INST1_SEG1 0
> +#define GC_BASE__INST1_SEG2 0
> +#define GC_BASE__INST1_SEG3 0
> +#define GC_BASE__INST1_SEG4 0
> +
> +#define GC_BASE__INST2_SEG0 0
> +#define GC_BASE__INST2_SEG1 0
> +#define GC_BASE__INST2_SEG2 0
> +#define GC_BASE__INST2_SEG3 0
> +#define GC_BASE__INST2_SEG4 0
> +
> +#define GC_BASE__INST3_SEG0 0
> +#define GC_BASE__INST3_SEG1 0
> +#define GC_BASE__INST3_SEG2 0
> +#define GC_BASE__INST3_SEG3 0
> +#define GC_BASE__INST3_SEG4 0
> +
> +#define GC_BASE__INST4_SEG0 0
> +#define GC_BASE__INST4_SEG1 0
> +#define GC_BASE__INST4_SEG2 0
> +#define GC_BASE__INST4_SEG3 0
> +#define GC_BASE__INST4_SEG4 0
> +
> +#define MMHUB_BASE__INST0_SEG0 0x0001A000
> +#define MMHUB_BASE__INST0_SEG1 0
> +#define MMHUB_BASE__INST0_SEG2 0
> +#define MMHUB_BASE__INST0_SEG3 0
> +#define MMHUB_BASE__INST0_SEG4 0
> +
> +#define MMHUB_BASE__INST1_SEG0 0
> +#define MMHUB_BASE__INST1_SEG1 0
> +#define MMHUB_BASE__INST1_SEG2 0
> +#define MMHUB_BASE__INST1_SEG3 0
> +#define MMHUB_BASE__INST1_SEG4 0
> +
> +#define MMHUB_BASE__INST2_SEG0 0
> +#define MMHUB_BASE__INST2_SEG1 0
> +#define MMHUB_BASE__INST2_SEG2 0
> +#define MMHUB_BASE__INST2_SEG3 0
> +#define MMHUB_BASE__INST2_SEG4 0
> +
> +#define MMHUB_BASE__INST3_SEG0 0
> +#define MMHUB_BASE__INST3_SEG1 0
> +#define MMHUB_BASE__INST3_SEG2 0
> +#define MMHUB_BASE__INST3_SEG3 0
> +#define MMHUB_BASE__INST3_SEG4 0
> +
> +#define MMHUB_BASE__INST4_SEG0 0
> +#define MMHUB_BASE__INST4_SEG1 0
> +#define MMHUB_BASE__INST4_SEG2 0
> +#define MMHUB_BASE__INST4_SEG3 0
> +#define MMHUB_BASE__INST4_SEG4 0
> +
> +#define RSMU_BASE__INST0_SEG0 0x00012000
> +#define RSMU_BASE__INST0_SEG1 0
> +#define RSMU_BASE__INST0_SEG2 0
> +#define RSMU_BASE__INST0_SEG3 0
> +#define RSMU_BASE__INST0_SEG4 0
> +
> +#define RSMU_BASE__INST1_SEG0 0
> +#define RSMU_BASE__INST1_SEG1 0
> +#define RSMU_BASE__INST1_SEG2 0
> +#define RSMU_BASE__INST1_SEG3 0
> +#define RSMU_BASE__INST1_SEG4 0
> +
> +#define RSMU_BASE__INST2_SEG0 0
> +#define RSMU_BASE__INST2_SEG1 0
> +#define RSMU_BASE__INST2_SEG2 0
> +#define RSMU_BASE__INST2_SEG3 0
> +#define RSMU_BASE__INST2_SEG4 0
> +
> +#define RSMU_BASE__INST3_SEG0 0
> +#define RSMU_BASE__INST3_SEG1 0
> +#define RSMU_BASE__INST3_SEG2 0
> +#define RSMU_BASE__INST3_SEG3 0
> +#define RSMU_BASE__INST3_SEG4 0
> +
> +#define RSMU_BASE__INST4_SEG0 0
> +#define RSMU_BASE__INST4_SEG1 0
> +#define RSMU_BASE__INST4_SEG2 0
> +#define RSMU_BASE__INST4_SEG3 0
> +#define RSMU_BASE__INST4_SEG4 0
> +
> +#define HDP_BASE__INST0_SEG0 0x00000F20
> +#define HDP_BASE__INST0_SEG1 0
> +#define HDP_BASE__INST0_SEG2 0
> +#define HDP_BASE__INST0_SEG3 0
> +#define HDP_BASE__INST0_SEG4 0
> +
> +#define HDP_BASE__INST1_SEG0 0
> +#define HDP_BASE__INST1_SEG1 0
> +#define HDP_BASE__INST1_SEG2 0
> +#define HDP_BASE__INST1_SEG3 0
> +#define HDP_BASE__INST1_SEG4 0
> +
> +#define HDP_BASE__INST2_SEG0 0
> +#define HDP_BASE__INST2_SEG1 0
> +#define HDP_BASE__INST2_SEG2 0
> +#define HDP_BASE__INST2_SEG3 0
> +#define HDP_BASE__INST2_SEG4 0
> +
> +#define HDP_BASE__INST3_SEG0 0
> +#define HDP_BASE__INST3_SEG1 0
> +#define HDP_BASE__INST3_SEG2 0
> +#define HDP_BASE__INST3_SEG3 0
> +#define HDP_BASE__INST3_SEG4 0
> +
> +#define HDP_BASE__INST4_SEG0 0
> +#define HDP_BASE__INST4_SEG1 0
> +#define HDP_BASE__INST4_SEG2 0
> +#define HDP_BASE__INST4_SEG3 0
> +#define HDP_BASE__INST4_SEG4 0
> +
> +#define OSSSYS_BASE__INST0_SEG0 0x000010A0
> +#define OSSSYS_BASE__INST0_SEG1 0
> +#define OSSSYS_BASE__INST0_SEG2 0
> +#define OSSSYS_BASE__INST0_SEG3 0
> +#define OSSSYS_BASE__INST0_SEG4 0
> +
> +#define OSSSYS_BASE__INST1_SEG0 0
> +#define OSSSYS_BASE__INST1_SEG1 0
> +#define OSSSYS_BASE__INST1_SEG2 0
> +#define OSSSYS_BASE__INST1_SEG3 0
> +#define OSSSYS_BASE__INST1_SEG4 0
> +
> +#define OSSSYS_BASE__INST2_SEG0 0
> +#define OSSSYS_BASE__INST2_SEG1 0
> +#define OSSSYS_BASE__INST2_SEG2 0
> +#define OSSSYS_BASE__INST2_SEG3 0
> +#define OSSSYS_BASE__INST2_SEG4 0
> +
> +#define OSSSYS_BASE__INST3_SEG0 0
> +#define OSSSYS_BASE__INST3_SEG1 0
> +#define OSSSYS_BASE__INST3_SEG2 0
> +#define OSSSYS_BASE__INST3_SEG3 0
> +#define OSSSYS_BASE__INST3_SEG4 0
> +
> +#define OSSSYS_BASE__INST4_SEG0 0
> +#define OSSSYS_BASE__INST4_SEG1 0
> +#define OSSSYS_BASE__INST4_SEG2 0
> +#define OSSSYS_BASE__INST4_SEG3 0
> +#define OSSSYS_BASE__INST4_SEG4 0
> +
> +#define SDMA0_BASE__INST0_SEG0 0x00001260
> +#define SDMA0_BASE__INST0_SEG1 0
> +#define SDMA0_BASE__INST0_SEG2 0
> +#define SDMA0_BASE__INST0_SEG3 0
> +#define SDMA0_BASE__INST0_SEG4 0
> +
> +#define SDMA0_BASE__INST1_SEG0 0
> +#define SDMA0_BASE__INST1_SEG1 0
> +#define SDMA0_BASE__INST1_SEG2 0
> +#define SDMA0_BASE__INST1_SEG3 0
> +#define SDMA0_BASE__INST1_SEG4 0
> +
> +#define SDMA0_BASE__INST2_SEG0 0
> +#define SDMA0_BASE__INST2_SEG1 0
> +#define SDMA0_BASE__INST2_SEG2 0
> +#define SDMA0_BASE__INST2_SEG3 0
> +#define SDMA0_BASE__INST2_SEG4 0
> +
> +#define SDMA0_BASE__INST3_SEG0 0
> +#define SDMA0_BASE__INST3_SEG1 0
> +#define SDMA0_BASE__INST3_SEG2 0
> +#define SDMA0_BASE__INST3_SEG3 0
> +#define SDMA0_BASE__INST3_SEG4 0
> +
> +#define SDMA0_BASE__INST4_SEG0 0
> +#define SDMA0_BASE__INST4_SEG1 0
> +#define SDMA0_BASE__INST4_SEG2 0
> +#define SDMA0_BASE__INST4_SEG3 0
> +#define SDMA0_BASE__INST4_SEG4 0
> +
> +#define SDMA1_BASE__INST0_SEG0 0x00001460
> +#define SDMA1_BASE__INST0_SEG1 0
> +#define SDMA1_BASE__INST0_SEG2 0
> +#define SDMA1_BASE__INST0_SEG3 0
> +#define SDMA1_BASE__INST0_SEG4 0
> +
> +#define SDMA1_BASE__INST1_SEG0 0
> +#define SDMA1_BASE__INST1_SEG1 0
> +#define SDMA1_BASE__INST1_SEG2 0
> +#define SDMA1_BASE__INST1_SEG3 0
> +#define SDMA1_BASE__INST1_SEG4 0
> +
> +#define SDMA1_BASE__INST2_SEG0 0
> +#define SDMA1_BASE__INST2_SEG1 0
> +#define SDMA1_BASE__INST2_SEG2 0
> +#define SDMA1_BASE__INST2_SEG3 0
> +#define SDMA1_BASE__INST2_SEG4 0
> +
> +#define SDMA1_BASE__INST3_SEG0 0
> +#define SDMA1_BASE__INST3_SEG1 0
> +#define SDMA1_BASE__INST3_SEG2 0
> +#define SDMA1_BASE__INST3_SEG3 0
> +#define SDMA1_BASE__INST3_SEG4 0
> +
> +#define SDMA1_BASE__INST4_SEG0 0
> +#define SDMA1_BASE__INST4_SEG1 0
> +#define SDMA1_BASE__INST4_SEG2 0
> +#define SDMA1_BASE__INST4_SEG3 0
> +#define SDMA1_BASE__INST4_SEG4 0
> +
> +#define XDMA_BASE__INST0_SEG0 0x00003400
> +#define XDMA_BASE__INST0_SEG1 0
> +#define XDMA_BASE__INST0_SEG2 0
> +#define XDMA_BASE__INST0_SEG3 0
> +#define XDMA_BASE__INST0_SEG4 0
> +
> +#define XDMA_BASE__INST1_SEG0 0
> +#define XDMA_BASE__INST1_SEG1 0
> +#define XDMA_BASE__INST1_SEG2 0
> +#define XDMA_BASE__INST1_SEG3 0
> +#define XDMA_BASE__INST1_SEG4 0
> +
> +#define XDMA_BASE__INST2_SEG0 0
> +#define XDMA_BASE__INST2_SEG1 0
> +#define XDMA_BASE__INST2_SEG2 0
> +#define XDMA_BASE__INST2_SEG3 0
> +#define XDMA_BASE__INST2_SEG4 0
> +
> +#define XDMA_BASE__INST3_SEG0 0
> +#define XDMA_BASE__INST3_SEG1 0
> +#define XDMA_BASE__INST3_SEG2 0
> +#define XDMA_BASE__INST3_SEG3 0
> +#define XDMA_BASE__INST3_SEG4 0
> +
> +#define XDMA_BASE__INST4_SEG0 0
> +#define XDMA_BASE__INST4_SEG1 0
> +#define XDMA_BASE__INST4_SEG2 0
> +#define XDMA_BASE__INST4_SEG3 0
> +#define XDMA_BASE__INST4_SEG4 0
> +
> +#define UMC_BASE__INST0_SEG0 0x00014000
> +#define UMC_BASE__INST0_SEG1 0
> +#define UMC_BASE__INST0_SEG2 0
> +#define UMC_BASE__INST0_SEG3 0
> +#define UMC_BASE__INST0_SEG4 0
> +
> +#define UMC_BASE__INST1_SEG0 0
> +#define UMC_BASE__INST1_SEG1 0
> +#define UMC_BASE__INST1_SEG2 0
> +#define UMC_BASE__INST1_SEG3 0
> +#define UMC_BASE__INST1_SEG4 0
> +
> +#define UMC_BASE__INST2_SEG0 0
> +#define UMC_BASE__INST2_SEG1 0
> +#define UMC_BASE__INST2_SEG2 0
> +#define UMC_BASE__INST2_SEG3 0
> +#define UMC_BASE__INST2_SEG4 0
> +
> +#define UMC_BASE__INST3_SEG0 0
> +#define UMC_BASE__INST3_SEG1 0
> +#define UMC_BASE__INST3_SEG2 0
> +#define UMC_BASE__INST3_SEG3 0
> +#define UMC_BASE__INST3_SEG4 0
> +
> +#define UMC_BASE__INST4_SEG0 0
> +#define UMC_BASE__INST4_SEG1 0
> +#define UMC_BASE__INST4_SEG2 0
> +#define UMC_BASE__INST4_SEG3 0
> +#define UMC_BASE__INST4_SEG4 0
> +
> +#define THM_BASE__INST0_SEG0 0x00016600
> +#define THM_BASE__INST0_SEG1 0
> +#define THM_BASE__INST0_SEG2 0
> +#define THM_BASE__INST0_SEG3 0
> +#define THM_BASE__INST0_SEG4 0
> +
> +#define THM_BASE__INST1_SEG0 0
> +#define THM_BASE__INST1_SEG1 0
> +#define THM_BASE__INST1_SEG2 0
> +#define THM_BASE__INST1_SEG3 0
> +#define THM_BASE__INST1_SEG4 0
> +
> +#define THM_BASE__INST2_SEG0 0
> +#define THM_BASE__INST2_SEG1 0
> +#define THM_BASE__INST2_SEG2 0
> +#define THM_BASE__INST2_SEG3 0
> +#define THM_BASE__INST2_SEG4 0
> +
> +#define THM_BASE__INST3_SEG0 0
> +#define THM_BASE__INST3_SEG1 0
> +#define THM_BASE__INST3_SEG2 0
> +#define THM_BASE__INST3_SEG3 0
> +#define THM_BASE__INST3_SEG4 0
> +
> +#define THM_BASE__INST4_SEG0 0
> +#define THM_BASE__INST4_SEG1 0
> +#define THM_BASE__INST4_SEG2 0
> +#define THM_BASE__INST4_SEG3 0
> +#define THM_BASE__INST4_SEG4 0
> +
> +#define SMUIO_BASE__INST0_SEG0 0x00016800
> +#define SMUIO_BASE__INST0_SEG1 0
> +#define SMUIO_BASE__INST0_SEG2 0
> +#define SMUIO_BASE__INST0_SEG3 0
> +#define SMUIO_BASE__INST0_SEG4 0
> +
> +#define SMUIO_BASE__INST1_SEG0 0
> +#define SMUIO_BASE__INST1_SEG1 0
> +#define SMUIO_BASE__INST1_SEG2 0
> +#define SMUIO_BASE__INST1_SEG3 0
> +#define SMUIO_BASE__INST1_SEG4 0
> +
> +#define SMUIO_BASE__INST2_SEG0 0
> +#define SMUIO_BASE__INST2_SEG1 0
> +#define SMUIO_BASE__INST2_SEG2 0
> +#define SMUIO_BASE__INST2_SEG3 0
> +#define SMUIO_BASE__INST2_SEG4 0
> +
> +#define SMUIO_BASE__INST3_SEG0 0
> +#define SMUIO_BASE__INST3_SEG1 0
> +#define SMUIO_BASE__INST3_SEG2 0
> +#define SMUIO_BASE__INST3_SEG3 0
> +#define SMUIO_BASE__INST3_SEG4 0
> +
> +#define SMUIO_BASE__INST4_SEG0 0
> +#define SMUIO_BASE__INST4_SEG1 0
> +#define SMUIO_BASE__INST4_SEG2 0
> +#define SMUIO_BASE__INST4_SEG3 0
> +#define SMUIO_BASE__INST4_SEG4 0
> +
> +#define PWR_BASE__INST0_SEG0 0x00016A00
> +#define PWR_BASE__INST0_SEG1 0
> +#define PWR_BASE__INST0_SEG2 0
> +#define PWR_BASE__INST0_SEG3 0
> +#define PWR_BASE__INST0_SEG4 0
> +
> +#define PWR_BASE__INST1_SEG0 0
> +#define PWR_BASE__INST1_SEG1 0
> +#define PWR_BASE__INST1_SEG2 0
> +#define PWR_BASE__INST1_SEG3 0
> +#define PWR_BASE__INST1_SEG4 0
> +
> +#define PWR_BASE__INST2_SEG0 0
> +#define PWR_BASE__INST2_SEG1 0
> +#define PWR_BASE__INST2_SEG2 0
> +#define PWR_BASE__INST2_SEG3 0
> +#define PWR_BASE__INST2_SEG4 0
> +
> +#define PWR_BASE__INST3_SEG0 0
> +#define PWR_BASE__INST3_SEG1 0
> +#define PWR_BASE__INST3_SEG2 0
> +#define PWR_BASE__INST3_SEG3 0
> +#define PWR_BASE__INST3_SEG4 0
> +
> +#define PWR_BASE__INST4_SEG0 0
> +#define PWR_BASE__INST4_SEG1 0
> +#define PWR_BASE__INST4_SEG2 0
> +#define PWR_BASE__INST4_SEG3 0
> +#define PWR_BASE__INST4_SEG4 0
> +
> +#define CLK_BASE__INST0_SEG0 0x00016C00
> +#define CLK_BASE__INST0_SEG1 0
> +#define CLK_BASE__INST0_SEG2 0
> +#define CLK_BASE__INST0_SEG3 0
> +#define CLK_BASE__INST0_SEG4 0
> +
> +#define CLK_BASE__INST1_SEG0 0x00016E00
> +#define CLK_BASE__INST1_SEG1 0
> +#define CLK_BASE__INST1_SEG2 0
> +#define CLK_BASE__INST1_SEG3 0
> +#define CLK_BASE__INST1_SEG4 0
> +
> +#define CLK_BASE__INST2_SEG0 0x00017000
> +#define CLK_BASE__INST2_SEG1 0
> +#define CLK_BASE__INST2_SEG2 0
> +#define CLK_BASE__INST2_SEG3 0
> +#define CLK_BASE__INST2_SEG4 0
> +
> +#define CLK_BASE__INST3_SEG0 0x00017200
> +#define CLK_BASE__INST3_SEG1 0
> +#define CLK_BASE__INST3_SEG2 0
> +#define CLK_BASE__INST3_SEG3 0
> +#define CLK_BASE__INST3_SEG4 0
> +
> +#define CLK_BASE__INST4_SEG0 0x00017E00
> +#define CLK_BASE__INST4_SEG1 0
> +#define CLK_BASE__INST4_SEG2 0
> +#define CLK_BASE__INST4_SEG3 0
> +#define CLK_BASE__INST4_SEG4 0
> +
> +#define FUSE_BASE__INST0_SEG0 0x00017400
> +#define FUSE_BASE__INST0_SEG1 0
> +#define FUSE_BASE__INST0_SEG2 0
> +#define FUSE_BASE__INST0_SEG3 0
> +#define FUSE_BASE__INST0_SEG4 0
> +
> +#define FUSE_BASE__INST1_SEG0 0
> +#define FUSE_BASE__INST1_SEG1 0
> +#define FUSE_BASE__INST1_SEG2 0
> +#define FUSE_BASE__INST1_SEG3 0
> +#define FUSE_BASE__INST1_SEG4 0
> +
> +#define FUSE_BASE__INST2_SEG0 0
> +#define FUSE_BASE__INST2_SEG1 0
> +#define FUSE_BASE__INST2_SEG2 0
> +#define FUSE_BASE__INST2_SEG3 0
> +#define FUSE_BASE__INST2_SEG4 0
> +
> +#define FUSE_BASE__INST3_SEG0 0
> +#define FUSE_BASE__INST3_SEG1 0
> +#define FUSE_BASE__INST3_SEG2 0
> +#define FUSE_BASE__INST3_SEG3 0
> +#define FUSE_BASE__INST3_SEG4 0
> +
> +#define FUSE_BASE__INST4_SEG0 0
> +#define FUSE_BASE__INST4_SEG1 0
> +#define FUSE_BASE__INST4_SEG2 0
> +#define FUSE_BASE__INST4_SEG3 0
> +#define FUSE_BASE__INST4_SEG4 0
> +#endif
> +
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-01-22 12:20 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-01-22 12:15 [PATCH 1/5] drm/amdgpu: split soc15ip header into ip and ip_offset header Hawking Zhang
[not found] ` <1516623354-24912-1-git-send-email-Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
2018-01-22 12:15 ` [PATCH 2/5] drm/amdgpu: include new ip and ip offset headers Hawking Zhang
2018-01-22 12:15 ` [PATCH 3/5] drm/amd/pp: " Hawking Zhang
2018-01-22 12:15 ` [PATCH 4/5] drm/amd/dc: include new ip and ip_offset headers Hawking Zhang
2018-01-22 12:15 ` [PATCH 5/5] drm/amdgpu: retire soc15ip.h Hawking Zhang
2018-01-22 12:20 ` [PATCH 1/5] drm/amdgpu: split soc15ip header into ip and ip_offset header Christian König
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