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From: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 01/13] drm/amd/powerplay: correct vega12 bootup values settings
Date: Tue, 19 Jun 2018 15:38:53 +0800	[thread overview]
Message-ID: <1529393945-16629-1-git-send-email-evan.quan@amd.com> (raw)

The vbios firmware structure changed between v3_1 and v3_2. So,
the code to setup bootup values needs different paths based
on header version.

Change-Id: I15140c4d80a91022f66a5052f4b9303fdab4ed9d
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 94 +++++++++++++++++++---
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h |  3 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c |  3 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h |  3 +
 4 files changed, 91 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
index 5325661..aa2faff 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
@@ -512,14 +512,82 @@ int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKI
 	return 0;
 }
 
+static void pp_atomfwctrl_copy_vbios_bootup_values_3_2(struct pp_hwmgr *hwmgr,
+			struct pp_atomfwctrl_bios_boot_up_values *boot_values,
+			struct atom_firmware_info_v3_2 *fw_info)
+{
+	uint32_t frequency = 0;
+
+	boot_values->ulRevision = fw_info->firmware_revision;
+	boot_values->ulGfxClk   = fw_info->bootup_sclk_in10khz;
+	boot_values->ulUClk     = fw_info->bootup_mclk_in10khz;
+	boot_values->usVddc     = fw_info->bootup_vddc_mv;
+	boot_values->usVddci    = fw_info->bootup_vddci_mv;
+	boot_values->usMvddc    = fw_info->bootup_mvddc_mv;
+	boot_values->usVddGfx   = fw_info->bootup_vddgfx_mv;
+	boot_values->ucCoolingID = fw_info->coolingsolution_id;
+	boot_values->ulSocClk   = 0;
+	boot_values->ulDCEFClk   = 0;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, &frequency))
+		boot_values->ulSocClk   = frequency;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCEFCLK_ID, &frequency))
+		boot_values->ulDCEFClk  = frequency;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_ECLK_ID, &frequency))
+		boot_values->ulEClk     = frequency;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_VCLK_ID, &frequency))
+		boot_values->ulVClk     = frequency;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCLK_ID, &frequency))
+		boot_values->ulDClk     = frequency;
+}
+
+static void pp_atomfwctrl_copy_vbios_bootup_values_3_1(struct pp_hwmgr *hwmgr,
+			struct pp_atomfwctrl_bios_boot_up_values *boot_values,
+			struct atom_firmware_info_v3_1 *fw_info)
+{
+	uint32_t frequency = 0;
+
+	boot_values->ulRevision = fw_info->firmware_revision;
+	boot_values->ulGfxClk   = fw_info->bootup_sclk_in10khz;
+	boot_values->ulUClk     = fw_info->bootup_mclk_in10khz;
+	boot_values->usVddc     = fw_info->bootup_vddc_mv;
+	boot_values->usVddci    = fw_info->bootup_vddci_mv;
+	boot_values->usMvddc    = fw_info->bootup_mvddc_mv;
+	boot_values->usVddGfx   = fw_info->bootup_vddgfx_mv;
+	boot_values->ucCoolingID = fw_info->coolingsolution_id;
+	boot_values->ulSocClk   = 0;
+	boot_values->ulDCEFClk   = 0;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency))
+		boot_values->ulSocClk   = frequency;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency))
+		boot_values->ulDCEFClk  = frequency;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_ECLK_ID, &frequency))
+		boot_values->ulEClk     = frequency;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_VCLK_ID, &frequency))
+		boot_values->ulVClk     = frequency;
+
+	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCLK_ID, &frequency))
+		boot_values->ulDClk     = frequency;
+}
+
 int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
 			struct pp_atomfwctrl_bios_boot_up_values *boot_values)
 {
-	struct atom_firmware_info_v3_1 *info = NULL;
+	struct atom_firmware_info_v3_2 *fwinfo_3_2;
+	struct atom_firmware_info_v3_1 *fwinfo_3_1;
+	struct atom_common_table_header *info = NULL;
 	uint16_t ix;
 
 	ix = GetIndexIntoMasterDataTable(firmwareinfo);
-	info = (struct atom_firmware_info_v3_1 *)
+	info = (struct atom_common_table_header *)
 		smu_atom_get_data_table(hwmgr->adev,
 				ix, NULL, NULL, NULL);
 
@@ -528,16 +596,18 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
 		return -EINVAL;
 	}
 
-	boot_values->ulRevision = info->firmware_revision;
-	boot_values->ulGfxClk   = info->bootup_sclk_in10khz;
-	boot_values->ulUClk     = info->bootup_mclk_in10khz;
-	boot_values->usVddc     = info->bootup_vddc_mv;
-	boot_values->usVddci    = info->bootup_vddci_mv;
-	boot_values->usMvddc    = info->bootup_mvddc_mv;
-	boot_values->usVddGfx   = info->bootup_vddgfx_mv;
-	boot_values->ucCoolingID = info->coolingsolution_id;
-	boot_values->ulSocClk   = 0;
-	boot_values->ulDCEFClk   = 0;
+	if ((info->format_revision == 3) && (info->content_revision == 2)) {
+		fwinfo_3_2 = (struct atom_firmware_info_v3_2 *)info;
+		pp_atomfwctrl_copy_vbios_bootup_values_3_2(hwmgr,
+				boot_values, fwinfo_3_2);
+	} else if ((info->format_revision == 3) && (info->content_revision == 1)) {
+		fwinfo_3_1 = (struct atom_firmware_info_v3_1 *)info;
+		pp_atomfwctrl_copy_vbios_bootup_values_3_1(hwmgr,
+				boot_values, fwinfo_3_1);
+	} else {
+		pr_info("Fw info table revision does not match!");
+		return -EINVAL;
+	}
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
index fe10aa4..745bd38 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
@@ -136,6 +136,9 @@ struct pp_atomfwctrl_bios_boot_up_values {
 	uint32_t   ulUClk;
 	uint32_t   ulSocClk;
 	uint32_t   ulDCEFClk;
+	uint32_t   ulEClk;
+	uint32_t   ulVClk;
+	uint32_t   ulDClk;
 	uint16_t   usVddc;
 	uint16_t   usVddci;
 	uint16_t   usMvddc;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 782e209..e81661cc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -803,6 +803,9 @@ static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
 		data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
 		data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 		data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
+		data->vbios_boot_state.eclock = boot_up_values.ulEClk;
+		data->vbios_boot_state.dclock = boot_up_values.ulDClk;
+		data->vbios_boot_state.vclock = boot_up_values.ulVClk;
 		smum_send_msg_to_smc_with_parameter(hwmgr,
 				PPSMC_MSG_SetMinDeepSleepDcefclk,
 			(uint32_t)(data->vbios_boot_state.dcef_clock / 100));
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
index e81ded1..49b38df 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
@@ -167,6 +167,9 @@ struct vega12_vbios_boot_state {
 	uint32_t    mem_clock;
 	uint32_t    soc_clock;
 	uint32_t    dcef_clock;
+	uint32_t    eclock;
+	uint32_t    dclock;
+	uint32_t    vclock;
 };
 
 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
-- 
2.7.4

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             reply	other threads:[~2018-06-19  7:38 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-19  7:38 Evan Quan [this message]
     [not found] ` <1529393945-16629-1-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19  7:38   ` [PATCH 02/13] drm/amd/powerplay: smc_dpm_info structure change Evan Quan
     [not found]     ` <1529393945-16629-2-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 14:57       ` Alex Deucher
2018-06-19  7:38   ` [PATCH 03/13] drm/amd/powerplay: drop the acg fix Evan Quan
     [not found]     ` <1529393945-16629-3-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 14:57       ` Alex Deucher
2018-06-19  7:38   ` [PATCH 04/13] drm/amd/powerplay: revise default dpm tables setup Evan Quan
     [not found]     ` <1529393945-16629-4-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 14:59       ` Alex Deucher
2018-06-19  7:38   ` [PATCH 05/13] drm/amd/powerplay: retrieve all clock ranges on startup Evan Quan
     [not found]     ` <1529393945-16629-5-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 15:03       ` Alex Deucher
2018-06-19  7:38   ` [PATCH 06/13] drm/amd/powerplay: revise clock level setup Evan Quan
     [not found]     ` <1529393945-16629-6-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 15:07       ` Alex Deucher
2018-06-19  7:38   ` [PATCH 07/13] drm/amd/powerplay: initialize uvd/vce powergate status Evan Quan
     [not found]     ` <1529393945-16629-7-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 15:10       ` Alex Deucher
     [not found]         ` <CADnq5_NSa8Bh_ffmz12Zu2XH4b3GawMdz_6vTF5NbFp_pLaLYA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-06-20  6:34           ` Quan, Evan
2018-06-19  7:39   ` [PATCH 08/13] drm/amd/powerplay: correct smc display config setting Evan Quan
     [not found]     ` <1529393945-16629-8-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 15:13       ` Alex Deucher
2018-06-19  7:39   ` [PATCH 09/13] drm/amd/powerplay: correct vega12 max num of dpm level Evan Quan
     [not found]     ` <1529393945-16629-9-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 15:13       ` Alex Deucher
2018-06-19  7:39   ` [PATCH 10/13] drm/amd/powerplay: apply clocks adjust rules on power state change Evan Quan
     [not found]     ` <1529393945-16629-10-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 15:16       ` Alex Deucher
     [not found]         ` <CADnq5_PqQ0aRcA=8iUq9qLow+W6rwpXhsj2GKRskn3xjwEbicw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-06-19 15:43           ` Zhu, Rex
     [not found]             ` <CY4PR12MB1687A705AE09BB6492A5C156FB700-rpdhrqHFk06Y0SjTqZDccQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-06-20  6:22               ` Quan, Evan
2018-06-20  6:17           ` Quan, Evan
     [not found]             ` <SN6PR12MB26567D8241FEECAF286CEBA8E4770-kxOKjb6HO/FeL/N0e1LXkAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-06-20 14:05               ` Deucher, Alexander
2018-06-19  7:39   ` [PATCH 11/13] drm/amd/powerplay: set vega12 pre display configurations Evan Quan
     [not found]     ` <1529393945-16629-11-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 15:18       ` Alex Deucher
2018-06-19  7:39   ` [PATCH 12/13] drm/amd/powerplay: correct vega12 thermal support as true Evan Quan
     [not found]     ` <1529393945-16629-12-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 15:18       ` Alex Deucher
2018-06-19  7:39   ` [PATCH 13/13] drm/amd/powerplay: cosmetic fix Evan Quan
     [not found]     ` <1529393945-16629-13-git-send-email-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-06-19 15:19       ` Alex Deucher

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