* [PATCH 2/2] drm/amd/pp: Unify the shared struct between pp and display
[not found] ` <1529474320-1048-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-06-20 5:58 ` Rex Zhu
2018-06-20 16:12 ` [PATCH 1/2] drm/amd/pp: Remove duplicate code in vega12_hwmgr.c Alex Deucher
1 sibling, 0 replies; 3+ messages in thread
From: Rex Zhu @ 2018-06-20 5:58 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
1. move shared struct dm_pp_wm_sets_with_clock_ranges_soc15 to
dm_pp_interface.h.
2. delete the same struct define in powerplay, use the struct
display defined.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 49 +-------------
drivers/gpu/drm/amd/include/dm_pp_interface.h | 79 +++++++++++++---------
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 28 ++++----
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 2 +-
7 files changed, 65 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index 2b83f92..7a187f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -28,6 +28,7 @@
#include "os_types.h"
#include "dc_types.h"
+#include "dm_pp_interface.h"
struct pp_smu_funcs_rv;
@@ -123,54 +124,6 @@ struct dm_pp_single_disp_config {
struct dc_link_settings link_settings; /* DP only */
};
-#define MAX_WM_SETS 4
-
-enum dm_pp_wm_set_id {
- WM_SET_A = 0,
- WM_SET_B,
- WM_SET_C,
- WM_SET_D,
- WM_SET_INVALID = 0xffff,
-};
-
-struct dm_pp_clock_range_for_wm_set {
- enum dm_pp_wm_set_id wm_set_id;
- uint32_t wm_min_eng_clk_in_khz;
- uint32_t wm_max_eng_clk_in_khz;
- uint32_t wm_min_mem_clk_in_khz;
- uint32_t wm_max_mem_clk_in_khz;
-};
-
-struct dm_pp_wm_sets_with_clock_ranges {
- uint32_t num_wm_sets;
- struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS];
-};
-
-struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
- enum dm_pp_wm_set_id wm_set_id;
- uint32_t wm_min_dcfclk_clk_in_khz;
- uint32_t wm_max_dcfclk_clk_in_khz;
- uint32_t wm_min_mem_clk_in_khz;
- uint32_t wm_max_mem_clk_in_khz;
-};
-
-struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
- enum dm_pp_wm_set_id wm_set_id;
- uint32_t wm_min_socclk_clk_in_khz;
- uint32_t wm_max_socclk_clk_in_khz;
- uint32_t wm_min_mem_clk_in_khz;
- uint32_t wm_max_mem_clk_in_khz;
-};
-
-struct dm_pp_wm_sets_with_clock_ranges_soc15 {
- uint32_t num_wm_dmif_sets;
- uint32_t num_wm_mcif_sets;
- struct dm_pp_clock_range_for_dmif_wm_set_soc15
- wm_dmif_clocks_ranges[MAX_WM_SETS];
- struct dm_pp_clock_range_for_mcif_wm_set_soc15
- wm_mcif_clocks_ranges[MAX_WM_SETS];
-};
-
#define MAX_DISPLAY_CONFIGS 6
struct dm_pp_display_configuration {
diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index 7852952..e0089f1 100644
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -189,39 +189,52 @@ struct pp_display_clock_request {
uint32_t clock_freq_in_khz;
};
-#define PP_MAX_WM_SETS 4
-
-enum pp_wm_set_id {
- DC_WM_SET_A = 0,
- DC_WM_SET_B,
- DC_WM_SET_C,
- DC_WM_SET_D,
- DC_WM_SET_INVALID = 0xffff,
-};
-
-struct pp_wm_set_with_dmif_clock_range_soc15 {
- enum pp_wm_set_id wm_set_id;
- uint32_t wm_min_dcefclk_in_khz;
- uint32_t wm_max_dcefclk_in_khz;
- uint32_t wm_min_memclk_in_khz;
- uint32_t wm_max_memclk_in_khz;
-};
-
-struct pp_wm_set_with_mcif_clock_range_soc15 {
- enum pp_wm_set_id wm_set_id;
- uint32_t wm_min_socclk_in_khz;
- uint32_t wm_max_socclk_in_khz;
- uint32_t wm_min_memclk_in_khz;
- uint32_t wm_max_memclk_in_khz;
-};
-
-struct pp_wm_sets_with_clock_ranges_soc15 {
- uint32_t num_wm_sets_dmif;
- uint32_t num_wm_sets_mcif;
- struct pp_wm_set_with_dmif_clock_range_soc15
- wm_sets_dmif[PP_MAX_WM_SETS];
- struct pp_wm_set_with_mcif_clock_range_soc15
- wm_sets_mcif[PP_MAX_WM_SETS];
+#define MAX_WM_SETS 4
+
+enum dm_pp_wm_set_id {
+ WM_SET_A = 0,
+ WM_SET_B,
+ WM_SET_C,
+ WM_SET_D,
+ WM_SET_INVALID = 0xffff,
+};
+
+struct dm_pp_clock_range_for_wm_set {
+ enum dm_pp_wm_set_id wm_set_id;
+ uint32_t wm_min_eng_clk_in_khz;
+ uint32_t wm_max_eng_clk_in_khz;
+ uint32_t wm_min_mem_clk_in_khz;
+ uint32_t wm_max_mem_clk_in_khz;
+};
+
+struct dm_pp_wm_sets_with_clock_ranges {
+ uint32_t num_wm_sets;
+ struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS];
+};
+
+struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
+ enum dm_pp_wm_set_id wm_set_id;
+ uint32_t wm_min_dcfclk_clk_in_khz;
+ uint32_t wm_max_dcfclk_clk_in_khz;
+ uint32_t wm_min_mem_clk_in_khz;
+ uint32_t wm_max_mem_clk_in_khz;
+};
+
+struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
+ enum dm_pp_wm_set_id wm_set_id;
+ uint32_t wm_min_socclk_clk_in_khz;
+ uint32_t wm_max_socclk_clk_in_khz;
+ uint32_t wm_min_mem_clk_in_khz;
+ uint32_t wm_max_mem_clk_in_khz;
+};
+
+struct dm_pp_wm_sets_with_clock_ranges_soc15 {
+ uint32_t num_wm_dmif_sets;
+ uint32_t num_wm_mcif_sets;
+ struct dm_pp_clock_range_for_dmif_wm_set_soc15
+ wm_dmif_clocks_ranges[MAX_WM_SETS];
+ struct dm_pp_clock_range_for_mcif_wm_set_soc15
+ wm_mcif_clocks_ranges[MAX_WM_SETS];
};
#endif /* _DM_PP_INTERFACE_ */
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 4ca8033..48ae990 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1134,7 +1134,7 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
void *clock_ranges)
{
struct smu10_hwmgr *data = hwmgr->backend;
- struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
Watermarks_t *table = &(data->water_marks_table);
int result = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
index 93a3d02..5dd375d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -652,7 +652,7 @@ int smu_get_voltage_dependency_table_ppt_v1(
}
int smu_set_watermarks_for_clocks_ranges(void *wt_table,
- struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
{
uint32_t i;
struct watermarks *table = wt_table;
@@ -660,49 +660,49 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
if (!table || !wm_with_clock_ranges)
return -EINVAL;
- if (wm_with_clock_ranges->num_wm_sets_dmif > 4 || wm_with_clock_ranges->num_wm_sets_mcif > 4)
+ if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || wm_with_clock_ranges->num_wm_mcif_sets > 4)
return -EINVAL;
- for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
+ for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
table->WatermarkRow[1][i].MinClock =
cpu_to_le16((uint16_t)
- (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
+ (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
100);
table->WatermarkRow[1][i].MaxClock =
cpu_to_le16((uint16_t)
- (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
+ (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
100);
table->WatermarkRow[1][i].MinUclk =
cpu_to_le16((uint16_t)
- (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
+ (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
100);
table->WatermarkRow[1][i].MaxUclk =
cpu_to_le16((uint16_t)
- (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
+ (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
100);
table->WatermarkRow[1][i].WmSetting = (uint8_t)
- wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
+ wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
}
- for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
+ for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
table->WatermarkRow[0][i].MinClock =
cpu_to_le16((uint16_t)
- (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
+ (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /
100);
table->WatermarkRow[0][i].MaxClock =
cpu_to_le16((uint16_t)
- (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
+ (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /
100);
table->WatermarkRow[0][i].MinUclk =
cpu_to_le16((uint16_t)
- (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
+ (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
100);
table->WatermarkRow[0][i].MaxUclk =
cpu_to_le16((uint16_t)
- (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
+ (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
100);
table->WatermarkRow[0][i].WmSetting = (uint8_t)
- wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
+ wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
}
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
index 916cc01..5454289 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
@@ -107,7 +107,7 @@ int smu_get_voltage_dependency_table_ppt_v1(
struct phm_ppt_v1_clock_voltage_dependency_table *dep_table);
int smu_set_watermarks_for_clocks_ranges(void *wt_table,
- struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 8554ede..c03200c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4198,7 +4198,7 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
void *clock_range)
{
struct vega10_hwmgr *data = hwmgr->backend;
- struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
Watermarks_t *table = &(data->smc_state_table.water_marks_table);
int result = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 81b20d1..731b33a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1717,7 +1717,7 @@ static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
{
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
Watermarks_t *table = &(data->smc_state_table.water_marks_table);
- struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
int result = 0;
if (!data->registry_data.disable_water_mark &&
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 1/2] drm/amd/pp: Remove duplicate code in vega12_hwmgr.c
[not found] ` <1529474320-1048-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-20 5:58 ` [PATCH 2/2] drm/amd/pp: Unify the shared struct between pp and display Rex Zhu
@ 2018-06-20 16:12 ` Alex Deucher
1 sibling, 0 replies; 3+ messages in thread
From: Alex Deucher @ 2018-06-20 16:12 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Wed, Jun 20, 2018 at 1:58 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> use smu_helper function smu_set_watermarks_for_clocks_ranges
> in vega12_set_watermarks_for_clocks_ranges.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 43 +---------------------
> 1 file changed, 1 insertion(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index bcb64cd..81b20d1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1719,52 +1719,11 @@ static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> Watermarks_t *table = &(data->smc_state_table.water_marks_table);
> struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
> int result = 0;
> - uint32_t i;
>
> if (!data->registry_data.disable_water_mark &&
> data->smu_features[GNLD_DPM_DCEFCLK].supported &&
> data->smu_features[GNLD_DPM_SOCCLK].supported) {
> - for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
> - table->WatermarkRow[WM_DCEFCLK][i].MinClock =
> - cpu_to_le16((uint16_t)
> - (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
> - 100);
> - table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
> - cpu_to_le16((uint16_t)
> - (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
> - 100);
> - table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
> - cpu_to_le16((uint16_t)
> - (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
> - 100);
> - table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
> - cpu_to_le16((uint16_t)
> - (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
> - 100);
> - table->WatermarkRow[WM_DCEFCLK][i].WmSetting = (uint8_t)
> - wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
> - }
> -
> - for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
> - table->WatermarkRow[WM_SOCCLK][i].MinClock =
> - cpu_to_le16((uint16_t)
> - (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
> - 100);
> - table->WatermarkRow[WM_SOCCLK][i].MaxClock =
> - cpu_to_le16((uint16_t)
> - (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
> - 100);
> - table->WatermarkRow[WM_SOCCLK][i].MinUclk =
> - cpu_to_le16((uint16_t)
> - (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
> - 100);
> - table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
> - cpu_to_le16((uint16_t)
> - (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
> - 100);
> - table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
> - wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
> - }
> + smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
> data->water_marks_bitmap |= WaterMarksExist;
> data->water_marks_bitmap &= ~WaterMarksLoaded;
> }
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 3+ messages in thread