[PATCH] drm/amd/powerplay: initialize uvd/vce powergate status v2

[PATCH] drm/amd/powerplay: initialize uvd/vce powergate status v2

[Evan Quan]

On UVD/VCE dpm disabled, the powergate status should be
set as true. So that we will not try to gate them(enable dpm
for now).

v2: added check for uvd/vce powergate status before gating

Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 45c8f2d..28b172e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -777,6 +777,21 @@ static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
+{
+	struct vega12_hwmgr *data =
+			(struct vega12_hwmgr *)(hwmgr->backend);
+
+	data->uvd_power_gated = true;
+	data->vce_power_gated = true;
+
+	if (data->smu_features[GNLD_DPM_UVD].enabled)
+		data->uvd_power_gated = false;
+
+	if (data->smu_features[GNLD_DPM_VCE].enabled)
+		data->vce_power_gated = false;
+}
+
 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 {
 	struct vega12_hwmgr *data =
@@ -801,6 +816,8 @@ static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 		}
 	}
 
+	vega12_init_powergate_state(hwmgr);
+
 	return 0;
 }
 
@@ -1985,6 +2002,9 @@ static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 {
 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 
+	if (data->vce_power_gated == bgate)
+		return 0;
+
 	data->vce_power_gated = bgate;
 	vega12_enable_disable_vce_dpm(hwmgr, !bgate);
 }
@@ -1993,6 +2013,9 @@ static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 {
 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 
+	if (data->uvd_power_gated == bgate)
+		return 0;
+
 	data->uvd_power_gated = bgate;
 	vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
 }
-- 
2.7.4

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[PATCH 1/2] drm/amd/powerplay: correct smc display config for multi monitor

[Evan Quan]

Need to take into account multi-head with synced displays.

Change-Id: I2ad53f47ce1dff0fa8f6ae944986567443cca04e
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 28b172e..df91dde 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1401,7 +1401,8 @@ static int vega12_notify_smc_display_config_after_ps_adjustment(
 	struct pp_display_clock_request clock_req;
 	uint32_t clk_request;
 
-	if (hwmgr->display_config->num_display > 1)
+	if ((hwmgr->display_config->num_display > 1) &&
+		!hwmgr->display_config->multi_monitor_in_sync)
 		vega12_notify_smc_display_change(hwmgr, false);
 	else
 		vega12_notify_smc_display_change(hwmgr, true);
-- 
2.7.4

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[PATCH 2/2] drm/amd/powerplay: drop unnecessary uclk hard min setting

[Evan Quan]

We don't need to set uclk hard min here because this will
be set with other clocks on power state change.

Change-Id: I05d28f881f5cff5108b9dea36e95a917d58c123a
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index df91dde..8e2efa6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1399,7 +1399,6 @@ static int vega12_notify_smc_display_config_after_ps_adjustment(
 			(struct vega12_hwmgr *)(hwmgr->backend);
 	struct PP_Clocks min_clocks = {0};
 	struct pp_display_clock_request clock_req;
-	uint32_t clk_request;
 
 	if ((hwmgr->display_config->num_display > 1) &&
 		!hwmgr->display_config->multi_monitor_in_sync)
@@ -1427,15 +1426,6 @@ static int vega12_notify_smc_display_config_after_ps_adjustment(
 		}
 	}
 
-	if (data->smu_features[GNLD_DPM_UCLK].enabled) {
-		clk_request = (PPCLK_UCLK << 16) | (min_clocks.memoryClock) / 100;
-		PP_ASSERT_WITH_CODE(
-			smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetHardMinByFreq, clk_request) == 0,
-			"[PhwVega12_NotifySMCDisplayConfigAfterPowerStateAdjustment] Attempt to set UCLK HardMin Failed!",
-			return -1);
-		data->dpm_table.mem_table.dpm_state.hard_min_level = min_clocks.memoryClock;
-	}
-
 	return 0;
 }
 
-- 
2.7.4

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RE: [PATCH] drm/amd/powerplay: initialize uvd/vce powergate status v2

[Quan, Evan]

> that we will not try to gate them(enable dpm for now).
Sorry, there seems a typo in the description(enable -> disable).
I will send out another patch with this typo addressed.

Regards,
Evan
> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Wednesday, June 20, 2018 2:09 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH] drm/amd/powerplay: initialize uvd/vce powergate status
> v2
> 
> On UVD/VCE dpm disabled, the powergate status should be set as true. So
> that we will not try to gate them(enable dpm for now).
> 
> v2: added check for uvd/vce powergate status before gating
> 
> Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 23
> ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 45c8f2d..28b172e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -777,6 +777,21 @@ static int vega12_set_allowed_featuresmask(struct
> pp_hwmgr *hwmgr)
>  	return 0;
>  }
> 
> +static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) {
> +	struct vega12_hwmgr *data =
> +			(struct vega12_hwmgr *)(hwmgr->backend);
> +
> +	data->uvd_power_gated = true;
> +	data->vce_power_gated = true;
> +
> +	if (data->smu_features[GNLD_DPM_UVD].enabled)
> +		data->uvd_power_gated = false;
> +
> +	if (data->smu_features[GNLD_DPM_VCE].enabled)
> +		data->vce_power_gated = false;
> +}
> +
>  static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)  {
>  	struct vega12_hwmgr *data =
> @@ -801,6 +816,8 @@ static int vega12_enable_all_smu_features(struct
> pp_hwmgr *hwmgr)
>  		}
>  	}
> 
> +	vega12_init_powergate_state(hwmgr);
> +
>  	return 0;
>  }
> 
> @@ -1985,6 +2002,9 @@ static void vega12_power_gate_vce(struct
> pp_hwmgr *hwmgr, bool bgate)  {
>  	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr-
> >backend);
> 
> +	if (data->vce_power_gated == bgate)
> +		return 0;
> +
>  	data->vce_power_gated = bgate;
>  	vega12_enable_disable_vce_dpm(hwmgr, !bgate);  } @@ -1993,6
> +2013,9 @@ static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr,
> bool bgate)  {
>  	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr-
> >backend);
> 
> +	if (data->uvd_power_gated == bgate)
> +		return 0;
> +
>  	data->uvd_power_gated = bgate;
>  	vega12_enable_disable_uvd_dpm(hwmgr, !bgate);  }
> --
> 2.7.4

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