From: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 8/9] drm/amdgpu: Add a argument in emit_cntxcntl interface
Date: Thu, 6 Dec 2018 20:14:06 +0800 [thread overview]
Message-ID: <1544098447-21648-7-git-send-email-Rex.Zhu@amd.com> (raw)
In-Reply-To: <1544098447-21648-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
add a point of struct amdgpu_job in emit_cntxcntl
interface in order to get the csa mc address per ctx
when emit ce metadata in baremetal.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 20 ++++++++++++--------
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 ++++++++++------
6 files changed, 31 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index c48207b3..5329044 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -208,7 +208,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
status |= AMDGPU_HAVE_CTX_SWITCH;
status |= job->preamble_status;
- amdgpu_ring_emit_cntxcntl(ring, status);
+ amdgpu_ring_emit_cntxcntl(ring, job, status);
}
for (i = 0; i < num_ibs; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 0beb01f..7aa46cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -157,7 +157,7 @@ struct amdgpu_ring_funcs {
void (*begin_use)(struct amdgpu_ring *ring);
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
- void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
+ void (*emit_cntxcntl) (struct amdgpu_ring *ring, struct amdgpu_job *job, uint32_t flags);
void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
@@ -236,7 +236,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
-#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
+#define amdgpu_ring_emit_cntxcntl(r, job, d) (r)->funcs->emit_cntxcntl((r), (job), (d))
#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 5b25c26..976f94a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2976,7 +2976,9 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
return clock;
}
-static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ uint32_t flags)
{
if (flags & AMDGPU_HAVE_CTX_SWITCH)
gfx_v6_0_ring_emit_vgt_flush(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 243b8c5..ab62117 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2275,7 +2275,9 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, control);
}
-static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ uint32_t flags)
{
uint32_t dw2 = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index d529cef..3ac2d8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -723,8 +723,8 @@ enum {
static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
-static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
-static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
+static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring, struct amdgpu_job *job);
+static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring, struct amdgpu_job *job);
static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
{
@@ -6127,7 +6127,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
control |= INDIRECT_BUFFER_PRE_ENB(1);
if (!(ib->flags & AMDGPU_IB_FLAG_CE))
- gfx_v8_0_ring_emit_de_meta(ring);
+ gfx_v8_0_ring_emit_de_meta(ring, job);
}
amdgpu_ring_write(ring, header);
@@ -6386,12 +6386,14 @@ static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, 0);
}
-static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ uint32_t flags)
{
uint32_t dw2 = 0;
if (amdgpu_sriov_vf(ring->adev))
- gfx_v8_0_ring_emit_ce_meta(ring);
+ gfx_v8_0_ring_emit_ce_meta(ring, job);
dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
if (flags & AMDGPU_HAVE_CTX_SWITCH) {
@@ -7182,7 +7184,8 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
.funcs = &gfx_v8_0_ip_funcs,
};
-static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
+static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring,
+ struct amdgpu_job *job)
{
uint64_t ce_payload_addr;
int cnt_ce;
@@ -7196,7 +7199,7 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
} else {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
+ ce_payload_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job) +
offsetof(struct vi_gfx_meta_data, ce_payload);
cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
}
@@ -7211,7 +7214,8 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
}
-static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
+static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring,
+ struct amdgpu_job *job)
{
uint64_t de_payload_addr, gds_addr, csa_addr;
int cnt_de;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 81c1578..dd2d535 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -297,7 +297,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
struct amdgpu_cu_info *cu_info);
static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
-static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
+static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, struct amdgpu_job *job);
static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
{
@@ -4067,7 +4067,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
control |= INDIRECT_BUFFER_PRE_ENB(1);
if (!(ib->flags & AMDGPU_IB_FLAG_CE))
- gfx_v9_0_ring_emit_de_meta(ring);
+ gfx_v9_0_ring_emit_de_meta(ring, job);
}
amdgpu_ring_write(ring, header);
@@ -4320,7 +4320,8 @@ static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, 0);
}
-static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
+static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring,
+ struct amdgpu_job *job)
{
struct v9_ce_ib_state ce_payload = {0};
uint64_t csa_addr;
@@ -4339,7 +4340,8 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
}
-static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
+static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring,
+ struct amdgpu_job *job)
{
struct v9_de_ib_state de_payload = {0};
uint64_t csa_addr, gds_addr;
@@ -4367,12 +4369,14 @@ static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
}
-static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+ struct amdgpu_job *job,
+ uint32_t flags)
{
uint32_t dw2 = 0;
if (amdgpu_sriov_vf(ring->adev))
- gfx_v9_0_ring_emit_ce_meta(ring);
+ gfx_v9_0_ring_emit_ce_meta(ring, job);
gfx_v9_0_ring_emit_tmz(ring, true);
--
1.9.1
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next prev parent reply other threads:[~2018-12-06 12:14 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-06 12:14 [PATCH 2/9] drm/amdgpu: Refine function amdgpu_csa_vaddr Rex Zhu
[not found] ` <1544098447-21648-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:14 ` [PATCH 3/9] drm/amdgpu: Use dynamical reserved vm size Rex Zhu
[not found] ` <1544098447-21648-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:32 ` Christian König
[not found] ` <ca2a8aaa-3a0b-8c8e-1d5a-ec2e12c70434-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-12-06 14:13 ` Zhu, Rex
2018-12-06 12:14 ` [PATCH 4/9] drm/amdgpu: Add a bitmask in amdgpu_ctx_mgr Rex Zhu
[not found] ` <1544098447-21648-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:33 ` Christian König
[not found] ` <ab6bcc8e-8f88-5cb9-c2e8-5322a907bdac-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-12-06 14:48 ` Zhu, Rex
[not found] ` <BYAPR12MB2775D509B792B3D869B1BC8EFBA90-ZGDeBxoHBPmJeBUhB162ZQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-12-06 14:56 ` Koenig, Christian
2018-12-06 12:14 ` [PATCH 5/9] drm/amdgpu: Delay map sriov csa addr to ctx init Rex Zhu
[not found] ` <1544098447-21648-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:38 ` Christian König
2018-12-06 12:14 ` [PATCH 6/9] drm/amdgpu: Create csa per ctx Rex Zhu
[not found] ` <1544098447-21648-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:46 ` Christian König
2018-12-06 12:14 ` [PATCH 7/9] drm/amdgpu: Add csa mc address into job structure Rex Zhu
[not found] ` <1544098447-21648-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:39 ` Christian König
2018-12-06 12:14 ` Rex Zhu [this message]
[not found] ` <1544098447-21648-7-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:40 ` [PATCH 8/9] drm/amdgpu: Add a argument in emit_cntxcntl interface Christian König
2018-12-06 12:14 ` [PATCH 9/9] drm/amdgpu: Remove sriov check when insert ce/de meta_data Rex Zhu
[not found] ` <1544098447-21648-8-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:42 ` Christian König
2018-12-06 12:28 ` [PATCH 2/9] drm/amdgpu: Refine function amdgpu_csa_vaddr Christian König
-- strict thread matches above, loose matches on Subject: below --
2018-12-06 11:32 [PATCH 1/9] drm/amdgpu: Limit vm max ctx number to 4096 Rex Zhu
[not found] ` <1544095957-21101-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 11:32 ` [PATCH 8/9] drm/amdgpu: Add a argument in emit_cntxcntl interface Rex Zhu
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