From: "Christian König" <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 2/9] drm/amdgpu: Refine function amdgpu_csa_vaddr
Date: Thu, 6 Dec 2018 13:28:02 +0100 [thread overview]
Message-ID: <38bd4a0b-dd41-d897-9ece-48327aa3e00c@gmail.com> (raw)
In-Reply-To: <1544098447-21648-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Am 06.12.18 um 13:14 schrieb Rex Zhu:
> on baremetal, driver create csa per ctx.
> So add a function argument: ctx_id to
> get csa gpu addr.
> In Sriov, driver create csa per process,
> so ctx id always 1.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 5 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> 5 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
> index 0c590dd..44b046f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
> @@ -24,11 +24,12 @@
>
> #include "amdgpu.h"
>
> -uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
> +uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id)
> {
> uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
>
> - addr -= AMDGPU_VA_RESERVED_SIZE;
> + addr -= AMDGPU_VA_RESERVED_SIZE * id;
> +
It might be better to add the SRIOV handling here instead. E.g. like the
following:
if (amdgpu_sriov_vf(adev))
addr -= AMDGPU_VA_RESERVED_SIZE;
else
addr -= AMDGPU_CSA_SIZE * id;
Apart from that looks good to me, but might be better to re-order the
patches.
Regards,
Christian.
> addr = amdgpu_gmc_sign_extend(addr);
>
> return addr;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
> index 524b443..aaf1fba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
> @@ -28,7 +28,7 @@
> #define AMDGPU_CSA_SIZE (128 * 1024)
>
> uint32_t amdgpu_get_total_csa_size(struct amdgpu_device *adev);
> -uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev);
> +uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev, uint32_t id);
> int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo **bo,
> u32 domain, uint32_t size);
> int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 08d04f6..f736bda 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -977,9 +977,9 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
> goto error_vm;
> }
>
> - if (amdgpu_sriov_vf(adev)) {
> - uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
>
> + if (amdgpu_sriov_vf(adev)) {
> + uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) & AMDGPU_GMC_HOLE_MASK;
> r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
> &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
> if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index bdae563..d529cef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -7192,11 +7192,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
> } ce_payload = {};
>
> if (ring->adev->virt.chained_ib_support) {
> - ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
> + ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
> offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
> cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
> } else {
> - ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
> + ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
> offsetof(struct vi_gfx_meta_data, ce_payload);
> cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
> }
> @@ -7220,7 +7220,7 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
> struct vi_de_ib_state_chained_ib chained;
> } de_payload = {};
>
> - csa_addr = amdgpu_csa_vaddr(ring->adev);
> + csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
> gds_addr = csa_addr + 4096;
> if (ring->adev->virt.chained_ib_support) {
> de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 928034c..81c1578 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4327,7 +4327,7 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
> int cnt;
>
> cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
> - csa_addr = amdgpu_csa_vaddr(ring->adev);
> + csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
>
> amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
> amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
> @@ -4345,7 +4345,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
> uint64_t csa_addr, gds_addr;
> int cnt;
>
> - csa_addr = amdgpu_csa_vaddr(ring->adev);
> + csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
> gds_addr = csa_addr + 4096;
> de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
> de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
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next prev parent reply other threads:[~2018-12-06 12:28 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-06 12:14 [PATCH 2/9] drm/amdgpu: Refine function amdgpu_csa_vaddr Rex Zhu
[not found] ` <1544098447-21648-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:14 ` [PATCH 3/9] drm/amdgpu: Use dynamical reserved vm size Rex Zhu
[not found] ` <1544098447-21648-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:32 ` Christian König
[not found] ` <ca2a8aaa-3a0b-8c8e-1d5a-ec2e12c70434-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-12-06 14:13 ` Zhu, Rex
2018-12-06 12:14 ` [PATCH 4/9] drm/amdgpu: Add a bitmask in amdgpu_ctx_mgr Rex Zhu
[not found] ` <1544098447-21648-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:33 ` Christian König
[not found] ` <ab6bcc8e-8f88-5cb9-c2e8-5322a907bdac-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-12-06 14:48 ` Zhu, Rex
[not found] ` <BYAPR12MB2775D509B792B3D869B1BC8EFBA90-ZGDeBxoHBPmJeBUhB162ZQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-12-06 14:56 ` Koenig, Christian
2018-12-06 12:14 ` [PATCH 5/9] drm/amdgpu: Delay map sriov csa addr to ctx init Rex Zhu
[not found] ` <1544098447-21648-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:38 ` Christian König
2018-12-06 12:14 ` [PATCH 6/9] drm/amdgpu: Create csa per ctx Rex Zhu
[not found] ` <1544098447-21648-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:46 ` Christian König
2018-12-06 12:14 ` [PATCH 7/9] drm/amdgpu: Add csa mc address into job structure Rex Zhu
[not found] ` <1544098447-21648-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:39 ` Christian König
2018-12-06 12:14 ` [PATCH 8/9] drm/amdgpu: Add a argument in emit_cntxcntl interface Rex Zhu
[not found] ` <1544098447-21648-7-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:40 ` Christian König
2018-12-06 12:14 ` [PATCH 9/9] drm/amdgpu: Remove sriov check when insert ce/de meta_data Rex Zhu
[not found] ` <1544098447-21648-8-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 12:42 ` Christian König
2018-12-06 12:28 ` Christian König [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-12-06 12:22 [PATCH 2/9] drm/amdgpu: Refine function amdgpu_csa_vaddr Rex Zhu
2018-12-06 12:15 Rex Zhu
2018-12-06 11:32 [PATCH 1/9] drm/amdgpu: Limit vm max ctx number to 4096 Rex Zhu
[not found] ` <1544095957-21101-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-12-06 11:32 ` [PATCH 2/9] drm/amdgpu: Refine function amdgpu_csa_vaddr Rex Zhu
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